From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com []) by mx.groups.io with SMTP id smtpd.web09.27647.1612143476489046256 for ; Sun, 31 Jan 2021 17:37:57 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: dgeogGx4dpV+wNHNKQSIHKu9NH4aFjSfcsM2zymu2bHglI5fTD84JAIUeYhUHebbX3nXqSlSda jsZONcHfin+w== X-IronPort-AV: E=McAfee;i="6000,8403,9881"; a="160388136" X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="160388136" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 31 Jan 2021 17:37:57 -0800 IronPort-SDR: 9c2zO4fP0XkjsWmOpNlt9OGy8cBocg0t2bVe+8WUuBX8gzueNap4TYAYUraIBWfNETKOFikvh1 M6MTwb414fQA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,391,1602572400"; d="scan'208";a="368718854" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 31 Jan 2021 17:37:56 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Date: Mon, 1 Feb 2021 09:36:55 +0800 Message-Id: <20210201013657.1833-38-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210201013657.1833-1-heng.luo@intel.com> References: <20210201013657.1833-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following DSC files: * Fru/TglCpu * Fru/TglPch Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc | 11 +++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc | 9 +++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc | 20 ++++++++++= ++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc | 8 ++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc | 7 +++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc | 30 ++++++++++= ++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc | 9 +++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc | 13 ++++++++++= +++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc | 8 ++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc | 10 ++++++++++ 10 files changed, 125 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc b/S= ilicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc new file mode 100644 index 0000000000..99ee0eccac --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc @@ -0,0 +1,11 @@ +## @file=0D +# Component description file for the TigerLake CPU Common FRU libraries.= =0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +VtdInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/= PeiDxeSmmVtdInfoLib.inf=0D +CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpu= PcieRpLib/PeiDxeSmmCpuPcieRpLib.inf=0D +CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CpuPcieRp/Library/PeiD= xeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc b/Silicon= /Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc new file mode 100644 index 0000000000..874e4cbaad --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc @@ -0,0 +1,9 @@ +## @file=0D +# Component description file for the Tigerlake CPU DXE FRU drivers.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc b/Sili= con/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc new file mode 100644 index 0000000000..5c72c2ac61 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc @@ -0,0 +1,20 @@ +## @file=0D +# Component description file for the Tigerlake CPU DXE FRU libraries.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivat= e/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf=0D +DxeGraphicsInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/= DxeGraphicsInitLib/DxeGraphicsInitLib.inf=0D +DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPriva= te/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf=0D +DxeVtdInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdInit= Lib/DxeVtdInitLib.inf=0D +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdPo= licyLib/DxeVtdPolicyLib.inf=0D +DxeVtdInitFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Vtd/LibraryPrivate/DxeV= tdInitLib/DxeVtdInitFruLib.inf=0D +=0D +=0D +#=0D +# CPU PCIe IpBlock=0D +#=0D +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryPrivate/Dx= eCpuPcieRpLib/DxeCpuPcieRpLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc b/Silicon= /Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc new file mode 100644 index 0000000000..de8288364a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc @@ -0,0 +1,8 @@ +## @file=0D +# Component description file for the Tigerlake CPU PEI FRU drivers.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc b/Sili= con/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc new file mode 100644 index 0000000000..5355ecb288 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc @@ -0,0 +1,7 @@ +## @file=0D +# Component description file for the Tigerlake CPU PEI FRU ibraries.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc b/S= ilicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc new file mode 100644 index 0000000000..b7ba1f752c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc @@ -0,0 +1,30 @@ +## @file=0D +# Component description file for the Tigerlake PCH Common FRU libraries.= =0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D + PsfLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSm= mPsfLibVer2.inf=0D + PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib= /PeiDxeSmmPchPcrLib.inf=0D + PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDx= eSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf=0D + GbeMdiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbe= MdiLib/PeiDxeSmmGbeMdiLib.inf=0D + GbeLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiDxe= SmmGbeLib.inf=0D + EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/Pei= DxeSmmEspiLib.inf=0D + PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxe= SmmPmcLib.inf=0D + PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf=0D + PmcPrivateLibWithS3|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/Pe= iDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf=0D + SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpiCo= mmonLib/BaseSpiCommonLib.inf=0D + GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/Pei= DxeSmmGpioLib.inf=0D + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxe= SmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf=0D + GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpi= oCheckConflictLib/BaseGpioCheckConflictLib.inf=0D + PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmm= PchDmiLib/PeiDxeSmmPchDmiLib.inf=0D + PchDmiWithS3Lib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/Pei= DxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf=0D + SataLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Sata/Library/PeiDxeSmmSataLib/Pei= DxeSmmSataLibVer2.inf=0D + SpiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiDxeSmmSpiAcce= ssLib/PeiDxeSmmSpiAccessLib.inf=0D + SpiAccessPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/Pe= iDxeSmmSpiAccessPrivateLib/PeiDxeSmmSpiAccessPrivateLib.inf=0D + PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPchP= cieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf=0D + PcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PcieClien= tRpLib/PcieClientRpLib.inf=0D + PciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivat= e/PciExpressHelpersLibrary/PeiDxeSmmPciExpressHelpersLib.inf=0D + BasePcieHelperLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/BasePcie= HelperLib/BasePcieHelperLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc b/Silicon= /Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc new file mode 100644 index 0000000000..9fefc6b4c9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc @@ -0,0 +1,9 @@ +## @file=0D +# Component description file for the Tigerlake PCH DXE FRU drivers.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc b/Sili= con/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc new file mode 100644 index 0000000000..e9be448baa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc @@ -0,0 +1,13 @@ +## @file=0D +# Component description file for the Tigerlake PCH DXE FRU libraries.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D + DxeHdaNhltLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Hda/Library/DxeHdaNhltLib/D= xeHdaNhltLib.inf=0D + DxeHdaPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Hda/LibraryPrivate/DxeHda= PolicyLib/DxeHdaPolicyLib.inf=0D + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseGp= ioHelpersLibNull/BaseGpioHelpersLibNull.inf=0D + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Dxe= GpioNameBufferLib/DxeGpioNameBufferLib.inf=0D + DxeGpioPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/DxeG= pioPolicyLib/DxeGpioPolicyLib.inf=0D + DxePchPcieRpPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPriva= te/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc b/Silicon= /Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc new file mode 100644 index 0000000000..2eacbe905c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc @@ -0,0 +1,8 @@ +## @file=0D +# Component description file for the Tigerlake PCH PEI FRU drivers.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc b/Sili= con/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc new file mode 100644 index 0000000000..d8e6313084 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc @@ -0,0 +1,10 @@ +## @file=0D +# Component description file for the Tigerlake PCH PEI FRU libraries.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpi= oHelpersLib/PeiGpioHelpersLib.inf=0D + GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/Pei= GpioNameBufferLib/PeiGpioNameBufferLib.inf=0D --=20 2.24.0.windows.2