From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga02.intel.com (mga02.intel.com [134.134.136.20]) by mx.groups.io with SMTP id smtpd.web10.2281.1612407581546439199 for ; Wed, 03 Feb 2021 18:59:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.20, mailfrom: ray.ni@intel.com) IronPort-SDR: +sHoirMVgGwbqtgyNdEm2z2kkdIrl3y9RWSa613bJDlZbPzHZdwyfP+MYoxdoTcfhk3GSI69JH LCZSI8o8H90w== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="168269633" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="168269633" Received: from fmsmga001.fm.intel.com ([10.253.24.23]) by orsmga101.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Feb 2021 18:59:40 -0800 IronPort-SDR: GW13SBaYBItJvo3yGDgccaoEXxmi022SN2I2byoE4dJdhD3TRijwmMxLsbZ13tNmFkETIWQF3r yIY4J3sANZJA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="480711034" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by fmsmga001.fm.intel.com with ESMTP; 03 Feb 2021 18:59:37 -0800 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH 1/2] UefiCpuPkg/MpInitLib: Use NASM struc to avoid hardcode offset Date: Thu, 4 Feb 2021 10:59:20 +0800 Message-Id: <20210204025921.1428-2-ray.ni@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20210204025921.1428-1-ray.ni@intel.com> References: <20210204025921.1428-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In Windows environment, "dumpbin /disasm" is used to verify the disassembly before and after using NASM struc doesn't change. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 52 ++++++++++-------- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 35 ++++++------ UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 54 ++++++++++--------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 46 ++++++++-------- 4 files changed, 98 insertions(+), 89 deletions(-) diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc b/UefiCpuPkg/Libra= ry/MpInitLib/Ia32/MpEqu.inc index 4f5a7c859a..244c1e72b7 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -19,25 +19,31 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1=0D CPU_SWITCH_STATE_LOADED equ 2=0D =0D -LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart)=0D -StackStartAddressLocation equ LockLocation + 04h=0D -StackSizeLocation equ LockLocation + 08h=0D -ApProcedureLocation equ LockLocation + 0Ch=0D -GdtrLocation equ LockLocation + 10h=0D -IdtrLocation equ LockLocation + 16h=0D -BufferStartLocation equ LockLocation + 1Ch=0D -ModeOffsetLocation equ LockLocation + 20h=0D -ApIndexLocation equ LockLocation + 24h=0D -CodeSegmentLocation equ LockLocation + 28h=0D -DataSegmentLocation equ LockLocation + 2Ch=0D -EnableExecuteDisableLocation equ LockLocation + 30h=0D -Cr3Location equ LockLocation + 34h=0D -InitFlagLocation equ LockLocation + 38h=0D -CpuInfoLocation equ LockLocation + 3Ch=0D -NumApsExecutingLocation equ LockLocation + 40h=0D -InitializeFloatingPointUnitsAddress equ LockLocation + 48h=0D -ModeTransitionMemoryLocation equ LockLocation + 4Ch=0D -ModeTransitionSegmentLocation equ LockLocation + 50h=0D -ModeHighMemoryLocation equ LockLocation + 52h=0D -ModeHighSegmentLocation equ LockLocation + 56h=0D -=0D +MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelPro= cStart)=0D +struc MP_CPU_EXCHANGE_INFO=0D + .Lock: resd 1=0D + .StackStart: resd 1=0D + .StackSize: resd 1=0D + .CFunction: resd 1=0D + .GdtrProfile: resb 6=0D + .IdtrProfile: resb 6=0D + .BufferStart: resd 1=0D + .ModeOffset: resd 1=0D + .ApIndex: resd 1=0D + .CodeSegment: resd 1=0D + .DataSegment: resd 1=0D + .EnableExecuteDisable: resd 1=0D + .Cr3: resd 1=0D + .InitFlag: resd 1=0D + .CpuInfo: resd 1=0D + .NumApsExecuting: resd 1=0D + .CpuMpData: resd 1=0D + .InitializeFloatingPointUnits: resd 1=0D + .ModeTransitionMemory: resd 1=0D + .ModeTransitionSegment:resw 1=0D + .ModeHighMemory: resd 1=0D + .ModeHighSegment: resw 1=0D + .Enable5LevelPaging: resb 1=0D + .SevEsIsEnabled: resb 1=0D + .GhcbBase: resd 1=0D +endstruc=0D diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index 7e81d24aa6..908c2eb447 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -39,21 +39,21 @@ BITS 16 mov fs, ax=0D mov gs, ax=0D =0D - mov si, BufferStartLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Buf= ferStart=0D mov ebx, [si]=0D =0D - mov si, DataSegmentLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Dat= aSegment=0D mov edx, [si]=0D =0D ;=0D ; Get start address of 32-bit code in low memory (<1MB)=0D ;=0D - mov edi, ModeTransitionMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Mod= eTransitionMemory=0D =0D - mov si, GdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Gdtr= Profile=0D o32 lgdt [cs:si]=0D =0D - mov si, IdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Idtr= Profile=0D o32 lidt [cs:si]=0D =0D ;=0D @@ -82,7 +82,7 @@ Flat32Start: ; protecte= d mode entry point mov esi, ebx=0D =0D mov edi, esi=0D - add edi, EnableExecuteDisableLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.En= ableExecuteDisable=0D cmp byte [edi], 0=0D jz SkipEnableExecuteDisable=0D =0D @@ -96,7 +96,7 @@ Flat32Start: ; protecte= d mode entry point wrmsr=0D =0D mov edi, esi=0D - add edi, Cr3Location=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Cr= 3=0D mov eax, dword [edi]=0D mov cr3, eax=0D =0D @@ -110,19 +110,19 @@ Flat32Start: ; prot= ected mode entry point =0D SkipEnableExecuteDisable:=0D mov edi, esi=0D - add edi, InitFlagLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Ini= tFlag=0D cmp dword [edi], 1 ; 1 =3D=3D ApInitConfig=0D jnz GetApicId=0D =0D ; Increment the number of APs executing here as early as possible=0D ; This is decremented in C code when AP is finished executing=0D mov edi, esi=0D - add edi, NumApsExecutingLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Num= ApsExecuting=0D lock inc dword [edi]=0D =0D ; AP init=0D mov edi, esi=0D - add edi, LockLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET=0D mov eax, NotVacantFlag=0D =0D TestLock:=0D @@ -131,7 +131,7 @@ TestLock: jz TestLock=0D =0D mov ecx, esi=0D - add ecx, ApIndexLocation=0D + add ecx, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.ApI= ndex=0D inc dword [ecx]=0D mov ebx, [ecx]=0D =0D @@ -140,13 +140,13 @@ Releaselock: xchg [edi], eax=0D =0D mov edi, esi=0D - add edi, StackSizeLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Sta= ckSize=0D mov eax, [edi]=0D mov ecx, ebx=0D inc ecx=0D mul ecx ; EAX =3D StackSize * (Cp= uNumber + 1)=0D mov edi, esi=0D - add edi, StackStartAddressLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Sta= ckStart=0D add eax, [edi]=0D mov esp, eax=0D jmp CProcedureInvoke=0D @@ -179,7 +179,7 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp()=0D ;=0D xor ebx, ebx=0D - lea eax, [esi + CpuInfoLocation]=0D + lea eax, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_= INFO.CpuInfo]=0D mov edi, [eax]=0D =0D GetNextProcNumber:=0D @@ -203,13 +203,12 @@ CProcedureInvoke: =0D push ebx ; Push ApIndex=0D mov eax, esi=0D - add eax, LockLocation=0D + add eax, MP_CPU_EXCHANGE_INFO_OFFSET=0D push eax ; push address of exchange info data buff= er=0D =0D mov edi, esi=0D - add edi, ApProcedureLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.CFu= nction=0D mov eax, [edi]=0D -=0D call eax ; Invoke C function=0D =0D jmp $ ; Never reach here=0D diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc index c92daaaffd..3974330991 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -19,27 +19,31 @@ CPU_SWITCH_STATE_IDLE equ 0 CPU_SWITCH_STATE_STORED equ 1=0D CPU_SWITCH_STATE_LOADED equ 2=0D =0D -LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart)=0D -StackStartAddressLocation equ LockLocation + 08h=0D -StackSizeLocation equ LockLocation + 10h=0D -ApProcedureLocation equ LockLocation + 18h=0D -GdtrLocation equ LockLocation + 20h=0D -IdtrLocation equ LockLocation + 2Ah=0D -BufferStartLocation equ LockLocation + 34h=0D -ModeOffsetLocation equ LockLocation + 3Ch=0D -ApIndexLocation equ LockLocation + 44h=0D -CodeSegmentLocation equ LockLocation + 4Ch=0D -DataSegmentLocation equ LockLocation + 54h=0D -EnableExecuteDisableLocation equ LockLocation + 5Ch=0D -Cr3Location equ LockLocation + 64h=0D -InitFlagLocation equ LockLocation + 6Ch=0D -CpuInfoLocation equ LockLocation + 74h=0D -NumApsExecutingLocation equ LockLocation + 7Ch=0D -InitializeFloatingPointUnitsAddress equ LockLocation + 8Ch=0D -ModeTransitionMemoryLocation equ LockLocation + 94h=0D -ModeTransitionSegmentLocation equ LockLocation + 98h=0D -ModeHighMemoryLocation equ LockLocation + 9Ah=0D -ModeHighSegmentLocation equ LockLocation + 9Eh=0D -Enable5LevelPagingLocation equ LockLocation + 0A0h=0D -SevEsIsEnabledLocation equ LockLocation + 0A1h=0D -GhcbBaseLocation equ LockLocation + 0A2h=0D +MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelPro= cStart)=0D +struc MP_CPU_EXCHANGE_INFO=0D + .Lock: resq 1=0D + .StackStart: resq 1=0D + .StackSize: resq 1=0D + .CFunction: resq 1=0D + .GdtrProfile: resb 10=0D + .IdtrProfile: resb 10=0D + .BufferStart: resq 1=0D + .ModeOffset: resq 1=0D + .ApIndex: resq 1=0D + .CodeSegment: resq 1=0D + .DataSegment: resq 1=0D + .EnableExecuteDisable: resq 1=0D + .Cr3: resq 1=0D + .InitFlag: resq 1=0D + .CpuInfo: resq 1=0D + .NumApsExecuting: resq 1=0D + .CpuMpData: resq 1=0D + .InitializeFloatingPointUnits: resq 1=0D + .ModeTransitionMemory: resd 1=0D + .ModeTransitionSegment:resw 1=0D + .ModeHighMemory: resd 1=0D + .ModeHighSegment: resw 1=0D + .Enable5LevelPaging: resb 1=0D + .SevEsIsEnabled: resb 1=0D + .GhcbBase: resq 1=0D +endstruc=0D diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index aecfd07bc0..423beb2cca 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -43,21 +43,21 @@ BITS 16 mov fs, ax=0D mov gs, ax=0D =0D - mov si, BufferStartLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Buf= ferStart=0D mov ebx, [si]=0D =0D - mov si, DataSegmentLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Dat= aSegment=0D mov edx, [si]=0D =0D ;=0D ; Get start address of 32-bit code in low memory (<1MB)=0D ;=0D - mov edi, ModeTransitionMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Mod= eTransitionMemory=0D =0D - mov si, GdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Gdtr= Profile=0D o32 lgdt [cs:si]=0D =0D - mov si, IdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Idtr= Profile=0D o32 lidt [cs:si]=0D =0D ;=0D @@ -85,7 +85,7 @@ Flat32Start: ; protecte= d mode entry point ;=0D ; Enable execute disable bit=0D ;=0D - mov esi, EnableExecuteDisableLocation=0D + mov esi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Ena= bleExecuteDisable=0D cmp byte [ebx + esi], 0=0D jz SkipEnableExecuteDisableBit=0D =0D @@ -101,7 +101,7 @@ SkipEnableExecuteDisableBit: mov eax, cr4=0D bts eax, 5=0D =0D - mov esi, Enable5LevelPagingLocation=0D + mov esi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Ena= ble5LevelPaging=0D cmp byte [ebx + esi], 0=0D jz SkipEnable5LevelPaging=0D =0D @@ -117,7 +117,7 @@ SkipEnable5LevelPaging: ;=0D ; Load page table=0D ;=0D - mov esi, Cr3Location ; Save CR3 in ecx=0D + mov esi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Cr3= ; Save CR3 in ecx=0D mov ecx, [ebx + esi]=0D mov cr3, ecx ; Load CR3=0D =0D @@ -139,26 +139,26 @@ SkipEnable5LevelPaging: ;=0D ; Far jump to 64-bit code=0D ;=0D - mov edi, ModeHighMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Mod= eHighMemory=0D add edi, ebx=0D jmp far [edi]=0D =0D BITS 64=0D LongModeStart:=0D mov esi, ebx=0D - lea edi, [esi + InitFlagLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_I= NFO.InitFlag]=0D cmp qword [edi], 1 ; ApInitConfig=0D jnz GetApicId=0D =0D ; Increment the number of APs executing here as early as possible=0D ; This is decremented in C code when AP is finished executing=0D mov edi, esi=0D - add edi, NumApsExecutingLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Num= ApsExecuting=0D lock inc dword [edi]=0D =0D ; AP init=0D mov edi, esi=0D - add edi, LockLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Loc= k=0D mov rax, NotVacantFlag=0D =0D TestLock:=0D @@ -166,7 +166,7 @@ TestLock: cmp rax, NotVacantFlag=0D jz TestLock=0D =0D - lea ecx, [esi + ApIndexLocation]=0D + lea ecx, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_I= NFO.ApIndex]=0D inc dword [ecx]=0D mov ebx, [ecx]=0D =0D @@ -175,17 +175,17 @@ Releaselock: xchg qword [edi], rax=0D ; program stack=0D mov edi, esi=0D - add edi, StackSizeLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Sta= ckSize=0D mov eax, dword [edi]=0D mov ecx, ebx=0D inc ecx=0D mul ecx ; EAX =3D StackSize * (Cp= uNumber + 1)=0D mov edi, esi=0D - add edi, StackStartAddressLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Sta= ckStart=0D add rax, qword [edi]=0D mov rsp, rax=0D =0D - lea edi, [esi + SevEsIsEnabledLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_I= NFO.SevEsIsEnabled]=0D cmp byte [edi], 1 ; SevEsIsEnabled=0D jne CProcedureInvoke=0D =0D @@ -199,7 +199,7 @@ Releaselock: mov ecx, ebx=0D mul ecx ; EAX =3D SIZE_4K * 2 * C= puNumber=0D mov edi, esi=0D - add edi, GhcbBaseLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.Ghc= bBase=0D add rax, qword [edi]=0D mov rdx, rax=0D shr rdx, 32=0D @@ -208,7 +208,7 @@ Releaselock: jmp CProcedureInvoke=0D =0D GetApicId:=0D - lea edi, [esi + SevEsIsEnabledLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_I= NFO.SevEsIsEnabled]=0D cmp byte [edi], 1 ; SevEsIsEnabled=0D jne DoCpuid=0D =0D @@ -302,7 +302,7 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp()=0D ;=0D xor ebx, ebx=0D - lea eax, [esi + CpuInfoLocation]=0D + lea eax, [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_= INFO.CpuInfo]=0D mov rdi, [eax]=0D =0D GetNextProcNumber:=0D @@ -321,17 +321,17 @@ CProcedureInvoke: push rbp=0D mov rbp, rsp=0D =0D - mov rax, qword [esi + InitializeFloatingPointUnitsAddress]=0D + mov rax, qword [esi + MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCH= ANGE_INFO.InitializeFloatingPointUnits]=0D sub rsp, 20h=0D call rax ; Call assembly function to initialize FP= U per UEFI spec=0D add rsp, 20h=0D =0D mov edx, ebx ; edx is ApIndex=0D mov ecx, esi=0D - add ecx, LockLocation ; rcx is address of exchange info data bu= ffer=0D + add ecx, MP_CPU_EXCHANGE_INFO_OFFSET ; rcx is address of exchan= ge info data buffer=0D =0D mov edi, esi=0D - add edi, ApProcedureLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_OFFSET + MP_CPU_EXCHANGE_INFO.CFu= nction=0D mov rax, qword [edi]=0D =0D sub rsp, 20h=0D --=20 2.27.0.windows.1