From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga18.intel.com (mga18.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5219.1612428674130530214 for ; Thu, 04 Feb 2021 00:51:14 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: Fdwic2gNqqnMyGnZ13WQSJCK033vj2x3Kb5rcphNHI6hwSny23tudmqTNJ8G62m4yEwdNZLTMr +hvI2kksurpQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="168880807" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="168880807" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:10 -0800 IronPort-SDR: +GCQ2rGTdI9JTM+RskQs6dNhqsows4jElzuvf905i29/CCjzENNjVQ+8ZNI+hyI6WUZoo2nYQW LqRCI5x9mDrg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062093" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:08 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Date: Thu, 4 Feb 2021 16:48:51 +0800 Message-Id: <20210204084919.3603-12-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Fru/TglPch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPc= rRegs.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ 1 file changed, 66 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Re= gister/PchPcrRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludeP= rivate/Register/PchPcrRegs.h new file mode 100644 index 0000000000..4987d21f09 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/= PchPcrRegs.h @@ -0,0 +1,66 @@ +/** @file=0D + Register names for PCH private chipset register=0D +=0D +Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PCR_H_=0D +#define _PCH_REGS_PCR_H_=0D +=0D +/**=0D + Definition for SBI PID=0D + The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI pro= gramming as well.=0D +**/=0D +#define PID_CNVI 0x73=0D +#define PID_ICLK 0xAD=0D +#define PID_DMI 0x88=0D +#define PID_PSTH 0x89=0D +#define PID_ESPISPI 0x72=0D +#define PID_SPF 0x85=0D +#define PID_SPE 0x84=0D +#define PID_SPD 0x83=0D +#define PID_SPC 0x82=0D +#define PID_SPB 0x81=0D +#define PID_SPA 0x80=0D +#define PID_PSF6 0x7F=0D +#define PID_PSF4 0xBD=0D +#define PID_PSF3 0xBC=0D +#define PID_PSF2 0xBB=0D +#define PID_PSF1 0xBA=0D +#define PID_GPIOCOM0 0x6E=0D +#define PID_GPIOCOM1 0x6D=0D +#define PID_GPIOCOM2 0x6C=0D +#define PID_GPIOCOM3 0x6B=0D +#define PID_GPIOCOM4 0x6A=0D +#define PID_GPIOCOM5 0x69=0D +#define PID_CSME_PSF 0x8F=0D +=0D +#endif=0D --=20 2.24.0.windows.2