From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com []) by mx.groups.io with SMTP id smtpd.web09.5264.1612428705251082584 for ; Thu, 04 Feb 2021 00:51:46 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: z/YMkNvOTGYdnug1MMCT0rhhNLg7ZxfGJw69DlZDzKIsZO7fj8MxOnu/plL/7m3Iqo00B8C5ac edW2kVzJj2JQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160957362" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160957362" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:21 -0800 IronPort-SDR: SzTrRkgHgdo9T3gVZxRcYFaewr+yX7wSm7Ey5wIrV2SD+yex9QL0u3mcTF4rCyIwzJ10hOpl6j 3MWNwBNHfELw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062203" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:15 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Date: Thu, 4 Feb 2021 16:48:55 +0800 Message-Id: <20210204084919.3603-16-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/Gbe/IncludePrivate * IpBlock/Gbe/Library * IpBlock/Gbe/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/GbeMd= iLib.h | 324 ++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register/GbeR= egs.h | 68 ++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/GbeL= ib.c | 121 ++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiD= xeSmmGbeLib.inf | 43 ++++++++++++++++++++++++++++++++++++++++= +++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeM= diLib/GbeMdiLib.c | 388 ++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeM= diLib/PeiDxeSmmGbeMdiLib.inf | 34 ++++++++++++++++++++++++++++++++++ 6 files changed, 978 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/L= ibrary/GbeMdiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludeP= rivate/Library/GbeMdiLib.h new file mode 100644 index 0000000000..b8274ed3dc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Library/= GbeMdiLib.h @@ -0,0 +1,324 @@ +/** @file=0D + Header file for GbeMdiLib.=0D +=0D + Conventions:=0D +=0D + - Prefixes:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register sizes=0D + Definitions beginning with "N_" are the bit position=0D + - In general, PCH registers are denoted by "_PCH_" in register names=0D + - Registers / bits that are different between PCH generations are denote= d by=0D + "_PCH_[generation_name]_" in register/bit names.=0D + - Registers / bits that are specific to PCH-H denoted by "_H_" in regist= er/bit names.=0D + Registers / bits that are specific to PCH-LP denoted by "_LP_" in regi= ster/bit names.=0D + e.g., "_PCH_LP_"=0D + Registers / bits names without or _LP_ apply for LP.=0D + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]"=0D + at the end of the register/bit names=0D + - Registers / bits of new devices introduced in a PCH generation will be= just named=0D + as "_PCH_" without [generation_name] inserted.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GBE_MDI_LIB_H_=0D +#define _GBE_MDI_LIB_H_=0D +=0D +//=0D +// Maximum loop time for GbE status check=0D +// 4000 * 50 =3D 200 mSec in total=0D +//=0D +#define GBE_MAX_LOOP_TIME 4000=0D +#define GBE_ACQUIRE_MDIO_DELAY 50=0D +#define GBE_MDI_SET_PAGE_DELAY 4000 // 4 mSec delay after setting page=0D +=0D +//=0D +// LAN PHY MDI settings=0D +//=0D +// MDI Control Register Bits=0D +// 31:30 Reserved=0D +// This field is reserved and returns 0.=0D +// 29 Interrupt Enable.=0D +// When this bit is set to 1 by software, it causes the device to as= sert=0D +// an interrupt indicating the end of an MDI cycle.=0D +// 28 Ready.=0D +// Set to 1 by the device at the end of MDI transaction (i.e., indic= ates a Read or=0D +// Write has been completed. It should be reset to 0 by software at = the same time the=0D +// command is written.=0D +// 27:26 Opcode=0D +// For an MDI write, the opcode equals 01b, and for MDI read, 10b. 0= 0b and=0D +// 11b are reserved and should not be used.=0D +// 25:21 PHYAdd=0D +// PHY Address=0D +// 20:16 RegAdd=0D +// PHY Register Address=0D +// 15:0 Data=0D +=0D +#define B_PHY_MDI_READY BIT28=0D +#define B_PHY_MDI_READ BIT27=0D +#define B_PHY_MDI_WRITE BIT26=0D +//=0D +// PHY SPECIFIC registers=0D +//=0D +#define B_PHY_MDI_PHY_ADDRESS_02 BIT22=0D +//=0D +// PHY GENERAL registers=0D +// Registers 0 to 15 are defined by the specification=0D +// Registers 16 to 31 are left available to the vendor=0D +//=0D +#define B_PHY_MDI_PHY_ADDRESS_01 BIT21=0D +#define B_PHY_MDI_PHY_ADDRESS_MASK (BIT25 | BIT24 | BIT23 | BIT22 | BIT= 21)=0D +//=0D +// PHY Identifier Register 2=0D +// Bits [15:10] - PHY ID Number - The PHY identifier composed of bits 3= through 18=0D +// of the Organizationally Unique Identi= fier (OUI)=0D +// Bits [9:4] - Device Model Number=0D +// Bits [3:0] - Device Revision Number=0D +//=0D +#define R_PHY_MDI_GENEREAL_REGISTER_03_PHY_IDENTIFIER_2 0x00030000=0D +=0D +#define MDI_REG_SHIFT(x) (x << 16)=0D +#define B_PHY_MDI_PHY_REGISTER_MASK (BIT20 | BIT19 | BIT= 18 | BIT17 | BIT16)=0D +#define R_PHY_MDI_PHY_REG_SET_ADDRESS 0x00110000 // Used a= fter new page setting=0D +#define R_PHY_MDI_PHY_REG_DATA_READ_WRITE 0x00120000=0D +#define R_PHY_MDI_PHY_REG_SET_PAGE 0x001F0000=0D +=0D +//=0D +// LAN PHY MDI registers and bits=0D +//=0D +=0D +//=0D +// Page 769 Port Control Registers=0D +// 6020h (769 * 32)=0D +//=0D +#define PHY_MDI_PAGE_769_PORT_CONTROL_REGISTERS 769=0D +//=0D +// Custom Mode Control PHY Address 01, Page 769, Register 16=0D +//=0D +#define R_PHY_MDI_PAGE_769_REGISETER_16_CMC 0x0010=0D +//=0D +// Custom Mode Control=0D +// Page 769, Register 16, BIT 10=0D +// 0 - normal MDIO frequency access=0D +// 1 - reduced MDIO frequency access (slow mdio)=0D +// required for read during cable disconnect=0D +//=0D +#define B_PHY_MDI_PAGE_769_REGISETER_16_CMC_MDIO_FREQ_ACCESS BIT10= =0D +//=0D +// Port General Configuration PHY Address 01, Page 769, Register 17=0D +//=0D +#define R_PHY_MDI_PAGE_769_REGISETER_17_PGC 0x0011=0D +//=0D +// Page 769, Register 17, BIT 4=0D +// Enables host wake up=0D +//=0D +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_HOST_WAKE_UP BIT4=0D +//=0D +// Page 769, Register 17, BIT 2=0D +// Globally enable the MAC power down feature while the=0D +// GbE supports WoL. When set to 1b,=0D +// pages 800 and 801 are enabled for=0D +// configuration and Host_WU_Active is not blocked for writes.=0D +//=0D +#define B_PHY_MDI_PAGE_769_REGISETER_17_PGC_MACPD_ENABLE BIT2=0D +=0D +//=0D +// Page 800 Wake Up Registers=0D +// 6400h (800 * 32)=0D +//=0D +#define PHY_MDI_PAGE_800_WAKE_UP_REGISTERS 800=0D +//=0D +// Wake Up Control - WUC PHY Address 01, Page 800, Register 1=0D +// 1h (Register 1)=0D +//=0D +#define R_PHY_MDI_PAGE_800_REGISETER_1_WUC 0x0001=0D +//=0D +// Wake Up Control - (WUC)=0D +// Page 800, Register 1, BIT 0=0D +// Advance Power Management Enable (APME)=0D +// If set to 1b, APM wake up is enabled.=0D +//=0D +#define B_PHY_MDI_PAGE_800_REGISETER_1_WUC_APME BIT0=0D +//=0D +// Receive Address Low - RAL PHY Address 01, Page 800, Register 16=0D +// 10h (Register 16)=0D +//=0D +#define R_PHY_MDI_PAGE_800_REGISETER_16_RAL0 0x0010=0D +//=0D +// Receive Address Low - RAL PHY Address 01, Page 800, Register 17=0D +// 11h (Register 17)=0D +//=0D +#define R_PHY_MDI_PAGE_800_REGISETER_17_RAL1 0x0011=0D +//=0D +// Receive Address High - RAH PHY Address 01, Page 800, Register 18=0D +// 12h (Register 18)=0D +//=0D +#define R_PHY_MDI_PAGE_800_REGISETER_18_RAH0 0x0012=0D +//=0D +// Receive Address High - RAH PHY Address 01, Page 800, Register 19=0D +// 13h (Register 19)=0D +//=0D +#define R_PHY_MDI_PAGE_800_REGISETER_19_RAH1 0x0013=0D +//=0D +// Setting AV (BIT15 RAH is divided on two registers)=0D +// RAH Register 19, Page 800, BIT 31=0D +//=0D +// Address valid (AV)=0D +// When this bit is set, the relevant RAL and RAH are valid=0D +//=0D +#define B_PHY_MDI_PAGE_800_REGISETER_19_RAH1_ADDRESS_VALID BIT15= =0D +//=0D +// Page 803 Host WoL Packet=0D +// 6460h (803 * 32)=0D +//=0D +#define PHY_MDI_PAGE_803_HOST_WOL_PACKET 803=0D +//=0D +// Host WoL Packet Clear - HWPC PHY Address 01, Page 803, Register 66=0D +//=0D +#define R_PHY_MDI_PAGE_803_REGISETER_66_HWPC 0x0042=0D +=0D +=0D +/**=0D + Change Extended Device Control Register BIT 11 to 1 which=0D + forces the interface between the MAC and the Phy to be on SMBus.=0D + Cleared on the assertion of PCI reset.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D +**/=0D +VOID=0D +GbeMdiForceMACtoSMB (=0D + IN UINT32 GbeBar=0D + );=0D +=0D +/**=0D + Test for MDIO operation complete.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_TIMEOUT=0D +**/=0D +EFI_STATUS=0D +GbeMdiWaitReady (=0D + IN UINT32 GbeBar=0D + );=0D +=0D +/**=0D + Acquire MDIO software semaphore.=0D +=0D + 1. Ensure that MBARA offset F00h [5] =3D 1b=0D + 2. Poll MBARA offset F00h [5] up to 200ms=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_TIMEOUT=0D +**/=0D +EFI_STATUS=0D +GbeMdiAcquireMdio (=0D + IN UINT32 GbeBar=0D + );=0D +=0D +/**=0D + Release MDIO software semaphore by clearing MBARA offset F00h [5]=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +**/=0D +VOID=0D +GbeMdiReleaseMdio (=0D + IN UINT32 GbeBar=0D + );=0D +=0D +/**=0D + Sets page on MDI=0D + Page setting is attempted twice.=0D + If first attempt failes MAC and the Phy are force to be on SMBus=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] Data Value to write in lower 16bits.=0D +=0D + @retval EFI_SUCCESS Page setting was successfull=0D + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiSetPage (=0D + IN UINT32 GbeBar,=0D + IN UINT32 Page=0D + );=0D +=0D +/**=0D + Sets Register in current page.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] register Register number=0D +=0D + @return EFI_STATUS=0D +**/=0D +EFI_STATUS=0D +GbeMdiSetRegister (=0D + IN UINT32 GbeBar,=0D + IN UINT32 Register=0D + );=0D +=0D +=0D +/**=0D + Perform MDI read.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] PhyAddress Phy Address General - 02 or Specific - 01=0D + @param [in] PhyRegister Phy Register=0D + @param [out] ReadData Return Value=0D +=0D + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady=0D + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady=0D + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiRead (=0D + IN UINT32 GbeBar,=0D + IN UINT32 PhyAddress,=0D + IN UINT32 PhyRegister,=0D + OUT UINT16 *ReadData=0D + );=0D +=0D +/**=0D + Perform MDI write.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] PhyAddress Phy Address General - 02 or Specific - 01=0D + @param [in] PhyRegister Phy Register=0D + @param [in] WriteData Value to write in lower 16bits.=0D +=0D + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady=0D + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady=0D + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiWrite (=0D + IN UINT32 GbeBar,=0D + IN UINT32 PhyAddress,=0D + IN UINT32 PhyRegister,=0D + IN UINT32 WriteData=0D + );=0D +=0D +/**=0D + Gets Phy Revision and Model Number=0D + from PHY IDENTIFIER register 2 (offset 3)=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [out] LanPhyRevision Return Value=0D +=0D + @return EFI_STATUS=0D + @return EFI_INVALID_PARAMETER When GbeBar is incorrect=0D +**/=0D +EFI_STATUS=0D +GbeMdiGetLanPhyRevision (=0D + IN UINT32 GbeBar,=0D + OUT UINT16 *LanPhyRevision=0D + );=0D +=0D +#endif // _GBE_MDI_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/R= egister/GbeRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePr= ivate/Register/GbeRegs.h new file mode 100644 index 0000000000..307f1e159e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/IncludePrivate/Register= /GbeRegs.h @@ -0,0 +1,68 @@ +/** @file=0D + Register names for GbE device=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GBE_REGS_H_=0D +#define _GBE_REGS_H_=0D +=0D +#define R_GBE_CFG_MBARA 0x10=0D +#define N_GBE_CFG_MBARA_ALIGN 17=0D +#define R_GBE_CFG_PMCS 0xCC=0D +#define B_GBE_CFG_PMCS_PS (BIT1 | BIT0)=0D +#define V_GBE_CFG_PMCS_PS0 0x00=0D +//=0D +// Gigabit Ethernet LAN Capabilities and Status Registers (Memory space)=0D +//=0D +#define R_GBE_MEM_CSR_CTRL 0=0D +//=0D +// LANPHYPC:=0D +// Connects to the LCD DEVICE_OFF# signal in the=0D +// LAN Connected Device=0D +//=0D +#define B_GBE_MEM_CSR_CTRL_LANPHYPC_OVERRIDE BIT16 // When set to 1 SW dr= iver has the ability to control the LANPHYPC pin value.=0D +#define B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL BIT17 // When set to 1 this = bit will define the value of the LANPHYPC pin.=0D +#define R_GBE_MEM_CSR_CTRL_EXT 0x0018=0D +#define B_GBE_MEM_CSR_CTRL_EXT_LPCD BIT2 //LCD Power Cycle Done (L= PCD). This bit indicates whether LCD power cycle is done=0D + //- the bit is set 50/100= mSec after LANPHYPC pin assertion.=0D +#define B_GBE_MEM_CSR_CTRL_EXT_FORCE_SMB BIT11=0D +#define R_GBE_MEM_CSR_MDIC 0x0020=0D +#define B_GBE_MEM_CSR_MDIC_RB BIT28=0D +#define R_GBE_MEM_CSR_EXTCNF_CTRL 0x0F00=0D +#define B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG BIT5=0D +#define R_GBE_MEM_CSR_RAL 0x5400=0D +#define R_GBE_MEM_CSR_RAH 0x5404=0D +#define B_GBE_MEM_CSR_RAH_RAH 0x0000FFFF=0D +#define R_GBE_MEM_CSR_WUC 0x5800=0D +#define B_GBE_MEM_CSR_WUC_APME BIT0=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSm= mGbeLib/GbeLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/Pe= iDxeSmmGbeLib/GbeLib.c new file mode 100644 index 0000000000..3b51b9eb62 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib= /GbeLib.c @@ -0,0 +1,121 @@ +/** @file=0D + Gbe Library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Check whether GbE region is valid=0D + Check SPI region directly since GbE might be disabled in SW.=0D +=0D + @retval TRUE Gbe Region is valid=0D + @retval FALSE Gbe Region is invalid=0D +**/=0D +BOOLEAN=0D +IsGbeRegionValid (=0D + VOID=0D + )=0D +{=0D + return SpiIsGbeRegionValid ();=0D +}=0D +=0D +/**=0D + Check whether GBE controller is enabled in the platform.=0D +=0D + @retval TRUE GbE is enabled=0D + @retval FALSE GbE is disabled=0D +**/=0D +BOOLEAN=0D +IsGbePresent (=0D + VOID=0D + )=0D +{=0D + //=0D + // Check PCH Support=0D + //=0D + if (!PchIsGbeSupported ()) {=0D + return FALSE;=0D + }=0D + //=0D + // Check PMC strap/fuse=0D + //=0D + if (!PmcIsGbeSupported ()) {=0D + return FALSE;=0D + }=0D + //=0D + // Check GbE NVM=0D + //=0D + if (IsGbeRegionValid () =3D=3D FALSE) {=0D + return FALSE;=0D + }=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Verifies Gigabit Ethernet PCI Class Code=0D +=0D + @param [in] GbePciCfgBase GbE PCI Config Space Address=0D +=0D + @retval TRUE GbE Class Code match=0D + @retval FALSE GbE Class Code does not match=0D +**/=0D +BOOLEAN=0D +STATIC=0D +GbeCheckClassCode (=0D + UINT64 GbePciCfgBase=0D + )=0D +{=0D + UINT8 BaseCode;=0D + UINT8 SubClassCode;=0D +=0D + SubClassCode =3D PciSegmentRead8 (GbePciCfgBase + PCI_CLASSCODE_OFFSET = + 1);=0D + BaseCode =3D PciSegmentRead8 (GbePciCfgBase + PCI_CLASSCODE_OFFSET = + 2);=0D +=0D + if ((BaseCode !=3D PCI_CLASS_NETWORK) || (SubClassCode !=3D PCI_CLASS_NE= TWORK_ETHERNET)) {=0D + DEBUG ((DEBUG_ERROR, "GbeCheckClassCode : BaseCode(0x%x) or ClassCode(= 0x%x) is not supported\n", BaseCode, SubClassCode));=0D + ASSERT (FALSE);=0D + return FALSE;=0D + }=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Checks if Gbe is Enabled or Disabled=0D +=0D + @retval BOOLEAN TRUE if device is enabled, FALSE otherwise.=0D +**/=0D +BOOLEAN=0D +IsGbeEnabled (=0D + VOID=0D + )=0D +{=0D + UINT64 GbePciBase;=0D +=0D + GbePciBase =3D GbePciCfgBase ();=0D +=0D + if (PciSegmentRead32 (GbePciBase) !=3D 0xFFFFFFFF) {=0D + return GbeCheckClassCode (GbePciBase);=0D + }=0D +=0D + return FALSE;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSm= mGbeLib/PeiDxeSmmGbeLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe= /Library/PeiDxeSmmGbeLib/PeiDxeSmmGbeLib.inf new file mode 100644 index 0000000000..4fef1288af --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/Library/PeiDxeSmmGbeLib= /PeiDxeSmmGbeLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# Gbe Library.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmGbeLib=0D +FILE_GUID =3D FC022ED0-6EB3-43E1-A740-0BA27CBBD010=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D GbeLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PchInfoLib=0D +PchPcrLib=0D +PchCycleDecodingLib=0D +PmcPrivateLib=0D +SpiAccessLib=0D +GbeMdiLib=0D +PchPciBdfLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +GbeLib.c=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/P= eiDxeSmmGbeMdiLib/GbeMdiLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/G= be/LibraryPrivate/PeiDxeSmmGbeMdiLib/GbeMdiLib.c new file mode 100644 index 0000000000..7917474406 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSm= mGbeMdiLib/GbeMdiLib.c @@ -0,0 +1,388 @@ +/** @file=0D + Gbe MDI Library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + Validates both Phy Address and Regster.=0D +=0D + @param [in] PhyAddress=0D + @param [in] PhyRegister=0D +=0D + @retval BOOLEAN TRUE Validation passed=0D + FALSE If the data is not within its range=0D +=0D +**/=0D +BOOLEAN=0D +IsPhyAddressRegisterValid (=0D + IN UINT32 PhyAddress,=0D + IN UINT32 PhyRegister=0D + )=0D +{=0D + if (((PhyAddress & (~B_PHY_MDI_PHY_ADDRESS_MASK)) !=3D 0) || ((PhyRegist= er & (~B_PHY_MDI_PHY_REGISTER_MASK)) !=3D 0)) {=0D + DEBUG ((DEBUG_ERROR, "IsPhyAddressRegisterValid validation failed! Phy= Address: 0x%08X PhyRegister: 0x%08X \n", PhyAddress, PhyRegister));=0D + return FALSE;=0D + }=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Change Extended Device Control Register BIT 11 to 1 which=0D + forces the interface between the MAC and the Phy to be on SMBus.=0D + Cleared on the assertion of PCI reset.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D +**/=0D +VOID=0D +GbeMdiForceMacToSmb (=0D + IN UINT32 GbeBar=0D + )=0D +{=0D + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL_EXT, B_GBE_MEM_CSR_CTRL_EXT_FORCE_= SMB);=0D +}=0D +=0D +/**=0D + Test for MDIO operation complete.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_TIMEOUT=0D +**/=0D +EFI_STATUS=0D +GbeMdiWaitReady (=0D + IN UINT32 GbeBar=0D + )=0D +{=0D + UINT32 Count;=0D +=0D + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) {=0D + if (MmioRead32 (GbeBar + R_GBE_MEM_CSR_MDIC) & B_GBE_MEM_CSR_MDIC_RB) = {=0D + return EFI_SUCCESS;=0D + }=0D + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY);=0D + }=0D + DEBUG ((DEBUG_ERROR, "GbeMdiWaitReady Timeout reached. MDIO operation fa= iled to complete in %d micro seconds\n", GBE_MAX_LOOP_TIME * GBE_ACQUIRE_MD= IO_DELAY));=0D + return EFI_TIMEOUT;=0D +}=0D +=0D +/**=0D + Acquire MDIO software semaphore.=0D +=0D + 1. Ensure that MBARA offset F00h [5] =3D 1b=0D + 2. Poll MBARA offset F00h [5] up to 200ms=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_TIMEOUT=0D +**/=0D +EFI_STATUS=0D +GbeMdiAcquireMdio (=0D + IN UINT32 GbeBar=0D + )=0D +{=0D + UINT32 ExtCnfCtrl;=0D + UINT32 Count;=0D +=0D + MmioOr32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL, B_GBE_MEM_CSR_EXTCNF_CTRL_= SWFLAG);=0D + for (Count =3D 0; Count < GBE_MAX_LOOP_TIME; ++Count) {=0D + ExtCnfCtrl =3D MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL);=0D + if (ExtCnfCtrl & B_GBE_MEM_CSR_EXTCNF_CTRL_SWFLAG) {=0D + return EFI_SUCCESS;=0D + }=0D + MicroSecondDelay (GBE_ACQUIRE_MDIO_DELAY);=0D + }=0D + DEBUG ((DEBUG_ERROR, "GbeMdiAcquireMdio Timeout. Unable to acquire MDIO = Semaphore in %d micro seconds\n", GBE_MAX_LOOP_TIME * GBE_ACQUIRE_MDIO_DELA= Y));=0D + return EFI_TIMEOUT;=0D +}=0D +=0D +/**=0D + Release MDIO software semaphore by clearing MBARA offset F00h [5]=0D +=0D + @param [in] GbeBar GbE MMIO space=0D +**/=0D +VOID=0D +GbeMdiReleaseMdio (=0D + IN UINT32 GbeBar=0D + )=0D +{=0D + ASSERT (MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL) & B_GBE_MEM_CSR_= EXTCNF_CTRL_SWFLAG);=0D + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL, (UINT32) ~B_GBE_MEM_CSR_E= XTCNF_CTRL_SWFLAG);=0D + ASSERT ((MmioRead32 (GbeBar + R_GBE_MEM_CSR_EXTCNF_CTRL) & B_GBE_MEM_CSR= _EXTCNF_CTRL_SWFLAG) =3D=3D 0);=0D +}=0D +=0D +/**=0D + Sets page on MDI=0D + Page setting is attempted twice.=0D + If first attempt failes MAC and the Phy are force to be on SMBus.=0D +=0D + Waits 4 mSec after page setting=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] Data Value to write in lower 16bits.=0D +=0D + @retval EFI_SUCCESS Page setting was successfull=0D + @retval EFI_DEVICE_ERROR Returned if both attermps of setting page fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiSetPage (=0D + IN UINT32 GbeBar,=0D + IN UINT32 Page=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_MD= I_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | R_PHY_MDI_PHY_REG_SET_PAGE | ((Page * = 32) & 0xFFFF)));=0D +=0D + Status =3D GbeMdiWaitReady (GbeBar);=0D +=0D + if (Status =3D=3D EFI_TIMEOUT) {=0D + DEBUG ((DEBUG_INFO, "GbeMdiSetPage Timeout reached. Forcing the interf= ace between the MAC and the Phy to be on SMBus\n"));=0D + GbeMdiForceMacToSmb (GbeBar);=0D + //=0D + // Retry page setting=0D + //=0D + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_= MDI_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | R_PHY_MDI_PHY_REG_SET_PAGE | ((Page = * 32) & 0xFFFF)));=0D + Status =3D GbeMdiWaitReady (GbeBar);=0D + if (Status =3D=3D EFI_TIMEOUT) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiSetPage retry page setting failed!\n"));= =0D + return EFI_DEVICE_ERROR;=0D + }=0D + }=0D +=0D + //=0D + // Delay required for page to set properly=0D + //=0D + MicroSecondDelay (GBE_MDI_SET_PAGE_DELAY);=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Sets Register in current page.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] register Register number valid only in lower 16 Bits=0D +=0D + @return EFI_STATUS=0D +**/=0D +EFI_STATUS=0D +GbeMdiSetRegister (=0D + IN UINT32 GbeBar,=0D + IN UINT32 Register=0D + )=0D +{=0D + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_MD= I_WRITE | B_PHY_MDI_PHY_ADDRESS_01 | R_PHY_MDI_PHY_REG_SET_ADDRESS | (Regis= ter & 0xFFFF)));=0D + return GbeMdiWaitReady (GbeBar);=0D +}=0D +=0D +/**=0D + Perform MDI write.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] PhyAddress Phy Address General - 02 or Specific - 01=0D + @param [in] PhyRegister Phy Register=0D + @param [in] WriteData Value to write in lower 16bits.=0D +=0D + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady=0D + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady=0D + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiWrite (=0D + IN UINT32 GbeBar,=0D + IN UINT32 PhyAddress,=0D + IN UINT32 PhyRegister,=0D + IN UINT32 WriteData=0D + )=0D +{=0D + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiWrite PhyAddressRegister validaton failed!= \n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_MD= I_WRITE | PhyAddress | PhyRegister | (WriteData & 0xFFFF)));=0D + return GbeMdiWaitReady (GbeBar);=0D +}=0D +=0D +/**=0D + Perform MDI read.=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [in] PhyAddress Phy Address General - 02 or Specific - 01=0D + @param [in] PhyRegister Phy Register=0D + @param [out] ReadData Return Value=0D +=0D + @retval EFI_SUCCESS Based on response from GbeMdiWaitReady=0D + @retval EFI_TIMEOUT Based on response from GbeMdiWaitReady=0D + @retval EFI_INVALID_PARAMETER If Phy Address or Register validaton fail= ed=0D +**/=0D +EFI_STATUS=0D +GbeMdiRead (=0D + IN UINT32 GbeBar,=0D + IN UINT32 PhyAddress,=0D + IN UINT32 PhyRegister,=0D + OUT UINT16 *ReadData=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + if(!IsPhyAddressRegisterValid (PhyAddress, PhyRegister)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiRead PhyAddressRegister validaton failed!\= n"));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + MmioWrite32 (GbeBar + R_GBE_MEM_CSR_MDIC, (~B_PHY_MDI_READY) & (B_PHY_MD= I_READ | PhyAddress | PhyRegister));=0D + Status =3D GbeMdiWaitReady (GbeBar);=0D + if (EFI_SUCCESS =3D=3D Status) {=0D + *ReadData =3D (UINT16) MmioRead32 (GbeBar + R_GBE_MEM_CSR_MDIC);=0D + }=0D + return Status;=0D +}=0D +=0D +/**=0D + Gets Phy Revision and Model Number=0D + from PHY IDENTIFIER register 2 (offset 3)=0D +=0D + @param [in] GbeBar GbE MMIO space=0D + @param [out] LanPhyRevision Return Value=0D +=0D + @return EFI_STATUS=0D + @return EFI_INVALID_PARAMETER When GbeBar is incorrect=0D + When Phy register or address is out of bou= nds=0D +**/=0D +EFI_STATUS=0D +GbeMdiGetLanPhyRevision (=0D + IN UINT32 GbeBar,=0D + OUT UINT16 *LanPhyRevision=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT8 LpcdLoop;=0D + UINT8 Delay;=0D +=0D + if (!((GbeBar & 0xFFFFF000) > 0)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision GbeBar validation failed= ! Bar: 0x%08X \n", GbeBar));=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Status =3D GbeMdiAcquireMdio (GbeBar);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to aquire MDIO se= maphore. Status: %r\n", Status));=0D + return Status;=0D + }=0D +=0D + Status =3D GbeMdiSetPage (GbeBar, PHY_MDI_PAGE_769_PORT_CONTROL_REGISTER= S);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to Set Page 769. = Status: %r\n", Status));=0D + GbeMdiReleaseMdio (GbeBar);=0D + return Status;=0D + }=0D +=0D + //=0D + // Set register to: Custom Mode Control=0D + // Reduced MDIO frequency access (slow mdio)=0D + // BIT 10 set to 1=0D + //=0D + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT = (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), BIT13 | B_PHY_MDI_PAGE_769_REGISETER= _16_CMC_MDIO_FREQ_ACCESS | BIT8 | BIT7);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to enable slow MD= IO mode. Status: %r\n", Status));=0D + GbeMdiReleaseMdio (GbeBar);=0D + return Status;=0D + }=0D +=0D + //=0D + // Read register PHY Version from PHY IDENTIFIER 2 (offset 0x3)=0D + // Bits [9:4] - Device Model Number=0D + // Bits [3:0] - Device Revision Number=0D + //=0D + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, R_PHY_MDI_GENER= EAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision);=0D +=0D + //=0D + // Failed to obtain PHY REV=0D + //=0D + if (*LanPhyRevision =3D=3D 0x0) {=0D + if ((MmioRead32 (GbeBar + R_GBE_MEM_CSR_CTRL) & (B_GBE_MEM_CSR_CTRL_LA= NPHYPC_OVERRIDE | B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL))) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read Phy Rev= ision. Other component tried to initialize GbE and failed.\n"));=0D + Status =3D EFI_DEVICE_ERROR;=0D + goto phy_exit;=0D + }=0D + DEBUG ((DEBUG_INFO, "GbeMdiGetLanPhyRevision failed to read Revision. = Overriding LANPHYPC\n", Status));=0D + //=0D + // Taking over LANPHYPC=0D + // 1. SW signal override - 1st cycle.=0D + // 2. Turn LCD on - 2nd cycle.=0D + //=0D + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL, B_GBE_MEM_CSR_CTRL_LANPHYPC_OVE= RRIDE);=0D + MmioOr32 (GbeBar + R_GBE_MEM_CSR_CTRL, B_GBE_MEM_CSR_CTRL_LANPHYPC_VAL= );=0D +=0D + //=0D + // Poll on LPCD for 100mSec=0D + //=0D + LpcdLoop =3D 101;=0D + while (LpcdLoop > 0) {=0D + if (MmioRead32 (GbeBar + R_GBE_MEM_CSR_CTRL_EXT) & B_GBE_MEM_CSR_CTR= L_EXT_LPCD) {=0D + break;=0D + } else {=0D + LpcdLoop--;=0D + MicroSecondDelay (1000);=0D + }=0D + }=0D +=0D + if (LpcdLoop > 0) {=0D + Delay =3D 100;=0D + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, R_PHY_MDI_G= ENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision);=0D + while (*LanPhyRevision =3D=3D 0 && Delay > 0) {=0D + Status =3D GbeMdiRead (GbeBar, B_PHY_MDI_PHY_ADDRESS_02, R_PHY_MDI= _GENEREAL_REGISTER_03_PHY_IDENTIFIER_2, LanPhyRevision);=0D + if (EFI_ERROR(Status)) {=0D + break;=0D + }=0D + MicroSecondDelay (1000);=0D + Delay --;=0D + }=0D + }=0D + //=0D + // Restore LANPHYPC=0D + // 1. Turn LCD off - 1st cycle.=0D + // 2. Remove SW signal override - 2nd cycle.=0D + //=0D + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_CTRL, (UINT32) ~B_GBE_MEM_CSR_CTRL_L= ANPHYPC_VAL);=0D + MmioAnd32 (GbeBar + R_GBE_MEM_CSR_CTRL, (UINT32) ~B_GBE_MEM_CSR_CTRL_L= ANPHYPC_OVERRIDE);=0D + }=0D +=0D +phy_exit:=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to read Revision = and Model Number from PHY Identifier 2. Status: %r\n", Status));=0D + GbeMdiReleaseMdio (GbeBar);=0D + return Status;=0D + }=0D +=0D + //=0D + // Switch back to normal MDIO frequency access=0D + //=0D + Status =3D GbeMdiWrite (GbeBar, B_PHY_MDI_PHY_ADDRESS_01, MDI_REG_SHIFT= (R_PHY_MDI_PAGE_769_REGISETER_16_CMC), (~B_PHY_MDI_PAGE_769_REGISETER_16_C= MC_MDIO_FREQ_ACCESS) & (BIT13 | BIT8 | BIT7));=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "GbeMdiGetLanPhyRevision failed to disable slow M= DIO mode. Status: %r\n", Status));=0D + }=0D +=0D + GbeMdiReleaseMdio (GbeBar);=0D +=0D + return Status;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/P= eiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf b/Silicon/Intel/TigerlakeSiliconPk= g/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf new file mode 100644 index 0000000000..99a01177f6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Gbe/LibraryPrivate/PeiDxeSm= mGbeMdiLib/PeiDxeSmmGbeMdiLib.inf @@ -0,0 +1,34 @@ +## @file=0D +# Gbe MDI Library.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmGbeMdiLib=0D +FILE_GUID =3D 0360E6F6-892A-4852-BF98-15C0D30D8A48=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D GbeMdiLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +TimerLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +GbeMdiLib.c=0D --=20 2.24.0.windows.2