From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [Patch V2 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers
Date: Thu, 4 Feb 2021 16:48:41 +0800 [thread overview]
Message-ID: <20210204084919.3603-2-heng.luo@intel.com> (raw)
In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Include/Library
* Include/Ppi
* Include/Protocol
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h | 332 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h | 153 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h | 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h | 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h | 342 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h | 720 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h | 149 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h | 27 +++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h | 256 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h | 173 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h | 355 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h | 79 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h | 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h | 113 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h | 290 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h | 34 ++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h | 33 +++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h | 75 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h | 73 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h | 22 ++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h | 301 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
26 files changed, 4199 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h
new file mode 100644
index 0000000000..dbf786ec9a
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h
@@ -0,0 +1,64 @@
+/** @file
+ Header file for Config Block Lib implementation
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _CONFIG_BLOCK_LIB_H_
+#define _CONFIG_BLOCK_LIB_H_
+
+/**
+ Create config block table
+
+ @param[in] TotalSize - Max size to be allocated for the Config Block Table
+ @param[out] ConfigBlockTableAddress - On return, points to a pointer to the beginning of Config Block Table Address
+
+ @retval EFI_INVALID_PARAMETER - Invalid Parameter
+ @retval EFI_OUT_OF_RESOURCES - Out of resources
+ @retval EFI_SUCCESS - Successfully created Config Block Table at ConfigBlockTableAddress
+**/
+EFI_STATUS
+EFIAPI
+CreateConfigBlockTable (
+ IN UINT16 TotalSize,
+ OUT VOID **ConfigBlockTableAddress
+ );
+
+/**
+ Add config block into config block table structure
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add new Config Block or
+ Config Block Offset Table is full and cannot add new Config Block.
+ @retval EFI_SUCCESS - Successfully added Config Block
+**/
+EFI_STATUS
+EFIAPI
+AddConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ OUT VOID **ConfigBlockAddress
+ );
+
+/**
+ Retrieve a specific Config Block data by GUID
+
+ @param[in] ConfigBlockTableAddress - A pointer to the beginning of Config Block Table Address
+ @param[in] ConfigBlockGuid - A pointer to the GUID uses to search specific Config Block
+ @param[out] ConfigBlockAddress - On return, points to a pointer to the beginning of Config Block Address
+
+ @retval EFI_NOT_FOUND - Could not find the Config Block
+ @retval EFI_SUCCESS - Config Block found and return
+**/
+EFI_STATUS
+EFIAPI
+GetConfigBlock (
+ IN VOID *ConfigBlockTableAddress,
+ IN EFI_GUID *ConfigBlockGuid,
+ OUT VOID **ConfigBlockAddress
+ );
+
+#endif // _CONFIG_BLOCK_LIB_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h
new file mode 100644
index 0000000000..564fcccb43
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h
@@ -0,0 +1,332 @@
+/** @file
+ Header file for CPU REGBAR ACCESS library.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _CPU_REGBAR_ACCESS_LIB_H_
+#define _CPU_REGBAR_ACCESS_LIB_H_
+
+#define INVALID_DATA_64 0xFFFFFFFFFFFFFFFF
+#define INVALID_DATA_32 0xFFFFFFFF
+#define INVALID_DATA_16 0xFFFF
+#define INVALID_DATA_8 0xFF
+#define INVALID_PID 0xFF
+
+typedef UINT8 CPU_SB_DEVICE_PID;
+
+/**
+ Read REGBAR register.
+ It returns REGBAR register and size in 8bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT64 REGBAR register value.
+**/
+UINT64
+CpuRegbarRead64 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset
+ );
+
+
+/**
+ Read REGBAR register.
+ It returns REGBAR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 REGBAR register value.
+**/
+UINT32
+CpuRegbarRead32 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset
+ );
+
+/**
+ Read REGBAR register.
+ It returns REGBAR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 REGBAR register value.
+**/
+UINT16
+CpuRegbarRead16 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset
+ );
+
+/**
+ Read REGBAR register.
+ It returns REGBAR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 REGBAR regsiter value
+**/
+UINT8
+CpuRegbarRead8 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 8bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT64 Value written to register
+**/
+UINT64
+CpuRegbarWrite64 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT64 Data
+ );
+
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+CpuRegbarWrite32 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT32 Data
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+CpuRegbarWrite16 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT16 Data
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+CpuRegbarWrite8 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT8 Data
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+CpuRegbarOr32 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT32 OrData
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+CpuRegbarOr16 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT16 OrData
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+CpuRegbarOr8 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT8 OrData
+ );
+
+/**
+ Performs a bitwise AND of a 32-bit data.
+ It programs REGBAR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevice CPU SB Device
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData And Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+CpuRegbarAnd32 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT32 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 16-bit data.
+ It programs REGBAR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevice CPU SB Device
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData And Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+CpuRegbarAnd16 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT16 AndData
+ );
+
+/**
+ Performs a bitwise AND of a 8-bit data.
+ It programs REGBAR register and size in 1byte.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevice CPU SB Device
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData And Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+CpuRegbarAnd8 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT8 AndData
+ );
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+CpuRegbarAndThenOr32 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+CpuRegbarAndThenOr16 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write REGBAR register.
+ It programs REGBAR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] CpuSbDevicePid CPU SB Device Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+CpuRegbarAndThenOr8 (
+ IN CPU_SB_DEVICE_PID CpuSbDevicePid,
+ IN UINT16 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h
new file mode 100644
index 0000000000..c48ea3667f
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h
@@ -0,0 +1,153 @@
+/** @file
+ Prototype of the DxePchHdaNhltLib library.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _DXE_HDA_NHLT_LIB_H_
+#define _DXE_HDA_NHLT_LIB_H_
+
+#include <DxeHdaNhlt.h>
+
+/**
+ Returns pointer to Endpoint ENDPOINT_DESCRIPTOR structure.
+
+ @param[in] *NhltTable Endpoint for which Format address is retrieved
+ @param[in] FormatIndex Index of Format to be retrieved
+
+ @retval Pointer to ENDPOINT_DESCRIPTOR structure with given index
+**/
+ENDPOINT_DESCRIPTOR *
+GetNhltEndpoint (
+ IN CONST NHLT_ACPI_TABLE *NhltTable,
+ IN CONST UINT8 EndpointIndex
+ );
+
+/**
+ Returns pointer to Endpoint Specific Configuration SPECIFIC_CONFIG structure.
+
+ @param[in] *Endpoint Endpoint for which config address is retrieved
+
+ @retval Pointer to SPECIFIC_CONFIG structure with endpoint's capabilities
+**/
+SPECIFIC_CONFIG *
+GetNhltEndpointDeviceCapabilities (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint
+ );
+
+/**
+ Returns pointer to all Formats Configuration FORMATS_CONFIG structure.
+
+ @param[in] *Endpoint Endpoint for which Formats address is retrieved
+
+ @retval Pointer to FORMATS_CONFIG structure
+**/
+FORMATS_CONFIG *
+GetNhltEndpointFormatsConfig (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint
+ );
+
+/**
+ Returns pointer to Format Configuration FORMAT_CONFIG structure.
+
+ @param[in] *Endpoint Endpoint for which Format address is retrieved
+ @param[in] FormatIndex Index of Format to be retrieved
+
+ @retval Pointer to FORMAT_CONFIG structure with given index
+**/
+FORMAT_CONFIG *
+GetNhltEndpointFormat (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint,
+ IN CONST UINT8 FormatIndex
+ );
+
+/**
+ Returns pointer to all Device Information DEVICES_INFO structure.
+
+ @param[in] *Endpoint Endpoint for which DevicesInfo address is retrieved
+
+ @retval Pointer to DEVICES_INFO structure
+**/
+DEVICES_INFO *
+GetNhltEndpointDevicesInfo (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint
+ );
+
+/**
+ Returns pointer to Device Information DEVICES_INFO structure.
+
+ @param[in] *Endpoint Endpoint for which Device Info address is retrieved
+ @param[in] DeviceInfoIndex Index of Device Info to be retrieved
+
+ @retval Pointer to DEVICE_INFO structure with given index
+**/
+DEVICE_INFO *
+GetNhltEndpointDeviceInfo (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint,
+ IN CONST UINT8 DeviceInfoIndex
+ );
+
+
+/**
+ Returns pointer to OED Configuration SPECIFIC_CONFIG structure.
+
+ @param[in] *NhltTable NHLT table for which OED address is retrieved
+
+ @retval Pointer to SPECIFIC_CONFIG structure with NHLT capabilities
+**/
+SPECIFIC_CONFIG *
+GetNhltOedConfig (
+ IN CONST NHLT_ACPI_TABLE *NhltTable
+ );
+
+/**
+ Prints Format configuration.
+
+ @param[in] *Format Format to be printed
+
+ @retval None
+**/
+VOID
+NhltFormatDump (
+ IN CONST FORMAT_CONFIG *Format
+ );
+
+
+/**
+ Prints Endpoint configuration.
+
+ @param[in] *Endpoint Endpoint to be printed
+
+ @retval None
+**/
+VOID
+NhltEndpointDump (
+ IN CONST ENDPOINT_DESCRIPTOR *Endpoint
+ );
+
+/**
+ Prints OED (Offload Engine Driver) configuration.
+
+ @param[in] *OedConfig OED to be printed
+
+ @retval None
+**/
+VOID
+NhltOedConfigDump (
+ IN CONST SPECIFIC_CONFIG *OedConfig
+ );
+
+/**
+ Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offload Engine Driver) Configuration Table).
+
+ @param[in] *NhltTable The NHLT table to print
+
+ @retval None
+**/
+VOID
+NhltAcpiTableDump (
+ IN NHLT_ACPI_TABLE *NhltTable
+ );
+
+#endif // _DXE_HDA_NHLT_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h
new file mode 100644
index 0000000000..6d8466ab7a
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h
@@ -0,0 +1,140 @@
+/** @file
+ Header file for PchEspiLib.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _ESPI_LIB_H_
+#define _ESPI_LIB_H_
+
+/**
+ Checks if there's second slave connected under CS#1
+
+ @retval TRUE There's second slave
+ @retval FALSE There's no second slave
+**/
+BOOLEAN
+IsEspiSecondSlaveSupported (
+ VOID
+ );
+
+/**
+ Checks in slave General Capabilities register if it supports channel with requested number
+
+ @param[in] SlaveId Id of slave to check
+ @param[in] ChannelNumber Number of channel of which to check
+
+ @retval TRUE Channel with requested number is supported by slave device
+ @retval FALSE Channel with requested number is not supported by slave device
+**/
+BOOLEAN
+IsEspiSlaveChannelSupported (
+ UINT8 SlaveId,
+ UINT8 ChannelNumber
+ );
+
+/**
+ Is eSPI enabled in strap.
+
+ @retval TRUE Espi is enabled in strap
+ @retval FALSE Espi is disabled in strap
+**/
+BOOLEAN
+IsEspiEnabled (
+ VOID
+ );
+
+/**
+ Get configuration from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ OUT UINT32 *OutData
+ );
+
+/**
+ Set eSPI slave configuration
+
+ Note: A Set_Configuration must always be followed by a Get_Configuration in order to ensure
+ that the internal state of the eSPI-MC is consistent with the Slave's register settings.
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] SlaveAddress Slave Configuration Register Address
+ @param[in] InData Configuration data to write
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_INVALID_PARAMETER Slave configuration register address exceed maximum allowed
+ @retval EFI_INVALID_PARAMETER Slave configuration register address is not DWord aligned
+ @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7FF has been locked
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveSetConfig (
+ IN UINT32 SlaveId,
+ IN UINT32 SlaveAddress,
+ IN UINT32 InData
+ );
+
+/**
+ Get status from eSPI slave
+
+ @param[in] SlaveId eSPI slave ID
+ @param[out] OutData Configuration data read
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveGetStatus (
+ IN UINT32 SlaveId,
+ OUT UINT16 *OutData
+ );
+
+/**
+ eSPI slave in-band reset
+
+ @param[in] SlaveId eSPI slave ID
+
+ @retval EFI_SUCCESS Operation succeed
+ @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is used in PchLp
+ @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of operation
+**/
+EFI_STATUS
+PchEspiSlaveInBandReset (
+ IN UINT32 SlaveId
+ );
+
+/**
+ eSPI Slave channel reset helper function
+
+ @param[in] SlaveId eSPI slave ID
+ @param[in] ChannelNumber Number of channel to reset
+
+ @retval EFI_SUCCESS Operation succeeded
+ @retval EFI_UNSUPPORTED Slave doesn't support that channel or invalid number specified
+ @retval EFI_TIMEOUT Operation has timeouted
+**/
+EFI_STATUS
+PchEspiSlaveChannelReset (
+ IN UINT8 SlaveId,
+ IN UINT8 ChannelNumber
+ );
+
+#endif // _ESPI_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h
new file mode 100644
index 0000000000..9d72b9ac7c
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h
@@ -0,0 +1,63 @@
+/** @file
+ Header file for GbeLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GBE_LIB_H_
+#define _GBE_LIB_H_
+
+/**
+ Check whether GbE region is valid
+ Check SPI region directly since GbE might be disabled in SW.
+
+ @retval TRUE Gbe Region is valid
+ @retval FALSE Gbe Region is invalid
+**/
+BOOLEAN
+IsGbeRegionValid (
+ VOID
+ );
+
+/**
+ Check whether GBE controller is enabled in the platform.
+
+ @retval TRUE GbE is enabled
+ @retval FALSE GbE is disabled
+**/
+BOOLEAN
+IsGbePresent (
+ VOID
+ );
+
+/**
+ Checks if Gbe is Enabled or Disabled
+
+ @retval BOOLEAN TRUE if device is enabled, FALSE otherwise.
+**/
+BOOLEAN
+IsGbeEnabled (
+ VOID
+ );
+
+/**
+ Returns Gigabit Ethernet PCI Device Number
+
+ @retval GbE device number
+**/
+UINT8
+GbeDevNumber (
+ VOID
+ );
+
+/**
+ Returns Gigabit Ethernet PCI Function Number
+
+ @retval GbE function number
+**/
+UINT8
+GbeFuncNumber (
+ VOID
+ );
+
+#endif // _GBE_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h
new file mode 100644
index 0000000000..88a21efb32
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h
@@ -0,0 +1,342 @@
+/** @file
+ Header file for GpioConfig structure used by GPIO library.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_CONFIG_H_
+#define _GPIO_CONFIG_H_
+
+#pragma pack(push, 1)
+
+///
+/// For any GpioPad usage in code use GPIO_PAD type
+///
+typedef UINT32 GPIO_PAD;
+
+///
+/// GpioPad with additional native function information.
+/// This type is used to represent signal muxing alternatives. Platform will provide such value to
+/// identify muxing selection for given signal on a specific SOC.
+/// Please refer to the board layout
+///
+typedef UINT32 GPIO_NATIVE_PAD;
+
+
+///
+/// For any GpioGroup usage in code use GPIO_GROUP type
+///
+typedef UINT32 GPIO_GROUP;
+
+/**
+ GPIO configuration structure used for pin programming.
+ Structure contains fields that can be used to configure pad.
+**/
+typedef struct {
+ /**
+ Pad Mode
+ Pad can be set as GPIO or one of its native functions.
+ When in native mode setting Direction (except Inversion), OutputState,
+ InterruptConfig, Host Software Pad Ownership and OutputStateLock are unnecessary.
+ Refer to definition of GPIO_PAD_MODE.
+ Refer to EDS for each native mode according to the pad.
+ **/
+ UINT32 PadMode : 5;
+ /**
+ Host Software Pad Ownership
+ Set pad to ACPI mode or GPIO Driver Mode.
+ Refer to definition of GPIO_HOSTSW_OWN.
+ **/
+ UINT32 HostSoftPadOwn : 2;
+ /**
+ GPIO Direction
+ Can choose between In, In with inversion, Out, both In and Out, both In with inversion and out or disabling both.
+ Refer to definition of GPIO_DIRECTION for supported settings.
+ **/
+ UINT32 Direction : 6;
+ /**
+ Output State
+ Set Pad output value.
+ Refer to definition of GPIO_OUTPUT_STATE for supported settings.
+ This setting takes place when output is enabled.
+ **/
+ UINT32 OutputState : 2;
+ /**
+ GPIO Interrupt Configuration
+ Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).
+ This setting is applicable only if GPIO is in GpioMode with input enabled.
+ Refer to definition of GPIO_INT_CONFIG for supported settings.
+ **/
+ UINT32 InterruptConfig : 9;
+ /**
+ GPIO Power Configuration.
+ This setting controls Pad Reset Configuration.
+ Refer to definition of GPIO_RESET_CONFIG for supported settings.
+ **/
+ UINT32 PowerConfig : 8;
+ /**
+ GPIO Electrical Configuration
+ This setting controls pads termination.
+ Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.
+ **/
+ UINT32 ElectricalConfig : 9;
+ /**
+ GPIO Lock Configuration
+ This setting controls pads lock.
+ Refer to definition of GPIO_LOCK_CONFIG for supported settings.
+ **/
+ UINT32 LockConfig : 4;
+ /**
+ Additional GPIO configuration
+ Refer to definition of GPIO_OTHER_CONFIG for supported settings.
+ **/
+ UINT32 OtherSettings : 9;
+
+ UINT32 RsvdBits : 10; ///< Reserved bits for future extension
+} GPIO_CONFIG;
+
+
+typedef enum {
+ GpioHardwareDefault = 0x0 ///< Leave setting unmodified
+} GPIO_HARDWARE_DEFAULT;
+
+/**
+ GPIO Pad Mode
+ Refer to GPIO documentation on native functions available for certain pad.
+ If GPIO is set to one of NativeX modes then following settings are not applicable
+ and can be skipped:
+ - Interrupt related settings
+ - Host Software Ownership
+ - Output/Input enabling/disabling
+ - Output lock
+**/
+typedef enum {
+ GpioPadModeHwDefault = 0x0,
+ GpioPadModeGpio = 0x1,
+ GpioPadModeNative1 = 0x3,
+ GpioPadModeNative2 = 0x5,
+ GpioPadModeNative3 = 0x7,
+ GpioPadModeNative4 = 0x9,
+ GpioPadModeNative5 = 0xB,
+ GpioPadModeNative6 = 0xD,
+ GpioPadModeNative7 = 0xF
+} GPIO_PAD_MODE;
+
+/**
+ Host Software Pad Ownership modes
+ This setting affects GPIO interrupt status registers. Depending on chosen ownership
+ some GPIO Interrupt status register get updated and other masked.
+ Please refer to EDS for HOSTSW_OWN register description.
+**/
+typedef enum {
+ GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified
+ /**
+ Set HOST ownership to ACPI.
+ Use this setting if pad is not going to be used by GPIO OS driver.
+ If GPIO is configured to generate SCI/SMI/NMI then this setting must be
+ used for interrupts to work
+ **/
+ GpioHostOwnAcpi = 0x1,
+ /**
+ Set HOST ownership to GPIO Driver mode.
+ Use this setting only if GPIO pad should be controlled by GPIO OS Driver.
+ GPIO OS Driver will be able to control the pad if appropriate entry in
+ ACPI exists (refer to ACPI specification for GpioIo and GpioInt descriptors)
+ **/
+ GpioHostOwnGpio = 0x3
+} GPIO_HOSTSW_OWN;
+
+///
+/// GPIO Direction
+///
+typedef enum {
+ GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified
+ GpioDirInOut = (0x1 | (0x1 << 3)), ///< Set pad for both output and input
+ GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and input with inversion
+ GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only
+ GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion
+ GpioDirOut = 0x5, ///< Set pad for output only
+ GpioDirNone = 0x7 ///< Disable both output and input
+} GPIO_DIRECTION;
+
+/**
+ GPIO Output State
+ This field is relevant only if output is enabled
+**/
+typedef enum {
+ GpioOutDefault = 0x0, ///< Leave output value unmodified
+ GpioOutLow = 0x1, ///< Set output to low
+ GpioOutHigh = 0x3 ///< Set output to high
+} GPIO_OUTPUT_STATE;
+
+/**
+ GPIO interrupt configuration
+ This setting is applicable only if pad is in GPIO mode and has input enabled.
+ GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/SCI/SMI/NMI)
+ and how it is triggered (edge or level). Refer to PADCFG_DW0 register description in
+ EDS for details on this settings.
+ Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to GpioIntBothEdge
+ to describe an interrupt e.g. GpioIntApic | GpioIntLevel
+ If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this pad.
+ If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this pad.
+ Not all GPIO are capable of generating an SMI or NMI interrupt.
+ When routing GPIO to cause an IOxAPIC interrupt care must be taken, as this
+ interrupt cannot be shared and its IRQn number is not configurable.
+ Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)
+ If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt descriptor
+ exist then use only trigger type setting (from GpioIntLevel to GpioIntBothEdge).
+ This type of GPIO Driver interrupt doesn't have any additional routing setting
+ required to be set by BIOS. Interrupt is handled by GPIO OS Driver.
+**/
+
+typedef enum {
+ GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified
+ GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation
+ GpioIntNmi = 0x3, ///< Enable NMI interrupt only
+ GpioIntSmi = 0x5, ///< Enable SMI interrupt only
+ GpioIntSci = 0x9, ///< Enable SCI interrupt only
+ GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only
+ GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered
+ GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of edge depends on input inversion)
+ GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger
+ GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered
+} GPIO_INT_CONFIG;
+
+#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CONFIG for interrupt source
+#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CONFIG for interrupt type
+
+/**
+ GPIO Power Configuration
+ GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) which will
+ be used to reset certain GPIO settings.
+ Refer to EDS for settings that are controllable by PadRstCfg.
+**/
+typedef enum {
+ GpioResetDefault = 0x00, ///< Leave value of pad reset unmodified
+ /**
+ Resume Reset (RSMRST)
+ GPP: PadRstCfg = 00b = "Powergood"
+ GPD: PadRstCfg = 11b = "Resume Reset"
+ Pad setting will reset on:
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ **/
+ GpioResumeReset = 0x01,
+ /**
+ Host Deep Reset
+ PadRstCfg = 01b = "Deep GPIO Reset"
+ Pad settings will reset on:
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ **/
+ GpioHostDeepReset = 0x03,
+ /**
+ Platform Reset (PLTRST)
+ PadRstCfg = 10b = "GPIO Reset"
+ Pad settings will reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ - G3
+ **/
+ GpioPlatformReset = 0x05,
+ /**
+ Deep Sleep Well Reset (DSW_PWROK)
+ GPP: not applicable
+ GPD: PadRstCfg = 00b = "Powergood"
+ Pad settings will reset on:
+ - G3
+ Pad settings will not reset on:
+ - S3/S4/S5 transition
+ - Warm/Cold/Global reset
+ - DeepSx transition
+ **/
+ GpioDswReset = 0x07
+} GPIO_RESET_CONFIG;
+
+/**
+ GPIO Electrical Configuration
+ Configuration options for GPIO termination setting
+**/
+typedef enum {
+ GpioTermDefault = 0x0, ///< Leave termination setting unmodified
+ GpioTermNone = 0x1, ///< none
+ GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down
+ GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down
+ GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up
+ GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up
+ GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up
+ GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up
+ GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up
+ /**
+ Native function controls pads termination
+ This setting is applicable only to some native modes.
+ Please check EDS to determine which native functionality
+ can control pads termination
+ **/
+ GpioTermNative = 0x1F
+} GPIO_ELECTRICAL_CONFIG;
+
+#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for GPIO_ELECTRICAL_CONFIG for termination value
+
+/**
+ GPIO LockConfiguration
+ Set GPIO configuration lock and output state lock.
+ GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.
+ By default GPIO pads will be locked unless GPIO lib is explicitly
+ informed that certain pad is to be left unlocked.
+ Lock settings reset is in Powergood domain. Care must be taken when using this setting
+ as fields it locks may be reset by a different signal and can be controlled
+ by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library provides
+ functions which allow to unlock a GPIO pad. If possible each GPIO lib function will try to unlock
+ an already locked pad upon request for reconfiguration
+**/
+typedef enum {
+ /**
+ Perform default action
+ - if pad is an GPO, lock configuration but leave output unlocked
+ - if pad is an GPI, lock everything
+ - if pad is in native, lock everything
+**/
+ GpioLockDefault = 0x0,
+ GpioPadConfigUnlock = 0x3, ///< Leave Pad configuration unlocked
+ GpioPadConfigLock = 0x1, ///< Lock Pad configuration
+ GpioOutputStateUnlock = 0xC, ///< Leave Pad output control unlocked
+ GpioPadUnlock = 0xF, ///< Leave both Pad configuration and output control unlocked
+ GpioPadLock = 0x5, ///< Lock both Pad configuration and output control
+ /**
+ Below statuses are used for
+ return from GpioGetPadConfig function
+ **/
+ GpioLockTxLockCfgUnLock = 0x7, ///< Tx State locked, Pad Configuration unlocked
+ GpioLockTxUnLockCfgLock = 0xD ///< Tx State unlocked, Pad Configuration locked
+} GPIO_LOCK_CONFIG;
+
+#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOCK_CONFIG for Pad Configuration Lock
+#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOCK_CONFIG for Pad Output Lock
+
+/**
+ Other GPIO Configuration
+ GPIO_OTHER_CONFIG is used for less often settings and for future extensions
+ Supported settings:
+ - RX raw override to '1' - allows to override input value to '1'
+ This setting is applicable only if in input mode (both in GPIO and native usage).
+ The override takes place at the internal pad state directly from buffer and before the RXINV.
+**/
+typedef enum {
+ GpioRxRaw1Default = 0x0, ///< Use default input override value
+ GpioRxRaw1Dis = 0x1, ///< Don't override input
+ GpioRxRaw1En = 0x3 ///< Override input to '1'
+} GPIO_OTHER_CONFIG;
+
+#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_OTHER_CONFIG for RxRaw1 setting
+
+#pragma pack(pop)
+
+#endif //_GPIO_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h
new file mode 100644
index 0000000000..5b3cf502a0
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h
@@ -0,0 +1,720 @@
+/** @file
+ Header file for GpioLib.
+ All function in this library is available for PEI, DXE, and SMM
+
+ @note: When GPIO pads are owned by ME Firmware, BIOS/host should not
+ attempt to access these GPIO Pads registers, registers value
+ returned in this case will be 0xFF.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_LIB_H_
+#define _GPIO_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+#define GPIO_NAME_LENGTH_MAX 32
+
+typedef struct {
+ GPIO_PAD GpioPad;
+ GPIO_CONFIG GpioConfig;
+} GPIO_INIT_CONFIG;
+
+/**
+ This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG structure.
+ Structure contains fields that can be used to configure each pad.
+ Pad not configured using GPIO_INIT_CONFIG will be left with hardware default values.
+ Separate fields could be set to hardware default if it does not matter, except
+ GpioPad and PadMode.
+ Function will work in most efficient way if pads which belong to the same group are
+ placed in adjacent records of the table.
+ Although function can enable pads for Native mode, such programming is done
+ by reference code when enabling related silicon feature.
+
+ @param[in] NumberofItem Number of GPIO pads to be updated
+ @param[in] GpioInitTableAddress GPIO initialization table
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioConfigurePads (
+ IN UINT32 NumberOfItems,
+ IN GPIO_INIT_CONFIG *GpioInitTableAddress
+ );
+
+//
+// Functions for setting/getting multiple GpioPad settings
+//
+
+/**
+ This procedure will read multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[out] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadConfig (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_CONFIG *GpioData
+ );
+
+/**
+ This procedure will configure multiple GPIO settings
+
+ @param[in] GpioPad GPIO Pad
+ @param[in] GpioData GPIO data structure
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_CONFIG *GpioData
+ );
+
+//
+// Functions for setting/getting single GpioPad properties
+//
+
+/**
+ This procedure will set GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetOutputValue (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO output level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] OutputVal GPIO Output value
+ 0: OutputLow, 1: OutputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetOutputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *OutputVal
+ );
+
+/**
+ This procedure will get GPIO input level
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InputVal GPIO Input value
+ 0: InputLow, 1: InputHigh
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputValue (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InputVal
+ );
+
+/**
+ This procedure will get GPIO IOxAPIC interrupt number
+
+ @param[in] GpioPad GPIO pad
+ @param[out] IrqNum IRQ number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadIoApicIrqNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *IrqNum
+ );
+
+/**
+ This procedure will configure GPIO input inversion
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for GPIO input inversion
+ 0: No input inversion, 1: Invert input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetInputInversion (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 Value
+ );
+
+/**
+ This procedure will get GPIO pad input inversion value
+
+ @param[in] GpioPad GPIO pad
+ @param[out] InvertState GPIO inversion state
+ 0: No input inversion, 1: Inverted input
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetInputInversion (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *InvertState
+ );
+
+/**
+ This procedure will set GPIO interrupt settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Level/Edge
+ use GPIO_INT_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadInterruptConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_INT_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO electrical settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of termination
+ use GPIO_ELECTRICAL_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadElectricalConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_ELECTRICAL_CONFIG Value
+ );
+
+/**
+ This procedure will set GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value for Pad Reset Configuration
+ use GPIO_RESET_CONFIG as argument
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG Value
+ );
+
+/**
+ This procedure will get GPIO Reset settings
+
+ @param[in] GpioPad GPIO pad
+ @param[in] Value Value of Pad Reset Configuration
+ based on GPIO_RESET_CONFIG
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadResetConfig (
+ IN GPIO_PAD GpioPad,
+ IN GPIO_RESET_CONFIG *Value
+ );
+
+/**
+ This procedure will get Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadHostSwOwn Value of Host Software Pad Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadHostSwOwn
+ );
+
+/**
+ This procedure will set Gpio Pad Host Software Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[in] PadHostSwOwn Pad Host Software Owner
+ 0: ACPI Mode, 1: GPIO Driver mode
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioSetHostSwOwnershipForPad (
+ IN GPIO_PAD GpioPad,
+ IN UINT32 PadHostSwOwn
+ );
+
+///
+/// Possible values of Pad Ownership
+/// If Pad is not under Host ownership then GPIO registers
+/// are not accessible by host (e.g. BIOS) and reading them
+/// will return 0xFFs.
+///
+typedef enum {
+ GpioPadOwnHost = 0x0,
+ GpioPadOwnCsme = 0x1,
+ GpioPadOwnIsh = 0x2,
+} GPIO_PAD_OWN;
+
+/**
+ This procedure will get Gpio Pad Ownership
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadOwnVal Value of Pad Ownership
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadOwnership (
+ IN GPIO_PAD GpioPad,
+ OUT GPIO_PAD_OWN *PadOwnVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockRegVal Value of PadCfgLock register
+ Bit position - PadNumber
+ Bit value - 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLock for selected pad
+ 0: NotLocked, 1: Locked
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLock (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLock
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register
+ Bit position - PadNumber
+ Bit value - 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioGetPadCfgLockTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ OUT UINT32 *PadCfgLockTxRegVal
+ );
+
+/**
+ This procedure will check state of Pad Config Tx Lock for selected pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] PadCfgLock PadCfgLockTx for selected pad
+ 0: NotLockedTx, 1: LockedTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetPadCfgLockTx (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *PadCfgLockTx
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlock Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnlock, 1: Unlock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlock
+ );
+
+/**
+ This procedure will clear PadCfgLock for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLock Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLock, 1: Lock
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLock
+ );
+
+/**
+ This procedure will set PadCfgLock for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfg (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pads within one group.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLockTx register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToUnlockTx Bitmask for pads which are going to be unlocked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotUnLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioUnlockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToUnlockTx
+ );
+
+/**
+ This procedure will clear PadCfgLockTx for selected pad.
+ Unlocking a pad will cause an SMI (if enabled)
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioUnlockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pads within one group
+
+ @param[in] Group GPIO group
+ @param[in] DwNum PadCfgLock register number for current group.
+ For group which has less then 32 pads per group DwNum must be 0.
+ @param[in] PadsToLockTx Bitmask for pads which are going to be locked,
+ Bit position - PadNumber
+ Bit value - 0: DoNotLockTx, 1: LockTx
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number
+**/
+EFI_STATUS
+GpioLockPadCfgTxForGroupDw (
+ IN GPIO_GROUP Group,
+ IN UINT32 DwNum,
+ IN UINT32 PadsToLockTx
+ );
+
+/**
+ This procedure will set PadCfgLockTx for selected pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioLockPadCfgTx (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get Group to GPE mapping.
+ It will assume that only first 32 pads can be mapped to GPE.
+ To handle cases where groups have more than 32 pads and higher part of group
+ can be mapped please refer to GpioGetGroupDwToGpeDwX()
+
+ @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0
+ @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1
+ @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetGroupToGpeDwX (
+ IN GPIO_GROUP *GroupToGpeDw0,
+ IN GPIO_GROUP *GroupToGpeDw1,
+ IN GPIO_GROUP *GroupToGpeDw2
+ );
+
+/**
+ This procedure will get Group to GPE mapping. If group has more than 32 bits
+ it is possible to map only single DW of pins (e.g. 0-31, 32-63) because
+ ACPI GPE_DWx register is 32 bits large.
+
+ @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0
+ @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0
+ @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1
+ @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1
+ @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2
+ @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid group or pad number
+**/
+EFI_STATUS
+GpioGetGroupDwToGpeDwX (
+ OUT GPIO_GROUP *GroupToGpeDw0,
+ OUT UINT32 *GroupDwForGpeDw0,
+ OUT GPIO_GROUP *GroupToGpeDw1,
+ OUT UINT32 *GroupDwForGpeDw1,
+ OUT GPIO_GROUP *GroupToGpeDw2,
+ OUT UINT32 *GroupDwForGpeDw2
+ );
+
+/**
+ This procedure will get GPE number for provided GpioPad.
+ PCH allows to configure mapping between GPIO groups and related GPE (GpioSetGroupToGpeDwX())
+ what results in the fact that certain Pad can cause different General Purpose Event. Only three
+ GPIO groups can be mapped to cause unique GPE (1-tier), all others groups will be under one common
+ event (GPE_111 for 2-tier).
+
+ 1-tier:
+ Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used
+ to determine what _LXX ACPI method would be called on event on selected GPIO pad
+
+ 2-tier:
+ Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to 1-tier GPE
+ will be under one master GPE_111 which is linked to _L6F ACPI method. If it is needed to determine
+ what Pad from 2-tier has caused the event, _L6F method should check GPI_GPE_STS and GPI_GPE_EN
+ registers for all GPIO groups not mapped to 1-tier GPE.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpeNumber GPE number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpeNumber (
+ IN GPIO_PAD GpioPad,
+ OUT UINT32 *GpeNumber
+ );
+
+/**
+ This procedure is used to clear SMI STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiSmiSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used by Smi Dispatcher and will clear
+ all GPI SMI Status bits
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioClearAllGpiSmiSts (
+ VOID
+ );
+
+/**
+ This procedure is used to disable all GPI SMI
+
+ @retval EFI_SUCCESS The function completed successfully
+**/
+EFI_STATUS
+GpioDisableAllGpiSmi (
+ VOID
+ );
+
+/**
+ This procedure is used to register GPI SMI dispatch function.
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpiNum GPI number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiSmiNum (
+ IN GPIO_PAD GpioPad,
+ OUT UINTN *GpiNum
+ );
+
+/**
+ This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier architecture
+
+ @param[in] GpioPad GPIO pad
+
+ @retval Data 0 means 1-tier, 1 means 2-tier
+**/
+BOOLEAN
+GpioCheckFor2Tier (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to clear GPE STS for a specified GpioPad
+
+ @param[in] GpioPad GPIO pad
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioClearGpiGpeSts (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure is used to read GPE STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] GpeSts Gpe status for given pad
+ The GpeSts is true if the status register is set for given Pad number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiGpeSts (
+ IN GPIO_PAD GpioPad,
+ OUT BOOLEAN *GpeSts
+ );
+
+/**
+ This procedure is used to get SMI STS for a specified Pad
+
+ @param[in] GpioPad GPIO pad
+ @param[out] SmiSts Smi status for given pad
+ The SmiSts is true if the status register is set for given Pad number
+
+ @retval EFI_SUCCESS The function completed successfully
+ @retval EFI_INVALID_PARAMETER Invalid GpioPad
+**/
+EFI_STATUS
+GpioGetGpiSmiSts (
+ IN GPIO_PAD GpioPad,
+ OUT BOOLEAN *SmiSts
+ );
+
+/**
+ Generates GPIO name from GpioPad
+
+ @param[in] GpioPad GpioPad
+ @param[out] GpioNameBuffer Caller allocated buffer for GPIO name of GPIO_NAME_LENGTH_MAX size
+ @param[in] GpioNameBufferSize Size of the buffer
+
+ @retval CHAR8* Pointer to the GPIO name
+**/
+CHAR8*
+GpioGetPadName (
+ IN GPIO_PAD GpioPad,
+ OUT CHAR8* GpioNameBuffer,
+ IN UINT32 GpioNameBufferSize
+ );
+
+/**
+ Generates GPIO group name from GroupIndex
+
+ @param[in] GroupIndex Gpio GroupIndex
+
+ @retval CHAR8* Pointer to the GPIO group name
+**/
+CONST
+CHAR8*
+GpioGetGroupName (
+ IN UINT32 GroupIndex
+ );
+
+#endif // _GPIO_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h
new file mode 100644
index 0000000000..b09600dd30
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h
@@ -0,0 +1,149 @@
+/** @file
+ Header file for GpioLib for native and Si specific usage.
+ All function in this library is available for PEI, DXE, and SMM,
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GPIO_NATIVE_LIB_H_
+#define _GPIO_NATIVE_LIB_H_
+
+#include <Library/GpioConfig.h>
+
+/**
+ This procedure will get number of pads for certain GPIO group
+
+ @param[in] Group GPIO group number
+
+ @retval Value Pad number for group
+ If illegal group number then return 0
+**/
+UINT32
+GpioGetPadPerGroup (
+ IN GPIO_GROUP Group
+ );
+
+/**
+ This procedure will get number of groups
+
+ @param[in] none
+
+ @retval Value Group number
+**/
+UINT32
+GpioGetNumberOfGroups (
+ VOID
+ );
+/**
+ This procedure will get lowest group
+
+ @param[in] none
+
+ @retval Value Lowest Group
+**/
+GPIO_GROUP
+GpioGetLowestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get highest group
+
+ @param[in] none
+
+ @retval Value Highest Group
+**/
+GPIO_GROUP
+GpioGetHighestGroup (
+ VOID
+ );
+
+/**
+ This procedure will get group
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from GpioPad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will get group index (0 based) from group
+
+ @param[in] GpioGroup Gpio Group
+
+ @retval Value Group Index
+**/
+UINT32
+GpioGetGroupIndexFromGroup (
+ IN GPIO_GROUP GpioGroup
+ );
+
+/**
+ This procedure will get group from group index (0 based)
+
+ @param[in] GroupIndex Group Index
+
+ @retval GpioGroup Gpio Group
+**/
+GPIO_GROUP
+GpioGetGroupFromGroupIndex (
+ IN UINT32 GroupIndex
+ );
+
+/**
+ This procedure will get pad number (0 based) from Gpio Pad
+
+ @param[in] GpioPad Gpio Pad
+
+ @retval Value Pad Number
+**/
+UINT32
+GpioGetPadNumberFromGpioPad (
+ IN GPIO_PAD GpioPad
+ );
+
+/**
+ This procedure will return GpioPad from Group and PadNumber
+
+ @param[in] Group GPIO group
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupAndPadNumber (
+ IN GPIO_GROUP Group,
+ IN UINT32 PadNumber
+ );
+
+/**
+ This procedure will return GpioPad from GroupIndex and PadNumber
+
+ @param[in] GroupIndex GPIO GroupIndex
+ @param[in] PadNumber GPIO PadNumber
+
+ @retval GpioPad GpioPad
+**/
+GPIO_PAD
+GpioGetGpioPadFromGroupIndexAndPadNumber (
+ IN UINT32 GroupIndex,
+ IN UINT32 PadNumber
+ );
+
+#endif // _GPIO_NATIVE_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h
new file mode 100644
index 0000000000..a53887ffcb
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h
@@ -0,0 +1,27 @@
+/** @file
+ Get Pci Express address library implementation.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _MM_PCI_LIB_H_
+#define _MM_PCI_LIB_H_
+
+/**
+ This procedure will get PCIE address
+
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+
+ @retval PCIE address
+**/
+UINTN
+EFIAPI
+MmPciBase (
+ IN UINT32 Bus,
+ IN UINT32 Device,
+ IN UINT32 Function
+);
+
+#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h
new file mode 100644
index 0000000000..3c46029b7f
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h
@@ -0,0 +1,123 @@
+/** @file
+ Header file for PchPcieRpLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIERP_LIB_H_
+#define _PCH_PCIERP_LIB_H_
+
+#include <Library/PchPcrLib.h>
+
+/**
+ PCIe controller bifurcation configuration.
+**/
+typedef enum {
+ PcieBifurcationDefault = 0,
+ PcieBifurcation4x1,
+ PcieBifurcation1x2_2x1,
+ PcieBifurcation2x2,
+ PcieBifurcation1x4,
+ PcieBifurcation4x2,
+ PcieBifurcation1x4_2x2,
+ PcieBifurcation2x2_1x4,
+ PcieBifurcation2x4,
+ PcieBifurcation1x8,
+ PcieBifurcationUnknown,
+ PcieBifurcationMax
+} PCIE_BIFURCATION_CONFIG;
+
+/**
+ This function returns PID according to PCIe controller index
+
+ @param[in] ControllerIndex PCIe controller index
+
+ @retval PCH_SBI_PID Returns PID for SBI Access
+**/
+PCH_SBI_PID
+PchGetPcieControllerSbiPid (
+ IN UINT32 ControllerIndex
+ );
+
+/**
+ This function returns PID according to Root Port Number
+
+ @param[in] RpIndex Root Port Index (0-based)
+
+ @retval PCH_SBI_PID Returns PID for SBI Access
+**/
+PCH_SBI_PID
+GetRpSbiPid (
+ IN UINTN RpIndex
+ );
+
+/**
+ Get Pch Pcie Root Port Device and Function Number by Root Port physical Number
+
+ @param[in] RpNumber Root port physical number. (0-based)
+ @param[out] RpDev Return corresponding root port device number.
+ @param[out] RpFun Return corresponding root port function number.
+
+ @retval EFI_SUCCESS
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpDevFun (
+ IN UINTN RpNumber,
+ OUT UINTN *RpDev,
+ OUT UINTN *RpFun
+ );
+
+/**
+ Get Root Port physical Number by Pch Pcie Root Port Device and Function Number
+
+ @param[in] RpDev Root port device number.
+ @param[in] RpFun Root port function number.
+ @param[out] RpNumber Return corresponding physical Root Port index (0-based)
+
+ @retval EFI_SUCCESS Physical root port is retrieved
+ @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid
+ @retval EFI_UNSUPPORTED Root port device and function is not assigned to any physical root port
+**/
+EFI_STATUS
+EFIAPI
+GetPchPcieRpNumber (
+ IN UINTN RpDev,
+ IN UINTN RpFun,
+ OUT UINTN *RpNumber
+ );
+
+/**
+ Gets pci segment base address of PCIe root port.
+
+ @param RpIndex Root Port Index (0 based)
+ @return PCIe port base address.
+**/
+UINT64
+PchPcieBase (
+ IN UINT32 RpIndex
+ );
+
+/**
+ Determines whether L0s is supported on current stepping.
+
+ @return TRUE if L0s is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieL0sSupported (
+ VOID
+ );
+
+/**
+ Some early PCH steppings require Native ASPM to be disabled due to hardware issues:
+ - RxL0s exit causes recovery
+ - Disabling PCIe L0s capability disables L1
+ Use this function to determine affected steppings.
+
+ @return TRUE if Native ASPM is supported, FALSE otherwise
+**/
+BOOLEAN
+PchIsPcieNativeAspmSupported (
+ VOID
+ );
+#endif // _PCH_PCIERP_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h
new file mode 100644
index 0000000000..f46c3da0e1
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h
@@ -0,0 +1,256 @@
+/** @file
+ Header file for PchPcrLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCR_LIB_H_
+#define _PCH_PCR_LIB_H_
+
+#include <PchReservedResources.h>
+
+/**
+ Definition for PCR address
+ The PCR address is used to the PCR MMIO programming
+
+ SBREG_BAR_20BITADDRESS is configured by SoC
+
+ SBREG_BAR_20BITADDRESS=1, the format has included 16b addressing.
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+
+ SBREG_BAR_20BITADDRESS=0
+ +---------------------------------------------------------------------------------------------+
+ | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] | Addr[1:0] |
+ +----------------+-----------------------+-----------------+----------------------------------+
+ | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegister[15:2] |
+ +---------------------------------------------------------------------------------------------+
+**/
+#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0xFFFF))
+
+/**
+ PCH PCR boot script accessing macro
+ Those macros are only available for DXE phase.
+**/
+#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \
+ S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), Count, Buffer); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd) \
+ S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), DataOr, DataAnd); \
+
+#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \
+ S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), BitMask, BitValue, 1, 1);
+
+typedef UINT8 PCH_SBI_PID;
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT32 PCR register value.
+**/
+UINT32
+PchPcrRead32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT16 PCR register value.
+**/
+UINT16
+PchPcrRead16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Read PCR register.
+ It returns PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of this Port ID
+
+ @retval UINT8 PCR register value
+**/
+UINT8
+PchPcrRead8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+**/
+UINT32
+PchPcrWrite32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+**/
+UINT16
+PchPcrWrite16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] Data Input Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+**/
+UINT8
+PchPcrWrite8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 InData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value written to register
+
+**/
+UINT32
+PchPcrAndThenOr32 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register and read back.
+ The read back ensures the PCR cycle is completed before next operation.
+ It programs PCR register and size in 4bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT32 Value read back from the register
+**/
+UINT32
+PchPcrAndThenOr32WithReadback (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT32 AndData,
+ IN UINT32 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 2bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT16 Value written to register
+
+**/
+UINT16
+PchPcrAndThenOr16 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT16 AndData,
+ IN UINT16 OrData
+ );
+
+/**
+ Write PCR register.
+ It programs PCR register and size in 1bytes.
+ The Offset should not exceed 0xFFFF and must be aligned with size.
+
+ @param[in] Pid Port ID
+ @param[in] Offset Register offset of Port ID.
+ @param[in] AndData AND Data. Must be the same size as Size parameter.
+ @param[in] OrData OR Data. Must be the same size as Size parameter.
+
+ @retval UINT8 Value written to register
+
+**/
+UINT8
+PchPcrAndThenOr8 (
+ IN PCH_SBI_PID Pid,
+ IN UINT32 Offset,
+ IN UINT8 AndData,
+ IN UINT8 OrData
+ );
+
+
+typedef enum {
+ PchIpDmi = 1,
+ PchIpIclk,
+} PCH_IP_PID_ENUM;
+
+#define PCH_INVALID_PID 0
+
+/**
+ Get PCH IP PID number
+
+ @param[in] IpEnum PCH IP in PCH_IP_PID_ENUM
+
+ @retval 0 PID of this IP is not supported
+ !0 PID of the IP.
+**/
+PCH_SBI_PID
+PchPcrGetPid (
+ PCH_IP_PID_ENUM IpEnum
+ );
+
+#endif // _PCH_PCR_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h
new file mode 100644
index 0000000000..8ab20f0db7
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h
@@ -0,0 +1,173 @@
+/** @file
+ Header file for PCI Express helpers base library
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCIE_HELPER_LIB_H_
+#define _PCIE_HELPER_LIB_H_
+
+#include <PcieRegs.h>
+#include <Library/PciSegmentLib.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/BaseLib.h>
+#include <Library/DebugLib.h>
+#include <IndustryStandard/Pci.h>
+
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 = PCI Power Management Interface
+ 0x04 = Slot Identification
+ 0x05 = MSI Capability
+ 0x10 = PCI Express Capability
+
+ @param[in] DeviceBase device's base address
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieBaseFindCapId (
+ IN UINT64 DeviceBase,
+ IN UINT8 CapId
+ );
+
+/**
+ Find the Offset to a given Capabilities ID
+ CAPID list:
+ 0x01 = PCI Power Management Interface
+ 0x04 = Slot Identification
+ 0x05 = MSI Capability
+ 0x10 = PCI Express Capability
+
+ @param[in] Segment Pci Segment Number
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT8
+PcieFindCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT8 CapId
+ );
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 = Advanced Error Reporting Capability
+ 0x0002 = Virtual Channel Capability
+ 0x0003 = Device Serial Number Capability
+ 0x0004 = Power Budgeting Capability
+
+ @param[in] DeviceBase device base address
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found, this includes situation where device doesn't exist
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieBaseFindExtendedCapId (
+ IN UINT64 DeviceBase,
+ IN UINT16 CapId
+ );
+
+/**
+ Search and return the offset of desired Pci Express Capability ID
+ CAPID list:
+ 0x0001 = Advanced Error Rreporting Capability
+ 0x0002 = Virtual Channel Capability
+ 0x0003 = Device Serial Number Capability
+ 0x0004 = Power Budgeting Capability
+
+ @param[in] Segment Pci Segment Number
+ @param[in] Bus Pci Bus Number
+ @param[in] Device Pci Device Number
+ @param[in] Function Pci Function Number
+ @param[in] CapId Extended CAPID to search for
+
+ @retval 0 CAPID not found
+ @retval Other CAPID found, Offset of desired CAPID
+**/
+UINT16
+PcieFindExtendedCapId (
+ IN UINT8 Segment,
+ IN UINT8 Bus,
+ IN UINT8 Device,
+ IN UINT8 Function,
+ IN UINT16 CapId
+ );
+
+/*
+ Checks device's Slot Clock Configuration
+
+ @param[in] Base device's base address
+ @param[in] PcieCapOffset devices Pci express capability list register offset
+
+ @retval TRUE when device device uses slot clock, FALSE otherwise
+*/
+BOOLEAN
+GetScc (
+ UINT64 Base,
+ UINT8 PcieCapOffset
+ );
+
+/*
+ Sets Common Clock Configuration bit for given device.
+ @param[in] PcieCapOffset devices Pci express capability list register offset
+ @param[in] Base device's base address
+*/
+VOID
+EnableCcc (
+ UINT64 Base,
+ UINT8 PcieCapOffset
+ );
+
+/*
+ Retrains link behind given device.
+ It only makes sense to call it for downstream ports.
+ If called for upstream port nothing will happen, it won't enter infinite loop.
+
+ @param[in] Base device's base address
+ @param[in] PcieCapOffset devices Pci express capability list register offset
+ @param[boolean] WaitUnitlDone when TRUE, function waits until link has retrained
+*/
+VOID
+RetrainLink (
+ UINT64 Base,
+ UINT8 PcieCapOffset,
+ BOOLEAN WaitUntilDone
+ );
+
+/*
+ Checks if device at given address exists
+
+ @param[in] Base device's base address
+
+ @retval TRUE when device exists; FALSE otherwise
+*/
+BOOLEAN
+IsDevicePresent (
+ UINT64 Base
+ );
+
+/*
+ Checks if device is a multifunction device
+
+ @param[in] Base device's base address
+
+ @retval TRUE if multifunction; FALSE otherwise
+*/
+BOOLEAN
+IsMultifunctionDevice (
+ UINT64 Base
+ );
+#endif // _PCIE_HELPER_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h
new file mode 100644
index 0000000000..0b8ad7a182
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h
@@ -0,0 +1,355 @@
+/** @file
+ Header file for PmcLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PMC_LIB_H_
+#define _PMC_LIB_H_
+
+#pragma pack(1)
+
+typedef enum {
+ PmcTPch25_10us = 0,
+ PmcTPch25_100us,
+ PmcTPch25_1ms,
+ PmcTPch25_10ms,
+} PMC_TPCH25_TIMING;
+
+typedef enum {
+ PmcNotASleepState,
+ PmcInS0State,
+ PmcS1SleepState,
+ PmcS2SleepState,
+ PmcS3SleepState,
+ PmcS4SleepState,
+ PmcS5SleepState,
+ PmcUndefinedState,
+} PMC_SLEEP_STATE;
+
+typedef struct {
+ UINT32 Buf0;
+ UINT32 Buf1;
+ UINT32 Buf2;
+ UINT32 Buf3;
+} PMC_IPC_COMMAND_BUFFER;
+
+//
+// Structure to Check different attributes for CrashLog supported by PMC.
+//
+typedef union {
+ struct {
+ UINT32 Avail : 1; ///< CrashLog feature availability bit
+ UINT32 Dis : 1; ///< CrasLog Disable bit
+ UINT32 Rsvd : 2; ///< Reserved
+ UINT32 Size : 12; ///< CrasLog data size. (If it is zero, use default size 0xC00)
+ UINT32 BaseOffset : 16; ///< Start offset of CrashLog in PMC SSRAM
+ } Bits;
+ struct {
+ UINT32 Avail : 1; ///< CrashLog feature availability bit
+ UINT32 Dis : 1; ///< CrasLog Disable bit
+ UINT32 Mech : 2; ///< CrashLog mechanism
+ UINT32 ManuTri : 1; ///< Manul trigger command.
+ UINT32 Clr : 1; ///< Clear Command
+ UINT32 AllReset : 1; ///< Trigger on all reset command
+ UINT32 ReArm : 1; ///< Re-arm command
+ UINT32 Rsvd : 20; ///< Pch Specific reserved
+ UINT32 CrashLogReq: 1; ///< Crash log requestor flow
+ UINT32 TriArmedSts: 1; ///< Trigger armed status, re-arm indication bit.
+ UINT32 TriAllReset: 1; ///< Trigger on all resets status
+ UINT32 CrashDisSts: 1; ///< Crash log disabled status
+ UINT32 PchRsvd : 16; ///< Pch Specific reserved
+ UINT32 DesTableOffset: 16; ///< Descriptor Table offset
+ } Bits64;
+ UINT32 Uint32;
+ UINT64 Uint64;
+} PMC_IPC_DISCOVERY_BUF;
+
+typedef union {
+ struct {
+ UINT32 Offset : 16;
+ UINT32 Size : 16;
+ } Info;
+ UINT32 Uint32;
+} PMC_CRASHLOG_RECORDS;
+
+typedef struct PmcCrashLogLink {
+ PMC_CRASHLOG_RECORDS Record;
+ UINT64 AllocateAddress;
+ struct PmcCrashLogLink *Next;
+} PMC_CRASHLOG_LINK;
+
+#pragma pack()
+
+/**
+ Get PCH ACPI base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT16
+PmcGetAcpiBase (
+ VOID
+ );
+
+/**
+ Get PCH PWRM base address.
+
+ @retval Address Address of PWRM base address.
+**/
+UINT32
+PmcGetPwrmBase (
+ VOID
+ );
+
+/**
+ This function sets tPCH25 timing
+
+ @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms)
+**/
+VOID
+PmcSetTPch25Timing (
+ IN PMC_TPCH25_TIMING TimingValue
+ );
+
+/**
+ This function checks if RTC Power Failure occurred by
+ reading RTC_PWR_FLR bit
+
+ @retval RTC Power Failure state: TRUE - Battery is always present.
+ FALSE - CMOS is cleared.
+**/
+BOOLEAN
+PmcIsRtcBatteryGood (
+ VOID
+ );
+
+/**
+ This function checks if Power Failure occurred by
+ reading PWR_FLR bit
+
+ @retval Power Failure state
+**/
+BOOLEAN
+PmcIsPowerFailureDetected (
+ VOID
+ );
+
+/**
+ This function checks if Power Failure occurred by
+ reading SUS_PWR_FLR bit
+
+ @retval SUS Power Failure state
+**/
+BOOLEAN
+PmcIsSusPowerFailureDetected (
+ VOID
+ );
+
+/**
+ This function clears Power Failure status (PWR_FLR)
+**/
+VOID
+PmcClearPowerFailureStatus (
+ VOID
+ );
+
+/**
+ This function clears Global Reset status (GBL_RST_STS)
+**/
+VOID
+PmcClearGlobalResetStatus (
+ VOID
+ );
+
+/**
+ This function clears Host Reset status (HOST_RST_STS)
+**/
+VOID
+PmcClearHostResetStatus (
+ VOID
+ );
+
+/**
+ This function clears SUS Power Failure status (SUS_PWR_FLR)
+**/
+VOID
+PmcClearSusPowerFailureStatus (
+ VOID
+ );
+
+/**
+ This function sets state to which platform will get after power is reapplied
+
+ @param[in] PowerStateAfterG3 0: S0 state (boot)
+ 1: S5/S4 State
+**/
+VOID
+PmcSetPlatformStateAfterPowerFailure (
+ IN UINT8 PowerStateAfterG3
+ );
+
+/**
+ This function enables Power Button SMI
+**/
+VOID
+PmcEnablePowerButtonSmi (
+ VOID
+ );
+
+/**
+ This function disables Power Button SMI
+**/
+VOID
+PmcDisablePowerButtonSmi (
+ VOID
+ );
+
+/**
+ This function reads PM Timer Count driven by 3.579545 MHz clock
+
+ @retval PM Timer Count
+**/
+UINT32
+PmcGetTimerCount (
+ VOID
+ );
+
+/**
+ Get Sleep Type that platform has waken from
+
+ @retval SleepType Sleep Type
+**/
+PMC_SLEEP_STATE
+PmcGetSleepTypeAfterWake (
+ VOID
+ );
+
+/**
+ Clear PMC Wake Status
+**/
+VOID
+PmcClearWakeStatus (
+ VOID
+ );
+
+/**
+ Configure sleep state
+
+ @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE
+**/
+VOID
+PmcSetSleepState (
+ PMC_SLEEP_STATE SleepState
+ );
+
+/**
+ Check if platform boots after shutdown caused by power button override event
+
+ @retval TRUE Power Button Override occurred in last system boot
+ @retval FALSE Power Button Override didn't occur
+**/
+BOOLEAN
+PmcIsPowerButtonOverrideDetected (
+ VOID
+ );
+
+/**
+ This function will set the DISB - DRAM Initialization Scratchpad Bit.
+**/
+VOID
+PmcSetDramInitScratchpad (
+ VOID
+ );
+
+/**
+ Check global SMI enable is set
+
+ @retval TRUE Global SMI enable is set
+ FALSE Global SMI enable is not set
+**/
+BOOLEAN
+PmcIsGblSmiEn (
+ VOID
+ );
+
+/**
+ This function checks if SMI Lock is set
+
+ @retval SMI Lock state
+**/
+BOOLEAN
+PmcIsSmiLockSet (
+ VOID
+ );
+
+/**
+ This function checks if Debug Mode is locked
+
+ @retval Debug Mode Lock state
+**/
+BOOLEAN
+PmcIsDebugModeLocked (
+ VOID
+ );
+
+/**
+ Check TCO second timeout status.
+
+ @retval TRUE TCO reboot happened.
+ @retval FALSE TCO reboot didn't happen.
+**/
+BOOLEAN
+TcoSecondToHappened (
+ VOID
+ );
+
+/**
+ This function clears the Second TO status bit
+**/
+VOID
+TcoClearSecondToStatus (
+ VOID
+ );
+
+/**
+ Check TCO SMI ENABLE is locked
+
+ @retval TRUE TCO SMI ENABLE is locked
+ FALSE TCO SMI ENABLE is not locked
+**/
+BOOLEAN
+TcoIsSmiLock (
+ VOID
+ );
+
+/**
+ Check if user wants to turn off in PEI phase
+
+**/
+VOID
+CheckPowerOffNow(
+ VOID
+ );
+
+
+/**
+ Clear any SMI status or wake status left from boot.
+**/
+VOID
+ClearSmiAndWake (
+ VOID
+ );
+
+/**
+ Function to check if Dirty Warm Reset occurs
+ (Global Reset has been converted to Host Reset)
+
+ @reval TRUE DWR occurs
+ @reval FALSE Normal boot flow
+**/
+BOOLEAN
+PmcIsDwrBootMode (
+ VOID
+ );
+
+#endif // _PMC_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h
new file mode 100644
index 0000000000..9ab55ad9d0
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h
@@ -0,0 +1,79 @@
+/** @file
+ System reset Library Services. This library class defines a set of
+ methods that reset the whole system.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef __RESET_SYSTEM_LIB_H__
+#define __RESET_SYSTEM_LIB_H__
+
+/**
+ This function causes a system-wide reset (cold reset), in which
+ all circuitry within the system returns to its initial state. This type of reset
+ is asynchronous to system operation and operates without regard to
+ cycle boundaries.
+
+ If this function returns, it means that the system does not support cold reset.
+**/
+VOID
+EFIAPI
+ResetCold (
+ VOID
+ );
+
+/**
+ This function causes a system-wide initialization (warm reset), in which all processors
+ are set to their initial state. Pending cycles are not corrupted.
+
+ If this function returns, it means that the system does not support warm reset.
+**/
+VOID
+EFIAPI
+ResetWarm (
+ VOID
+ );
+
+/**
+ This function causes the system to enter a power state equivalent
+ to the ACPI G2/S5 or G3 states.
+
+ If this function returns, it means that the system does not support shutdown reset.
+**/
+VOID
+EFIAPI
+ResetShutdown (
+ VOID
+ );
+
+/**
+ This function causes the system to enter S3 and then wake up immediately.
+
+ If this function returns, it means that the system does not support S3 feature.
+**/
+VOID
+EFIAPI
+EnterS3WithImmediateWake (
+ VOID
+ );
+
+/**
+ This function causes a systemwide reset. The exact type of the reset is
+ defined by the EFI_GUID that follows the Null-terminated Unicode string passed
+ into ResetData. If the platform does not recognize the EFI_GUID in ResetData
+ the platform must pick a supported reset type to perform.The platform may
+ optionally log the parameters from any non-normal reset that occurs.
+
+ @param[in] DataSize The size, in bytes, of ResetData.
+ @param[in] ResetData The data buffer starts with a Null-terminated string,
+ followed by the EFI_GUID.
+**/
+VOID
+EFIAPI
+ResetPlatformSpecific (
+ IN UINTN DataSize,
+ IN VOID *ResetData
+ );
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h
new file mode 100644
index 0000000000..bc1555ed19
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h
@@ -0,0 +1,112 @@
+/** @file
+ Header file for SataLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SATA_LIB_H_
+#define _SATA_LIB_H_
+
+#define SATA_1_CONTROLLER_INDEX 0
+#define SATA_2_CONTROLLER_INDEX 1
+#define SATA_3_CONTROLLER_INDEX 2
+
+/**
+ Get Maximum Sata Port Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Maximum Sata Port Number
+**/
+UINT8
+MaxSataPortNum (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets Maximum Sata Controller Number
+
+ @retval Maximum Sata Controller Number
+**/
+UINT8
+MaxSataControllerNum (
+ VOID
+ );
+
+/**
+ Get SATA controller's Port Present Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval Port Present Status
+**/
+UINT8
+GetSataPortPresentStatus (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Get SATA controller Function Disable Status
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval 0 SATA Controller is not Function Disabled
+ @retval 1 SATA Controller is Function Disabled
+**/
+BOOLEAN
+SataControllerFunctionDisableStatus (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Get SATA controller ABAR size
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller ABAR size
+**/
+UINT32
+GetSataAbarSize (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Get SATA controller AHCI base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller AHCI base address
+**/
+UINT32
+GetSataAhciBase (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Check if SATA controller supports RST remapping
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval TRUE Controller supports remapping
+ @retval FALSE Controller does not support remapping
+**/
+BOOLEAN
+IsRemappingSupportedOnSata (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Checks if SoC supports the SATA PGD power down on given
+ SATA controller.
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval TRUE SATA PGD power down supported
+ @retval FALSE SATA PGD power down not supported
+**/
+BOOLEAN
+IsSataPowerGatingSupported (
+ IN UINT32 SataCtrlIndex
+ );
+
+#endif // _SATA_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h
new file mode 100644
index 0000000000..3c8aae6ac2
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h
@@ -0,0 +1,113 @@
+/** @file
+ Header file for Serial Io Common Lib
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SERIAL_IO_ACCESS_LIB_H_
+#define _SERIAL_IO_ACCESS_LIB_H_
+
+/**
+ Returns BAR0
+
+ @param[in] PciCfgBase Pci Config Base
+
+ @retval 64bit MMIO BAR Address
+**/
+UINT64
+GetSerialIoBar (
+ IN UINT64 PciCfgBase
+ );
+
+/**
+ Returns I2C Pci Config Space
+
+ @param[in] I2cNumber I2C Number
+
+ @retval I2C Pci Config Space Address
+**/
+UINT64
+GetSerialIoI2cPciCfg (
+ IN UINT8 I2cNumber
+ );
+
+/**
+ Returns SPI Pci Config Space
+
+ @param[in] SpiNumber SPI Number
+
+ @retval SPI Pci Config Space Address
+**/
+UINT64
+GetSerialIoSpiPciCfg (
+ IN UINT8 SpiNumber
+ );
+
+/**
+ Returns UART Pci Config Space
+
+ @param[in] UartNumber UART Number
+
+ @retval UART Pci Config Space Address
+**/
+UINT64
+GetSerialIoUartPciCfg (
+ IN UINT8 UartNumber
+ );
+
+/**
+ Checks if Device with given PciDeviceId is one of SerialIo I2C controllers
+ If yes, its number is returned through I2cIndex parameter, otherwise I2cIndex is not updated
+
+ @param[in] PciDevId Device ID
+ @param[out] I2cNumber Number of SerialIo I2C controller
+
+ @retval TRUE yes it is a SerialIo I2C controller
+ @retval FALSE no it isn't a SerialIo I2C controller
+**/
+BOOLEAN
+IsSerialIoI2cDeviceId (
+ IN UINT16 PciDevId,
+ OUT UINT8 *I2cNumber
+ );
+
+/**
+ Checks if I2c is Function 0 Enabled
+
+ @param[in] I2cIndex Number of the SerialIo I2C controller
+
+ @retval TRUE Enabled
+ @retval FALSE Disabled
+**/
+BOOLEAN
+IsSerialIoI2cFunction0Enabled (
+ IN UINT8 I2cIndex
+ );
+
+/**
+ Checks if Uart is Function 0 Enabled
+
+ @param[in] UartIndex Number of the SerialIo Uart controller
+
+ @retval TRUE Enabled
+ @retval FALSE Disabled
+**/
+BOOLEAN
+IsSerialIoUartFunction0Enabled (
+ IN UINT8 UartIndex
+ );
+
+/**
+ Checks if Spi is Function 0 Enabled
+
+ @param[in] SpiIndex Number of the SerialIo Spi controller
+
+ @retval TRUE Enabled
+ @retval FALSE Disabled
+**/
+BOOLEAN
+IsSerialIoSpiFunction0Enabled (
+ IN UINT8 SpiIndex
+ );
+
+#endif // _SERIAL_IO_ACCESS_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
new file mode 100644
index 0000000000..7732ccf59e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h
@@ -0,0 +1,56 @@
+/** @file
+ Prototype of the SiConfigBlockLib library.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_CONFIG_BLOCK_LIB_H_
+#define _SI_CONFIG_BLOCK_LIB_H_
+
+
+typedef
+VOID
+(*LOAD_DEFAULT_FUNCTION) (
+ IN VOID *ConfigBlockPointer
+ );
+
+typedef struct {
+ EFI_GUID *Guid;
+ UINT16 Size;
+ UINT8 Revision;
+ LOAD_DEFAULT_FUNCTION LoadDefault;
+} COMPONENT_BLOCK_ENTRY;
+
+/**
+ GetComponentConfigBlockTotalSize get config block table total size.
+
+ @param[in] ComponentBlocks Component blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval Size of config block table
+**/
+UINT16
+EFIAPI
+GetComponentConfigBlockTotalSize (
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+
+/**
+ AddComponentConfigBlocks add all config blocks.
+
+ @param[in] ConfigBlockTableAddress The pointer to add config blocks
+ @param[in] ComponentBlocks Config blocks array
+ @param[in] TotalBlockCount Number of blocks
+
+ @retval EFI_SUCCESS The policy default is initialized.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer
+**/
+EFI_STATUS
+EFIAPI
+AddComponentConfigBlocks (
+ IN VOID *ConfigBlockTableAddress,
+ IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,
+ IN UINT16 TotalBlockCount
+ );
+#endif // _SI_CONFIG_BLOCK_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h
new file mode 100644
index 0000000000..50f9e048b3
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h
@@ -0,0 +1,290 @@
+/** @file
+ SPI library header for abstraction of SPI HW registers accesses
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SPI_ACCESS_LIB_H_
+#define _SPI_ACCESS_LIB_H_
+
+/**
+ Returns SPI PCI Config Space base address
+
+ @retval UINT64 SPI Config Space base address
+**/
+UINT64
+SpiGetPciCfgAddress (
+ VOID
+ );
+
+/**
+ Returns SPI BAR0 value
+
+ @retval UINT32 PCH SPI BAR0 value
+**/
+UINT32
+SpiGetBar0 (
+ VOID
+ );
+
+/**
+ Returns SPI Device number
+
+ @retval UINT8 PCH SPI Device number
+**/
+UINT8
+SpiDeviceNumber (
+ VOID
+ );
+
+/**
+ Returns SPI Function number
+
+ @retval UINT8 PCH SPI Function number
+**/
+UINT8
+SpiFunctionNumber (
+ VOID
+ );
+
+/**
+ Returns descriptor signature
+
+ @retval UINT32 Descriptor signature
+**/
+UINT32
+SpiGetDescriptorSignature (
+ VOID
+ );
+
+/**
+ Returns supported features and R/W frequencies of Flash Component
+
+ @retval UINT32 Flash Component features descriptor
+**/
+UINT32
+SpiGetFlashComponentDescription (
+ VOID
+ );
+
+/**
+ Returns number of Flash Components
+
+ @retval UINT32 Flash components number
+**/
+UINT32
+SpiGetFlashComponentsNumber (
+ VOID
+ );
+
+/**
+ Returns total Flash size with regards to number of flash components
+
+ @retval UINT32 Total Flash Memory size
+**/
+UINT32
+SpiGetTotalFlashSize (
+ VOID
+ );
+
+/**
+ Checks if PCH SPI Controler is present and available
+
+ @retval TRUE PCH SPI controller is avaialable
+ @retval FALSE PCH SPI controller is not available
+**/
+BOOLEAN
+SpiIsControllerAvailable (
+ VOID
+ );
+
+/**
+ Checks BIOS lock bits for proper value and checks if write protection is enabled
+ Expected vales are: LE bit set, EISS bit set and WPD bit cleared
+
+ @retval TRUE All protection bits are set correctly
+ @retval FALSE Not all protection bits had exepcted values
+**/
+BOOLEAN
+SpiIsWriteProtectionEnabled (
+ VOID
+ );
+
+/**
+ Returns Flash Descriptor Override Pin Strap status
+
+ @retval TRUE Flash Descriptor override is enabled
+ @retval FALSE Flash Descriptor override is disabled
+**/
+BOOLEAN
+SpiIsFlashDescriptorOverrideEnabled (
+ VOID
+ );
+
+/**
+ Returns Flash Configuration Lock Down bit status
+
+ @retval TRUE Flash Configuration Lock Down bit is set
+ @retval FALSE Flash Configuration Lock Down bit is not set
+**/
+BOOLEAN
+SpiIsFlashConfigurationLockDownEnabled (
+ VOID
+ );
+
+/**
+ Returns Top Swap functionality enable state
+
+ @retval TRUE Top Swap is enabled
+ @retval FALSE Top Swap is disabled
+**/
+BOOLEAN
+SpiIsTopSwapEnabled (
+ VOID
+ );
+
+/**
+ Return Component Property Parameter Table for a given component number
+
+ @param[in] ComponentNumber SPI Component number
+ @param[out] CppTable Component Poperty Parameter Table value
+
+ @retval TRUE Vendor Specific Component Capabilities Register value was read
+ @reval FALSE Vendor Specific Component Capabilities Register value was not present
+**/
+BOOLEAN
+SpiGetComponentPropertyParameterTable (
+ IN UINT8 ComponentNumber,
+ OUT UINT32 *CppTable
+ );
+
+/**
+ Returns valid bit status in given Component Property Parameter Table
+
+ @param[in] CppTable Component Poperty Parameter Table value
+
+ @retval TRUE Valid bit is set
+ @reval FALSE Valid bit is not set
+**/
+BOOLEAN
+SpiIsCppValidBitSet (
+ IN UINT32 CppTable
+ );
+
+/**
+ Checks if Flash Descriptor is valid
+
+ @retval TRUE Flash Descriptor is valid
+ @retval FALSE Flash Descriptor is invalid
+**/
+BOOLEAN
+SpiIsFlashDescriptorValid (
+ VOID
+ );
+
+/**
+ Returns masked BIOS Master Read Access
+
+ @retval UINT32 Already masked BIOS Master Read Access
+**/
+UINT32
+SpiGetMasterReadAccess (
+ VOID
+ );
+
+/**
+ Returns masked BIOS Master Write Access
+
+ @retval UINT32 Already masked BIOS Master Write Access
+**/
+UINT32
+SpiGetMasterWriteAccess (
+ VOID
+ );
+
+/**
+ Returns GbE Region Access rights
+
+ @retval UINT32 GbE Region access rights
+**/
+UINT32
+SpiGetGbeRegionAccess (
+ VOID
+ );
+
+/**
+ Returns CSME region access rights
+
+ @retval UINT32 CSME Region Access rights
+**/
+UINT32
+SpiGetCsmeRegionAccess (
+ VOID
+ );
+
+/**
+ Returns EC region access right
+
+ @retval UINT32 EC Region access rights
+**/
+UINT32
+SpiGetEcRegionAccess (
+ VOID
+ );
+
+/**
+ Checks if Slave Attached Flash (SAF) mode is active
+
+ @retval TRUE SAF mode is active
+ @retval FALSE SAF mode is not active
+**/
+BOOLEAN
+SpiIsSafModeActive (
+ VOID
+ );
+
+/**
+ Checks validity of GbE region
+
+ @retval TRUE GbE region is valid
+ @retval FALSE GbE regios in invalid
+**/
+BOOLEAN
+SpiIsGbeRegionValid (
+ VOID
+ );
+
+/**
+ Returns status of BIOS Interface Lockdown
+
+ @retval TRUE BIOS Interface Lockdown is enabled
+ @retval FALSE BIOS Interface Lockdown is disabled
+**/
+BOOLEAN
+SpiIsBiosInterfaceLockdownEnabled (
+ VOID
+ );
+
+/**
+ Returns TRUE if BIOS Boot Strap is set to SPI
+
+ @retval TRUE BIOS Boot strap is set to SPI
+ @retval FALSE BIOS Boot strap is set to LPC/eSPI
+**/
+BOOLEAN
+SpiIsBiosBootFromSpi (
+ VOID
+ );
+
+/**
+ Check SPI write status disable is set
+
+ @retval TRUE Write status disable is set
+ @retval FALSE Write status disable is not set
+**/
+BOOLEAN
+SpiIsWriteStatusDisable (
+ VOID
+ );
+
+#endif // _SPI_ACCESS_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h
new file mode 100644
index 0000000000..69eed8d32d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h
@@ -0,0 +1,53 @@
+/** @file
+ Header file for VtdInfoLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _VTD_INFO_LIB_H_
+#define _VTD_INFO_LIB_H_
+
+#include <Base.h>
+#include <Uefi/UefiBaseType.h>
+#include <Library/HobLib.h>
+
+#define VTD_ENGINE_NUMBER 7
+
+#pragma pack(1)
+
+/**
+ Get VTD Engine Base Address from PCD values.
+
+ @param[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
+
+ @retval VTD Engine Base Address
+**/
+UINT32
+GetVtdBaseAddress (
+ IN UINT8 VtdEngineNumber
+ );
+
+/**
+ Read VTD Engine Base Address from VTD BAR Offsets.
+
+ @param[in] VtdEngineNumber - Engine number for which VTD Base Adderess is required.
+
+ @retval VTD Engine Base Address
+**/
+UINT32
+ReadVtdBaseAddress (
+ IN UINT8 VtdEngineNumber
+ );
+
+/**
+ GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number
+
+ @retval Vtd Engine Number
+**/
+UINT8
+GetMaxVtdEngineNumber(
+ VOID
+);
+
+#pragma pack()
+#endif // _VTD_INFO_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
new file mode 100644
index 0000000000..3fd917c2b9
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h
@@ -0,0 +1,34 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_PREMEM_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit()
+};
+
+extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
new file mode 100644
index 0000000000..9cb34728cc
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h
@@ -0,0 +1,33 @@
+/** @file
+ This file defines the function to initialize default silicon policy PPI.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
+
+//
+// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.
+//
+typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_PPI;
+
+/**
+ Initialize and install default silicon policy PPI
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PEI_POLICY_INIT) (
+ VOID
+ );
+
+///
+/// This PPI provides function to install default silicon policy
+///
+struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {
+ PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()
+};
+
+extern EFI_GUID gSiDefaultPolicyInitPpiGuid;
+
+#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h
new file mode 100644
index 0000000000..5f4d467439
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h
@@ -0,0 +1,75 @@
+/** @file
+ Silicon Policy PPI is used for specifying platform
+ related Intel silicon information and policy setting.
+ This PPI is consumed by the silicon PEI modules and carried
+ over to silicon DXE modules.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_POLICY_PPI_H_
+#define _SI_POLICY_PPI_H_
+
+#include <SiPolicyStruct.h>
+#include <PchPolicyCommon.h>
+#include <PchPreMemPolicyCommon.h>
+#include <MePolicyCommon.h>
+#include <CpuPolicyCommon.h>
+#include <Uefi.h>
+#include <Library/ConfigBlockLib.h>
+
+#ifndef DISABLED
+#define DISABLED 0
+#endif
+#ifndef ENABLED
+#define ENABLED 1
+#endif
+
+extern EFI_GUID gSiPreMemPolicyPpiGuid;
+extern EFI_GUID gSiPolicyPpiGuid;
+
+
+#include <GraphicsConfig.h>
+extern EFI_GUID gGraphicsPeiPreMemConfigGuid;
+extern EFI_GUID gGraphicsPeiConfigGuid;
+
+#include <VtdConfig.h>
+extern EFI_GUID gVtdConfigGuid;
+
+#include <GnaConfig.h>
+extern EFI_GUID gGnaConfigGuid;
+
+#include <CpuPcieConfig.h>
+extern EFI_GUID gCpuPciePeiPreMemConfigGuid;
+extern EFI_GUID gCpuPcieRpConfigGuid;
+
+#include <HybridGraphicsConfig.h>
+extern EFI_GUID gHybridGraphicsConfigGuid;
+
+#include <ConfigBlock/PramPreMemConfig.h>
+#include <MemoryConfig.h>
+extern EFI_GUID gMemoryConfigGuid;
+extern EFI_GUID gMemoryConfigNoCrcGuid;
+
+#include <ConfigBlock/SaMiscPeiPreMemConfig.h>
+extern EFI_GUID gSaMiscPeiPreMemConfigGuid;
+
+#include <ConfigBlock/SaMiscPeiConfig.h>
+extern EFI_GUID gSaMiscPeiConfigGuid;
+
+
+#include <TraceHubConfig.h>
+extern EFI_GUID gCpuTraceHubConfigGuid;
+
+#include <HostBridgeConfig.h>
+extern EFI_GUID gHostBridgePeiPreMemConfigGuid;
+extern EFI_GUID gHostBridgePeiConfigGuid;
+
+#include <CpuDmiPreMemConfig.h>
+extern EFI_GUID gCpuDmiPreMemConfigGuid;
+
+typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;
+typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;
+
+#endif // _SI_POLICY_PPI_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h
new file mode 100644
index 0000000000..1d69ee0e8d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h
@@ -0,0 +1,61 @@
+/** @file
+ Protocol to retrieve the GOP driver version
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GOP_COMPONENT_NAME2_H_
+#define _GOP_COMPONENT_NAME2_H_
+
+
+typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL;
+
+///
+/// GOP Component protocol for retrieving driver name
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL * This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverName
+ );
+
+///
+/// GOP Component protocol for retrieving controller name
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL * This,
+ IN EFI_HANDLE ControllerHandle,
+ IN EFI_HANDLE ChildHandle OPTIONAL,
+ IN CHAR8 *Language,
+ OUT CHAR16 **ControllerName
+ );
+
+///
+/// GOP Component protocol for retrieving driver version
+///
+typedef
+EFI_STATUS
+(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (
+ IN GOP_COMPONENT_NAME2_PROTOCOL * This,
+ IN CHAR8 *Language,
+ OUT CHAR16 **DriverVersion
+ );
+
+/**
+ GOP Component protocol\n
+ This protocol will be installed by GOP driver and can be used to retrieve GOP information.
+**/
+struct _GOP_COMPONENT_NAME2_PROTOCOL {
+ GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Protocol function to get driver name
+ GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Protocol function to get driver version
+ GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Protocol function to get controller name
+ CHAR8 *SupportedLanguages; ///< Number of Supported languages.
+};
+
+extern EFI_GUID gGopComponentName2ProtocolGuid;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h
new file mode 100644
index 0000000000..c8dc17008e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h
@@ -0,0 +1,73 @@
+/** @file
+ Interface definition for GopPolicy Protocol.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _GOP_POLICY_PROTOCOL_H_
+#define _GOP_POLICY_PROTOCOL_H_
+
+
+#define GOP_POLICY_PROTOCOL_REVISION_01 0x01
+#define GOP_POLICY_PROTOCOL_REVISION_03 0x03
+
+typedef enum {
+ LidClosed,
+ LidOpen,
+ LidStatusMax
+} LID_STATUS;
+
+typedef enum {
+ Docked,
+ UnDocked,
+ DockStatusMax
+} DOCK_STATUS;
+
+///
+/// Function to retrieve LID status
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_LID_STATUS) (
+ OUT LID_STATUS * CurrentLidStatus
+ );
+
+///
+/// Function to retrieve Dock status
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_PLATFORM_DOCK_STATUS) (
+ OUT DOCK_STATUS CurrentDockStatus
+);
+
+///
+/// Function to retrieve VBT table address and size
+///
+typedef
+EFI_STATUS
+(EFIAPI *GET_VBT_DATA) (
+ OUT EFI_PHYSICAL_ADDRESS * VbtAddress,
+ OUT UINT32 *VbtSize
+ );
+
+/**
+ System Agent Graphics Output Protocol (GOP) - Policy Protocol\n
+ Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs for EFI boot\n
+ When GOP Driver is used this protocol can be consumed by GOP driver or platform code for GOP relevant initialization\n
+ All functions in this protocol should be initialized by platform code basing on platform implementation\n
+**/
+typedef struct {
+ UINT32 Revision; ///< Protocol revision
+ GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function to get Lid Status. Platform code should provide this function basing on design.
+ GET_VBT_DATA GetVbtData; ///< Protocol function to get Vbt Data address and size. Platform code should provide this function basing on design.
+ GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer for get platform dock status.
+ EFI_GUID GopOverrideGuid; ///< A GUID provided by BIOS in case GOP is to be overridden.
+} GOP_POLICY_PROTOCOL;
+
+extern EFI_GUID gGopPolicyProtocolGuid;
+extern EFI_GUID gGen12PolicyProtocolGuid;
+extern EFI_GUID gGen9PolicyProtocolGuid;
+extern EFI_GUID gIntelGraphicsVbtGuid;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
new file mode 100644
index 0000000000..c030f771e3
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h
@@ -0,0 +1,22 @@
+/** @file
+ This file is part of the IGD OpRegion Implementation. The IGD OpRegion is
+ an interface between system BIOS, ASL code, and Graphics drivers.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IGD_OPREGION_PROTOCOL_H_
+#define _IGD_OPREGION_PROTOCOL_H_
+
+#include <IndustryStandard/IgdOpRegion.h>
+
+extern EFI_GUID gIgdOpRegionProtocolGuid;
+
+///
+/// IGD OpRegion Protocol
+///
+typedef struct {
+ IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure
+} IGD_OPREGION_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h
new file mode 100644
index 0000000000..c13dc5a5f5
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h
@@ -0,0 +1,301 @@
+/** @file
+ This file defines the PCH SPI Protocol which implements the
+ Intel(R) PCH SPI Host Controller Compatibility Interface.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SPI_PROTOCOL_H_
+#define _PCH_SPI_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSpiProtocolGuid;
+extern EFI_GUID gPchSmmSpiProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;
+
+//
+// SPI protocol data structures and definitions
+//
+
+/**
+ Flash Region Type
+**/
+typedef enum {
+ FlashRegionDescriptor,
+ FlashRegionBios,
+ FlashRegionMe,
+ FlashRegionGbE,
+ FlashRegionPlatformData,
+ FlashRegionDer,
+ FlashRegionSecondaryBios,
+ FlashRegionuCodePatch,
+ FlashRegionEC,
+ FlashRegionDeviceExpansion2,
+ FlashRegionIE,
+ FlashRegion10Gbe_A,
+ FlashRegion10Gbe_B,
+ FlashRegion13,
+ FlashRegion14,
+ FlashRegion15,
+ FlashRegionAll,
+ FlashRegionMax
+} FLASH_REGION_TYPE;
+//
+// Protocol member functions
+//
+
+/**
+ Read data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[out] Buffer The Pointer to caller-allocated buffer containing the dada received.
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *Buffer
+ );
+
+/**
+ Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+ @param[in] Buffer Pointer to caller-allocated buffer containing the data sent during the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ IN UINT8 *Buffer
+ );
+
+/**
+ Erase some area on the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for flash cycle which is listed in the Descriptor.
+ @param[in] Address The Flash Linear Address must fall within a region for which BIOS has access permissions.
+ @param[in] ByteCount Number of bytes in the data portion of the SPI cycle.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_ERASE) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ IN UINT32 Address,
+ IN UINT32 ByteCount
+ );
+
+/**
+ Read SFDP data from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] Address The starting byte address for SFDP data read.
+ @param[in] ByteCount Number of bytes in SFDP data portion of the SPI cycle
+ @param[out] SfdpData The Pointer to caller-allocated buffer containing the SFDP data received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 Address,
+ IN UINT32 ByteCount,
+ OUT UINT8 *SfdpData
+ );
+
+/**
+ Read Jedec Id from the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ComponentNumber The Componen Number for chip select
+ @param[in] ByteCount Number of bytes in JedecId data portion of the SPI cycle, the data size is 3 typically
+ @param[out] JedecId The Pointer to caller-allocated buffer containing JEDEC ID received
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT8 ComponentNumber,
+ IN UINT32 ByteCount,
+ OUT UINT8 *JedecId
+ );
+
+/**
+ Write the status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[in] StatusValue The Pointer to caller-allocated buffer containing the value of Status register writing
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ IN UINT8 *StatusValue
+ );
+
+/**
+ Read status register in the flash part.
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] ByteCount Number of bytes in Status data portion of the SPI cycle, the data size is 1 typically
+ @param[out] StatusValue The Pointer to caller-allocated buffer containing the value of Status register received.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 ByteCount,
+ OUT UINT8 *StatusValue
+ );
+
+/**
+ Get the SPI region base and size, based on the enum type
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] FlashRegionType The Flash Region type for for the base address which is listed in the Descriptor.
+ @param[out] BaseAddress The Flash Linear Address for the Region 'n' Base
+ @param[out] RegionSize The size for the Region 'n'
+
+ @retval EFI_SUCCESS Read success
+ @retval EFI_INVALID_PARAMETER Invalid region type given
+ @retval EFI_DEVICE_ERROR The region is not used
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN FLASH_REGION_TYPE FlashRegionType,
+ OUT UINT32 *BaseAddress,
+ OUT UINT32 *RegionSize
+ );
+
+/**
+ Read PCH Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing PCH Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ Read CPU Soft Strap Values
+
+ @param[in] This Pointer to the PCH_SPI_PROTOCOL instance.
+ @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUSBA.
+ @param[in] ByteCount Number of bytes in SoftStrap data portion of the SPI cycle.
+ @param[out] SoftStrapValue The Pointer to caller-allocated buffer containing CPU Soft Strap Value.
+ If the value of ByteCount is 0, the data type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Soft Strap Length
+ It is the caller's responsibility to make sure Buffer is large enough for the total number of bytes read.
+
+ @retval EFI_SUCCESS Command succeed.
+ @retval EFI_INVALID_PARAMETER The parameters specified are not valid.
+ @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (
+ IN PCH_SPI_PROTOCOL *This,
+ IN UINT32 SoftStrapAddr,
+ IN UINT32 ByteCount,
+ OUT VOID *SoftStrapValue
+ );
+
+/**
+ These protocols/PPI allows a platform module to perform SPI operations through the
+ Intel PCH SPI Host Controller Interface.
+**/
+struct _PCH_SPI_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ PCH_SPI_FLASH_READ FlashRead; ///< Read data from the flash part.
+ PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to the flash part. Remark: Erase may be needed before write to the flash part.
+ PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some area on the flash part.
+ PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP data from the flash part.
+ PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id from the flash part.
+ PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the status register in the flash part.
+ PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status register in the flash part.
+ PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI region base and size
+ PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft Strap Values
+ PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft Strap Values
+};
+
+/**
+ PCH SPI PPI/PROTOCOL revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SPI_SERVICES_REVISION 1
+
+#endif
--
2.24.0.windows.2
next prev parent reply other threads:[~2021-02-04 8:50 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-04 8:48 [Patch V2 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-04 8:48 ` Heng Luo [this message]
2021-02-05 5:52 ` [Patch V2 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-05 5:53 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-05 5:56 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-05 5:59 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-05 6:21 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-05 7:40 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04 8:48 ` [Patch V2 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04 8:48 ` [Patch V2 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04 8:48 ` [Patch V2 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04 8:48 ` [Patch V2 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04 8:48 ` [Patch V2 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04 8:48 ` [Patch V2 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04 8:48 ` [Patch V2 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04 8:48 ` [Patch V2 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04 8:48 ` [Patch V2 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04 8:49 ` [Patch V2 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04 8:49 ` [Patch V2 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04 8:49 ` [Patch V2 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04 8:49 ` [Patch V2 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04 8:49 ` [Patch V2 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04 8:49 ` [Patch V2 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04 8:49 ` [Patch V2 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04 8:49 ` [Patch V2 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04 8:49 ` [Patch V2 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04 8:49 ` [Patch V2 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04 8:49 ` [Patch V2 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04 8:49 ` [Patch V2 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04 8:49 ` [Patch V2 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04 8:49 ` [Patch V2 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04 8:49 ` [Patch V2 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04 8:49 ` [Patch V2 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04 8:49 ` [Patch V2 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04 8:49 ` [Patch V2 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-04 8:49 ` [Patch V2 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
[not found] ` <20210204084919.3603-40-heng.luo@intel.com>
2021-02-04 20:09 ` [Patch V2 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Nate DeSimone
2021-02-05 3:51 ` [Patch V2 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Chaganty, Rangasai V
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