From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com [192.55.52.151]) by mx.groups.io with SMTP id smtpd.web09.5252.1612428653220279512 for ; Thu, 04 Feb 2021 00:50:53 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.151, mailfrom: heng.luo@intel.com) IronPort-SDR: TOirHRNIrzCDGpIHe+3DL9IlQpPc2BHphk9hGiVhWFIvpSvEdgkwfq7KgT5HxkU6pTRv3vSf3X G/VSJIEPe9UQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160957209" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160957209" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:50:51 -0800 IronPort-SDR: UiabqVMAkaXKObZManzwzejLSs4X9taEyv3BdSqSjgBSwCrZ3PvESy7iFcdToOEUSApzLw2swq 22kCnlh5ojLw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393061939" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:50:47 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Date: Thu, 4 Feb 2021 16:48:41 +0800 Message-Id: <20210204084919.3603-2-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Include/Library * Include/Ppi * Include/Protocol Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h |= 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h |= 332 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h |= 153 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h |= 140 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h |= 63 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h |= 342 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h |= 720 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h |= 149 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h |= 27 +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h |= 123 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h |= 256 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h |= 173 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h |= 355 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h |= 79 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h |= 112 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h |= 113 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h |= 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h |= 290 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h |= 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolicy.h |= 34 ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h |= 33 +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h |= 75 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h |= 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h |= 73 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h |= 22 ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h |= 301 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ 26 files changed, 4199 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockL= ib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h new file mode 100644 index 0000000000..dbf786ec9a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ConfigBlockLib.h @@ -0,0 +1,64 @@ +/** @file=0D + Header file for Config Block Lib implementation=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _CONFIG_BLOCK_LIB_H_=0D +#define _CONFIG_BLOCK_LIB_H_=0D +=0D +/**=0D + Create config block table=0D +=0D + @param[in] TotalSize - Max size to be allocated f= or the Config Block Table=0D + @param[out] ConfigBlockTableAddress - On return, points to a poi= nter to the beginning of Config Block Table Address=0D +=0D + @retval EFI_INVALID_PARAMETER - Invalid Parameter=0D + @retval EFI_OUT_OF_RESOURCES - Out of resources=0D + @retval EFI_SUCCESS - Successfully created Config Block Table = at ConfigBlockTableAddress=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CreateConfigBlockTable (=0D + IN UINT16 TotalSize,=0D + OUT VOID **ConfigBlockTableAddress=0D + );=0D +=0D +/**=0D + Add config block into config block table structure=0D +=0D + @param[in] ConfigBlockTableAddress - A pointer to the beginning= of Config Block Table Address=0D + @param[out] ConfigBlockAddress - On return, points to a poi= nter to the beginning of Config Block Address=0D +=0D + @retval EFI_OUT_OF_RESOURCES - Config Block Table is full and cannot add= new Config Block or=0D + Config Block Offset Table is full and can= not add new Config Block.=0D + @retval EFI_SUCCESS - Successfully added Config Block=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +AddConfigBlock (=0D + IN VOID *ConfigBlockTableAddress,=0D + OUT VOID **ConfigBlockAddress=0D + );=0D +=0D +/**=0D + Retrieve a specific Config Block data by GUID=0D +=0D + @param[in] ConfigBlockTableAddress - A pointer to the beginnin= g of Config Block Table Address=0D + @param[in] ConfigBlockGuid - A pointer to the GUID use= s to search specific Config Block=0D + @param[out] ConfigBlockAddress - On return, points to a po= inter to the beginning of Config Block Address=0D +=0D + @retval EFI_NOT_FOUND - Could not find the Config Block=0D + @retval EFI_SUCCESS - Config Block found and return=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetConfigBlock (=0D + IN VOID *ConfigBlockTableAddress,=0D + IN EFI_GUID *ConfigBlockGuid,=0D + OUT VOID **ConfigBlockAddress=0D + );=0D +=0D +#endif // _CONFIG_BLOCK_LIB_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAcc= essLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAcces= sLib.h new file mode 100644 index 0000000000..564fcccb43 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/CpuRegbarAccessLib.h @@ -0,0 +1,332 @@ +/** @file=0D + Header file for CPU REGBAR ACCESS library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_REGBAR_ACCESS_LIB_H_=0D +#define _CPU_REGBAR_ACCESS_LIB_H_=0D +=0D +#define INVALID_DATA_64 0xFFFFFFFFFFFFFFFF=0D +#define INVALID_DATA_32 0xFFFFFFFF=0D +#define INVALID_DATA_16 0xFFFF=0D +#define INVALID_DATA_8 0xFF=0D +#define INVALID_PID 0xFF=0D +=0D +typedef UINT8 CPU_SB_DEVICE_PID;=0D +=0D +/**=0D + Read REGBAR register.=0D + It returns REGBAR register and size in 8bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT64 REGBAR register value.=0D +**/=0D +UINT64=0D +CpuRegbarRead64 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset=0D + );=0D +=0D +=0D +/**=0D + Read REGBAR register.=0D + It returns REGBAR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT32 REGBAR register value.=0D +**/=0D +UINT32=0D +CpuRegbarRead32 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset=0D + );=0D +=0D +/**=0D + Read REGBAR register.=0D + It returns REGBAR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT16 REGBAR register value.=0D +**/=0D +UINT16=0D +CpuRegbarRead16 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset=0D + );=0D +=0D +/**=0D + Read REGBAR register.=0D + It returns REGBAR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT8 REGBAR regsiter value=0D +**/=0D +UINT8=0D +CpuRegbarRead8 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 8bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size p= arameter.=0D +=0D + @retval UINT64 Value written to register=0D +**/=0D +UINT64=0D +CpuRegbarWrite64 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT64 Data=0D + );=0D +=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size p= arameter.=0D +=0D + @retval UINT32 Value written to register=0D +**/=0D +UINT32=0D +CpuRegbarWrite32 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT32 Data=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size p= arameter.=0D +=0D + @retval UINT16 Value written to register=0D +**/=0D +UINT16=0D +CpuRegbarWrite16 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT16 Data=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size p= arameter.=0D +=0D + @retval UINT8 Value written to register=0D +**/=0D +UINT8=0D +CpuRegbarWrite8 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT8 Data=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT32 Value written to register=0D +=0D +**/=0D +UINT32=0D +CpuRegbarOr32 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT16 Value written to register=0D +=0D +**/=0D +UINT16=0D +CpuRegbarOr16 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT16 OrData=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT8 Value written to register=0D +=0D +**/=0D +UINT8=0D +CpuRegbarOr8 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT8 OrData=0D + );=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit data.=0D + It programs REGBAR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevice CPU SB Device=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData And Data. Must be the same size as Size par= ameter.=0D +=0D + @retval UINT32 Value written to register=0D +=0D +**/=0D +UINT32=0D +CpuRegbarAnd32 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT32 AndData=0D + );=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit data.=0D + It programs REGBAR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevice CPU SB Device=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData And Data. Must be the same size as Size par= ameter.=0D +=0D + @retval UINT16 Value written to register=0D +=0D +**/=0D +UINT16=0D +CpuRegbarAnd16 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT16 AndData=0D + );=0D +=0D +/**=0D + Performs a bitwise AND of a 8-bit data.=0D + It programs REGBAR register and size in 1byte.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevice CPU SB Device=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData And Data. Must be the same size as Size par= ameter.=0D +=0D + @retval UINT8 Value written to register=0D +=0D +**/=0D +UINT8=0D +CpuRegbarAnd8 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT8 AndData=0D + );=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size par= ameter.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT32 Value written to register=0D +=0D +**/=0D +UINT32=0D +CpuRegbarAndThenOr32 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size par= ameter.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT16 Value written to register=0D +=0D +**/=0D +UINT16=0D +CpuRegbarAndThenOr16 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + );=0D +=0D +/**=0D + Write REGBAR register.=0D + It programs REGBAR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] CpuSbDevicePid CPU SB Device Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size par= ameter.=0D + @param[in] OrData OR Data. Must be the same size as Size para= meter.=0D +=0D + @retval UINT8 Value written to register=0D +=0D +**/=0D +UINT8=0D +CpuRegbarAndThenOr8 (=0D + IN CPU_SB_DEVICE_PID CpuSbDevicePid,=0D + IN UINT16 Offset,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLi= b.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h new file mode 100644 index 0000000000..c48ea3667f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/DxeHdaNhltLib.h @@ -0,0 +1,153 @@ +/** @file=0D + Prototype of the DxePchHdaNhltLib library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _DXE_HDA_NHLT_LIB_H_=0D +#define _DXE_HDA_NHLT_LIB_H_=0D +=0D +#include =0D +=0D +/**=0D + Returns pointer to Endpoint ENDPOINT_DESCRIPTOR structure.=0D +=0D + @param[in] *NhltTable Endpoint for which Format address is retrieved= =0D + @param[in] FormatIndex Index of Format to be retrieved=0D +=0D + @retval Pointer to ENDPOINT_DESCRIPTOR structure with g= iven index=0D +**/=0D +ENDPOINT_DESCRIPTOR *=0D +GetNhltEndpoint (=0D + IN CONST NHLT_ACPI_TABLE *NhltTable,=0D + IN CONST UINT8 EndpointIndex=0D + );=0D +=0D +/**=0D + Returns pointer to Endpoint Specific Configuration SPECIFIC_CONFIG struc= ture.=0D +=0D + @param[in] *Endpoint Endpoint for which config address is retrieved= =0D +=0D + @retval Pointer to SPECIFIC_CONFIG structure with endpo= int's capabilities=0D +**/=0D +SPECIFIC_CONFIG *=0D +GetNhltEndpointDeviceCapabilities (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint=0D + );=0D +=0D +/**=0D + Returns pointer to all Formats Configuration FORMATS_CONFIG structure.=0D +=0D + @param[in] *Endpoint Endpoint for which Formats address is retrieved= =0D +=0D + @retval Pointer to FORMATS_CONFIG structure=0D +**/=0D +FORMATS_CONFIG *=0D +GetNhltEndpointFormatsConfig (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint=0D + );=0D +=0D +/**=0D + Returns pointer to Format Configuration FORMAT_CONFIG structure.=0D +=0D + @param[in] *Endpoint Endpoint for which Format address is retrieved= =0D + @param[in] FormatIndex Index of Format to be retrieved=0D +=0D + @retval Pointer to FORMAT_CONFIG structure with given i= ndex=0D +**/=0D +FORMAT_CONFIG *=0D +GetNhltEndpointFormat (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint,=0D + IN CONST UINT8 FormatIndex=0D + );=0D +=0D +/**=0D + Returns pointer to all Device Information DEVICES_INFO structure.=0D +=0D + @param[in] *Endpoint Endpoint for which DevicesInfo address is retri= eved=0D +=0D + @retval Pointer to DEVICES_INFO structure=0D +**/=0D +DEVICES_INFO *=0D +GetNhltEndpointDevicesInfo (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint=0D + );=0D +=0D +/**=0D + Returns pointer to Device Information DEVICES_INFO structure.=0D +=0D + @param[in] *Endpoint Endpoint for which Device Info address is ret= rieved=0D + @param[in] DeviceInfoIndex Index of Device Info to be retrieved=0D +=0D + @retval Pointer to DEVICE_INFO structure with given i= ndex=0D +**/=0D +DEVICE_INFO *=0D +GetNhltEndpointDeviceInfo (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint,=0D + IN CONST UINT8 DeviceInfoIndex=0D + );=0D +=0D +=0D +/**=0D + Returns pointer to OED Configuration SPECIFIC_CONFIG structure.=0D +=0D + @param[in] *NhltTable NHLT table for which OED address is retrieved=0D +=0D + @retval Pointer to SPECIFIC_CONFIG structure with NHLT = capabilities=0D +**/=0D +SPECIFIC_CONFIG *=0D +GetNhltOedConfig (=0D + IN CONST NHLT_ACPI_TABLE *NhltTable=0D + );=0D +=0D +/**=0D + Prints Format configuration.=0D +=0D + @param[in] *Format Format to be printed=0D +=0D + @retval None=0D +**/=0D +VOID=0D +NhltFormatDump (=0D + IN CONST FORMAT_CONFIG *Format=0D + );=0D +=0D +=0D +/**=0D + Prints Endpoint configuration.=0D +=0D + @param[in] *Endpoint Endpoint to be printed=0D +=0D + @retval None=0D +**/=0D +VOID=0D +NhltEndpointDump (=0D + IN CONST ENDPOINT_DESCRIPTOR *Endpoint=0D + );=0D +=0D +/**=0D + Prints OED (Offload Engine Driver) configuration.=0D +=0D + @param[in] *OedConfig OED to be printed=0D +=0D + @retval None=0D +**/=0D +VOID=0D +NhltOedConfigDump (=0D + IN CONST SPECIFIC_CONFIG *OedConfig=0D + );=0D +=0D +/**=0D + Prints NHLT (Non HDA-Link Table) to be exposed via ACPI (aka. OED (Offlo= ad Engine Driver) Configuration Table).=0D +=0D + @param[in] *NhltTable The NHLT table to print=0D +=0D + @retval None=0D +**/=0D +VOID=0D +NhltAcpiTableDump (=0D + IN NHLT_ACPI_TABLE *NhltTable=0D + );=0D +=0D +#endif // _DXE_HDA_NHLT_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h b/= Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h new file mode 100644 index 0000000000..6d8466ab7a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/EspiLib.h @@ -0,0 +1,140 @@ +/** @file=0D + Header file for PchEspiLib.=0D + All function in this library is available for PEI, DXE, and SMM,=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _ESPI_LIB_H_=0D +#define _ESPI_LIB_H_=0D +=0D +/**=0D + Checks if there's second slave connected under CS#1=0D +=0D + @retval TRUE There's second slave=0D + @retval FALSE There's no second slave=0D +**/=0D +BOOLEAN=0D +IsEspiSecondSlaveSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks in slave General Capabilities register if it supports channel wit= h requested number=0D +=0D + @param[in] SlaveId Id of slave to check=0D + @param[in] ChannelNumber Number of channel of which to check=0D +=0D + @retval TRUE Channel with requested number is supported by slave de= vice=0D + @retval FALSE Channel with requested number is not supported by slav= e device=0D +**/=0D +BOOLEAN=0D +IsEspiSlaveChannelSupported (=0D + UINT8 SlaveId,=0D + UINT8 ChannelNumber=0D + );=0D +=0D +/**=0D + Is eSPI enabled in strap.=0D +=0D + @retval TRUE Espi is enabled in strap=0D + @retval FALSE Espi is disabled in strap=0D +**/=0D +BOOLEAN=0D +IsEspiEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Get configuration from eSPI slave=0D +=0D + @param[in] SlaveId eSPI slave ID=0D + @param[in] SlaveAddress Slave Configuration Register Address=0D + @param[out] OutData Configuration data read=0D +=0D + @retval EFI_SUCCESS Operation succeed=0D + @retval EFI_INVALID_PARAMETER Slave ID is not supported=0D + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp=0D + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed=0D + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned=0D + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation=0D +**/=0D +EFI_STATUS=0D +PchEspiSlaveGetConfig (=0D + IN UINT32 SlaveId,=0D + IN UINT32 SlaveAddress,=0D + OUT UINT32 *OutData=0D + );=0D +=0D +/**=0D + Set eSPI slave configuration=0D +=0D + Note: A Set_Configuration must always be followed by a Get_Configuration= in order to ensure=0D + that the internal state of the eSPI-MC is consistent with the Slave's re= gister settings.=0D +=0D + @param[in] SlaveId eSPI slave ID=0D + @param[in] SlaveAddress Slave Configuration Register Address=0D + @param[in] InData Configuration data to write=0D +=0D + @retval EFI_SUCCESS Operation succeed=0D + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp=0D + @retval EFI_INVALID_PARAMETER Slave configuration register address excee= d maximum allowed=0D + @retval EFI_INVALID_PARAMETER Slave configuration register address is no= t DWord aligned=0D + @retval EFI_ACCESS_DENIED eSPI Slave write to address range 0 to 0x7= FF has been locked=0D + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation=0D +**/=0D +EFI_STATUS=0D +PchEspiSlaveSetConfig (=0D + IN UINT32 SlaveId,=0D + IN UINT32 SlaveAddress,=0D + IN UINT32 InData=0D + );=0D +=0D +/**=0D + Get status from eSPI slave=0D +=0D + @param[in] SlaveId eSPI slave ID=0D + @param[out] OutData Configuration data read=0D +=0D + @retval EFI_SUCCESS Operation succeed=0D + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp=0D + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation=0D +**/=0D +EFI_STATUS=0D +PchEspiSlaveGetStatus (=0D + IN UINT32 SlaveId,=0D + OUT UINT16 *OutData=0D + );=0D +=0D +/**=0D + eSPI slave in-band reset=0D +=0D + @param[in] SlaveId eSPI slave ID=0D +=0D + @retval EFI_SUCCESS Operation succeed=0D + @retval EFI_INVALID_PARAMETER Slave ID is not supported or SlaveId 1 is = used in PchLp=0D + @retval EFI_DEVICE_ERROR Error in SCRS during polling stage of oper= ation=0D +**/=0D +EFI_STATUS=0D +PchEspiSlaveInBandReset (=0D + IN UINT32 SlaveId=0D + );=0D +=0D +/**=0D + eSPI Slave channel reset helper function=0D +=0D + @param[in] SlaveId eSPI slave ID=0D + @param[in] ChannelNumber Number of channel to reset=0D +=0D + @retval EFI_SUCCESS Operation succeeded=0D + @retval EFI_UNSUPPORTED Slave doesn't support that channel or inva= lid number specified=0D + @retval EFI_TIMEOUT Operation has timeouted=0D +**/=0D +EFI_STATUS=0D +PchEspiSlaveChannelReset (=0D + IN UINT8 SlaveId,=0D + IN UINT8 ChannelNumber=0D + );=0D +=0D +#endif // _ESPI_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h b/S= ilicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h new file mode 100644 index 0000000000..9d72b9ac7c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GbeLib.h @@ -0,0 +1,63 @@ +/** @file=0D + Header file for GbeLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GBE_LIB_H_=0D +#define _GBE_LIB_H_=0D +=0D +/**=0D + Check whether GbE region is valid=0D + Check SPI region directly since GbE might be disabled in SW.=0D +=0D + @retval TRUE Gbe Region is valid=0D + @retval FALSE Gbe Region is invalid=0D +**/=0D +BOOLEAN=0D +IsGbeRegionValid (=0D + VOID=0D + );=0D +=0D +/**=0D + Check whether GBE controller is enabled in the platform.=0D +=0D + @retval TRUE GbE is enabled=0D + @retval FALSE GbE is disabled=0D +**/=0D +BOOLEAN=0D +IsGbePresent (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if Gbe is Enabled or Disabled=0D +=0D + @retval BOOLEAN TRUE if device is enabled, FALSE otherwise.=0D +**/=0D +BOOLEAN=0D +IsGbeEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Device Number=0D +=0D + @retval GbE device number=0D +**/=0D +UINT8=0D +GbeDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Function Number=0D +=0D + @retval GbE function number=0D +**/=0D +UINT8=0D +GbeFuncNumber (=0D + VOID=0D + );=0D +=0D +#endif // _GBE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h= b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h new file mode 100644 index 0000000000..88a21efb32 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioConfig.h @@ -0,0 +1,342 @@ +/** @file=0D + Header file for GpioConfig structure used by GPIO library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_CONFIG_H_=0D +#define _GPIO_CONFIG_H_=0D +=0D +#pragma pack(push, 1)=0D +=0D +///=0D +/// For any GpioPad usage in code use GPIO_PAD type=0D +///=0D +typedef UINT32 GPIO_PAD;=0D +=0D +///=0D +/// GpioPad with additional native function information.=0D +/// This type is used to represent signal muxing alternatives. Platform wi= ll provide such value to=0D +/// identify muxing selection for given signal on a specific SOC.=0D +/// Please refer to the board layout=0D +///=0D +typedef UINT32 GPIO_NATIVE_PAD;=0D +=0D +=0D +///=0D +/// For any GpioGroup usage in code use GPIO_GROUP type=0D +///=0D +typedef UINT32 GPIO_GROUP;=0D +=0D +/**=0D + GPIO configuration structure used for pin programming.=0D + Structure contains fields that can be used to configure pad.=0D +**/=0D +typedef struct {=0D + /**=0D + Pad Mode=0D + Pad can be set as GPIO or one of its native functions.=0D + When in native mode setting Direction (except Inversion), OutputState,=0D + InterruptConfig, Host Software Pad Ownership and OutputStateLock are unn= ecessary.=0D + Refer to definition of GPIO_PAD_MODE.=0D + Refer to EDS for each native mode according to the pad.=0D + **/=0D + UINT32 PadMode : 5;=0D + /**=0D + Host Software Pad Ownership=0D + Set pad to ACPI mode or GPIO Driver Mode.=0D + Refer to definition of GPIO_HOSTSW_OWN.=0D + **/=0D + UINT32 HostSoftPadOwn : 2;=0D + /**=0D + GPIO Direction=0D + Can choose between In, In with inversion, Out, both In and Out, both In = with inversion and out or disabling both.=0D + Refer to definition of GPIO_DIRECTION for supported settings.=0D + **/=0D + UINT32 Direction : 6;=0D + /**=0D + Output State=0D + Set Pad output value.=0D + Refer to definition of GPIO_OUTPUT_STATE for supported settings.=0D + This setting takes place when output is enabled.=0D + **/=0D + UINT32 OutputState : 2;=0D + /**=0D + GPIO Interrupt Configuration=0D + Set Pad to cause one of interrupts (IOxAPIC/SCI/SMI/NMI).=0D + This setting is applicable only if GPIO is in GpioMode with input enable= d.=0D + Refer to definition of GPIO_INT_CONFIG for supported settings.=0D + **/=0D + UINT32 InterruptConfig : 9;=0D + /**=0D + GPIO Power Configuration.=0D + This setting controls Pad Reset Configuration.=0D + Refer to definition of GPIO_RESET_CONFIG for supported settings.=0D + **/=0D + UINT32 PowerConfig : 8;=0D + /**=0D + GPIO Electrical Configuration=0D + This setting controls pads termination.=0D + Refer to definition of GPIO_ELECTRICAL_CONFIG for supported settings.=0D + **/=0D + UINT32 ElectricalConfig : 9;=0D + /**=0D + GPIO Lock Configuration=0D + This setting controls pads lock.=0D + Refer to definition of GPIO_LOCK_CONFIG for supported settings.=0D + **/=0D + UINT32 LockConfig : 4;=0D + /**=0D + Additional GPIO configuration=0D + Refer to definition of GPIO_OTHER_CONFIG for supported settings.=0D + **/=0D + UINT32 OtherSettings : 9;=0D +=0D + UINT32 RsvdBits : 10; ///< Reserved bits for future extensi= on=0D +} GPIO_CONFIG;=0D +=0D +=0D +typedef enum {=0D + GpioHardwareDefault =3D 0x0 ///< Leave setting unmodified=0D +} GPIO_HARDWARE_DEFAULT;=0D +=0D +/**=0D + GPIO Pad Mode=0D + Refer to GPIO documentation on native functions available for certain pa= d.=0D + If GPIO is set to one of NativeX modes then following settings are not a= pplicable=0D + and can be skipped:=0D + - Interrupt related settings=0D + - Host Software Ownership=0D + - Output/Input enabling/disabling=0D + - Output lock=0D +**/=0D +typedef enum {=0D + GpioPadModeHwDefault =3D 0x0,=0D + GpioPadModeGpio =3D 0x1,=0D + GpioPadModeNative1 =3D 0x3,=0D + GpioPadModeNative2 =3D 0x5,=0D + GpioPadModeNative3 =3D 0x7,=0D + GpioPadModeNative4 =3D 0x9,=0D + GpioPadModeNative5 =3D 0xB,=0D + GpioPadModeNative6 =3D 0xD,=0D + GpioPadModeNative7 =3D 0xF=0D +} GPIO_PAD_MODE;=0D +=0D +/**=0D + Host Software Pad Ownership modes=0D + This setting affects GPIO interrupt status registers. Depending on chose= n ownership=0D + some GPIO Interrupt status register get updated and other masked.=0D + Please refer to EDS for HOSTSW_OWN register description.=0D +**/=0D +typedef enum {=0D + GpioHostOwnDefault =3D 0x0, ///< Leave ownership value unmodified=0D + /**=0D + Set HOST ownership to ACPI.=0D + Use this setting if pad is not going to be used by GPIO OS driver.=0D + If GPIO is configured to generate SCI/SMI/NMI then this setting must be= =0D + used for interrupts to work=0D + **/=0D + GpioHostOwnAcpi =3D 0x1,=0D + /**=0D + Set HOST ownership to GPIO Driver mode.=0D + Use this setting only if GPIO pad should be controlled by GPIO OS Driver= .=0D + GPIO OS Driver will be able to control the pad if appropriate entry in=0D + ACPI exists (refer to ACPI specification for GpioIo and GpioInt descript= ors)=0D + **/=0D + GpioHostOwnGpio =3D 0x3=0D +} GPIO_HOSTSW_OWN;=0D +=0D +///=0D +/// GPIO Direction=0D +///=0D +typedef enum {=0D + GpioDirDefault =3D 0x0, ///< Leave pad direction = setting unmodified=0D + GpioDirInOut =3D (0x1 | (0x1 << 3)), ///< Set pad for both out= put and input=0D + GpioDirInInvOut =3D (0x1 | (0x3 << 3)), ///< Set pad for both out= put and input with inversion=0D + GpioDirIn =3D (0x3 | (0x1 << 3)), ///< Set pad for input on= ly=0D + GpioDirInInv =3D (0x3 | (0x3 << 3)), ///< Set pad for input wi= th inversion=0D + GpioDirOut =3D 0x5, ///< Set pad for output o= nly=0D + GpioDirNone =3D 0x7 ///< Disable both output = and input=0D +} GPIO_DIRECTION;=0D +=0D +/**=0D + GPIO Output State=0D + This field is relevant only if output is enabled=0D +**/=0D +typedef enum {=0D + GpioOutDefault =3D 0x0, ///< Leave output value unmodified=0D + GpioOutLow =3D 0x1, ///< Set output to low=0D + GpioOutHigh =3D 0x3 ///< Set output to high=0D +} GPIO_OUTPUT_STATE;=0D +=0D +/**=0D + GPIO interrupt configuration=0D + This setting is applicable only if pad is in GPIO mode and has input ena= bled.=0D + GPIO_INT_CONFIG allows to choose which interrupt is generated (IOxAPIC/S= CI/SMI/NMI)=0D + and how it is triggered (edge or level). Refer to PADCFG_DW0 register de= scription in=0D + EDS for details on this settings.=0D + Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to G= pioIntBothEdge=0D + to describe an interrupt e.g. GpioIntApic | GpioIntLevel=0D + If GPIO is set to cause an SCI then also GPI_GPE_EN is enabled for this = pad.=0D + If GPIO is set to cause an NMI then also GPI_NMI_EN is enabled for this = pad.=0D + Not all GPIO are capable of generating an SMI or NMI interrupt.=0D + When routing GPIO to cause an IOxAPIC interrupt care must be taken, as t= his=0D + interrupt cannot be shared and its IRQn number is not configurable.=0D + Refer to EDS for GPIO pads IRQ numbers (PADCFG_DW1.IntSel)=0D + If GPIO is under GPIO OS driver control and appropriate ACPI GpioInt des= criptor=0D + exist then use only trigger type setting (from GpioIntLevel to GpioIntBo= thEdge).=0D + This type of GPIO Driver interrupt doesn't have any additional routing s= etting=0D + required to be set by BIOS. Interrupt is handled by GPIO OS Driver.=0D +**/=0D +=0D +typedef enum {=0D + GpioIntDefault =3D 0x0, ///< Leave value of interrupt routing= unmodified=0D + GpioIntDis =3D 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI inte= rrupt generation=0D + GpioIntNmi =3D 0x3, ///< Enable NMI interrupt only=0D + GpioIntSmi =3D 0x5, ///< Enable SMI interrupt only=0D + GpioIntSci =3D 0x9, ///< Enable SCI interrupt only=0D + GpioIntApic =3D 0x11, ///< Enable IOxAPIC interrupt only=0D + GpioIntLevel =3D (0x1 << 5), ///< Set interrupt as level triggered= =0D + GpioIntEdge =3D (0x3 << 5), ///< Set interrupt as edge triggered = (type of edge depends on input inversion)=0D + GpioIntLvlEdgDis =3D (0x5 << 5), ///< Disable interrupt trigger=0D + GpioIntBothEdge =3D (0x7 << 5) ///< Set interrupt as both edge trigg= ered=0D +} GPIO_INT_CONFIG;=0D +=0D +#define B_GPIO_INT_CONFIG_INT_SOURCE_MASK 0x1F ///< Mask for GPIO_INT_CON= FIG for interrupt source=0D +#define B_GPIO_INT_CONFIG_INT_TYPE_MASK 0xE0 ///< Mask for GPIO_INT_CON= FIG for interrupt type=0D +=0D +/**=0D + GPIO Power Configuration=0D + GPIO_RESET_CONFIG allows to set GPIO Reset type (PADCFG_DW0.PadRstCfg) w= hich will=0D + be used to reset certain GPIO settings.=0D + Refer to EDS for settings that are controllable by PadRstCfg.=0D +**/=0D +typedef enum {=0D + GpioResetDefault =3D 0x00, ///< Leave value of pad reset unmodi= fied=0D + /**=0D + Resume Reset (RSMRST)=0D + GPP: PadRstCfg =3D 00b =3D "Powergood"=0D + GPD: PadRstCfg =3D 11b =3D "Resume Reset"=0D + Pad setting will reset on:=0D + - DeepSx transition=0D + - G3=0D + Pad settings will not reset on:=0D + - S3/S4/S5 transition=0D + - Warm/Cold/Global reset=0D + **/=0D + GpioResumeReset =3D 0x01,=0D + /**=0D + Host Deep Reset=0D + PadRstCfg =3D 01b =3D "Deep GPIO Reset"=0D + Pad settings will reset on:=0D + - Warm/Cold/Global reset=0D + - DeepSx transition=0D + - G3=0D + Pad settings will not reset on:=0D + - S3/S4/S5 transition=0D + **/=0D + GpioHostDeepReset =3D 0x03,=0D + /**=0D + Platform Reset (PLTRST)=0D + PadRstCfg =3D 10b =3D "GPIO Reset"=0D + Pad settings will reset on:=0D + - S3/S4/S5 transition=0D + - Warm/Cold/Global reset=0D + - DeepSx transition=0D + - G3=0D + **/=0D + GpioPlatformReset =3D 0x05,=0D + /**=0D + Deep Sleep Well Reset (DSW_PWROK)=0D + GPP: not applicable=0D + GPD: PadRstCfg =3D 00b =3D "Powergood"=0D + Pad settings will reset on:=0D + - G3=0D + Pad settings will not reset on:=0D + - S3/S4/S5 transition=0D + - Warm/Cold/Global reset=0D + - DeepSx transition=0D + **/=0D + GpioDswReset =3D 0x07=0D +} GPIO_RESET_CONFIG;=0D +=0D +/**=0D + GPIO Electrical Configuration=0D + Configuration options for GPIO termination setting=0D +**/=0D +typedef enum {=0D + GpioTermDefault =3D 0x0, ///< Leave termination setting unmodi= fied=0D + GpioTermNone =3D 0x1, ///< none=0D + GpioTermWpd5K =3D 0x5, ///< 5kOhm weak pull-down=0D + GpioTermWpd20K =3D 0x9, ///< 20kOhm weak pull-down=0D + GpioTermWpu1K =3D 0x13, ///< 1kOhm weak pull-up=0D + GpioTermWpu2K =3D 0x17, ///< 2kOhm weak pull-up=0D + GpioTermWpu5K =3D 0x15, ///< 5kOhm weak pull-up=0D + GpioTermWpu20K =3D 0x19, ///< 20kOhm weak pull-up=0D + GpioTermWpu1K2K =3D 0x1B, ///< 1kOhm & 2kOhm weak pull-up=0D + /**=0D + Native function controls pads termination=0D + This setting is applicable only to some native modes.=0D + Please check EDS to determine which native functionality=0D + can control pads termination=0D + **/=0D + GpioTermNative =3D 0x1F=0D +} GPIO_ELECTRICAL_CONFIG;=0D +=0D +#define B_GPIO_ELECTRICAL_CONFIG_TERMINATION_MASK 0x1F ///< Mask for = GPIO_ELECTRICAL_CONFIG for termination value=0D +=0D +/**=0D + GPIO LockConfiguration=0D + Set GPIO configuration lock and output state lock.=0D + GpioPadConfigUnlock/Lock and GpioOutputStateUnlock can be OR'ed.=0D + By default GPIO pads will be locked unless GPIO lib is explicitly=0D + informed that certain pad is to be left unlocked.=0D + Lock settings reset is in Powergood domain. Care must be taken when usin= g this setting=0D + as fields it locks may be reset by a different signal and can be control= led=0D + by what is in GPIO_RESET_CONFIG (PADCFG_DW0.PadRstCfg). GPIO library pro= vides=0D + functions which allow to unlock a GPIO pad. If possible each GPIO lib fu= nction will try to unlock=0D + an already locked pad upon request for reconfiguration=0D +**/=0D +typedef enum {=0D + /**=0D + Perform default action=0D + - if pad is an GPO, lock configuration but leave output unlocked=0D + - if pad is an GPI, lock everything=0D + - if pad is in native, lock everything=0D +**/=0D + GpioLockDefault =3D 0x0,=0D + GpioPadConfigUnlock =3D 0x3, ///< Leave Pad configuration unlocked= =0D + GpioPadConfigLock =3D 0x1, ///< Lock Pad configuration=0D + GpioOutputStateUnlock =3D 0xC, ///< Leave Pad output control unlocked= =0D + GpioPadUnlock =3D 0xF, ///< Leave both Pad configuration and = output control unlocked=0D + GpioPadLock =3D 0x5, ///< Lock both Pad configuration and o= utput control=0D + /**=0D + Below statuses are used for=0D + return from GpioGetPadConfig function=0D + **/=0D + GpioLockTxLockCfgUnLock =3D 0x7, ///< Tx State locked, Pad Configuratio= n unlocked=0D + GpioLockTxUnLockCfgLock =3D 0xD ///< Tx State unlocked, Pad Configurat= ion locked=0D +} GPIO_LOCK_CONFIG;=0D +=0D +#define B_GPIO_LOCK_CONFIG_PAD_CONF_LOCK_MASK 0x3 ///< Mask for GPIO_LOC= K_CONFIG for Pad Configuration Lock=0D +#define B_GPIO_LOCK_CONFIG_OUTPUT_LOCK_MASK 0xC ///< Mask for GPIO_LOC= K_CONFIG for Pad Output Lock=0D +=0D +/**=0D + Other GPIO Configuration=0D + GPIO_OTHER_CONFIG is used for less often settings and for future extensi= ons=0D + Supported settings:=0D + - RX raw override to '1' - allows to override input value to '1'=0D + This setting is applicable only if in input mode (both in GPIO and n= ative usage).=0D + The override takes place at the internal pad state directly from buf= fer and before the RXINV.=0D +**/=0D +typedef enum {=0D + GpioRxRaw1Default =3D 0x0, ///< Use default input override va= lue=0D + GpioRxRaw1Dis =3D 0x1, ///< Don't override input=0D + GpioRxRaw1En =3D 0x3 ///< Override input to '1'=0D +} GPIO_OTHER_CONFIG;=0D +=0D +#define B_GPIO_OTHER_CONFIG_RXRAW_MASK 0x3 ///< Mask for GPIO_= OTHER_CONFIG for RxRaw1 setting=0D +=0D +#pragma pack(pop)=0D +=0D +#endif //_GPIO_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h b/= Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h new file mode 100644 index 0000000000..5b3cf502a0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioLib.h @@ -0,0 +1,720 @@ +/** @file=0D + Header file for GpioLib.=0D + All function in this library is available for PEI, DXE, and SMM=0D +=0D + @note: When GPIO pads are owned by ME Firmware, BIOS/host should not=0D + attempt to access these GPIO Pads registers, registers value=0D + returned in this case will be 0xFF.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_LIB_H_=0D +#define _GPIO_LIB_H_=0D +=0D +#include =0D +=0D +#define GPIO_NAME_LENGTH_MAX 32=0D +=0D +typedef struct {=0D + GPIO_PAD GpioPad;=0D + GPIO_CONFIG GpioConfig;=0D +} GPIO_INIT_CONFIG;=0D +=0D +/**=0D + This procedure will initialize multiple GPIO pins. Use GPIO_INIT_CONFIG = structure.=0D + Structure contains fields that can be used to configure each pad.=0D + Pad not configured using GPIO_INIT_CONFIG will be left with hardware def= ault values.=0D + Separate fields could be set to hardware default if it does not matter, = except=0D + GpioPad and PadMode.=0D + Function will work in most efficient way if pads which belong to the sam= e group are=0D + placed in adjacent records of the table.=0D + Although function can enable pads for Native mode, such programming is d= one=0D + by reference code when enabling related silicon feature.=0D +=0D + @param[in] NumberofItem Number of GPIO pads to be updated= =0D + @param[in] GpioInitTableAddress GPIO initialization table=0D +=0D + @retval EFI_SUCCESS The function completed successfull= y=0D + @retval EFI_INVALID_PARAMETER Invalid group or pad number=0D +**/=0D +EFI_STATUS=0D +GpioConfigurePads (=0D + IN UINT32 NumberOfItems,=0D + IN GPIO_INIT_CONFIG *GpioInitTableAddress=0D + );=0D +=0D +//=0D +// Functions for setting/getting multiple GpioPad settings=0D +//=0D +=0D +/**=0D + This procedure will read multiple GPIO settings=0D +=0D + @param[in] GpioPad GPIO Pad=0D + @param[out] GpioData GPIO data structure=0D +=0D + @retval EFI_SUCCESS The function completed successfull= y=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadConfig (=0D + IN GPIO_PAD GpioPad,=0D + OUT GPIO_CONFIG *GpioData=0D + );=0D +=0D +/**=0D + This procedure will configure multiple GPIO settings=0D +=0D + @param[in] GpioPad GPIO Pad=0D + @param[in] GpioData GPIO data structure=0D +=0D + @retval EFI_SUCCESS The function completed successfull= y=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetPadConfig (=0D + IN GPIO_PAD GpioPad,=0D + IN GPIO_CONFIG *GpioData=0D + );=0D +=0D +//=0D +// Functions for setting/getting single GpioPad properties=0D +//=0D +=0D +/**=0D + This procedure will set GPIO output level=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Output value=0D + 0: OutputLow, 1: OutputHigh=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetOutputValue (=0D + IN GPIO_PAD GpioPad,=0D + IN UINT32 Value=0D + );=0D +=0D +/**=0D + This procedure will get GPIO output level=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] OutputVal GPIO Output value=0D + 0: OutputLow, 1: OutputHigh=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetOutputValue (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *OutputVal=0D + );=0D +=0D +/**=0D + This procedure will get GPIO input level=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] InputVal GPIO Input value=0D + 0: InputLow, 1: InputHigh=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetInputValue (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *InputVal=0D + );=0D +=0D +/**=0D + This procedure will get GPIO IOxAPIC interrupt number=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] IrqNum IRQ number=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadIoApicIrqNumber (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *IrqNum=0D + );=0D +=0D +/**=0D + This procedure will configure GPIO input inversion=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Value for GPIO input inversion=0D + 0: No input inversion, 1: Invert input=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetInputInversion (=0D + IN GPIO_PAD GpioPad,=0D + IN UINT32 Value=0D + );=0D +=0D +/**=0D + This procedure will get GPIO pad input inversion value=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] InvertState GPIO inversion state=0D + 0: No input inversion, 1: Inverted input= =0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetInputInversion (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *InvertState=0D + );=0D +=0D +/**=0D + This procedure will set GPIO interrupt settings=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Value of Level/Edge=0D + use GPIO_INT_CONFIG as argument=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetPadInterruptConfig (=0D + IN GPIO_PAD GpioPad,=0D + IN GPIO_INT_CONFIG Value=0D + );=0D +=0D +/**=0D + This procedure will set GPIO electrical settings=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Value of termination=0D + use GPIO_ELECTRICAL_CONFIG as argument=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetPadElectricalConfig (=0D + IN GPIO_PAD GpioPad,=0D + IN GPIO_ELECTRICAL_CONFIG Value=0D + );=0D +=0D +/**=0D + This procedure will set GPIO Reset settings=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Value for Pad Reset Configuration=0D + use GPIO_RESET_CONFIG as argument=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetPadResetConfig (=0D + IN GPIO_PAD GpioPad,=0D + IN GPIO_RESET_CONFIG Value=0D + );=0D +=0D +/**=0D + This procedure will get GPIO Reset settings=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] Value Value of Pad Reset Configuration=0D + based on GPIO_RESET_CONFIG=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadResetConfig (=0D + IN GPIO_PAD GpioPad,=0D + IN GPIO_RESET_CONFIG *Value=0D + );=0D +=0D +/**=0D + This procedure will get Gpio Pad Host Software Ownership=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] PadHostSwOwn Value of Host Software Pad Owner=0D + 0: ACPI Mode, 1: GPIO Driver mode=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetHostSwOwnershipForPad (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *PadHostSwOwn=0D + );=0D +=0D +/**=0D + This procedure will set Gpio Pad Host Software Ownership=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[in] PadHostSwOwn Pad Host Software Owner=0D + 0: ACPI Mode, 1: GPIO Driver mode=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioSetHostSwOwnershipForPad (=0D + IN GPIO_PAD GpioPad,=0D + IN UINT32 PadHostSwOwn=0D + );=0D +=0D +///=0D +/// Possible values of Pad Ownership=0D +/// If Pad is not under Host ownership then GPIO registers=0D +/// are not accessible by host (e.g. BIOS) and reading them=0D +/// will return 0xFFs.=0D +///=0D +typedef enum {=0D + GpioPadOwnHost =3D 0x0,=0D + GpioPadOwnCsme =3D 0x1,=0D + GpioPadOwnIsh =3D 0x2,=0D +} GPIO_PAD_OWN;=0D +=0D +/**=0D + This procedure will get Gpio Pad Ownership=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] PadOwnVal Value of Pad Ownership=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadOwnership (=0D + IN GPIO_PAD GpioPad,=0D + OUT GPIO_PAD_OWN *PadOwnVal=0D + );=0D +=0D +/**=0D + This procedure will check state of Pad Config Lock for pads within one g= roup=0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLock register number for current g= roup.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[out] PadCfgLockRegVal Value of PadCfgLock register=0D + Bit position - PadNumber=0D + Bit value - 0: NotLocked, 1: Locked=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number= =0D +**/=0D +EFI_STATUS=0D +GpioGetPadCfgLockForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + OUT UINT32 *PadCfgLockRegVal=0D + );=0D +=0D +/**=0D + This procedure will check state of Pad Config Lock for selected pad=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] PadCfgLock PadCfgLock for selected pad=0D + 0: NotLocked, 1: Locked=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadCfgLock (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *PadCfgLock=0D + );=0D +=0D +/**=0D + This procedure will check state of Pad Config Tx Lock for pads within on= e group=0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLockTx register number for current= group.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[out] PadCfgLockTxRegVal Value of PadCfgLockTx register=0D + Bit position - PadNumber=0D + Bit value - 0: NotLockedTx, 1: LockedTx= =0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number= =0D +**/=0D +EFI_STATUS=0D +GpioGetPadCfgLockTxForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + OUT UINT32 *PadCfgLockTxRegVal=0D + );=0D +=0D +/**=0D + This procedure will check state of Pad Config Tx Lock for selected pad=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] PadCfgLock PadCfgLockTx for selected pad=0D + 0: NotLockedTx, 1: LockedTx=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetPadCfgLockTx (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *PadCfgLockTx=0D + );=0D +=0D +/**=0D + This procedure will clear PadCfgLock for selected pads within one group.= =0D + Unlocking a pad will cause an SMI (if enabled)=0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLock register number for current g= roup.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[in] PadsToUnlock Bitmask for pads which are going to be u= nlocked,=0D + Bit position - PadNumber=0D + Bit value - 0: DoNotUnlock, 1: Unlock=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or pad number=0D +**/=0D +EFI_STATUS=0D +GpioUnlockPadCfgForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + IN UINT32 PadsToUnlock=0D + );=0D +=0D +/**=0D + This procedure will clear PadCfgLock for selected pad.=0D + Unlocking a pad will cause an SMI (if enabled)=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioUnlockPadCfg (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will set PadCfgLock for selected pads within one group=0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLock register number for current g= roup.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[in] PadsToLock Bitmask for pads which are going to be l= ocked,=0D + Bit position - PadNumber=0D + Bit value - 0: DoNotLock, 1: Lock=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number= =0D +**/=0D +EFI_STATUS=0D +GpioLockPadCfgForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + IN UINT32 PadsToLock=0D + );=0D +=0D +/**=0D + This procedure will set PadCfgLock for selected pad=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioLockPadCfg (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will clear PadCfgLockTx for selected pads within one grou= p.=0D + Unlocking a pad will cause an SMI (if enabled)=0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLockTx register number for current= group.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[in] PadsToUnlockTx Bitmask for pads which are going to be u= nlocked,=0D + Bit position - PadNumber=0D + Bit value - 0: DoNotUnLockTx, 1: LockTx= =0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or pad number=0D +**/=0D +EFI_STATUS=0D +GpioUnlockPadCfgTxForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + IN UINT32 PadsToUnlockTx=0D + );=0D +=0D +/**=0D + This procedure will clear PadCfgLockTx for selected pad.=0D + Unlocking a pad will cause an SMI (if enabled)=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioUnlockPadCfgTx (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will set PadCfgLockTx for selected pads within one group= =0D +=0D + @param[in] Group GPIO group=0D + @param[in] DwNum PadCfgLock register number for current g= roup.=0D + For group which has less then 32 pads pe= r group DwNum must be 0.=0D + @param[in] PadsToLockTx Bitmask for pads which are going to be l= ocked,=0D + Bit position - PadNumber=0D + Bit value - 0: DoNotLockTx, 1: LockTx=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or DwNum parameter number= =0D +**/=0D +EFI_STATUS=0D +GpioLockPadCfgTxForGroupDw (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 DwNum,=0D + IN UINT32 PadsToLockTx=0D + );=0D +=0D +/**=0D + This procedure will set PadCfgLockTx for selected pad=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioLockPadCfgTx (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will get Group to GPE mapping.=0D + It will assume that only first 32 pads can be mapped to GPE.=0D + To handle cases where groups have more than 32 pads and higher part of g= roup=0D + can be mapped please refer to GpioGetGroupDwToGpeDwX()=0D +=0D + @param[out] GroupToGpeDw0 GPIO group to be mapped to GPE_DW0=0D + @param[out] GroupToGpeDw1 GPIO group to be mapped to GPE_DW1=0D + @param[out] GroupToGpeDw2 GPIO group to be mapped to GPE_DW2=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or pad number=0D +**/=0D +EFI_STATUS=0D +GpioGetGroupToGpeDwX (=0D + IN GPIO_GROUP *GroupToGpeDw0,=0D + IN GPIO_GROUP *GroupToGpeDw1,=0D + IN GPIO_GROUP *GroupToGpeDw2=0D + );=0D +=0D +/**=0D + This procedure will get Group to GPE mapping. If group has more than 32 = bits=0D + it is possible to map only single DW of pins (e.g. 0-31, 32-63) because= =0D + ACPI GPE_DWx register is 32 bits large.=0D +=0D + @param[out] GroupToGpeDw0 GPIO group mapped to GPE_DW0=0D + @param[out] GroupDwForGpeDw0 DW of pins mapped to GPE_DW0=0D + @param[out] GroupToGpeDw1 GPIO group mapped to GPE_DW1=0D + @param[out] GroupDwForGpeDw1 DW of pins mapped to GPE_DW1=0D + @param[out] GroupToGpeDw2 GPIO group mapped to GPE_DW2=0D + @param[out] GroupDwForGpeDw2 DW of pins mapped to GPE_DW2=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid group or pad number=0D +**/=0D +EFI_STATUS=0D +GpioGetGroupDwToGpeDwX (=0D + OUT GPIO_GROUP *GroupToGpeDw0,=0D + OUT UINT32 *GroupDwForGpeDw0,=0D + OUT GPIO_GROUP *GroupToGpeDw1,=0D + OUT UINT32 *GroupDwForGpeDw1,=0D + OUT GPIO_GROUP *GroupToGpeDw2,=0D + OUT UINT32 *GroupDwForGpeDw2=0D + );=0D +=0D +/**=0D + This procedure will get GPE number for provided GpioPad.=0D + PCH allows to configure mapping between GPIO groups and related GPE (Gpi= oSetGroupToGpeDwX())=0D + what results in the fact that certain Pad can cause different General Pu= rpose Event. Only three=0D + GPIO groups can be mapped to cause unique GPE (1-tier), all others group= s will be under one common=0D + event (GPE_111 for 2-tier).=0D +=0D + 1-tier:=0D + Returned GpeNumber is in range <0,95>. GpioGetGpeNumber() can be used=0D + to determine what _LXX ACPI method would be called on event on selected = GPIO pad=0D +=0D + 2-tier:=0D + Returned GpeNumber is 0x6F (111). All GPIO pads which are not mapped to = 1-tier GPE=0D + will be under one master GPE_111 which is linked to _L6F ACPI method. If= it is needed to determine=0D + what Pad from 2-tier has caused the event, _L6F method should check GPI_= GPE_STS and GPI_GPE_EN=0D + registers for all GPIO groups not mapped to 1-tier GPE.=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] GpeNumber GPE number=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetGpeNumber (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINT32 *GpeNumber=0D + );=0D +=0D +/**=0D + This procedure is used to clear SMI STS for a specified Pad=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioClearGpiSmiSts (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure is used by Smi Dispatcher and will clear=0D + all GPI SMI Status bits=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D +**/=0D +EFI_STATUS=0D +GpioClearAllGpiSmiSts (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure is used to disable all GPI SMI=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D +**/=0D +EFI_STATUS=0D +GpioDisableAllGpiSmi (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure is used to register GPI SMI dispatch function.=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] GpiNum GPI number=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetGpiSmiNum (=0D + IN GPIO_PAD GpioPad,=0D + OUT UINTN *GpiNum=0D + );=0D +=0D +/**=0D + This procedure is used to check GPIO inputs belongs to 2 tier or 1 tier = architecture=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval Data 0 means 1-tier, 1 means 2-tier=0D +**/=0D +BOOLEAN=0D +GpioCheckFor2Tier (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure is used to clear GPE STS for a specified GpioPad=0D +=0D + @param[in] GpioPad GPIO pad=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioClearGpiGpeSts (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure is used to read GPE STS for a specified Pad=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] GpeSts Gpe status for given pad=0D + The GpeSts is true if the status registe= r is set for given Pad number=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetGpiGpeSts (=0D + IN GPIO_PAD GpioPad,=0D + OUT BOOLEAN *GpeSts=0D + );=0D +=0D +/**=0D + This procedure is used to get SMI STS for a specified Pad=0D +=0D + @param[in] GpioPad GPIO pad=0D + @param[out] SmiSts Smi status for given pad=0D + The SmiSts is true if the status registe= r is set for given Pad number=0D +=0D + @retval EFI_SUCCESS The function completed successfully=0D + @retval EFI_INVALID_PARAMETER Invalid GpioPad=0D +**/=0D +EFI_STATUS=0D +GpioGetGpiSmiSts (=0D + IN GPIO_PAD GpioPad,=0D + OUT BOOLEAN *SmiSts=0D + );=0D +=0D +/**=0D + Generates GPIO name from GpioPad=0D +=0D + @param[in] GpioPad GpioPad=0D + @param[out] GpioNameBuffer Caller allocated buffer for GPIO name of= GPIO_NAME_LENGTH_MAX size=0D + @param[in] GpioNameBufferSize Size of the buffer=0D +=0D + @retval CHAR8* Pointer to the GPIO name=0D +**/=0D +CHAR8*=0D +GpioGetPadName (=0D + IN GPIO_PAD GpioPad,=0D + OUT CHAR8* GpioNameBuffer,=0D + IN UINT32 GpioNameBufferSize=0D + );=0D +=0D +/**=0D + Generates GPIO group name from GroupIndex=0D +=0D + @param[in] GroupIndex Gpio GroupIndex=0D +=0D + @retval CHAR8* Pointer to the GPIO group name=0D +**/=0D +CONST=0D +CHAR8*=0D +GpioGetGroupName (=0D + IN UINT32 GroupIndex=0D + );=0D +=0D +#endif // _GPIO_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLi= b.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h new file mode 100644 index 0000000000..b09600dd30 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/GpioNativeLib.h @@ -0,0 +1,149 @@ +/** @file=0D + Header file for GpioLib for native and Si specific usage.=0D + All function in this library is available for PEI, DXE, and SMM,=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_NATIVE_LIB_H_=0D +#define _GPIO_NATIVE_LIB_H_=0D +=0D +#include =0D +=0D +/**=0D + This procedure will get number of pads for certain GPIO group=0D +=0D + @param[in] Group GPIO group number=0D +=0D + @retval Value Pad number for group=0D + If illegal group number then return 0=0D +**/=0D +UINT32=0D +GpioGetPadPerGroup (=0D + IN GPIO_GROUP Group=0D + );=0D +=0D +/**=0D + This procedure will get number of groups=0D +=0D + @param[in] none=0D +=0D + @retval Value Group number=0D +**/=0D +UINT32=0D +GpioGetNumberOfGroups (=0D + VOID=0D + );=0D +/**=0D + This procedure will get lowest group=0D +=0D + @param[in] none=0D +=0D + @retval Value Lowest Group=0D +**/=0D +GPIO_GROUP=0D +GpioGetLowestGroup (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will get highest group=0D +=0D + @param[in] none=0D +=0D + @retval Value Highest Group=0D +**/=0D +GPIO_GROUP=0D +GpioGetHighestGroup (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will get group=0D +=0D + @param[in] GpioPad Gpio Pad=0D +=0D + @retval Value Group=0D +**/=0D +GPIO_GROUP=0D +GpioGetGroupFromGpioPad (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will get group index (0 based) from GpioPad=0D +=0D + @param[in] GpioPad Gpio Pad=0D +=0D + @retval Value Group Index=0D +**/=0D +UINT32=0D +GpioGetGroupIndexFromGpioPad (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will get group index (0 based) from group=0D +=0D + @param[in] GpioGroup Gpio Group=0D +=0D + @retval Value Group Index=0D +**/=0D +UINT32=0D +GpioGetGroupIndexFromGroup (=0D + IN GPIO_GROUP GpioGroup=0D + );=0D +=0D +/**=0D + This procedure will get group from group index (0 based)=0D +=0D + @param[in] GroupIndex Group Index=0D +=0D + @retval GpioGroup Gpio Group=0D +**/=0D +GPIO_GROUP=0D +GpioGetGroupFromGroupIndex (=0D + IN UINT32 GroupIndex=0D + );=0D +=0D +/**=0D + This procedure will get pad number (0 based) from Gpio Pad=0D +=0D + @param[in] GpioPad Gpio Pad=0D +=0D + @retval Value Pad Number=0D +**/=0D +UINT32=0D +GpioGetPadNumberFromGpioPad (=0D + IN GPIO_PAD GpioPad=0D + );=0D +=0D +/**=0D + This procedure will return GpioPad from Group and PadNumber=0D +=0D + @param[in] Group GPIO group=0D + @param[in] PadNumber GPIO PadNumber=0D +=0D + @retval GpioPad GpioPad=0D +**/=0D +GPIO_PAD=0D +GpioGetGpioPadFromGroupAndPadNumber (=0D + IN GPIO_GROUP Group,=0D + IN UINT32 PadNumber=0D + );=0D +=0D +/**=0D + This procedure will return GpioPad from GroupIndex and PadNumber=0D +=0D + @param[in] GroupIndex GPIO GroupIndex=0D + @param[in] PadNumber GPIO PadNumber=0D +=0D + @retval GpioPad GpioPad=0D +**/=0D +GPIO_PAD=0D +GpioGetGpioPadFromGroupIndexAndPadNumber (=0D + IN UINT32 GroupIndex,=0D + IN UINT32 PadNumber=0D + );=0D +=0D +#endif // _GPIO_NATIVE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h b= /Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h new file mode 100644 index 0000000000..a53887ffcb --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/MmPciLib.h @@ -0,0 +1,27 @@ +/** @file=0D + Get Pci Express address library implementation.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _MM_PCI_LIB_H_=0D +#define _MM_PCI_LIB_H_=0D +=0D +/**=0D + This procedure will get PCIE address=0D +=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D +=0D + @retval PCIE address=0D +**/=0D +UINTN=0D +EFIAPI=0D +MmPciBase (=0D + IN UINT32 Bus,=0D + IN UINT32 Device,=0D + IN UINT32 Function=0D +);=0D +=0D +#endif // _PEI_DXE_SMM_MM_PCI_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib= .h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h new file mode 100644 index 0000000000..3c46029b7f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcieRpLib.h @@ -0,0 +1,123 @@ +/** @file=0D + Header file for PchPcieRpLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCIERP_LIB_H_=0D +#define _PCH_PCIERP_LIB_H_=0D +=0D +#include =0D +=0D +/**=0D + PCIe controller bifurcation configuration.=0D +**/=0D +typedef enum {=0D + PcieBifurcationDefault =3D 0,=0D + PcieBifurcation4x1,=0D + PcieBifurcation1x2_2x1,=0D + PcieBifurcation2x2,=0D + PcieBifurcation1x4,=0D + PcieBifurcation4x2,=0D + PcieBifurcation1x4_2x2,=0D + PcieBifurcation2x2_1x4,=0D + PcieBifurcation2x4,=0D + PcieBifurcation1x8,=0D + PcieBifurcationUnknown,=0D + PcieBifurcationMax=0D +} PCIE_BIFURCATION_CONFIG;=0D +=0D +/**=0D + This function returns PID according to PCIe controller index=0D +=0D + @param[in] ControllerIndex PCIe controller index=0D +=0D + @retval PCH_SBI_PID Returns PID for SBI Access=0D +**/=0D +PCH_SBI_PID=0D +PchGetPcieControllerSbiPid (=0D + IN UINT32 ControllerIndex=0D + );=0D +=0D +/**=0D + This function returns PID according to Root Port Number=0D +=0D + @param[in] RpIndex Root Port Index (0-based)=0D +=0D + @retval PCH_SBI_PID Returns PID for SBI Access=0D +**/=0D +PCH_SBI_PID=0D +GetRpSbiPid (=0D + IN UINTN RpIndex=0D + );=0D +=0D +/**=0D + Get Pch Pcie Root Port Device and Function Number by Root Port physical = Number=0D +=0D + @param[in] RpNumber Root port physical number. (0-based)=0D + @param[out] RpDev Return corresponding root port device nu= mber.=0D + @param[out] RpFun Return corresponding root port function = number.=0D +=0D + @retval EFI_SUCCESS=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPchPcieRpDevFun (=0D + IN UINTN RpNumber,=0D + OUT UINTN *RpDev,=0D + OUT UINTN *RpFun=0D + );=0D +=0D +/**=0D + Get Root Port physical Number by Pch Pcie Root Port Device and Function = Number=0D +=0D + @param[in] RpDev Root port device number.=0D + @param[in] RpFun Root port function number.=0D + @param[out] RpNumber Return corresponding physical Root Por= t index (0-based)=0D +=0D + @retval EFI_SUCCESS Physical root port is retrieved=0D + @retval EFI_INVALID_PARAMETER RpDev and/or RpFun are invalid=0D + @retval EFI_UNSUPPORTED Root port device and function is not a= ssigned to any physical root port=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPchPcieRpNumber (=0D + IN UINTN RpDev,=0D + IN UINTN RpFun,=0D + OUT UINTN *RpNumber=0D + );=0D +=0D +/**=0D + Gets pci segment base address of PCIe root port.=0D +=0D + @param RpIndex Root Port Index (0 based)=0D + @return PCIe port base address.=0D +**/=0D +UINT64=0D +PchPcieBase (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Determines whether L0s is supported on current stepping.=0D +=0D + @return TRUE if L0s is supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +PchIsPcieL0sSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Some early PCH steppings require Native ASPM to be disabled due to hardw= are issues:=0D + - RxL0s exit causes recovery=0D + - Disabling PCIe L0s capability disables L1=0D + Use this function to determine affected steppings.=0D +=0D + @return TRUE if Native ASPM is supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +PchIsPcieNativeAspmSupported (=0D + VOID=0D + );=0D +#endif // _PCH_PCIERP_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h = b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h new file mode 100644 index 0000000000..f46c3da0e1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PchPcrLib.h @@ -0,0 +1,256 @@ +/** @file=0D + Header file for PchPcrLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCR_LIB_H_=0D +#define _PCH_PCR_LIB_H_=0D +=0D +#include =0D +=0D +/**=0D + Definition for PCR address=0D + The PCR address is used to the PCR MMIO programming=0D +=0D + SBREG_BAR_20BITADDRESS is configured by SoC=0D +=0D + SBREG_BAR_20BITADDRESS=3D1, the format has included 16b addressing.=0D + +-----------------------------------------------------------------------= ----------------------+=0D + | Addr[63:28] | Addr[27:24] | Addr[23:16] | Addr[15:2] = | Addr[1:0] |=0D + +----------------+-----------------------+-----------------+------------= ----------------------+=0D + | REG_BAR[63:28] | TargetRegister[19:16] | TargetPort[7:0] | TargetRegis= ter[15:2] |=0D + +-----------------------------------------------------------------------= ----------------------+=0D +=0D + SBREG_BAR_20BITADDRESS=3D0=0D + +-----------------------------------------------------------------------= ----------------------+=0D + | Addr[63:24] | Addr[27:24] | Addr[23:16] | Addr[15:2] = | Addr[1:0] |=0D + +----------------+-----------------------+-----------------+------------= ----------------------+=0D + | REG_BAR[63:24] | REG_BAR[27:24] | TargetPort[7:0] | TargetRegis= ter[15:2] |=0D + +-----------------------------------------------------------------------= ----------------------+=0D +**/=0D +#define PCH_PCR_ADDRESS(Pid, Offset) (PCH_PCR_BASE_ADDRESS | (UINT32) (= ((Offset) & 0x0F0000) << 8) | ((UINT8)(Pid) << 16) | (UINT16) ((Offset) & 0= xFFFF))=0D +=0D +/**=0D + PCH PCR boot script accessing macro=0D + Those macros are only available for DXE phase.=0D +**/=0D +#define PCH_PCR_BOOT_SCRIPT_WRITE(Width, Pid, Offset, Count, Buffer) \=0D + S3BootScriptSaveMemWrite (Width, PCH_PCR_ADDRESS (Pid, Offset), = Count, Buffer); \=0D +=0D +#define PCH_PCR_BOOT_SCRIPT_READ_WRITE(Width, Pid, Offset, DataOr, DataAnd= ) \=0D + S3BootScriptSaveMemReadWrite (Width, PCH_PCR_ADDRESS (Pid, Offse= t), DataOr, DataAnd); \=0D +=0D +#define PCH_PCR_BOOT_SCRIPT_READ(Width, Pid, Offset, BitMask, BitValue) \= =0D + S3BootScriptSaveMemPoll (Width, PCH_PCR_ADDRESS (Pid, Offset), B= itMask, BitValue, 1, 1);=0D +=0D +typedef UINT8 PCH_SBI_PID;=0D +=0D +/**=0D + Read PCR register.=0D + It returns PCR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT32 PCR register value.=0D +**/=0D +UINT32=0D +PchPcrRead32 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset=0D + );=0D +=0D +/**=0D + Read PCR register.=0D + It returns PCR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT16 PCR register value.=0D +**/=0D +UINT16=0D +PchPcrRead16 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset=0D + );=0D +=0D +/**=0D + Read PCR register.=0D + It returns PCR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of this Port ID=0D +=0D + @retval UINT8 PCR register value=0D +**/=0D +UINT8=0D +PchPcrRead8 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size parameter= .=0D +=0D + @retval UINT32 Value written to register=0D +**/=0D +UINT32=0D +PchPcrWrite32 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT32 InData=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size parameter= .=0D +=0D + @retval UINT16 Value written to register=0D +**/=0D +UINT16=0D +PchPcrWrite16 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT16 InData=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] Data Input Data. Must be the same size as Size parameter= .=0D +=0D + @retval UINT8 Value written to register=0D +**/=0D +UINT8=0D +PchPcrWrite8 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT8 InData=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size parameter.= =0D + @param[in] OrData OR Data. Must be the same size as Size parameter.=0D +=0D + @retval UINT32 Value written to register=0D +=0D +**/=0D +UINT32=0D +PchPcrAndThenOr32 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D + Write PCR register and read back.=0D + The read back ensures the PCR cycle is completed before next operation.= =0D + It programs PCR register and size in 4bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size parameter.= =0D + @param[in] OrData OR Data. Must be the same size as Size parameter.=0D +=0D + @retval UINT32 Value read back from the register=0D +**/=0D +UINT32=0D +PchPcrAndThenOr32WithReadback (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 2bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size parameter.= =0D + @param[in] OrData OR Data. Must be the same size as Size parameter.=0D +=0D + @retval UINT16 Value written to register=0D +=0D +**/=0D +UINT16=0D +PchPcrAndThenOr16 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + );=0D +=0D +/**=0D + Write PCR register.=0D + It programs PCR register and size in 1bytes.=0D + The Offset should not exceed 0xFFFF and must be aligned with size.=0D +=0D + @param[in] Pid Port ID=0D + @param[in] Offset Register offset of Port ID.=0D + @param[in] AndData AND Data. Must be the same size as Size parameter.= =0D + @param[in] OrData OR Data. Must be the same size as Size parameter.=0D +=0D + @retval UINT8 Value written to register=0D +=0D +**/=0D +UINT8=0D +PchPcrAndThenOr8 (=0D + IN PCH_SBI_PID Pid,=0D + IN UINT32 Offset,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + );=0D +=0D +=0D +typedef enum {=0D + PchIpDmi =3D 1,=0D + PchIpIclk,=0D +} PCH_IP_PID_ENUM;=0D +=0D +#define PCH_INVALID_PID 0=0D +=0D +/**=0D + Get PCH IP PID number=0D +=0D + @param[in] IpEnum PCH IP in PCH_IP_PID_ENUM=0D +=0D + @retval 0 PID of this IP is not supported=0D + !0 PID of the IP.=0D +**/=0D +PCH_SBI_PID=0D +PchPcrGetPid (=0D + PCH_IP_PID_ENUM IpEnum=0D + );=0D +=0D +#endif // _PCH_PCR_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLi= b.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h new file mode 100644 index 0000000000..8ab20f0db7 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PcieHelperLib.h @@ -0,0 +1,173 @@ +/** @file=0D + Header file for PCI Express helpers base library=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCIE_HELPER_LIB_H_=0D +#define _PCIE_HELPER_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Find the Offset to a given Capabilities ID=0D + CAPID list:=0D + 0x01 =3D PCI Power Management Interface=0D + 0x04 =3D Slot Identification=0D + 0x05 =3D MSI Capability=0D + 0x10 =3D PCI Express Capability=0D +=0D + @param[in] DeviceBase device's base address=0D + @param[in] CapId CAPID to search for=0D +=0D + @retval 0 CAPID not found=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT8=0D +PcieBaseFindCapId (=0D + IN UINT64 DeviceBase,=0D + IN UINT8 CapId=0D + );=0D +=0D +/**=0D + Find the Offset to a given Capabilities ID=0D + CAPID list:=0D + 0x01 =3D PCI Power Management Interface=0D + 0x04 =3D Slot Identification=0D + 0x05 =3D MSI Capability=0D + 0x10 =3D PCI Express Capability=0D +=0D + @param[in] Segment Pci Segment Number=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D + @param[in] CapId CAPID to search for=0D +=0D + @retval 0 CAPID not found=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT8=0D +PcieFindCapId (=0D + IN UINT8 Segment,=0D + IN UINT8 Bus,=0D + IN UINT8 Device,=0D + IN UINT8 Function,=0D + IN UINT8 CapId=0D + );=0D +=0D +/**=0D + Search and return the offset of desired Pci Express Capability ID=0D + CAPID list:=0D + 0x0001 =3D Advanced Error Reporting Capability=0D + 0x0002 =3D Virtual Channel Capability=0D + 0x0003 =3D Device Serial Number Capability=0D + 0x0004 =3D Power Budgeting Capability=0D +=0D + @param[in] DeviceBase device base address=0D + @param[in] CapId Extended CAPID to search for=0D +=0D + @retval 0 CAPID not found, this includes situation= where device doesn't exist=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT16=0D +PcieBaseFindExtendedCapId (=0D + IN UINT64 DeviceBase,=0D + IN UINT16 CapId=0D + );=0D +=0D +/**=0D + Search and return the offset of desired Pci Express Capability ID=0D + CAPID list:=0D + 0x0001 =3D Advanced Error Rreporting Capability=0D + 0x0002 =3D Virtual Channel Capability=0D + 0x0003 =3D Device Serial Number Capability=0D + 0x0004 =3D Power Budgeting Capability=0D +=0D + @param[in] Segment Pci Segment Number=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D + @param[in] CapId Extended CAPID to search for=0D +=0D + @retval 0 CAPID not found=0D + @retval Other CAPID found, Offset of desired CAPID=0D +**/=0D +UINT16=0D +PcieFindExtendedCapId (=0D + IN UINT8 Segment,=0D + IN UINT8 Bus,=0D + IN UINT8 Device,=0D + IN UINT8 Function,=0D + IN UINT16 CapId=0D + );=0D +=0D +/*=0D + Checks device's Slot Clock Configuration=0D +=0D + @param[in] Base device's base address=0D + @param[in] PcieCapOffset devices Pci express capability list register = offset=0D +=0D + @retval TRUE when device device uses slot clock, FALSE otherwise=0D +*/=0D +BOOLEAN=0D +GetScc (=0D + UINT64 Base,=0D + UINT8 PcieCapOffset=0D + );=0D +=0D +/*=0D + Sets Common Clock Configuration bit for given device.=0D + @param[in] PcieCapOffset devices Pci express capability list register = offset=0D + @param[in] Base device's base address=0D +*/=0D +VOID=0D +EnableCcc (=0D + UINT64 Base,=0D + UINT8 PcieCapOffset=0D + );=0D +=0D +/*=0D + Retrains link behind given device.=0D + It only makes sense to call it for downstream ports.=0D + If called for upstream port nothing will happen, it won't enter infinite= loop.=0D +=0D + @param[in] Base device's base address=0D + @param[in] PcieCapOffset devices Pci express capability list regi= ster offset=0D + @param[boolean] WaitUnitlDone when TRUE, function waits until link has= retrained=0D +*/=0D +VOID=0D +RetrainLink (=0D + UINT64 Base,=0D + UINT8 PcieCapOffset,=0D + BOOLEAN WaitUntilDone=0D + );=0D +=0D +/*=0D + Checks if device at given address exists=0D +=0D + @param[in] Base device's base address=0D +=0D + @retval TRUE when device exists; FALSE otherwise=0D +*/=0D +BOOLEAN=0D +IsDevicePresent (=0D + UINT64 Base=0D + );=0D +=0D +/*=0D + Checks if device is a multifunction device=0D +=0D + @param[in] Base device's base address=0D +=0D + @retval TRUE if multifunction; FALSE otherwise=0D +*/=0D +BOOLEAN=0D +IsMultifunctionDevice (=0D + UINT64 Base=0D + );=0D +#endif // _PCIE_HELPER_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h b/S= ilicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h new file mode 100644 index 0000000000..0b8ad7a182 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/PmcLib.h @@ -0,0 +1,355 @@ +/** @file=0D + Header file for PmcLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PMC_LIB_H_=0D +#define _PMC_LIB_H_=0D +=0D +#pragma pack(1)=0D +=0D +typedef enum {=0D + PmcTPch25_10us =3D 0,=0D + PmcTPch25_100us,=0D + PmcTPch25_1ms,=0D + PmcTPch25_10ms,=0D +} PMC_TPCH25_TIMING;=0D +=0D +typedef enum {=0D + PmcNotASleepState,=0D + PmcInS0State,=0D + PmcS1SleepState,=0D + PmcS2SleepState,=0D + PmcS3SleepState,=0D + PmcS4SleepState,=0D + PmcS5SleepState,=0D + PmcUndefinedState,=0D +} PMC_SLEEP_STATE;=0D +=0D +typedef struct {=0D + UINT32 Buf0;=0D + UINT32 Buf1;=0D + UINT32 Buf2;=0D + UINT32 Buf3;=0D +} PMC_IPC_COMMAND_BUFFER;=0D +=0D +//=0D +// Structure to Check different attributes for CrashLog supported by PMC.= =0D +//=0D +typedef union {=0D + struct {=0D + UINT32 Avail : 1; ///< CrashLog feature availability bit= =0D + UINT32 Dis : 1; ///< CrasLog Disable bit=0D + UINT32 Rsvd : 2; ///< Reserved=0D + UINT32 Size : 12; ///< CrasLog data size. (If it is zero,= use default size 0xC00)=0D + UINT32 BaseOffset : 16; ///< Start offset of CrashLog in PMC SS= RAM=0D + } Bits;=0D + struct {=0D + UINT32 Avail : 1; ///< CrashLog feature availability bit= =0D + UINT32 Dis : 1; ///< CrasLog Disable bit=0D + UINT32 Mech : 2; ///< CrashLog mechanism=0D + UINT32 ManuTri : 1; ///< Manul trigger command.=0D + UINT32 Clr : 1; ///< Clear Command=0D + UINT32 AllReset : 1; ///< Trigger on all reset command=0D + UINT32 ReArm : 1; ///< Re-arm command=0D + UINT32 Rsvd : 20; ///< Pch Specific reserved=0D + UINT32 CrashLogReq: 1; ///< Crash log requestor flow=0D + UINT32 TriArmedSts: 1; ///< Trigger armed status, re-arm indic= ation bit.=0D + UINT32 TriAllReset: 1; ///< Trigger on all resets status=0D + UINT32 CrashDisSts: 1; ///< Crash log disabled status=0D + UINT32 PchRsvd : 16; ///< Pch Specific reserved=0D + UINT32 DesTableOffset: 16; ///< Descriptor Table offset=0D + } Bits64;=0D + UINT32 Uint32;=0D + UINT64 Uint64;=0D +} PMC_IPC_DISCOVERY_BUF;=0D +=0D +typedef union {=0D + struct {=0D + UINT32 Offset : 16;=0D + UINT32 Size : 16;=0D + } Info;=0D + UINT32 Uint32;=0D +} PMC_CRASHLOG_RECORDS;=0D +=0D +typedef struct PmcCrashLogLink {=0D + PMC_CRASHLOG_RECORDS Record;=0D + UINT64 AllocateAddress;=0D + struct PmcCrashLogLink *Next;=0D +} PMC_CRASHLOG_LINK;=0D +=0D +#pragma pack()=0D +=0D +/**=0D + Get PCH ACPI base address.=0D +=0D + @retval Address Address of PWRM base address.=0D +**/=0D +UINT16=0D +PmcGetAcpiBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get PCH PWRM base address.=0D +=0D + @retval Address Address of PWRM base address.=0D +**/=0D +UINT32=0D +PmcGetPwrmBase (=0D + VOID=0D + );=0D +=0D +/**=0D + This function sets tPCH25 timing=0D +=0D + @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms= )=0D +**/=0D +VOID=0D +PmcSetTPch25Timing (=0D + IN PMC_TPCH25_TIMING TimingValue=0D + );=0D +=0D +/**=0D + This function checks if RTC Power Failure occurred by=0D + reading RTC_PWR_FLR bit=0D +=0D + @retval RTC Power Failure state: TRUE - Battery is always present.=0D + FALSE - CMOS is cleared.=0D +**/=0D +BOOLEAN=0D +PmcIsRtcBatteryGood (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if Power Failure occurred by=0D + reading PWR_FLR bit=0D +=0D + @retval Power Failure state=0D +**/=0D +BOOLEAN=0D +PmcIsPowerFailureDetected (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if Power Failure occurred by=0D + reading SUS_PWR_FLR bit=0D +=0D + @retval SUS Power Failure state=0D +**/=0D +BOOLEAN=0D +PmcIsSusPowerFailureDetected (=0D + VOID=0D + );=0D +=0D +/**=0D + This function clears Power Failure status (PWR_FLR)=0D +**/=0D +VOID=0D +PmcClearPowerFailureStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + This function clears Global Reset status (GBL_RST_STS)=0D +**/=0D +VOID=0D +PmcClearGlobalResetStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + This function clears Host Reset status (HOST_RST_STS)=0D +**/=0D +VOID=0D +PmcClearHostResetStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + This function clears SUS Power Failure status (SUS_PWR_FLR)=0D +**/=0D +VOID=0D +PmcClearSusPowerFailureStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + This function sets state to which platform will get after power is reapp= lied=0D +=0D + @param[in] PowerStateAfterG3 0: S0 state (boot)=0D + 1: S5/S4 State=0D +**/=0D +VOID=0D +PmcSetPlatformStateAfterPowerFailure (=0D + IN UINT8 PowerStateAfterG3=0D + );=0D +=0D +/**=0D + This function enables Power Button SMI=0D +**/=0D +VOID=0D +PmcEnablePowerButtonSmi (=0D + VOID=0D + );=0D +=0D +/**=0D + This function disables Power Button SMI=0D +**/=0D +VOID=0D +PmcDisablePowerButtonSmi (=0D + VOID=0D + );=0D +=0D +/**=0D + This function reads PM Timer Count driven by 3.579545 MHz clock=0D +=0D + @retval PM Timer Count=0D +**/=0D +UINT32=0D +PmcGetTimerCount (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Sleep Type that platform has waken from=0D +=0D + @retval SleepType Sleep Type=0D +**/=0D +PMC_SLEEP_STATE=0D +PmcGetSleepTypeAfterWake (=0D + VOID=0D + );=0D +=0D +/**=0D + Clear PMC Wake Status=0D +**/=0D +VOID=0D +PmcClearWakeStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + Configure sleep state=0D +=0D + @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE=0D +**/=0D +VOID=0D +PmcSetSleepState (=0D + PMC_SLEEP_STATE SleepState=0D + );=0D +=0D +/**=0D + Check if platform boots after shutdown caused by power button override e= vent=0D +=0D + @retval TRUE Power Button Override occurred in last system boot=0D + @retval FALSE Power Button Override didn't occur=0D +**/=0D +BOOLEAN=0D +PmcIsPowerButtonOverrideDetected (=0D + VOID=0D + );=0D +=0D +/**=0D + This function will set the DISB - DRAM Initialization Scratchpad Bit.=0D +**/=0D +VOID=0D +PmcSetDramInitScratchpad (=0D + VOID=0D + );=0D +=0D +/**=0D + Check global SMI enable is set=0D +=0D + @retval TRUE Global SMI enable is set=0D + FALSE Global SMI enable is not set=0D +**/=0D +BOOLEAN=0D +PmcIsGblSmiEn (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if SMI Lock is set=0D +=0D + @retval SMI Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsSmiLockSet (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if Debug Mode is locked=0D +=0D + @retval Debug Mode Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsDebugModeLocked (=0D + VOID=0D + );=0D +=0D +/**=0D + Check TCO second timeout status.=0D +=0D + @retval TRUE TCO reboot happened.=0D + @retval FALSE TCO reboot didn't happen.=0D +**/=0D +BOOLEAN=0D +TcoSecondToHappened (=0D + VOID=0D + );=0D +=0D +/**=0D + This function clears the Second TO status bit=0D +**/=0D +VOID=0D +TcoClearSecondToStatus (=0D + VOID=0D + );=0D +=0D +/**=0D + Check TCO SMI ENABLE is locked=0D +=0D + @retval TRUE TCO SMI ENABLE is locked=0D + FALSE TCO SMI ENABLE is not locked=0D +**/=0D +BOOLEAN=0D +TcoIsSmiLock (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if user wants to turn off in PEI phase=0D +=0D +**/=0D +VOID=0D +CheckPowerOffNow(=0D + VOID=0D + );=0D +=0D +=0D +/**=0D + Clear any SMI status or wake status left from boot.=0D +**/=0D +VOID=0D +ClearSmiAndWake (=0D + VOID=0D + );=0D +=0D +/**=0D + Function to check if Dirty Warm Reset occurs=0D + (Global Reset has been converted to Host Reset)=0D +=0D + @reval TRUE DWR occurs=0D + @reval FALSE Normal boot flow=0D +**/=0D +BOOLEAN=0D +PmcIsDwrBootMode (=0D + VOID=0D + );=0D +=0D +#endif // _PMC_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemL= ib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h new file mode 100644 index 0000000000..9ab55ad9d0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/ResetSystemLib.h @@ -0,0 +1,79 @@ +/** @file=0D + System reset Library Services. This library class defines a set of=0D + methods that reset the whole system.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef __RESET_SYSTEM_LIB_H__=0D +#define __RESET_SYSTEM_LIB_H__=0D +=0D +/**=0D + This function causes a system-wide reset (cold reset), in which=0D + all circuitry within the system returns to its initial state. This type = of reset=0D + is asynchronous to system operation and operates without regard to=0D + cycle boundaries.=0D +=0D + If this function returns, it means that the system does not support cold= reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetCold (=0D + VOID=0D + );=0D +=0D +/**=0D + This function causes a system-wide initialization (warm reset), in which= all processors=0D + are set to their initial state. Pending cycles are not corrupted.=0D +=0D + If this function returns, it means that the system does not support warm= reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetWarm (=0D + VOID=0D + );=0D +=0D +/**=0D + This function causes the system to enter a power state equivalent=0D + to the ACPI G2/S5 or G3 states.=0D +=0D + If this function returns, it means that the system does not support shut= down reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetShutdown (=0D + VOID=0D + );=0D +=0D +/**=0D + This function causes the system to enter S3 and then wake up immediately= .=0D +=0D + If this function returns, it means that the system does not support S3 f= eature.=0D +**/=0D +VOID=0D +EFIAPI=0D +EnterS3WithImmediateWake (=0D + VOID=0D + );=0D +=0D +/**=0D + This function causes a systemwide reset. The exact type of the reset is= =0D + defined by the EFI_GUID that follows the Null-terminated Unicode string = passed=0D + into ResetData. If the platform does not recognize the EFI_GUID in Reset= Data=0D + the platform must pick a supported reset type to perform.The platform ma= y=0D + optionally log the parameters from any non-normal reset that occurs.=0D +=0D + @param[in] DataSize The size, in bytes, of ResetData.=0D + @param[in] ResetData The data buffer starts with a Null-terminated str= ing,=0D + followed by the EFI_GUID.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetPlatformSpecific (=0D + IN UINTN DataSize,=0D + IN VOID *ResetData=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h b/= Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h new file mode 100644 index 0000000000..bc1555ed19 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SataLib.h @@ -0,0 +1,112 @@ +/** @file=0D + Header file for SataLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SATA_LIB_H_=0D +#define _SATA_LIB_H_=0D +=0D +#define SATA_1_CONTROLLER_INDEX 0=0D +#define SATA_2_CONTROLLER_INDEX 1=0D +#define SATA_3_CONTROLLER_INDEX 2=0D +=0D +/**=0D + Get Maximum Sata Port Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval Maximum Sata Port Number=0D +**/=0D +UINT8=0D +MaxSataPortNum (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Gets Maximum Sata Controller Number=0D +=0D + @retval Maximum Sata Controller Number=0D +**/=0D +UINT8=0D +MaxSataControllerNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get SATA controller's Port Present Status=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval Port Present Status=0D +**/=0D +UINT8=0D +GetSataPortPresentStatus (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Get SATA controller Function Disable Status=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval 0 SATA Controller is not Function Disabled=0D + @retval 1 SATA Controller is Function Disabled=0D +**/=0D +BOOLEAN=0D +SataControllerFunctionDisableStatus (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Get SATA controller ABAR size=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller ABAR size=0D +**/=0D +UINT32=0D +GetSataAbarSize (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Get SATA controller AHCI base address=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller AHCI base address=0D +**/=0D +UINT32=0D +GetSataAhciBase (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Check if SATA controller supports RST remapping=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval TRUE Controller supports remapping=0D + @retval FALSE Controller does not support remapping=0D +**/=0D +BOOLEAN=0D +IsRemappingSupportedOnSata (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Checks if SoC supports the SATA PGD power down on given=0D + SATA controller.=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval TRUE SATA PGD power down supported=0D + @retval FALSE SATA PGD power down not supported=0D +**/=0D +BOOLEAN=0D +IsSataPowerGatingSupported (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +#endif // _SATA_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAcce= ssLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessL= ib.h new file mode 100644 index 0000000000..3c8aae6ac2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SerialIoAccessLib.h @@ -0,0 +1,113 @@ +/** @file=0D + Header file for Serial Io Common Lib=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_ACCESS_LIB_H_=0D +#define _SERIAL_IO_ACCESS_LIB_H_=0D +=0D +/**=0D + Returns BAR0=0D +=0D + @param[in] PciCfgBase Pci Config Base=0D +=0D + @retval 64bit MMIO BAR Address=0D +**/=0D +UINT64=0D +GetSerialIoBar (=0D + IN UINT64 PciCfgBase=0D + );=0D +=0D +/**=0D + Returns I2C Pci Config Space=0D +=0D + @param[in] I2cNumber I2C Number=0D +=0D + @retval I2C Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoI2cPciCfg (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Returns SPI Pci Config Space=0D +=0D + @param[in] SpiNumber SPI Number=0D +=0D + @retval SPI Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoSpiPciCfg (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Returns UART Pci Config Space=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval UART Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoUartPciCfg (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Checks if Device with given PciDeviceId is one of SerialIo I2C controlle= rs=0D + If yes, its number is returned through I2cIndex parameter, otherwise I2c= Index is not updated=0D +=0D + @param[in] PciDevId Device ID=0D + @param[out] I2cNumber Number of SerialIo I2C controller= =0D +=0D + @retval TRUE yes it is a SerialIo I2C controlle= r=0D + @retval FALSE no it isn't a SerialIo I2C control= ler=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cDeviceId (=0D + IN UINT16 PciDevId,=0D + OUT UINT8 *I2cNumber=0D + );=0D +=0D +/**=0D + Checks if I2c is Function 0 Enabled=0D +=0D + @param[in] I2cIndex Number of the SerialIo I2C control= ler=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cFunction0Enabled (=0D + IN UINT8 I2cIndex=0D + );=0D +=0D +/**=0D + Checks if Uart is Function 0 Enabled=0D +=0D + @param[in] UartIndex Number of the SerialIo Uart contr= oller=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoUartFunction0Enabled (=0D + IN UINT8 UartIndex=0D + );=0D +=0D +/**=0D + Checks if Spi is Function 0 Enabled=0D +=0D + @param[in] SpiIndex Number of the SerialIo Spi control= ler=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoSpiFunction0Enabled (=0D + IN UINT8 SpiIndex=0D + );=0D +=0D +#endif // _SERIAL_IO_ACCESS_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBloc= kLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib= .h new file mode 100644 index 0000000000..7732ccf59e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SiConfigBlockLib.h @@ -0,0 +1,56 @@ +/** @file=0D + Prototype of the SiConfigBlockLib library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_CONFIG_BLOCK_LIB_H_=0D +#define _SI_CONFIG_BLOCK_LIB_H_=0D +=0D +=0D +typedef=0D +VOID=0D +(*LOAD_DEFAULT_FUNCTION) (=0D + IN VOID *ConfigBlockPointer=0D + );=0D +=0D +typedef struct {=0D + EFI_GUID *Guid;=0D + UINT16 Size;=0D + UINT8 Revision;=0D + LOAD_DEFAULT_FUNCTION LoadDefault;=0D +} COMPONENT_BLOCK_ENTRY;=0D +=0D +/**=0D + GetComponentConfigBlockTotalSize get config block table total size.=0D +=0D + @param[in] ComponentBlocks Component blocks array=0D + @param[in] TotalBlockCount Number of blocks=0D +=0D + @retval Size of config block table=0D +**/=0D +UINT16=0D +EFIAPI=0D +GetComponentConfigBlockTotalSize (=0D + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,=0D + IN UINT16 TotalBlockCount=0D + );=0D +=0D +/**=0D + AddComponentConfigBlocks add all config blocks.=0D +=0D + @param[in] ConfigBlockTableAddress The pointer to add config blocks=0D + @param[in] ComponentBlocks Config blocks array=0D + @param[in] TotalBlockCount Number of blocks=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +AddComponentConfigBlocks (=0D + IN VOID *ConfigBlockTableAddress,=0D + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,=0D + IN UINT16 TotalBlockCount=0D + );=0D +#endif // _SI_CONFIG_BLOCK_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib= .h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h new file mode 100644 index 0000000000..50f9e048b3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/SpiAccessLib.h @@ -0,0 +1,290 @@ +/** @file=0D + SPI library header for abstraction of SPI HW registers accesses=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SPI_ACCESS_LIB_H_=0D +#define _SPI_ACCESS_LIB_H_=0D +=0D +/**=0D + Returns SPI PCI Config Space base address=0D +=0D + @retval UINT64 SPI Config Space base address=0D +**/=0D +UINT64=0D +SpiGetPciCfgAddress (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI BAR0 value=0D +=0D + @retval UINT32 PCH SPI BAR0 value=0D +**/=0D +UINT32=0D +SpiGetBar0 (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI Device number=0D +=0D + @retval UINT8 PCH SPI Device number=0D +**/=0D +UINT8=0D +SpiDeviceNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI Function number=0D +=0D + @retval UINT8 PCH SPI Function number=0D +**/=0D +UINT8=0D +SpiFunctionNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns descriptor signature=0D +=0D + @retval UINT32 Descriptor signature=0D +**/=0D +UINT32=0D +SpiGetDescriptorSignature (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns supported features and R/W frequencies of Flash Component=0D +=0D + @retval UINT32 Flash Component features descriptor=0D +**/=0D +UINT32=0D +SpiGetFlashComponentDescription (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns number of Flash Components=0D +=0D + @retval UINT32 Flash components number=0D +**/=0D +UINT32=0D +SpiGetFlashComponentsNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns total Flash size with regards to number of flash components=0D +=0D + @retval UINT32 Total Flash Memory size=0D +**/=0D +UINT32=0D +SpiGetTotalFlashSize (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if PCH SPI Controler is present and available=0D +=0D + @retval TRUE PCH SPI controller is avaialable=0D + @retval FALSE PCH SPI controller is not available=0D +**/=0D +BOOLEAN=0D +SpiIsControllerAvailable (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks BIOS lock bits for proper value and checks if write protection is= enabled=0D + Expected vales are: LE bit set, EISS bit set and WPD bit cleared=0D +=0D + @retval TRUE All protection bits are set correctly=0D + @retval FALSE Not all protection bits had exepcted values=0D +**/=0D +BOOLEAN=0D +SpiIsWriteProtectionEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Flash Descriptor Override Pin Strap status=0D +=0D + @retval TRUE Flash Descriptor override is enabled=0D + @retval FALSE Flash Descriptor override is disabled=0D +**/=0D +BOOLEAN=0D +SpiIsFlashDescriptorOverrideEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Flash Configuration Lock Down bit status=0D +=0D + @retval TRUE Flash Configuration Lock Down bit is set=0D + @retval FALSE Flash Configuration Lock Down bit is not set=0D +**/=0D +BOOLEAN=0D +SpiIsFlashConfigurationLockDownEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Top Swap functionality enable state=0D +=0D + @retval TRUE Top Swap is enabled=0D + @retval FALSE Top Swap is disabled=0D +**/=0D +BOOLEAN=0D +SpiIsTopSwapEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Return Component Property Parameter Table for a given component number=0D +=0D + @param[in] ComponentNumber SPI Component number=0D + @param[out] CppTable Component Poperty Parameter Table value=0D +=0D + @retval TRUE Vendor Specific Component Capabilities Register value was = read=0D + @reval FALSE Vendor Specific Component Capabilities Register value was = not present=0D +**/=0D +BOOLEAN=0D +SpiGetComponentPropertyParameterTable (=0D + IN UINT8 ComponentNumber,=0D + OUT UINT32 *CppTable=0D + );=0D +=0D +/**=0D + Returns valid bit status in given Component Property Parameter Table=0D +=0D + @param[in] CppTable Component Poperty Parameter Table value=0D +=0D + @retval TRUE Valid bit is set=0D + @reval FALSE Valid bit is not set=0D +**/=0D +BOOLEAN=0D +SpiIsCppValidBitSet (=0D + IN UINT32 CppTable=0D + );=0D +=0D +/**=0D + Checks if Flash Descriptor is valid=0D +=0D + @retval TRUE Flash Descriptor is valid=0D + @retval FALSE Flash Descriptor is invalid=0D +**/=0D +BOOLEAN=0D +SpiIsFlashDescriptorValid (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns masked BIOS Master Read Access=0D +=0D + @retval UINT32 Already masked BIOS Master Read Access=0D +**/=0D +UINT32=0D +SpiGetMasterReadAccess (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns masked BIOS Master Write Access=0D +=0D + @retval UINT32 Already masked BIOS Master Write Access=0D +**/=0D +UINT32=0D +SpiGetMasterWriteAccess (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns GbE Region Access rights=0D +=0D + @retval UINT32 GbE Region access rights=0D +**/=0D +UINT32=0D +SpiGetGbeRegionAccess (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns CSME region access rights=0D +=0D + @retval UINT32 CSME Region Access rights=0D +**/=0D +UINT32=0D +SpiGetCsmeRegionAccess (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns EC region access right=0D +=0D + @retval UINT32 EC Region access rights=0D +**/=0D +UINT32=0D +SpiGetEcRegionAccess (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if Slave Attached Flash (SAF) mode is active=0D +=0D + @retval TRUE SAF mode is active=0D + @retval FALSE SAF mode is not active=0D +**/=0D +BOOLEAN=0D +SpiIsSafModeActive (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks validity of GbE region=0D +=0D + @retval TRUE GbE region is valid=0D + @retval FALSE GbE regios in invalid=0D +**/=0D +BOOLEAN=0D +SpiIsGbeRegionValid (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns status of BIOS Interface Lockdown=0D +=0D + @retval TRUE BIOS Interface Lockdown is enabled=0D + @retval FALSE BIOS Interface Lockdown is disabled=0D +**/=0D +BOOLEAN=0D +SpiIsBiosInterfaceLockdownEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns TRUE if BIOS Boot Strap is set to SPI=0D +=0D + @retval TRUE BIOS Boot strap is set to SPI=0D + @retval FALSE BIOS Boot strap is set to LPC/eSPI=0D +**/=0D +BOOLEAN=0D +SpiIsBiosBootFromSpi (=0D + VOID=0D + );=0D +=0D +/**=0D + Check SPI write status disable is set=0D +=0D + @retval TRUE Write status disable is set=0D + @retval FALSE Write status disable is not set=0D +**/=0D +BOOLEAN=0D +SpiIsWriteStatusDisable (=0D + VOID=0D + );=0D +=0D +#endif // _SPI_ACCESS_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h= b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h new file mode 100644 index 0000000000..69eed8d32d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Library/VtdInfoLib.h @@ -0,0 +1,53 @@ +/** @file=0D + Header file for VtdInfoLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _VTD_INFO_LIB_H_=0D +#define _VTD_INFO_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#define VTD_ENGINE_NUMBER 7=0D +=0D +#pragma pack(1)=0D +=0D +/**=0D + Get VTD Engine Base Address from PCD values.=0D +=0D + @param[in] VtdEngineNumber - Engine number for which VTD Base Ad= deress is required.=0D +=0D + @retval VTD Engine Base Address=0D +**/=0D +UINT32=0D +GetVtdBaseAddress (=0D + IN UINT8 VtdEngineNumber=0D + );=0D +=0D +/**=0D + Read VTD Engine Base Address from VTD BAR Offsets.=0D +=0D + @param[in] VtdEngineNumber - Engine number for which VTD Base Ad= deress is required.=0D +=0D + @retval VTD Engine Base Address=0D +**/=0D +UINT32=0D +ReadVtdBaseAddress (=0D + IN UINT8 VtdEngineNumber=0D + );=0D +=0D +/**=0D + GetMaxVtdEngineNumber: Get Maximum Vtd Engine Number=0D +=0D + @retval Vtd Engine Number=0D +**/=0D +UINT8=0D +GetMaxVtdEngineNumber(=0D + VOID=0D +);=0D +=0D +#pragma pack()=0D +#endif // _VTD_INFO_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefau= ltPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefau= ltPolicy.h new file mode 100644 index 0000000000..3fd917c2b9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiPreMemSiDefaultPolic= y.h @@ -0,0 +1,34 @@ +/** @file=0D + This file defines the function to initialize default silicon policy PPI.= =0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_=0D +#define _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_=0D +=0D +//=0D +// Forward declaration for the PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI.=0D +//=0D +typedef struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI PEI_PREMEM_SI_DEFAUL= T_POLICY_INIT_PPI;=0D +=0D +/**=0D + Initialize and install default silicon policy PPI=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PEI_PREMEM_POLICY_INIT) (=0D + VOID=0D + );=0D +=0D +///=0D +/// This PPI provides function to install default silicon policy=0D +///=0D +struct _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI {=0D + PEI_PREMEM_POLICY_INIT PeiPreMemPolicyInit; ///< PeiPreMemPolicyInit= ()=0D +};=0D +=0D +extern EFI_GUID gSiPreMemDefaultPolicyInitPpiGuid;=0D +=0D +#endif // _PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPoli= cy.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h new file mode 100644 index 0000000000..9cb34728cc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/PeiSiDefaultPolicy.h @@ -0,0 +1,33 @@ +/** @file=0D + This file defines the function to initialize default silicon policy PPI.= =0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_=0D +#define _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_=0D +=0D +//=0D +// Forward declaration for the PEI_SI_DEFAULT_POLICY_INIT_PPI.=0D +//=0D +typedef struct _PEI_SI_DEFAULT_POLICY_INIT_PPI PEI_SI_DEFAULT_POLICY_INIT_= PPI;=0D +=0D +/**=0D + Initialize and install default silicon policy PPI=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PEI_POLICY_INIT) (=0D + VOID=0D + );=0D +=0D +///=0D +/// This PPI provides function to install default silicon policy=0D +///=0D +struct _PEI_SI_DEFAULT_POLICY_INIT_PPI {=0D + PEI_POLICY_INIT PeiPolicyInit; ///< PeiPolicyInit()=0D +};=0D +=0D +extern EFI_GUID gSiDefaultPolicyInitPpiGuid;=0D +=0D +#endif // _PEI_SI_DEFAULT_POLICY_INIT_PPI_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h b/Sil= icon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h new file mode 100644 index 0000000000..5f4d467439 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Ppi/SiPolicy.h @@ -0,0 +1,75 @@ +/** @file=0D + Silicon Policy PPI is used for specifying platform=0D + related Intel silicon information and policy setting.=0D + This PPI is consumed by the silicon PEI modules and carried=0D + over to silicon DXE modules.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SI_POLICY_PPI_H_=0D +#define _SI_POLICY_PPI_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#ifndef DISABLED=0D +#define DISABLED 0=0D +#endif=0D +#ifndef ENABLED=0D +#define ENABLED 1=0D +#endif=0D +=0D +extern EFI_GUID gSiPreMemPolicyPpiGuid;=0D +extern EFI_GUID gSiPolicyPpiGuid;=0D +=0D +=0D +#include =0D +extern EFI_GUID gGraphicsPeiPreMemConfigGuid;=0D +extern EFI_GUID gGraphicsPeiConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gVtdConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gGnaConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gCpuPciePeiPreMemConfigGuid;=0D +extern EFI_GUID gCpuPcieRpConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gHybridGraphicsConfigGuid;=0D +=0D +#include =0D +#include =0D +extern EFI_GUID gMemoryConfigGuid;=0D +extern EFI_GUID gMemoryConfigNoCrcGuid;=0D +=0D +#include =0D +extern EFI_GUID gSaMiscPeiPreMemConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gSaMiscPeiConfigGuid;=0D +=0D +=0D +#include =0D +extern EFI_GUID gCpuTraceHubConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gHostBridgePeiPreMemConfigGuid;=0D +extern EFI_GUID gHostBridgePeiConfigGuid;=0D +=0D +#include =0D +extern EFI_GUID gCpuDmiPreMemConfigGuid;=0D +=0D +typedef struct _SI_PREMEM_POLICY_STRUCT SI_PREMEM_POLICY_PPI;=0D +typedef struct _SI_POLICY_STRUCT SI_POLICY_PPI;=0D +=0D +#endif // _SI_POLICY_PPI_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponen= tName2.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentN= ame2.h new file mode 100644 index 0000000000..1d69ee0e8d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopComponentName2.h @@ -0,0 +1,61 @@ +/** @file=0D + Protocol to retrieve the GOP driver version=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GOP_COMPONENT_NAME2_H_=0D +#define _GOP_COMPONENT_NAME2_H_=0D +=0D +=0D +typedef struct _GOP_COMPONENT_NAME2_PROTOCOL GOP_COMPONENT_NAME2_PROTOCOL= ;=0D +=0D +///=0D +/// GOP Component protocol for retrieving driver name=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_NAME) (=0D + IN GOP_COMPONENT_NAME2_PROTOCOL * This,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **DriverName=0D + );=0D +=0D +///=0D +/// GOP Component protocol for retrieving controller name=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME) (=0D + IN GOP_COMPONENT_NAME2_PROTOCOL * This,=0D + IN EFI_HANDLE ControllerHandle,=0D + IN EFI_HANDLE ChildHandle OPTIONAL,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **ControllerName=0D + );=0D +=0D +///=0D +/// GOP Component protocol for retrieving driver version=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GOP_COMPONENT_NAME2_GET_DRIVER_VERSION) (=0D + IN GOP_COMPONENT_NAME2_PROTOCOL * This,=0D + IN CHAR8 *Language,=0D + OUT CHAR16 **DriverVersion=0D + );=0D +=0D +/**=0D + GOP Component protocol\n=0D + This protocol will be installed by GOP driver and can be used to retriev= e GOP information.=0D +**/=0D +struct _GOP_COMPONENT_NAME2_PROTOCOL {=0D + GOP_COMPONENT_NAME2_GET_DRIVER_NAME GetDriverName; ///< Pr= otocol function to get driver name=0D + GOP_COMPONENT_NAME2_GET_DRIVER_VERSION GetDriverVersion; ///< Pr= otocol function to get driver version=0D + GOP_COMPONENT_NAME2_GET_CONTROLLER_NAME GetControllerName; ///< Pr= otocol function to get controller name=0D + CHAR8 *SupportedLanguages; ///< Nu= mber of Supported languages.=0D +};=0D +=0D +extern EFI_GUID gGopComponentName2ProtocolGuid;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h= b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h new file mode 100644 index 0000000000..c8dc17008e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/GopPolicy.h @@ -0,0 +1,73 @@ +/** @file=0D + Interface definition for GopPolicy Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GOP_POLICY_PROTOCOL_H_=0D +#define _GOP_POLICY_PROTOCOL_H_=0D +=0D +=0D +#define GOP_POLICY_PROTOCOL_REVISION_01 0x01=0D +#define GOP_POLICY_PROTOCOL_REVISION_03 0x03=0D +=0D +typedef enum {=0D + LidClosed,=0D + LidOpen,=0D + LidStatusMax=0D +} LID_STATUS;=0D +=0D +typedef enum {=0D + Docked,=0D + UnDocked,=0D + DockStatusMax=0D +} DOCK_STATUS;=0D +=0D +///=0D +/// Function to retrieve LID status=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GET_PLATFORM_LID_STATUS) (=0D + OUT LID_STATUS * CurrentLidStatus=0D + );=0D +=0D +///=0D +/// Function to retrieve Dock status=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GET_PLATFORM_DOCK_STATUS) (=0D + OUT DOCK_STATUS CurrentDockStatus=0D +);=0D +=0D +///=0D +/// Function to retrieve VBT table address and size=0D +///=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *GET_VBT_DATA) (=0D + OUT EFI_PHYSICAL_ADDRESS * VbtAddress,=0D + OUT UINT32 *VbtSize=0D + );=0D +=0D +/**=0D + System Agent Graphics Output Protocol (GOP) - Policy Protocol\n=0D + Graphics Output Protocol (GOP) is a UEFI API replacing legacy Video ROMs= for EFI boot\n=0D + When GOP Driver is used this protocol can be consumed by GOP driver or p= latform code for GOP relevant initialization\n=0D + All functions in this protocol should be initialized by platform code ba= sing on platform implementation\n=0D +**/=0D +typedef struct {=0D + UINT32 Revision; ///< Protocol revision= =0D + GET_PLATFORM_LID_STATUS GetPlatformLidStatus; ///< Protocol function = to get Lid Status. Platform code should provide this function basing on des= ign.=0D + GET_VBT_DATA GetVbtData; ///< Protocol function = to get Vbt Data address and size. Platform code should provide this functio= n basing on design.=0D + GET_PLATFORM_DOCK_STATUS GetPlatformDockStatus; ///< Function pointer = for get platform dock status.=0D + EFI_GUID GopOverrideGuid; ///< A GUID provided b= y BIOS in case GOP is to be overridden.=0D +} GOP_POLICY_PROTOCOL;=0D +=0D +extern EFI_GUID gGopPolicyProtocolGuid;=0D +extern EFI_GUID gGen12PolicyProtocolGuid;=0D +extern EFI_GUID gGen9PolicyProtocolGuid;=0D +extern EFI_GUID gIntelGraphicsVbtGuid;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion= .h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h new file mode 100644 index 0000000000..c030f771e3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/IgdOpRegion.h @@ -0,0 +1,22 @@ +/** @file=0D + This file is part of the IGD OpRegion Implementation. The IGD OpRegion = is=0D + an interface between system BIOS, ASL code, and Graphics drivers.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _IGD_OPREGION_PROTOCOL_H_=0D +#define _IGD_OPREGION_PROTOCOL_H_=0D +=0D +#include =0D +=0D +extern EFI_GUID gIgdOpRegionProtocolGuid;=0D +=0D +///=0D +/// IGD OpRegion Protocol=0D +///=0D +typedef struct {=0D + IGD_OPREGION_STRUCTURE *OpRegion; ///< IGD Operation Region Structure=0D +} IGD_OPREGION_PROTOCOL;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h b/Sil= icon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h new file mode 100644 index 0000000000..c13dc5a5f5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Protocol/Spi.h @@ -0,0 +1,301 @@ +/** @file=0D + This file defines the PCH SPI Protocol which implements the=0D + Intel(R) PCH SPI Host Controller Compatibility Interface.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_SPI_PROTOCOL_H_=0D +#define _PCH_SPI_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchSpiProtocolGuid;=0D +extern EFI_GUID gPchSmmSpiProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_SPI_PROTOCOL PCH_SPI_PROTOCOL;=0D +=0D +//=0D +// SPI protocol data structures and definitions=0D +//=0D +=0D +/**=0D + Flash Region Type=0D +**/=0D +typedef enum {=0D + FlashRegionDescriptor,=0D + FlashRegionBios,=0D + FlashRegionMe,=0D + FlashRegionGbE,=0D + FlashRegionPlatformData,=0D + FlashRegionDer,=0D + FlashRegionSecondaryBios,=0D + FlashRegionuCodePatch,=0D + FlashRegionEC,=0D + FlashRegionDeviceExpansion2,=0D + FlashRegionIE,=0D + FlashRegion10Gbe_A,=0D + FlashRegion10Gbe_B,=0D + FlashRegion13,=0D + FlashRegion14,=0D + FlashRegion15,=0D + FlashRegionAll,=0D + FlashRegionMax=0D +} FLASH_REGION_TYPE;=0D +//=0D +// Protocol member functions=0D +//=0D +=0D +/**=0D + Read data from the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[out] Buffer The Pointer to caller-allocated buffer c= ontaining the dada received.=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_READ) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *Buffer=0D + );=0D +=0D +/**=0D + Write data to the flash part. Remark: Erase may be needed before write t= o the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D + @param[in] Buffer Pointer to caller-allocated buffer conta= ining the data sent during the SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_WRITE) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + IN UINT8 *Buffer=0D + );=0D +=0D +/**=0D + Erase some area on the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] FlashRegionType The Flash Region type for flash cycle wh= ich is listed in the Descriptor.=0D + @param[in] Address The Flash Linear Address must fall withi= n a region for which BIOS has access permissions.=0D + @param[in] ByteCount Number of bytes in the data portion of t= he SPI cycle.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_ERASE) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount=0D + );=0D +=0D +/**=0D + Read SFDP data from the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] ComponentNumber The Componen Number for chip select=0D + @param[in] Address The starting byte address for SFDP data = read.=0D + @param[in] ByteCount Number of bytes in SFDP data portion of = the SPI cycle=0D + @param[out] SfdpData The Pointer to caller-allocated buffer c= ontaining the SFDP data received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_READ_SFDP) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 Address,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *SfdpData=0D + );=0D +=0D +/**=0D + Read Jedec Id from the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] ComponentNumber The Componen Number for chip select=0D + @param[in] ByteCount Number of bytes in JedecId data portion = of the SPI cycle, the data size is 3 typically=0D + @param[out] JedecId The Pointer to caller-allocated buffer c= ontaining JEDEC ID received=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_READ_JEDEC_ID) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT8 ComponentNumber,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *JedecId=0D + );=0D +=0D +/**=0D + Write the status register in the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[in] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register writing=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_WRITE_STATUS) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT32 ByteCount,=0D + IN UINT8 *StatusValue=0D + );=0D +=0D +/**=0D + Read status register in the flash part.=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] ByteCount Number of bytes in Status data portion o= f the SPI cycle, the data size is 1 typically=0D + @param[out] StatusValue The Pointer to caller-allocated buffer c= ontaining the value of Status register received.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_FLASH_READ_STATUS) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT32 ByteCount,=0D + OUT UINT8 *StatusValue=0D + );=0D +=0D +/**=0D + Get the SPI region base and size, based on the enum type=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] FlashRegionType The Flash Region type for for the base a= ddress which is listed in the Descriptor.=0D + @param[out] BaseAddress The Flash Linear Address for the Region = 'n' Base=0D + @param[out] RegionSize The size for the Region 'n'=0D +=0D + @retval EFI_SUCCESS Read success=0D + @retval EFI_INVALID_PARAMETER Invalid region type given=0D + @retval EFI_DEVICE_ERROR The region is not used=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_GET_REGION_ADDRESS) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN FLASH_REGION_TYPE FlashRegionType,=0D + OUT UINT32 *BaseAddress,=0D + OUT UINT32 *RegionSize=0D + );=0D +=0D +/**=0D + Read PCH Soft Strap Values=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] SoftStrapAddr PCH Soft Strap address offset from FPSBA= .=0D + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle=0D + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining PCH Soft Strap Value.=0D + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_READ_PCH_SOFTSTRAP) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT32 SoftStrapAddr,=0D + IN UINT32 ByteCount,=0D + OUT VOID *SoftStrapValue=0D + );=0D +=0D +/**=0D + Read CPU Soft Strap Values=0D +=0D + @param[in] This Pointer to the PCH_SPI_PROTOCOL instance= .=0D + @param[in] SoftStrapAddr CPU Soft Strap address offset from FCPUS= BA.=0D + @param[in] ByteCount Number of bytes in SoftStrap data portio= n of the SPI cycle.=0D + @param[out] SoftStrapValue The Pointer to caller-allocated buffer c= ontaining CPU Soft Strap Value.=0D + If the value of ByteCount is 0, the data= type of SoftStrapValue should be UINT16 and SoftStrapValue will be PCH Sof= t Strap Length=0D + It is the caller's responsibility to mak= e sure Buffer is large enough for the total number of bytes read.=0D +=0D + @retval EFI_SUCCESS Command succeed.=0D + @retval EFI_INVALID_PARAMETER The parameters specified are not valid.= =0D + @retval EFI_DEVICE_ERROR Device error, command aborts abnormally.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SPI_READ_CPU_SOFTSTRAP) (=0D + IN PCH_SPI_PROTOCOL *This,=0D + IN UINT32 SoftStrapAddr,=0D + IN UINT32 ByteCount,=0D + OUT VOID *SoftStrapValue=0D + );=0D +=0D +/**=0D + These protocols/PPI allows a platform module to perform SPI operations t= hrough the=0D + Intel PCH SPI Host Controller Interface.=0D +**/=0D +struct _PCH_SPI_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + PCH_SPI_FLASH_READ FlashRead; ///< Read data fro= m the flash part.=0D + PCH_SPI_FLASH_WRITE FlashWrite; ///< Write data to= the flash part. Remark: Erase may be needed before write to the flash part= .=0D + PCH_SPI_FLASH_ERASE FlashErase; ///< Erase some ar= ea on the flash part.=0D + PCH_SPI_FLASH_READ_SFDP FlashReadSfdp; ///< Read SFDP dat= a from the flash part.=0D + PCH_SPI_FLASH_READ_JEDEC_ID FlashReadJedecId; ///< Read Jedec Id= from the flash part.=0D + PCH_SPI_FLASH_WRITE_STATUS FlashWriteStatus; ///< Write the sta= tus register in the flash part.=0D + PCH_SPI_FLASH_READ_STATUS FlashReadStatus; ///< Read status r= egister in the flash part.=0D + PCH_SPI_GET_REGION_ADDRESS GetRegionAddress; ///< Get the SPI r= egion base and size=0D + PCH_SPI_READ_PCH_SOFTSTRAP ReadPchSoftStrap; ///< Read PCH Soft= Strap Values=0D + PCH_SPI_READ_CPU_SOFTSTRAP ReadCpuSoftStrap; ///< Read CPU Soft= Strap Values=0D +};=0D +=0D +/**=0D + PCH SPI PPI/PROTOCOL revision number=0D +=0D + Revision 1: Initial version=0D +**/=0D +#define PCH_SPI_SERVICES_REVISION 1=0D +=0D +#endif=0D --=20 2.24.0.windows.2