From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web09.5259.1612428689991172976 for ; Thu, 04 Feb 2021 00:51:30 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: yMogZ8JDt6D524+8f79aJ0OqSA/zXOILuA5l1FVO2KiToNXNjUbVoUOIW64BfIcJmXhd1iXr19 k8jV14mempAQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160364703" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160364703" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:29 -0800 IronPort-SDR: bcYgLPpN12hwhk/Oo93P8UJFKDn61jjySHXsXkFF6VH1sDpgNdpMYw5XZdZ7ce76WzQtGL7SEg W5hVZhC6yUXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062310" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:28 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Date: Thu, 4 Feb 2021 16:49:03 +0800 Message-Id: <20210204084919.3603-24-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/Pmc/IncludePrivate * IpBlock/Pmc/Library * IpBlock/Pmc/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/PmcPr= ivateLib.h | 120 ++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register/PmcR= egsVer2.h | 52 ++++++++++++++++++++++++++= ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiD= xeSmmPmcLib.inf | 42 ++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PmcL= ib.c | 545 ++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcP= rivateLib/PeiDxeSmmPmcPrivateLibVer2.inf | 39 ++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcP= rivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf | 40 ++++++++++++++++++++++++++= ++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcP= rivateLib/PmcPrivateLib.c | 166 ++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcP= rivateLib/PmcPrivateLibWithS3.c | 122 ++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++ 8 files changed, 1126 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/L= ibrary/PmcPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Incl= udePrivate/Library/PmcPrivateLib.h new file mode 100644 index 0000000000..0f2f251d57 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Library/= PmcPrivateLib.h @@ -0,0 +1,120 @@ +/** @file=0D + Header file for private PmcLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PMC_PRIVATE_LIB_H_=0D +#define _PMC_PRIVATE_LIB_H_=0D +=0D +#include =0D +#include "Register/PmcRegs.h"=0D +=0D +/**=0D + This function checks if GbE device is supported (not disabled by fuse)=0D +=0D + @retval GbE support state=0D +**/=0D +BOOLEAN=0D +PmcIsGbeSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if LAN wake from DeepSx is enabled=0D +=0D + @retval Lan Wake state=0D +**/=0D +BOOLEAN=0D +PmcIsLanDeepSxWakeEnabled (=0D + VOID=0D + );=0D +=0D +/**=0D + This function sets SMI Lock with S3 Boot Script programming=0D +**/=0D +VOID=0D +PmcLockSmiWithS3BootScript (=0D + VOID=0D + );=0D +=0D +/**=0D + This function sets eSPI SMI Lock=0D + @attention This function must be called after eSPI SMI generation has be= en enabled.=0D + This setting is required in all boot modes and before EndOfDxe.=0D + If set value will be restored upon S3 resume by bootscript.=0D +**/=0D +VOID=0D +PmcLockEspiSmiWithS3BootScript (=0D + VOID=0D + );=0D +=0D +/**=0D + This function checks if eSPI SMI Lock is set=0D +=0D + @retval eSPI SMI Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsEspiSmiLockSet (=0D + VOID=0D + );=0D +=0D +typedef enum {=0D + PmcSwSmiRate1p5ms =3D 0,=0D + PmcSwSmiRate16ms,=0D + PmcSwSmiRate32ms,=0D + PmcSwSmiRate64ms=0D +} PMC_SWSMI_RATE;=0D +=0D +/**=0D + This function sets SW SMI Rate.=0D +=0D + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values= =0D +**/=0D +VOID=0D +PmcSetSwSmiRate (=0D + IN PMC_SWSMI_RATE SwSmiRate=0D + );=0D +=0D +typedef enum {=0D + PmcPeriodicSmiRate8s =3D 0,=0D + PmcPeriodicSmiRate16s,=0D + PmcPeriodicSmiRate32s,=0D + PmcPeriodicSmiRate64s=0D +} PMC_PERIODIC_SMI_RATE;=0D +=0D +/**=0D + This function sets Periodic SMI Rate.=0D +=0D + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for pos= sible values=0D +**/=0D +VOID=0D +PmcSetPeriodicSmiRate (=0D + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate=0D + );=0D +=0D +/**=0D + This function reads Power Button Level=0D +=0D + @retval State of PWRBTN# signal (0: Low, 1: High)=0D +**/=0D +UINT8=0D +PmcGetPwrBtnLevel (=0D + VOID=0D + );=0D +=0D +/**=0D + This function gets Group to GPE0 configuration=0D +=0D + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment=0D + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment=0D + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment=0D +**/=0D +VOID=0D +PmcGetGpioGpe (=0D + OUT UINT32 *GpeDw0Value,=0D + OUT UINT32 *GpeDw1Value,=0D + OUT UINT32 *GpeDw2Value=0D + );=0D +=0D +#endif // _PMC_PRIVATE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/R= egister/PmcRegsVer2.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Inclu= dePrivate/Register/PmcRegsVer2.h new file mode 100644 index 0000000000..986173dd7d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/IncludePrivate/Register= /PmcRegsVer2.h @@ -0,0 +1,52 @@ +/** @file=0D + Register names for Ver2 PCH PMC device=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PMC_TGL_H_=0D +#define _PCH_REGS_PMC_TGL_H_=0D +=0D +//=0D +// PWRM Registers=0D +//=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_B 0x0=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_A 0x2=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_R 0x3=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPD 0x4=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_S 0x5=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_H 0x6=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_D 0x7=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_F 0xA=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_C 0xB=0D +#define V_TGL_PCH_LP_PMC_PWRM_GPIO_CFG_GPP_E 0xC=0D +=0D +#endif // _PCH_REGS_PMC_TGL_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSm= mPmcLib/PeiDxeSmmPmcLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc= /Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf new file mode 100644 index 0000000000..eba6db767c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib= /PeiDxeSmmPmcLib.inf @@ -0,0 +1,42 @@ +## @file=0D +# PEI/DXE/SMM PCH PMC Lib.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPmcLib=0D +FILE_GUID =3D 9D60C364-5086-41E3-BC9D-C62AB7233DBF=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PmcLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PchCycleDecodingLib=0D +PchPcrLib=0D +PchInfoLib=0D +BaseMemoryLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Pcd]=0D +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress=0D +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress=0D +=0D +[Sources]=0D +PmcLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSm= mPmcLib/PmcLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/Pe= iDxeSmmPmcLib/PmcLib.c new file mode 100644 index 0000000000..78e596b268 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/Library/PeiDxeSmmPmcLib= /PmcLib.c @@ -0,0 +1,545 @@ +/** @file=0D + PCH PMC Library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get PCH ACPI base address.=0D +=0D + @retval Address Address of PWRM base address.=0D +**/=0D +UINT16=0D +PmcGetAcpiBase (=0D + VOID=0D + )=0D +{=0D + return PcdGet16 (PcdAcpiBaseAddress);=0D +}=0D +=0D +/**=0D + Get PCH PWRM base address.=0D +=0D + @retval Address Address of PWRM base address.=0D +**/=0D +UINT32=0D +PmcGetPwrmBase (=0D + VOID=0D + )=0D +{=0D + return PCH_PWRM_BASE_ADDRESS;=0D +}=0D +=0D +/**=0D + This function enables Power Button SMI=0D +**/=0D +VOID=0D +PmcEnablePowerButtonSmi (=0D + VOID=0D + )=0D +{=0D + IoOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);= =0D +}=0D +=0D +/**=0D + This function disables Power Button SMI=0D +**/=0D +VOID=0D +PmcDisablePowerButtonSmi (=0D + VOID=0D + )=0D +{=0D + IoAnd16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_EN, (UINT16)~B_ACPI_IO_PM1_EN= _PWRBTN);=0D +}=0D +=0D +/**=0D + This function reads PM Timer Count driven by 3.579545 MHz clock=0D +=0D + @retval PM Timer Count=0D +**/=0D +UINT32=0D +PmcGetTimerCount (=0D + VOID=0D + )=0D +{=0D + return IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_PM1_TMR) & B_ACPI_IO_PM1_= TMR_VAL;=0D +}=0D +=0D +/**=0D + Get Sleep Type that platform has waken from=0D +=0D + @retval SleepType Sleep Type=0D +**/=0D +PMC_SLEEP_STATE=0D +PmcGetSleepTypeAfterWake (=0D + VOID=0D + )=0D +{=0D + UINT16 AcpiBase;=0D + UINT32 PmconA;=0D +=0D + AcpiBase =3D PmcGetAcpiBase ();=0D + PmconA =3D MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A);=0D +=0D + DEBUG ((DEBUG_INFO, "PWRM_PMCON_A =3D 0x%x\n", PmconA));=0D +=0D + //=0D + // If Global Reset Status, Power Failure. Host Reset Status bits are set= , return S5 State=0D + //=0D + if ((PmconA & (B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS | B_PMC_PWRM_GEN_PMCON= _A_PWR_FLR | B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS)) !=3D 0) {=0D + return PmcNotASleepState;=0D + }=0D +=0D + if (IoRead16 (AcpiBase + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM1_STS_WAK) {=0D + switch (IoRead16 (AcpiBase + R_ACPI_IO_PM1_CNT) & B_ACPI_IO_PM1_CNT_SL= P_TYP) {=0D + case V_ACPI_IO_PM1_CNT_S0:=0D + return PmcInS0State;=0D +=0D + case V_ACPI_IO_PM1_CNT_S1:=0D + return PmcS1SleepState;=0D +=0D + case V_ACPI_IO_PM1_CNT_S3:=0D + return PmcS3SleepState;=0D +=0D + case V_ACPI_IO_PM1_CNT_S4:=0D + return PmcS4SleepState;=0D +=0D + case V_ACPI_IO_PM1_CNT_S5:=0D + return PmcS5SleepState;=0D +=0D + default:=0D + ASSERT (FALSE);=0D + return PmcUndefinedState;=0D + }=0D + } else {=0D + return PmcNotASleepState;=0D + }=0D +}=0D +=0D +/**=0D + Clear PMC Wake Status=0D +**/=0D +VOID=0D +PmcClearWakeStatus (=0D + VOID=0D + )=0D +{=0D + IoWrite16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_WAK)= ;=0D +}=0D +=0D +/**=0D + Configure sleep state=0D +=0D + @param[in] SleepState S0/S1/S3/S4/S5, refer to PMC_SLEEP_STATE=0D +**/=0D +VOID=0D +PmcSetSleepState (=0D + PMC_SLEEP_STATE SleepState=0D + )=0D +{=0D + UINT16 Data16;=0D +=0D + switch (SleepState) {=0D + case PmcInS0State:=0D + Data16 =3D V_ACPI_IO_PM1_CNT_S0;=0D + break;=0D +=0D + case PmcS1SleepState:=0D + Data16 =3D V_ACPI_IO_PM1_CNT_S1;=0D + break;=0D +=0D + case PmcS3SleepState:=0D + Data16 =3D V_ACPI_IO_PM1_CNT_S3;=0D + break;=0D +=0D + case PmcS4SleepState:=0D + Data16 =3D V_ACPI_IO_PM1_CNT_S4;=0D + break;=0D +=0D + case PmcS5SleepState:=0D + Data16 =3D V_ACPI_IO_PM1_CNT_S5;=0D + break;=0D +=0D + default:=0D + ASSERT (FALSE);=0D + return;=0D +=0D + }=0D + IoAndThenOr16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_CNT, (UINT16) ~B_ACPI_I= O_PM1_CNT_SLP_TYP, Data16);=0D +}=0D +=0D +/**=0D + Check if platform boots after shutdown caused by power button override e= vent=0D +=0D + @retval TRUE Power Button Override occurred in last system boot=0D + @retval FALSE Power Button Override didn't occur=0D +**/=0D +BOOLEAN=0D +PmcIsPowerButtonOverrideDetected (=0D + VOID=0D + )=0D +{=0D + return ((IoRead16 (PmcGetAcpiBase () + R_ACPI_IO_PM1_STS) & B_ACPI_IO_PM= 1_STS_PRBTNOR) !=3D 0);=0D +}=0D +=0D +/**=0D + This function sets tPCH25 timing=0D +=0D + @param[in] TimingValue tPCH25 timing value (10us, 100us, 1ms, 10ms= )=0D +**/=0D +VOID=0D +PmcSetTPch25Timing (=0D + IN PMC_TPCH25_TIMING TimingValue=0D + )=0D +{=0D + ASSERT (TimingValue <=3D PmcTPch25_10ms);=0D +=0D + MmioAndThenOr32 (=0D + (UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_CFG),=0D + (UINT32)~(B_PMC_PWRM_CFG_TIMING_TPCH25),=0D + TimingValue=0D + );=0D +}=0D +=0D +/**=0D + This function checks if RTC Power Failure occurred by=0D + reading RTC_PWR_FLR bit=0D +=0D + @retval RTC Power Failure state: TRUE - Battery is always present.=0D + FALSE - CMOS is cleared.=0D +**/=0D +BOOLEAN=0D +PmcIsRtcBatteryGood (=0D + VOID=0D + )=0D +{=0D + return ((MmioRead8 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_= PWRM_GEN_PMCON_B_RTC_PWR_STS) =3D=3D 0);=0D +}=0D +=0D +/**=0D + This function checks if Power Failure occurred by=0D + reading PWR_FLR bit=0D +=0D + @retval Power Failure state=0D +**/=0D +BOOLEAN=0D +PmcIsPowerFailureDetected (=0D + VOID=0D + )=0D +{=0D + return ((MmioRead16 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A) & B_PMC= _PWRM_GEN_PMCON_A_PWR_FLR) !=3D 0);=0D +}=0D +=0D +/**=0D + This function checks if Power Failure occurred by=0D + reading SUS_PWR_FLR bit=0D +=0D + @retval SUS Power Failure state=0D +**/=0D +BOOLEAN=0D +PmcIsSusPowerFailureDetected (=0D + VOID=0D + )=0D +{=0D + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A) & B_PMC= _PWRM_GEN_PMCON_A_SUS_PWR_FLR) !=3D 0);=0D +}=0D +=0D +/**=0D + This function clears Power Failure status (PWR_FLR)=0D +**/=0D +VOID=0D +PmcClearPowerFailureStatus (=0D + VOID=0D + )=0D +{=0D + //=0D + // Write 1 to clear PWR_FLR=0D + // Avoid clearing other W1C bits=0D + //=0D + MmioAndThenOr8 (=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1,=0D + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8),=0D + B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8=0D + );=0D +}=0D +=0D +/**=0D + This function clears Global Reset status (GBL_RST_STS)=0D +**/=0D +VOID=0D +PmcClearGlobalResetStatus (=0D + VOID=0D + )=0D +{=0D + //=0D + // Write 1 to clear GBL_RST_STS=0D + // Avoid clearing other W1C bits=0D + //=0D + MmioAndThenOr8 (=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 3,=0D + (UINT8) ~0,=0D + B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS >> 24=0D + );=0D +}=0D +=0D +/**=0D + This function clears Host Reset status (HOST_RST_STS)=0D +**/=0D +VOID=0D +PmcClearHostResetStatus (=0D + VOID=0D + )=0D +{=0D + //=0D + // Write 1 to clear HOST_RST_STS=0D + // Avoid clearing other W1C bits=0D + //=0D + MmioAndThenOr8 (=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1,=0D + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_PWR_FLR >> 8),=0D + B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS >> 8=0D + );=0D +}=0D +=0D +/**=0D + This function clears SUS Power Failure status (SUS_PWR_FLR)=0D +**/=0D +VOID=0D +PmcClearSusPowerFailureStatus (=0D + VOID=0D + )=0D +{=0D + //=0D + // BIOS clears this bit by writing a '1' to it.=0D + // Take care of other fields, so we don't clear them accidentally.=0D + //=0D + MmioAndThenOr8 (=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2,=0D + (UINT8) ~(B_PMC_PWRM_GEN_PMCON_A_MS4V >> 16),=0D + B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR >> 16=0D + );=0D +}=0D +=0D +/**=0D + This function sets state to which platform will get after power is reapp= lied=0D +=0D + @param[in] PowerStateAfterG3 0: S0 state (boot)=0D + 1: S5/S4 State=0D +**/=0D +VOID=0D +PmcSetPlatformStateAfterPowerFailure (=0D + IN UINT8 PowerStateAfterG3=0D + )=0D +{=0D + UINT32 PchPwrmBase;=0D +=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + if (PowerStateAfterG3) {=0D + MmioOr8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, B_PMC_PWRM_GEN_PMCON_A_= AFTERG3_EN);=0D + } else {=0D + MmioAnd8 (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A, (UINT8)~B_PMC_PWRM_GEN= _PMCON_A_AFTERG3_EN);=0D + }=0D +}=0D +=0D +/**=0D + This function will set the DISB - DRAM Initialization Scratchpad Bit.=0D +**/=0D +VOID=0D +PmcSetDramInitScratchpad (=0D + VOID=0D + )=0D +{=0D + //=0D + // Set B_CNL_PCH_PWRM_GEN_PMCON_A_DISB.=0D + // NOTE: Byte access and not clear BIT18 and BIT16 (W1C bits)=0D + //=0D + MmioAndThenOr8 (=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 2,=0D + (UINT8) ~((B_PMC_PWRM_GEN_PMCON_A_MS4V | B_PMC_PWRM_GEN_PMCON_A_SUS_PW= R_FLR) >> 16),=0D + B_PMC_PWRM_GEN_PMCON_A_DISB >> 16=0D + );=0D +}=0D +=0D +/**=0D + Check global SMI enable is set=0D +=0D + @retval TRUE Global SMI enable is set=0D + FALSE Global SMI enable is not set=0D +**/=0D +BOOLEAN=0D +PmcIsGblSmiEn (=0D + VOID=0D + )=0D +{=0D + return !!(IoRead32 (PmcGetAcpiBase () + R_ACPI_IO_SMI_EN) & B_ACPI_IO_SM= I_EN_GBL_SMI);=0D +}=0D +=0D +/**=0D + This function checks if SMI Lock is set=0D +=0D + @retval SMI Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsSmiLockSet (=0D + VOID=0D + )=0D +{=0D + return ((MmioRead8 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B)= ) & B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK) !=3D 0);=0D +}=0D +=0D +/**=0D + This function checks if Debug Mode is locked=0D +=0D + @retval Debug Mode Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsDebugModeLocked (=0D + VOID=0D + )=0D +{=0D + //=0D + // Get lock info from PWRMBASE + PM_CFG=0D + //=0D + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_CFG) & B_PMC_PWRM_CF= G_DBG_MODE_LOCK) !=3D 0);=0D +}=0D +=0D +/**=0D + Check TCO second timeout status.=0D +=0D + @retval TRUE TCO reboot happened.=0D + @retval FALSE TCO reboot didn't happen.=0D +**/=0D +BOOLEAN=0D +TcoSecondToHappened (=0D + VOID=0D + )=0D +{=0D + ///=0D + /// Read the Second TO status bit=0D + ///=0D + if ((IoRead8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS) & R_TCO_= IO_TCO2_STS) !=3D 0) {=0D + return TRUE;=0D + } else {=0D + return FALSE;=0D + }=0D +}=0D +=0D +/**=0D + This function clears the Second TO status bit=0D +**/=0D +VOID=0D +TcoClearSecondToStatus (=0D + VOID=0D + )=0D +{=0D + IoWrite8 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO2_STS, B_TCO_IO_TCO= 2_STS_SECOND_TO);=0D +}=0D +=0D +/**=0D + Check TCO SMI ENABLE is locked=0D +=0D + @retval TRUE TCO SMI ENABLE is locked=0D + FALSE TCO SMI ENABLE is not locked=0D +**/=0D +BOOLEAN=0D +TcoIsSmiLock (=0D + VOID=0D + )=0D +{=0D + return !!(IoRead16 (PcdGet16 (PcdTcoBaseAddress) + R_TCO_IO_TCO1_CNT) & = B_TCO_IO_TCO1_CNT_LOCK);=0D +}=0D +=0D +/**=0D + Check if user wants to turn off in PEI phase and power it off=0D + CAUTION: this function will potentially turn off your system=0D +**/=0D +VOID=0D +CheckPowerOffNow (=0D + VOID=0D + )=0D +{=0D + UINT16 ABase;=0D + UINT16 Pm1Sts;=0D +=0D + ABase =3D PmcGetAcpiBase ();=0D +=0D + //=0D + // Read and check the ACPI registers=0D + //=0D + Pm1Sts =3D IoRead16 (ABase + R_ACPI_IO_PM1_STS);=0D +=0D + DEBUG ((DEBUG_ERROR, "CheckPowerOffNow ()- Pm1Sts=3D 0x%04x\n", Pm1Sts))= ;=0D +=0D + if ((Pm1Sts & B_ACPI_IO_PM1_STS_PWRBTN) !=3D 0) {=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN);=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_CNT, V_ACPI_IO_PM1_CNT_S5);=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_CNT, V_ACPI_IO_PM1_CNT_S5 | B_ACPI_IO= _PM1_CNT_SLP_EN);=0D + }=0D +}=0D +=0D +/**=0D + Clear any SMI status or wake status.=0D +**/=0D +VOID=0D +ClearSmiAndWake (=0D + VOID=0D + )=0D +{=0D + UINT16 ABase;=0D + UINT16 Pm1Sts;=0D +=0D + ABase =3D PmcGetAcpiBase ();=0D +=0D + //=0D + // Clear any SMI or wake state from the boot=0D + //=0D + Pm1Sts =3D B_ACPI_IO_PM1_STS_PWRBTN;=0D +=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, Pm1Sts);=0D +=0D + //=0D + // Clear the GPE and PM enable=0D + //=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_EN, 0);=0D + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);=0D +}=0D +=0D +=0D +/**=0D + Function to check if Dirty Warm Reset occurs=0D + (Global Reset has been converted to Host Reset)=0D +=0D + @reval TRUE DWR occurs=0D + @reval FALSE Normal boot flow=0D +**/=0D +BOOLEAN=0D +PmcIsDwrBootMode (=0D + VOID=0D + )=0D +{=0D + UINT32 PchPwrmBase;=0D +=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D + ASSERT (PchPwrmBase !=3D 0);=0D +=0D + return !!(MmioRead32 (PchPwrmBase + R_PMC_PWRM_HPR_CAUSE0) & B_PMC_PWRM_= HPR_CAUSE0_GBL_TO_HOST);=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/P= eiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf b/Silicon/Intel/Tigerl= akeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPm= cPrivateLibVer2.inf new file mode 100644 index 0000000000..2bd57b79f0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf @@ -0,0 +1,39 @@ +## @file=0D +# PEI/DXE/SMM PCH PMC Private Lib Ver2.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPmcPrivateLibVer2=0D +FILE_GUID =3D EB69B12B-6D4C-4B12-BB31-66CBCC4C1DC7=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PmcPrivateLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PmcLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Pcd]=0D +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress=0D +=0D +[FixedPcd]=0D +=0D +[Sources]=0D +PmcPrivateLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/P= eiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf b/Silicon/Intel/Tige= rlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmm= PmcPrivateLibWithS3.inf new file mode 100644 index 0000000000..72a21cfe14 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf @@ -0,0 +1,40 @@ +## @file=0D +# PEI/DXE/SMM PCH private PMC Lib.=0D +# This part of PMC lib includes S3BootScript support=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPmcPrivateLibWithS3=0D +FILE_GUID =3D 5890CA5A-1955-4A02-A09C-01E4150606CC=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PmcPrivateLibWithS3=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PmcLib=0D +PcdLib=0D +S3BootScriptLib=0D +PchPciBdfLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +PmcPrivateLibWithS3.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/P= eiDxeSmmPmcPrivateLib/PmcPrivateLib.c b/Silicon/Intel/TigerlakeSiliconPkg/I= pBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLib.c new file mode 100644 index 0000000000..4f04765886 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PmcPrivateLib.c @@ -0,0 +1,166 @@ +/** @file=0D + PCH private PMC Library for all PCH generations.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This function checks if GbE device is supported (not disabled by fuse)=0D +=0D + @retval GbE support state=0D +**/=0D +BOOLEAN=0D +PmcIsGbeSupported (=0D + VOID=0D + )=0D +{=0D + //=0D + // Get fuse info from PWRMBASE + FUSE_SS_DIS_RD_2=0D + //=0D + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_FUSE_DIS_RD_2) & B_P= MC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS) =3D=3D 0);=0D +}=0D +=0D +/**=0D + This function checks if LAN wake from DeepSx is enabled=0D +=0D + @retval Lan Wake state=0D +**/=0D +BOOLEAN=0D +PmcIsLanDeepSxWakeEnabled (=0D + VOID=0D + )=0D +{=0D + //=0D + // Get wake info from PWRMBASE + DSX_CFG=0D + //=0D + return ((MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_DSX_CFG) & (UINT32) = B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN) !=3D 0);=0D +}=0D +=0D +/**=0D + This function checks if eSPI SMI Lock is set=0D +=0D + @retval eSPI SMI Lock state=0D +**/=0D +BOOLEAN=0D +PmcIsEspiSmiLockSet (=0D + VOID=0D + )=0D +{=0D + return ((MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A= )) & B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK) !=3D 0);=0D +}=0D +=0D +/**=0D + This function sets SW SMI Rate.=0D +=0D + @param[in] SwSmiRate Refer to PMC_SWSMI_RATE for possible values= =0D +**/=0D +VOID=0D +PmcSetSwSmiRate (=0D + IN PMC_SWSMI_RATE SwSmiRate=0D + )=0D +{=0D + UINT32 PchPwrmBase;=0D + STATIC UINT8 SwSmiRateRegVal[4] =3D {=0D + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS,=0D + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS,=0D + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS,=0D + V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS=0D + };=0D +=0D + ASSERT (SwSmiRate <=3D PmcSwSmiRate64ms);=0D +=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + //=0D + // SWSMI_RATE_SEL BIT (PWRMBASE offset 1020h[7:6]) bits are in RTC well= =0D + //=0D + MmioAndThenOr8 (=0D + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,=0D + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL,=0D + SwSmiRateRegVal[SwSmiRate]=0D + );=0D +}=0D +=0D +/**=0D + This function sets Periodic SMI Rate.=0D +=0D + @param[in] PeriodicSmiRate Refer to PMC_PERIODIC_SMI_RATE for pos= sible values=0D +**/=0D +VOID=0D +PmcSetPeriodicSmiRate (=0D + IN PMC_PERIODIC_SMI_RATE PeriodicSmiRate=0D + )=0D +{=0D + UINT32 PchPwrmBase;=0D + STATIC UINT8 PeriodicSmiRateRegVal[4] =3D {=0D + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S,=0D + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S,=0D + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S,=0D + V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S=0D + };=0D +=0D + ASSERT (PeriodicSmiRate <=3D PmcPeriodicSmiRate64s);=0D +=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + MmioAndThenOr8 (=0D + PchPwrmBase + R_PMC_PWRM_GEN_PMCON_A,=0D + (UINT8)~B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL,=0D + PeriodicSmiRateRegVal[PeriodicSmiRate]=0D + );=0D +}=0D +=0D +/**=0D + This function reads Power Button Level=0D +=0D + @retval State of PWRBTN# signal (0: Low, 1: High)=0D +**/=0D +UINT8=0D +PmcGetPwrBtnLevel (=0D + VOID=0D + )=0D +{=0D + if (MmioRead32 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_B) & B_PMC_PWRM= _GEN_PMCON_B_PWRBTN_LVL) {=0D + return 1;=0D + } else {=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D + This function gets Group to GPE0 configuration=0D +=0D + @param[out] GpeDw0Value GPIO Group to GPE_DW0 assignment=0D + @param[out] GpeDw1Value GPIO Group to GPE_DW1 assignment=0D + @param[out] GpeDw2Value GPIO Group to GPE_DW2 assignment=0D +**/=0D +VOID=0D +PmcGetGpioGpe (=0D + OUT UINT32 *GpeDw0Value,=0D + OUT UINT32 *GpeDw1Value,=0D + OUT UINT32 *GpeDw2Value=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D + Data32 =3D MmioRead32 ((UINTN) (PmcGetPwrmBase () + R_PMC_PWRM_GPIO_CFG)= );=0D +=0D + *GpeDw0Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW0) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW0);=0D + *GpeDw1Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW1) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW1);=0D + *GpeDw2Value =3D ((Data32 & B_PMC_PWRM_GPIO_CFG_GPE0_DW2) >> N_PMC_PWRM_= GPIO_CFG_GPE0_DW2);=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/P= eiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c b/Silicon/Intel/TigerlakeSilico= nPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PmcPrivateLibWithS3.c new file mode 100644 index 0000000000..02acd0d688 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Pmc/LibraryPrivate/PeiDxeSm= mPmcPrivateLib/PmcPrivateLibWithS3.c @@ -0,0 +1,122 @@ +/** @file=0D + PCH private PMC Library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This S3 BootScript only function disables triggering Global Reset of bot= h=0D + the Host and the ME partitions after CF9h write of 6h or Eh.=0D +**/=0D +VOID=0D +PmcDisableCf9GlobalResetInS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT32 Data;=0D +=0D + UINT32 PchPwrmBase;=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3);=0D +=0D + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR;=0D +=0D + S3BootScriptSaveMemWrite (=0D + S3BootScriptWidthUint32,=0D + (UINTN) PchPwrmBase +=0D + R_PMC_PWRM_ETR3,=0D + 1,=0D + &Data=0D + );=0D +}=0D +=0D +/**=0D + This S3 BootScript only function disables triggering Global Reset of bot= h=0D + the Host and the ME partitions after CF9h write of 6h or Eh.=0D + Global Reset configuration is locked after programming=0D +**/=0D +VOID=0D +PmcDisableCf9GlobalResetWithLockInS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT32 Data;=0D +=0D + UINT32 PchPwrmBase;=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + Data =3D MmioRead32 (PchPwrmBase + R_PMC_PWRM_ETR3);=0D +=0D + Data &=3D (UINT32) ~B_PMC_PWRM_ETR3_CF9GR;=0D + Data |=3D (UINT32) B_PMC_PWRM_ETR3_CF9LOCK;=0D +=0D + S3BootScriptSaveMemWrite (=0D + S3BootScriptWidthUint32,=0D + (UINTN) PchPwrmBase +=0D + R_PMC_PWRM_ETR3,=0D + 1,=0D + &Data=0D + );=0D +}=0D +=0D +/**=0D + This function sets SMI Lock with S3 Boot Script programming=0D +**/=0D +VOID=0D +PmcLockSmiWithS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT32 PchPwrmBase;=0D +=0D + PchPwrmBase =3D PmcGetPwrmBase ();=0D +=0D + MmioOr8 ((UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B), B_PMC_PWRM_GEN_= PMCON_B_SMI_LOCK);=0D +=0D + S3BootScriptSaveMemWrite (=0D + S3BootScriptWidthUint8,=0D + (UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B),=0D + 1,=0D + (VOID *) (UINTN) (PchPwrmBase + R_PMC_PWRM_GEN_PMCON_B)=0D + );=0D +}=0D +=0D +/**=0D + This function sets eSPI SMI Lock=0D + @attention This function must be called after eSPI SMI generation has be= en enabled.=0D + This setting is required in all boot modes and before EndOfDxe.=0D + If set value will be restored upon S3 resume by bootscript.=0D +**/=0D +VOID=0D +PmcLockEspiSmiWithS3BootScript (=0D + VOID=0D + )=0D +{=0D + UINT8 Data8Or;=0D + UINT8 Data8And;=0D +=0D + Data8Or =3D (UINT8) (B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK >> 8);=0D + Data8And =3D (UINT8)~((B_PMC_PWRM_GEN_PMCON_A_PWR_FLR | B_PMC_PWRM_GEN_P= MCON_A_HOST_RST_STS) >> 8);=0D +=0D + MmioAndThenOr8 (PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1, Data8And= , Data8Or);=0D + S3BootScriptSaveMemReadWrite (=0D + S3BootScriptWidthUint8,=0D + PmcGetPwrmBase () + R_PMC_PWRM_GEN_PMCON_A + 1,=0D + &Data8Or,=0D + &Data8And=0D + );=0D +}=0D --=20 2.24.0.windows.2