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Feb 2021 00:51:32 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Date: Thu, 4 Feb 2021 16:49:06 +0800 Message-Id: <20210204084919.3603-27-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/SerialIo/IncludePrivate * IpBlock/SerialIo/Library * IpBlock/SerialIo/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Library/= SerialIoPrivateLib.h | 377 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Register= /SerialIoRegsVer2.h | 108 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerial= IoAccessLib/PeiDxeSmmSerialIoAccessLib.inf | 35 +++++++++++++= ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerial= IoAccessLib/SerialIoAccessLib.c | 266 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf | 34 +++++++++++++= +++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLib.c | 156 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibI2c.c | 122 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c | 70 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibInternal.h | 20 +++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibSpi.c | 122 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c | 82 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibUart.c | 136 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSm= mSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c | 82 +++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 13 files changed, 1610 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePriv= ate/Library/SerialIoPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBloc= k/SerialIo/IncludePrivate/Library/SerialIoPrivateLib.h new file mode 100644 index 0000000000..47057cd2ef --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Lib= rary/SerialIoPrivateLib.h @@ -0,0 +1,377 @@ +/** @file=0D + Header file for Serial IO Private Lib implementation.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_PRIVATE_LIB_H_=0D +#define _SERIAL_IO_PRIVATE_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +/**=0D + Serial Io Pci Device State structure.=0D + Used to preserve current information about the device when it is configu= red in Pci mode prior to Pch Initialization.=0D +**/=0D +typedef struct {=0D + UINT64 PciCfgBar0; ///< Pci Config Space Base Address Register=0D + UINT8 PciCfgCommand; ///< Pci Config Space Command Register=0D + UINT8 PciCfgPmeCtrlSts; ///< Pci Config Space Pme Control Status=0D + UINT8 PprReset; ///< MMIO Proprietary Reset Register=0D +} SERIAL_IO_PCI_DEVICE_STATE;=0D +=0D +/**=0D + Checks if higher functions are enabled.=0D + Used for Function 0 Serial Io Device disabling=0D +=0D + @param[in] DeviceNum Device Number=0D +=0D + @retval TRUE At least one higher function device is enable= d=0D + FALSE Higher functions are disabled=0D +**/=0D +BOOLEAN=0D +SerialIoHigherFunctionsEnabled (=0D + IN UINT8 DeviceNum=0D + );=0D +=0D +/**=0D + Places SerialIo device in D3=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoSetD3 (=0D + IN UINT64 PciCfgBase=0D + );=0D +=0D +/**=0D + Places SerialIo device in D0=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoSetD0 (=0D + IN UINT64 PciCfgBase=0D + );=0D +=0D +/**=0D + Allows Memory Access=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D + @param[in] Hidden Mode that determines access type=0D +=0D +**/=0D +VOID=0D +SerialIoEnableMse (=0D + IN UINT64 PciCfgBase,=0D + IN BOOLEAN Hidden=0D + );=0D +=0D +/**=0D + Disable SerialIo memory access=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoDisableMse (=0D + IN UINT64 PciCfgBase=0D + );=0D +=0D +/**=0D + Disable SerialIo memory encoding=0D + Designated for Pci modes=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D + @param[in] RemoveTempBar Remove temporary mem base address or not=0D +=0D +**/=0D +VOID=0D +SerialIoMmioDisable (=0D + IN UINT64 PciCfgBase,=0D + IN BOOLEAN RemoveBar=0D + );=0D +=0D +/**=0D + Gets Fixed Base Address used for BAR0=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Config control offset=0D +**/=0D +UINT32=0D +GetSerialIoSpiFixedMmioAddress (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoSpiFixedPciCfgAddress (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Gets Spi Device Id=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoSpiDeviceId (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Checks if SPI is Hidden, and it's Pci Config space available=0D +=0D + @param[in] SpiNumber Selects Serial IO SPI device=0D +=0D + @retval TRUE SPI is in hidden mode=0D + @retval FALSE SPI is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoSpiHidden (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] SpiNumber SPI Number=0D + @param[in] SpiDeviceConfig SerialIo SPI Config=0D +=0D +**/=0D +VOID=0D +SerialIoSpiBootHandler (=0D + IN UINT8 SpiNumber,=0D + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig=0D + );=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] SpiNumber SPI Number=0D + @param[in] SpiDeviceConfig SerialIo SPI Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save=0D +=0D +**/=0D +VOID=0D +SerialIoSpiS3Handler (=0D + IN UINT8 SpiNumber,=0D + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + );=0D +=0D +/**=0D + Gets Pci Config control offset=0D +=0D + @param[in] UartNumber Serial IO device UART number=0D +=0D + @retval Config control offset=0D +**/=0D +UINT16=0D +GetSerialIoUartConfigControlOffset (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Gets Fixed Base Address used for BAR0=0D +=0D + @param[in] UartNumber Serial IO device UART number=0D +=0D + @retval Config control offset=0D +**/=0D +UINT32=0D +GetSerialIoUartFixedMmioAddress (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] UartNumber Serial IO device UART number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoUartFixedPciCfgAddress (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Returns UART S3 boot script PCI address=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval UART S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoUartS3PciBase (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Returns SPI S3 boot script PCI address=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval SPI S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoSpiS3PciBase (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Returns I2C S3 boot script PCI address=0D +=0D + @param[in] I2cNumber I2C Number=0D +=0D + @retval I2C S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoI2cS3PciBase (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Gets Uarts Device Id=0D +=0D + @param[in] UartNumbe Serial IO device UART number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoUartDeviceId (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Checks if UART is Hidden, and it's Pci Config space available=0D +=0D + @param[in] UartNumber Selects Serial IO UART device=0D +=0D + @retval TRUE UART is in hidden mode=0D + @retval FALSE UART is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoUartHidden (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] UartNumber UART Number=0D + @param[in] UartDeviceConfig SerialIo UART Config=0D +=0D +**/=0D +VOID=0D +SerialIoUartBootHandler (=0D + IN UINT8 UartNumber,=0D + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig=0D + );=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] UartNumber UART Number=0D + @param[in] UartDeviceConfig SerialIo UART Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save= =0D +=0D +**/=0D +VOID=0D +SerialIoUartS3Handler (=0D + IN UINT8 UartNumber,=0D + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + );=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] I2cNumber Serial IO device I2C number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoI2cFixedPciCfgAddress (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Gets I2C Device Id=0D +=0D + @param[in] I2cNumber Serial IO device I2C number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoI2cDeviceId (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Checks if I2C is Hidden, and it's Pci Config space available=0D +=0D + @param[in] 2cNumber Selects Serial IO I2C device=0D +=0D + @retval TRUE I2C is in hidden mode=0D + @retval FALSE I2C is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cHidden (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] I2cNumber I2C Number=0D + @param[in] I2cDeviceConfig SerialIo I2C Config=0D +=0D +**/=0D +VOID=0D +SerialIoI2cBootHandler (=0D + IN UINT8 I2cNumber,=0D + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig=0D + );=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] I2cNumber I2C Number=0D + @param[in] I2cDeviceConfig SerialIo I2C Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save=0D +=0D +**/=0D +VOID=0D +SerialIoI2cS3Handler (=0D + IN UINT8 I2cNumber,=0D + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + );=0D +=0D +#endif // _SERIAL_IO_PRIVATE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePriv= ate/Register/SerialIoRegsVer2.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock= /SerialIo/IncludePrivate/Register/SerialIoRegsVer2.h new file mode 100644 index 0000000000..01840b14c9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/IncludePrivate/Reg= ister/SerialIoRegsVer2.h @@ -0,0 +1,108 @@ +/** @file=0D + Device IDs for Serial IO Controllers for TGL PCH=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D +=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_REGS_VER2_H_=0D +#define _SERIAL_IO_REGS_VER2_H_=0D +//=0D +// Serial IO I2C0 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID 0xA0E8=0D +=0D +//=0D +// Serial IO I2C1 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID 0xA0E9=0D +=0D +//=0D +// Serial IO I2C2 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID 0xA0EA=0D +=0D +//=0D +// Serial IO I2C3 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID 0xA0EB=0D +=0D +//=0D +// Serial IO I2C4 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID 0xA0C5=0D +=0D +//=0D +// Serial IO I2C5 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID 0xA0C6=0D +=0D +//=0D +// Serial IO SPI0 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID 0xA0AA=0D +=0D +//=0D +// Serial IO SPI1 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID 0xA0AB=0D +=0D +//=0D +// Serial IO SPI2 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI2_DEVICE_ID 0xA0FB=0D +=0D +//=0D +// Serial IO SPI3 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_SPI3_DEVICE_ID 0xA0FD=0D +=0D +//=0D +// Serial IO UART0 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID 0xA0A8=0D +=0D +//=0D +// Serial IO UART1 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID 0xA0A9=0D +=0D +//=0D +// Serial IO UART2 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID 0xA0C7=0D +=0D +//=0D +// Serial IO UART3 Controller Registers=0D +//=0D +#define V_VER2_PCH_LP_SERIAL_IO_CFG_UART3_DEVICE_ID 0xA0DA=0D +=0D +#endif //_SERIAL_IO_REGS_VER2_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/Pei= DxeSmmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf b/Silicon/Intel/Tige= rlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/PeiDxeS= mmSerialIoAccessLib.inf new file mode 100644 index 0000000000..9178840ca8 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmS= erialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf @@ -0,0 +1,35 @@ +## @file=0D +# Component description file for PEI/DXE/SMM Serial Io Access Lib.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiDxeSmmSerialIoAccessLib=0D + FILE_GUID =3D F1A20692-26CA-4CA4-A775-695BBD6D3EC7=0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D SerialIoAccessLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + DebugLib=0D + PcdLib=0D + PciSegmentLib=0D + PchPcrLib=0D + SerialIoPrivateLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + SerialIoAccessLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/Pei= DxeSmmSerialIoAccessLib/SerialIoAccessLib.c b/Silicon/Intel/TigerlakeSilico= nPkg/IpBlock/SerialIo/Library/PeiDxeSmmSerialIoAccessLib/SerialIoAccessLib.c new file mode 100644 index 0000000000..2b3a3dca5a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/Library/PeiDxeSmmS= erialIoAccessLib/SerialIoAccessLib.c @@ -0,0 +1,266 @@ +/** @file=0D + Serial Io Common Lib implementation.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Returns BAR0=0D +=0D + @param[in] PciCfgBase Pci Config Base=0D +=0D + @retval 64bit MMIO BAR Address=0D +**/=0D +UINT64=0D +GetSerialIoBar (=0D + IN UINT64 PciCfgBase=0D + )=0D +{=0D + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) {=0D + return (UINT64) ((PciSegmentRead32 ((UINTN) (PciCfgBase + PCI_BASE_ADD= RESSREG_OFFSET)) & 0xFFFFF000) + LShiftU64 (PciSegmentRead32 ((UINTN) (PciC= fgBase + PCI_BASE_ADDRESSREG_OFFSET + 4)), 32));=0D + }=0D + return (UINT64) ((MmioRead32 ((UINTN) (PciCfgBase + PCI_BASE_ADDRESSREG_= OFFSET)) & 0xFFFFF000) + LShiftU64 (MmioRead32 ((UINTN) (PciCfgBase + PCI_B= ASE_ADDRESSREG_OFFSET + 4)), 32));=0D +}=0D +=0D +/**=0D + Returns I2C Pci Config Space=0D +=0D + @param[in] I2cNumber I2C Number=0D +=0D + @retval I2C Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoI2cPciCfg (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + if (IsSerialIoI2cHidden (I2cNumber)) {=0D + return (UINTN) GetSerialIoI2cFixedPciCfgAddress (I2cNumber);=0D + }=0D + return SerialIoI2cPciCfgBase (I2cNumber);=0D +}=0D +=0D +/**=0D + Returns SPI Pci Config Space=0D +=0D + @param[in] SpiNumber SPI Number=0D +=0D + @retval SPI Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoSpiPciCfg (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + if (IsSerialIoSpiHidden (SpiNumber)) {=0D + return (UINTN) GetSerialIoSpiFixedPciCfgAddress (SpiNumber);=0D + }=0D + return SerialIoSpiPciCfgBase (SpiNumber);=0D +}=0D +=0D +/**=0D + Returns UART Pci Config Space=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval UART Pci Config Space Address=0D +**/=0D +UINT64=0D +GetSerialIoUartPciCfg (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + if (IsSerialIoUartHidden (UartNumber)) {=0D + return GetSerialIoUartFixedPciCfgAddress (UartNumber);=0D + }=0D + return SerialIoUartPciCfgBase (UartNumber);=0D +}=0D +=0D +/**=0D + Returns SPI S3 boot script PCI address=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval SPI S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoSpiS3PciBase (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + if (IsSerialIoSpiHidden (SpiNumber)) {=0D + //=0D + // It's not expected to return Spi S3 Boot Script PCI address for non PC= I mode.=0D + //=0D + ASSERT (TRUE);=0D + }=0D + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoSpiDevNumber (SpiNumber),=0D + SerialIoSpiFuncNumber (SpiNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Returns UART S3 boot script PCI address=0D +=0D + @param[in] UartNumber UART Number=0D +=0D + @retval UART S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoUartS3PciBase (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + if (IsSerialIoUartHidden (UartNumber)) {=0D + //=0D + // It's not expected to return Uart S3 Boot Script PCI address for non P= CI mode.=0D + //=0D + ASSERT (TRUE);=0D + }=0D + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoUartDevNumber (UartNumber),=0D + SerialIoUartFuncNumber (UartNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Returns I2C S3 boot script PCI address=0D +=0D + @param[in] I2cNumber I2C Number=0D +=0D + @retval I2C S3 boot script PCI address=0D +**/=0D +UINT64=0D +GetSerialIoI2cS3PciBase (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + if (IsSerialIoI2cHidden (I2cNumber)) {=0D + //=0D + // It's not expected to return I2c S3 Boot Script PCI address for non PC= I mode.=0D + //=0D + ASSERT (TRUE);=0D + }=0D + return S3_BOOT_SCRIPT_LIB_PCI_ADDRESS (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoI2cDevNumber (I2cNumber),=0D + SerialIoI2cFuncNumber (I2cNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Checks if Device with given PciDeviceId is one of SerialIo I2C controlle= rs=0D + If yes, its number is returned through I2cIndex parameter, otherwise I2c= Index is not updated=0D +=0D + @param[in] PciDevId Device ID=0D + @param[out] I2cNumber Number of SerialIo I2C controller= =0D +=0D + @retval TRUE yes it is a SerialIo I2C controlle= r=0D + @retval FALSE no it isn't a SerialIo I2C control= ler=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cDeviceId (=0D + IN UINT16 PciDevId,=0D + OUT UINT8 *I2cNumber=0D + )=0D +{=0D + UINT8 Index;=0D +=0D + for (Index =3D 0; Index < GetPchMaxSerialIoI2cControllersNum (); Index++= ) {=0D + if (PciDevId =3D=3D GetSerialIoI2cDeviceId (Index)) {=0D + *I2cNumber =3D Index;=0D + return TRUE;=0D + }=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if I2c is Function 0 Enabled=0D +=0D + @param[in] I2cIndex Number of the SerialIo I2C control= ler=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cFunction0Enabled (=0D + IN UINT8 I2cIndex=0D + )=0D +{=0D + if (SerialIoI2cFuncNumber (I2cIndex) =3D=3D 0) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cIndex))) = {=0D + return TRUE;=0D + }=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if Uart is Function 0 Enabled=0D +=0D + @param[in] UartIndex Number of the SerialIo Uart contr= oller=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoUartFunction0Enabled (=0D + IN UINT8 UartIndex=0D + )=0D +{=0D + if (SerialIoUartFuncNumber (UartIndex) =3D=3D 0) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartIndex))= ) {=0D + return TRUE;=0D + }=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if Spi is Function 0 Enabled=0D +=0D + @param[in] SpiIndex Number of the SerialIo Spi control= ler=0D +=0D + @retval TRUE Enabled=0D + @retval FALSE Disabled=0D +**/=0D +BOOLEAN=0D +IsSerialIoSpiFunction0Enabled (=0D + IN UINT8 SpiIndex=0D + )=0D +{=0D + if (SerialIoSpiFuncNumber (SpiIndex) =3D=3D 0) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiIndex))) = {=0D + return TRUE;=0D + }=0D + }=0D + return FALSE;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf b/Silic= on/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSeria= lIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf new file mode 100644 index 0000000000..8981be2496 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf @@ -0,0 +1,34 @@ +## @file=0D +# Serial Io Private Lib Ver 2=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiDxeSmmSerialIoLibVer2=0D + FILE_GUID =3D 9D9F99CD-C072-48C2-BF78-ABA3D664C0FA=0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D SerialIoPrivateLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciSegmentLib=0D + SerialIoAccessLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + SerialIoPrivateLib.c=0D + SerialIoPrivateLibI2c.c=0D + SerialIoPrivateLibI2cVer2.c=0D + SerialIoPrivateLibSpi.c=0D + SerialIoPrivateLibSpiVer2.c=0D + SerialIoPrivateLibUart.c=0D + SerialIoPrivateLibUartVer2.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLib.c b/Silicon/Intel/Tigerl= akeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLib/S= erialIoPrivateLib.c new file mode 100644 index 0000000000..9b84c2dda6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLib.c @@ -0,0 +1,156 @@ +/** @file=0D + Serial IO Private Lib implementation.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Checks if higher functions are enabled.=0D + Used for Function 0 Serial Io Device disabling=0D +=0D + @param[in] DeviceNum Device Number=0D +=0D + @retval TRUE At least one higher function device is enable= d=0D + FALSE Higher functions are disabled=0D +**/=0D +BOOLEAN=0D +SerialIoHigherFunctionsEnabled (=0D + IN UINT8 DeviceNum=0D + )=0D +{=0D + UINT8 FuncNum;=0D + //=0D + // Check all other func devs(1 to 7) status except func 0.=0D + //=0D + for (FuncNum =3D 1; FuncNum <=3D PCI_MAX_FUNC; FuncNum++) {=0D + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (DEFAULT_PCI_SEGMENT_NUM= BER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_= PCH,=0D + DeviceNum,=0D + FuncNum,=0D + PCI_DEVICE_ID_OFFSET)=0D + ) !=3D 0xFFFF) {=0D + return TRUE;=0D + }=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Places SerialIo device in D3=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoSetD3 (=0D + IN UINT64 PciCfgBase=0D + )=0D +{=0D + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) {=0D + PciSegmentOr32 (PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BIT0= );=0D + } else {=0D + MmioOr8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, BIT1 | BIT= 0);=0D + //=0D + // Reading back value after write to ensure bridge observes the BAR1 w= rite access=0D + //=0D + MmioRead8 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);=0D + }=0D +}=0D +=0D +/**=0D + Places SerialIo device in D0=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoSetD0 (=0D + IN UINT64 PciCfgBase=0D + )=0D +{=0D + if (PciCfgBase < PCH_SERIAL_IO_BASE_ADDRESS) {=0D + PciSegmentAnd32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, (U= INT32) ~(BIT1 | BIT0));=0D + } else {=0D + MmioAnd32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS, (UINT32)= ~(BIT1 | BIT0));=0D + //=0D + // Reading back value after write to ensure bridge observes the BAR1 w= rite access=0D + //=0D + MmioRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_PME_CTRL_STS);=0D + }=0D +}=0D +=0D +/**=0D + Allows memory access=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D + @param[in] Hidden Mode that determines access type=0D +=0D +**/=0D +VOID=0D +SerialIoEnableMse (=0D + IN UINT64 PciCfgBase,=0D + IN BOOLEAN Hidden=0D + )=0D +{=0D + if (Hidden) {=0D + MmioOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMAND_MEM= ORY_SPACE);=0D + //=0D + // Reading back value after write to ensure bridge observes the BAR1 w= rite access=0D + //=0D + MmioRead16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET);=0D + } else {=0D + PciSegmentOr16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, EFI_PCI_COMMA= ND_MEMORY_SPACE);=0D + }=0D +}=0D +=0D +/**=0D + Disable SerialIo memory access=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D +=0D +**/=0D +VOID=0D +SerialIoDisableMse (=0D + IN UINT64 PciCfgBase=0D + )=0D +{=0D + PciSegmentAnd16 ((UINTN) PciCfgBase + PCI_COMMAND_OFFSET, (UINT16) ~EFI_= PCI_COMMAND_MEMORY_SPACE);=0D +}=0D +=0D +/**=0D + Disable SerialIo memory encoding=0D + Designated for Pci modes=0D +=0D + @param[in] PciCfgBase Pci Config Offset=0D + @param[in] RemoveTempBar Remove temporary mem base address or not=0D +=0D +**/=0D +VOID=0D +SerialIoMmioDisable (=0D + IN UINT64 PciCfgBase,=0D + IN BOOLEAN RemoveBar=0D + )=0D +{=0D + SerialIoDisableMse (PciCfgBase);=0D +=0D + if (RemoveBar =3D=3D TRUE) {=0D + PciSegmentWrite32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_BAR0_LOW, 0x0= );=0D + PciSegmentWrite32 ((UINTN) PciCfgBase + R_SERIAL_IO_CFG_BAR0_HIGH, 0x= 0);=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2c.c b/Silicon/Intel/Tig= erlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLi= b/SerialIoPrivateLibI2c.c new file mode 100644 index 0000000000..7601081cfa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2c.c @@ -0,0 +1,122 @@ +/** @file=0D + Common Serial IO Private Lib implementation - I2C part=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Checks if I2C is Hidden, and it's Pci Config space available=0D +=0D + @param[in] I2cNumber Selects Serial IO I2C device=0D +=0D + @retval TRUE I2C is in hidden mode=0D + @retval FALSE I2C is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoI2cHidden (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + if (MmioRead16 (GetSerialIoI2cFixedPciCfgAddress (I2cNumber) + PCI_DEVIC= E_ID_OFFSET) =3D=3D GetSerialIoI2cDeviceId (I2cNumber)) {=0D + return TRUE;=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] I2cNumber I2C Number=0D + @param[in] I2cDeviceConfig SerialIo I2C Config=0D +=0D +**/=0D +VOID=0D +SerialIoI2cBootHandler (=0D + IN UINT8 I2cNumber,=0D + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig=0D + )=0D +{=0D + UINT64 PciCfgBase;=0D + BOOLEAN TurnOff;=0D +=0D + TurnOff =3D FALSE;=0D +=0D + if (I2cDeviceConfig->Mode =3D=3D SerialIoI2cPci) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + if ((I2cDeviceConfig->Mode =3D=3D SerialIoI2cDisabled) && (SerialIoI2cFu= ncNumber (I2cNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cNumber)))= {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (TurnOff) {=0D + PciCfgBase =3D GetSerialIoI2cPciCfg (I2cNumber);=0D + SerialIoSetD3 (PciCfgBase);=0D + SerialIoMmioDisable (PciCfgBase, TRUE);=0D + }=0D +}=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] I2cNumber I2C Number=0D + @param[in] I2cDeviceConfig SerialIo I2C Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save=0D +=0D +**/=0D +VOID=0D +SerialIoI2cS3Handler (=0D + IN UINT8 I2cNumber,=0D + IN SERIAL_IO_I2C_CONFIG *I2cDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + )=0D +{=0D + BOOLEAN TurnOff;=0D + UINT64 PciCfgBase;=0D +=0D + *S3PciCfgBase =3D 0;=0D + TurnOff =3D FALSE;=0D +=0D + if (I2cDeviceConfig->Mode =3D=3D SerialIoI2cPci) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + if ((I2cDeviceConfig->Mode =3D=3D SerialIoI2cDisabled) && (SerialIoI2cFu= ncNumber (I2cNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoI2cDevNumber (I2cNumber)))= {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (TurnOff) {=0D + *S3PciCfgBase =3D GetSerialIoI2cS3PciBase (I2cNumber);=0D + PciCfgBase =3D GetSerialIoI2cPciCfg (I2cNumber);=0D + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_C= FG_PME_CTRL_STS);=0D + *Pme =3D *Pme | BIT0 | BIT1;=0D + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + PCI_COMMAND_O= FFSET);=0D + *Command =3D *Command & (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | = EFI_PCI_COMMAND_BUS_MASTER);=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c b/Silicon/Intel= /TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPriva= teLib/SerialIoPrivateLibI2cVer2.c new file mode 100644 index 0000000000..fd684ca2a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibI2cVer2.c @@ -0,0 +1,70 @@ +/** @file=0D + Serial IO I2C Private Lib implementation TigerLake specific.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoI2cDevId [] =3D {=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C0_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C1_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C2_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C3_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C4_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_I2C5_DEVICE_ID=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoI2c= FixedAddress [] =3D {=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x0000, PCH_SERIAL_IO_BASE_ADDRESS + 0x10= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x2000, PCH_SERIAL_IO_BASE_ADDRESS + 0x30= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x4000, PCH_SERIAL_IO_BASE_ADDRESS + 0x50= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x6000, PCH_SERIAL_IO_BASE_ADDRESS + 0x70= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x8000, PCH_SERIAL_IO_BASE_ADDRESS + 0x90= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0xA000, PCH_SERIAL_IO_BASE_ADDRESS + 0xB0= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0xC000, PCH_SERIAL_IO_BASE_ADDRESS + 0xD0= 00},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0xE000, PCH_SERIAL_IO_BASE_ADDRESS + 0xF0= 00}=0D +};=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] I2cNumber Serial IO device I2C number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoI2cFixedPciCfgAddress (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + return mSerialIoI2cFixedAddress[I2cNumber].Bar1;=0D +}=0D +=0D +=0D +/**=0D + Gets I2C Device Id=0D +=0D + @param[in] I2cNumber Serial IO device I2C number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoI2cDeviceId (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + return mPchLpSerialIoI2cDevId[I2cNumber];=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibInternal.h b/Silicon/Inte= l/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPriv= ateLib/SerialIoPrivateLibInternal.h new file mode 100644 index 0000000000..b5e8aba9ac --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibInternal.h @@ -0,0 +1,20 @@ +/** @file=0D + Header file for SerialIoPrivateLibInternal.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_PRIVATE_LIB_INTERNAL_H_=0D +#define _SERIAL_IO_PRIVATE_LIB_INTERNAL_H_=0D +=0D +typedef struct {=0D + UINT32 Bar0;=0D + UINT32 Bar1;=0D +} SERIAL_IO_CONTROLLER_DESCRIPTOR;=0D +=0D +typedef struct {=0D + UINT8 DevNum;=0D + UINT8 FuncNum;=0D +} SERIAL_IO_BDF_NUMBERS;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpi.c b/Silicon/Intel/Tig= erlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateLi= b/SerialIoPrivateLibSpi.c new file mode 100644 index 0000000000..a926941baf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpi.c @@ -0,0 +1,122 @@ +/** @file=0D + Common Serial IO Private Lib implementation - SPI part=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Checks if SPI is Hidden, and it's Pci Config space available=0D +=0D + @param[in] SpiNumber Selects Serial IO SPI device=0D +=0D + @retval TRUE SPI is in hidden mode=0D + @retval FALSE SPI is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoSpiHidden (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + if (MmioRead16 (GetSerialIoSpiFixedPciCfgAddress (SpiNumber) + PCI_DEVIC= E_ID_OFFSET) =3D=3D GetSerialIoSpiDeviceId (SpiNumber)) {=0D + return TRUE;=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] SpiNumber SPI Number=0D + @param[in] SpiDeviceConfig SerialIo SPI Config=0D +=0D +**/=0D +VOID=0D +SerialIoSpiBootHandler (=0D + IN UINT8 SpiNumber,=0D + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig=0D + )=0D +{=0D + UINT64 PciCfgBase;=0D + BOOLEAN TurnOff;=0D +=0D + TurnOff =3D FALSE;=0D +=0D + if (SpiDeviceConfig->Mode =3D=3D SerialIoSpiPci) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + if ((SpiDeviceConfig->Mode =3D=3D SerialIoSpiDisabled) && (SerialIoSpiFu= ncNumber (SpiNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiNumber)))= {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (TurnOff) {=0D + PciCfgBase =3D GetSerialIoSpiPciCfg (SpiNumber);=0D + SerialIoSetD3 (PciCfgBase);=0D + SerialIoMmioDisable (PciCfgBase, TRUE);=0D + }=0D +}=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] SpiNumber SPI Number=0D + @param[in] SpiDeviceConfig SerialIo SPI Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save=0D +=0D +**/=0D +VOID=0D +SerialIoSpiS3Handler (=0D + IN UINT8 SpiNumber,=0D + IN SERIAL_IO_SPI_CONFIG *SpiDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + )=0D +{=0D + BOOLEAN TurnOff;=0D + UINT64 PciCfgBase;=0D +=0D + *S3PciCfgBase =3D 0;=0D + TurnOff =3D FALSE;=0D +=0D + if (SpiDeviceConfig->Mode =3D=3D SerialIoSpiPci) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + if ((SpiDeviceConfig->Mode =3D=3D SerialIoSpiDisabled) && (SerialIoSpiFu= ncNumber (SpiNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoSpiDevNumber (SpiNumber)))= {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (TurnOff) {=0D + *S3PciCfgBase =3D GetSerialIoSpiS3PciBase (SpiNumber);=0D + PciCfgBase =3D GetSerialIoSpiPciCfg (SpiNumber);=0D + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_C= FG_PME_CTRL_STS);=0D + *Pme =3D *Pme | BIT0 | BIT1;=0D + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + PCI_COMMAND_O= FFSET);=0D + *Command =3D *Command & (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | = EFI_PCI_COMMAND_BUS_MASTER);=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c b/Silicon/Intel= /TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPriva= teLib/SerialIoPrivateLibSpiVer2.c new file mode 100644 index 0000000000..abda359202 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibSpiVer2.c @@ -0,0 +1,82 @@ +/** @file=0D + Serial IO Spi Private Lib implementation TigerLake specific.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoSpiDevId [] =3D {=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI0_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI1_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI2_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_SPI3_DEVICE_ID=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoSpi= FixedAddress [] =3D {=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x10000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= 1000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x12000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= 3000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x14000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= 5000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x16000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= 7000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x18000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= 9000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1A000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= B000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1C000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= D000}=0D +};=0D +=0D +/**=0D + Gets Fixed Base Address used for BAR0=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Config control offset=0D +**/=0D +UINT32=0D +GetSerialIoSpiFixedMmioAddress (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + return mSerialIoSpiFixedAddress[SpiNumber].Bar0;=0D +}=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoSpiFixedPciCfgAddress (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + return mSerialIoSpiFixedAddress[SpiNumber].Bar1;=0D +}=0D +=0D +/**=0D + Gets Spi Device Id=0D +=0D + @param[in] SpiNumber Serial IO device SPI number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoSpiDeviceId (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + return mPchLpSerialIoSpiDevId[SpiNumber];=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUart.c b/Silicon/Intel/Ti= gerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPrivateL= ib/SerialIoPrivateLibUart.c new file mode 100644 index 0000000000..0f7d6513ce --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibUart.c @@ -0,0 +1,136 @@ +/** @file=0D + Serial IO Private Lib implementation - UART part=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Checks if UART is Hidden, and it's Pci Config space available=0D +=0D + @param[in] UartNumber Selects Serial IO UART device=0D +=0D + @retval TRUE UART is in hidden mode=0D + @retval FALSE UART is not in hidden mode=0D +**/=0D +BOOLEAN=0D +IsSerialIoUartHidden (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + if (MmioRead16 (GetSerialIoUartFixedPciCfgAddress (UartNumber) + PCI_DEV= ICE_ID_OFFSET) =3D=3D GetSerialIoUartDeviceId (UartNumber)) {=0D + return TRUE;=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Configures Serial IO Controller before control is passd to the OS=0D +=0D + @param[in] UartNumber UART Number=0D + @param[in] UartDeviceConfig SerialIo UART Config=0D +=0D +**/=0D +VOID=0D +SerialIoUartBootHandler (=0D + IN UINT8 UartNumber,=0D + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig=0D + )=0D +{=0D + UINT64 PciCfgBase;=0D + BOOLEAN TurnOff;=0D +=0D + TurnOff =3D FALSE;=0D +=0D + //=0D + // Even if Uart is Hidden and in D3 SerialIoUartLib is capable of settin= g D0 during each write/read.=0D + // In case it is required for Os Debug DBG2 must be set to TRUE.=0D + //=0D + if (UartDeviceConfig->Mode =3D=3D SerialIoUartPci || UartDeviceConfig->M= ode =3D=3D SerialIoUartHidden) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + //=0D + // Uart in Com mode will be placed in D3 depending on PG configuration t= hrough ACPI _PS3=0D + //=0D +=0D + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartDisabled) && (SerialIoUar= tFuncNumber (UartNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartNumber)= )) {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (UartDeviceConfig->DBG2 =3D=3D TRUE) {=0D + TurnOff =3D FALSE;=0D + }=0D +=0D + if (TurnOff) {=0D + PciCfgBase =3D GetSerialIoUartPciCfg (UartNumber);=0D + SerialIoSetD3 (PciCfgBase);=0D + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartPci) || (UartDeviceConf= ig->Mode =3D=3D SerialIoUartDisabled)) {=0D + SerialIoMmioDisable (PciCfgBase, TRUE);=0D + }=0D + }=0D +}=0D +=0D +/**=0D + Sets Pme Control Status and Command register values required for S3 Boot= Script=0D +=0D + @param[in] UartNumber UART Number=0D + @param[in] UartDeviceConfig SerialIo UART Config=0D + @param[in/out] S3PciCfgBase S3 Boot Script Pci Config Base=0D + @param[in/out] Command Pci Command register data to save=0D + @param[in/out] Pme Pci Pme Control register data to save= =0D +=0D +**/=0D +VOID=0D +SerialIoUartS3Handler (=0D + IN UINT8 UartNumber,=0D + IN SERIAL_IO_UART_CONFIG *UartDeviceConfig,=0D + IN OUT UINT64 *S3PciCfgBase,=0D + IN OUT UINT32 *Command,=0D + IN OUT UINT32 *Pme=0D + )=0D +{=0D + BOOLEAN TurnOff;=0D + UINT64 PciCfgBase;=0D +=0D + *S3PciCfgBase =3D 0;=0D + TurnOff =3D FALSE;=0D +=0D + if (UartDeviceConfig->Mode =3D=3D SerialIoUartPci) {=0D + TurnOff =3D TRUE;=0D + }=0D +=0D + if ((UartDeviceConfig->Mode =3D=3D SerialIoUartDisabled) && (SerialIoUar= tFuncNumber (UartNumber) =3D=3D 0x0)) {=0D + if (SerialIoHigherFunctionsEnabled (SerialIoUartDevNumber (UartNumber)= )) {=0D + TurnOff =3D TRUE;=0D + }=0D + }=0D +=0D + if (TurnOff) {=0D + *S3PciCfgBase =3D GetSerialIoUartS3PciBase (UartNumber);=0D + PciCfgBase =3D GetSerialIoUartPciCfg (UartNumber);=0D + *Pme =3D PciSegmentRead32 ((UINTN) PciCfgBase + R_SERIAL_IO_C= FG_PME_CTRL_STS);=0D + *Pme =3D *Pme | BIT0 | BIT1;=0D + *Command =3D PciSegmentRead32 ((UINTN) PciCfgBase + PCI_COMMAND_O= FFSET);=0D + *Command =3D *Command & (UINT32)~(EFI_PCI_COMMAND_MEMORY_SPACE | = EFI_PCI_COMMAND_BUS_MASTER);=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPriv= ate/PeiDxeSmmSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c b/Silicon/Inte= l/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/PeiDxeSmmSerialIoPriv= ateLib/SerialIoPrivateLibUartVer2.c new file mode 100644 index 0000000000..91280f8e90 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/SerialIo/LibraryPrivate/Pei= DxeSmmSerialIoPrivateLib/SerialIoPrivateLibUartVer2.c @@ -0,0 +1,82 @@ +/** @file=0D + Serial IO Private Uart Lib implementation TigerLake specific.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mPchLpSerialIoUartDevId [] =3D {=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_UART0_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_UART1_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_UART2_DEVICE_ID,=0D + V_VER2_PCH_LP_SERIAL_IO_CFG_UART3_DEVICE_ID=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED SERIAL_IO_CONTROLLER_DESCRIPTOR mSerialIoUar= tFixedAddress [] =3D {=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x1E000, PCH_SERIAL_IO_BASE_ADDRESS + 0x1= F000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x20000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= 1000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x22000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= 3000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x24000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= 5000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x26000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= 7000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x28000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= 9000},=0D + {PCH_SERIAL_IO_BASE_ADDRESS + 0x2A000, PCH_SERIAL_IO_BASE_ADDRESS + 0x2= B000}=0D +};=0D +=0D +/**=0D + Gets Fixed Base Address used for BAR0=0D +=0D + @param[in] UartNumber Serial IO device UART number=0D +=0D + @retval Config control offset=0D +**/=0D +UINT32=0D +GetSerialIoUartFixedMmioAddress (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + return mSerialIoUartFixedAddress[UartNumber].Bar0;=0D +}=0D +=0D +/**=0D + Gets Fixed Address used for Pci Config Space manipulation=0D +=0D + @param[in] UartNumber Serial IO device UART number=0D +=0D + @retval Pci Config Address=0D +**/=0D +UINT32=0D +GetSerialIoUartFixedPciCfgAddress (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + return mSerialIoUartFixedAddress[UartNumber].Bar1;=0D +}=0D +=0D +/**=0D + Gets Uarts Device Id=0D +=0D + @param[in] UartNumbe Serial IO device UART number=0D +=0D + @retval Device Id=0D +**/=0D +UINT16=0D +GetSerialIoUartDeviceId (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + return mPchLpSerialIoUartDevId[UartNumber];=0D +}=0D --=20 2.24.0.windows.2