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04 Feb 2021 00:50:50 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other include headers Date: Thu, 4 Feb 2021 16:48:42 +0800 Message-Id: <20210204084919.3603-3-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Include/Pins * Include/Register * Include/*.h Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h | 53 += ++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h | 38 += +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h | 75 += ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h | 138 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h | 57 += ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h | 24 += +++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h | 155 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h | 110 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h | 72 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h | 121 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h | 226 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h | 16 += +++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h | 36 += +++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h | 93 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h | 258 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h | 45 += ++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h | 56 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h | 47 += ++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h | 51 += ++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h | 213 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h | 17 += ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h | 64 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 22 files changed, 1965 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h b/Sili= con/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h new file mode 100644 index 0000000000..ad34e4ea42 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock.h @@ -0,0 +1,53 @@ +/** @file=0D + Header file for Config Block Lib implementation=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _CONFIG_BLOCK_H_=0D +#define _CONFIG_BLOCK_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#pragma pack (push,1)=0D +=0D +///=0D +/// Config Block Header=0D +///=0D +typedef struct _CONFIG_BLOCK_HEADER {=0D + EFI_HOB_GUID_TYPE GuidHob; ///< Offset 0-23 GUID e= xtension HOB header=0D + UINT8 Revision; ///< Offset 24 Revisi= on of this config block=0D + UINT8 Attributes; ///< Offset 25 The ma= in revision for config block=0D + UINT8 Reserved[2]; ///< Offset 26-27 Reserv= ed for future use=0D +} CONFIG_BLOCK_HEADER;=0D +=0D +///=0D +/// Config Block=0D +///=0D +typedef struct _CONFIG_BLOCK {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Header= of config block=0D + //=0D + // Config Block Data=0D + //=0D +} CONFIG_BLOCK;=0D +=0D +///=0D +/// Config Block Table Header=0D +///=0D +typedef struct _CONFIG_BLOCK_TABLE_STRUCT {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 GUID n= umber for main entry of config block=0D + UINT8 Rsvd0[2]; ///< Offset 28-29 Reserv= ed for future use=0D + UINT16 NumberOfBlocks; ///< Offset 30-31 Number= of config blocks (N)=0D + UINT32 AvailableSize; ///< Offset 32-35 Curren= t config block table size=0D +///=0D +/// Individual Config Block Structures are added here in memory as part of= AddConfigBlock()=0D +///=0D +} CONFIG_BLOCK_TABLE_HEADER;=0D +#pragma pack (pop)=0D +=0D +#endif // _CONFIG_BLOCK_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h b/Silic= on/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h new file mode 100644 index 0000000000..23a408e8dc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/CpuPcieHob.h @@ -0,0 +1,38 @@ +/** @file=0D + The GUID definition for CpuPcieHob=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PCIE_HOB_H_=0D +#define _CPU_PCIE_HOB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +extern EFI_GUID gCpuPcieHobGuid;=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The CPU_PCIE_HOB block describes the expected configuration of the CpuPc= ie controllers=0D +**/=0D +typedef struct {=0D + ///=0D + /// These members describe the configuration of each CPU PCIe root port.= =0D + ///=0D + EFI_HOB_GUID_TYPE EfiHobGuidType; //= /< Offset 0 - 23: GUID Hob type structure for gCpuPcieHobGuid=0D + CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];=0D + UINT8 L1SubStates[CPU_PCIE_MAX_ROOT_PORTS]; ///< = The L1 Substates configuration of the root port=0D +=0D + UINT32 DekelFwVersionMinor; //= /< Dekel Firmware Minor Version=0D + UINT32 DekelFwVersionMajor; //= /< Dekel Firmware Major Version=0D + BOOLEAN InitPcieAspmAfterOprom; //= /< 1=3Dinitialize PCIe ASPM after Oprom; 0=3Dbefore (This will be set basin= g on policy)=0D + UINT32 RpEnabledMask; //= /< Rootport enabled mask based on DEVEN register=0D + UINT32 RpEnMaskFromDevEn; //= /< Rootport enabled mask based on Device Id=0D + UINT8 DisableClkReqMsg[CPU_PCIE_MAX_ROOT_PORTS]; = ///< 1=3DClkReqMsg disabled, 0=3DClkReqMsg enabled=0D + UINT8 SlotSelection; //= /< 1=3DM2 slot, 0=3DCEMx4 slot=0D + BOOLEAN ComplianceTest; //= /< Compliance Test based on policy=0D +} CPU_PCIE_HOB;=0D +#pragma pack (pop)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h = b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h new file mode 100644 index 0000000000..5b058c7a45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DmaRemappingTable.h @@ -0,0 +1,75 @@ +/** @file=0D + This code defines ACPI DMA Remapping table related definitions.=0D + See the System Agent BIOS specification for definition of the table.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DMA_REMAPPING_TABLE_H_=0D +#define _DMA_REMAPPING_TABLE_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#pragma pack(1)=0D +///=0D +/// DMAR table signature=0D +///=0D +#define EFI_ACPI_VTD_DMAR_TABLE_SIGNATURE 0x52414D44 ///< "DMAR"=0D +#define EFI_ACPI_DMAR_TABLE_REVISION 2=0D +#define EFI_ACPI_DRHD_ENGINE_HEADER_LENGTH 0x10=0D +#define EFI_ACPI_RMRR_HEADER_LENGTH 0x18=0D +#define MAX_PCI_DEPTH 5=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_DEVICE_SCOPE_STRUCTURE_HEADER DeviceScopeStructureHeader;= =0D + EFI_ACPI_DMAR_PCI_PATH PciPath; // device, func= tion=0D +} EFI_ACPI_DEV_SCOPE_STRUCTURE;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;=0D + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1];=0D +} EFI_ACPI_DRHD_ENGINE1_STRUCT;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_DRHD_HEADER DrhdHeader;=0D + //=0D + // @todo use PCD=0D + //=0D + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];=0D +} EFI_ACPI_DRHD_ENGINE3_STRUCT;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;=0D + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[2];=0D +} EFI_ACPI_RMRR_USB_STRUC;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;=0D + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD=0D +} EFI_ACPI_RMRR_IGD_STRUC;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_RMRR_HEADER RmrrHeader;=0D + EFI_ACPI_DEV_SCOPE_STRUCTURE DeviceScope[1]; // IGD - DiSM=0D +} EFI_ACPI_RMRR_IGD_DISM_STRUC;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_ANDD_HEADER AnddHeader;=0D + UINT8 AcpiObjectName[20];=0D +} EFI_ACPI_ANDD_STRUC;=0D +=0D +typedef struct {=0D + EFI_ACPI_DMAR_HEADER DmarHeader;=0D + EFI_ACPI_DRHD_ENGINE1_STRUCT DrhdEngine1;=0D + EFI_ACPI_DRHD_ENGINE3_STRUCT DrhdEngine3;=0D + EFI_ACPI_RMRR_IGD_STRUC RmrrIgd;=0D + EFI_ACPI_RMRR_IGD_DISM_STRUC RmrrIgdDism;=0D +} EFI_ACPI_DMAR_TABLE;=0D +=0D +#pragma pack()=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h b/Silic= on/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h new file mode 100644 index 0000000000..edb3855b68 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/DxeHdaNhlt.h @@ -0,0 +1,138 @@ +/** @file=0D + Header file for DxePchHdaNhltLib - NHLT structure definitions.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _DXE_HDA_NHLT_H_=0D +#define _DXE_HDA_NHLT_H_=0D +=0D +#include =0D +=0D +//=0D +// ACPI support protocol instance signature definition.=0D +//=0D +#define NHLT_ACPI_TABLE_SIGNATURE SIGNATURE_32 ('N', 'H', 'L', 'T')=0D +=0D +// MSFT defined structures=0D +#define SPEAKER_FRONT_LEFT 0x1=0D +#define SPEAKER_FRONT_RIGHT 0x2=0D +#define SPEAKER_FRONT_CENTER 0x4=0D +#define SPEAKER_BACK_LEFT 0x10=0D +#define SPEAKER_BACK_RIGHT 0x20=0D +=0D +#define KSAUDIO_SPEAKER_MONO (SPEAKER_FRONT_CENTER)=0D +#define KSAUDIO_SPEAKER_STEREO (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT)= =0D +#define KSAUDIO_SPEAKER_QUAD (SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT |= SPEAKER_BACK_LEFT | SPEAKER_BACK_RIGHT)=0D +=0D +#define WAVE_FORMAT_EXTENSIBLE 0xFFFE /* Microsoft */=0D +#define KSDATAFORMAT_SUBTYPE_PCM \=0D + {0x00000001, 0x0000, 0x0010, {0x80, 0x00, 0x00, 0xaa, 0x00, 0x38, = 0x9b, 0x71}}=0D +=0D +#pragma pack (push, 1)=0D +=0D +typedef struct {=0D + UINT16 wFormatTag;=0D + UINT16 nChannels;=0D + UINT32 nSamplesPerSec;=0D + UINT32 nAvgBytesPerSec;=0D + UINT16 nBlockAlign;=0D + UINT16 wBitsPerSample;=0D + UINT16 cbSize;=0D +} WAVEFORMATEX;=0D +=0D +typedef struct {=0D + WAVEFORMATEX Format;=0D + union {=0D + UINT16 wValidBitsPerSample;=0D + UINT16 wSamplesPerBlock;=0D + UINT16 wReserved;=0D + } Samples;=0D + UINT32 dwChannelMask;=0D + GUID SubFormat;=0D +} WAVEFORMATEXTENSIBLE;=0D +=0D +//=0D +// List of supported link type.=0D +//=0D +enum NHLT_LINK_TYPE=0D +{=0D + HdaNhltLinkHd =3D 0,=0D + HdaNhltLinkDsp =3D 1,=0D + HdaNhltLinkDmic =3D 2,=0D + HdaNhltLinkSsp =3D 3,=0D + HdaNhltLinkInvalid=0D +};=0D +=0D +//=0D +// List of supported device type.=0D +//=0D +enum NHLT_SSP_DEVICE_TYPE=0D +{=0D + HdaNhltSspDeviceBt =3D 0,=0D + HdaNhltSspDeviceI2s =3D 4,=0D + HdaNhltSspDeviceInvalid=0D +};=0D +=0D +enum NHLT_PDM_DEVICE_TYPE=0D +{=0D + HdaNhltPdmDeviceDmic =3D 0,=0D + HdaNhltPdmDeviceInvalid=0D +};=0D +=0D +typedef struct {=0D + UINT32 CapabilitiesSize;=0D + UINT8 Capabilities[1];=0D +} SPECIFIC_CONFIG;=0D +=0D +typedef struct {=0D + WAVEFORMATEXTENSIBLE Format;=0D + SPECIFIC_CONFIG FormatConfiguration;=0D +} FORMAT_CONFIG;=0D +=0D +typedef struct {=0D + UINT8 FormatsCount;=0D + FORMAT_CONFIG FormatsConfiguration[1];=0D +} FORMATS_CONFIG;=0D +=0D +typedef struct {=0D + UINT8 DeviceId[16];=0D + UINT8 DeviceInstanceId;=0D + UINT8 DevicePortId;=0D +} DEVICE_INFO;=0D +=0D +typedef struct {=0D + UINT8 DeviceInfoCount;=0D + DEVICE_INFO DeviceInformation[1];=0D +} DEVICES_INFO;=0D +=0D +typedef struct {=0D + UINT32 EndpointDescriptorLength;=0D + UINT8 LinkType;=0D + UINT8 InstanceId;=0D + UINT16 HwVendorId;=0D + UINT16 HwDeviceId;=0D + UINT16 HwRevisionId;=0D + UINT32 HwSubsystemId;=0D + UINT8 DeviceType;=0D + UINT8 Direction;=0D + UINT8 VirtualBusId;=0D + SPECIFIC_CONFIG EndpointConfig;=0D + FORMATS_CONFIG FormatsConfig;=0D + DEVICES_INFO DevicesInformation;=0D +} ENDPOINT_DESCRIPTOR;=0D +=0D +//=0D +// High Level Table structure=0D +//=0D +typedef struct {=0D + EFI_ACPI_DESCRIPTION_HEADER Header; //{'N', 'H', 'L', 'T'}=0D + UINT8 EndpointCount; // Actual number of endpoin= ts=0D + ENDPOINT_DESCRIPTOR EndpointDescriptors[1];=0D + SPECIFIC_CONFIG OedConfiguration;=0D +} NHLT_ACPI_TABLE;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _DXE_PCH_HDA_NHLT_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h b/Silicon/Inte= l/TigerlakeSiliconPkg/Include/Hda.h new file mode 100644 index 0000000000..ab3f2c9cd0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Hda.h @@ -0,0 +1,57 @@ +/** @file=0D + Header file for HD Audio configuration.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _HDA_H_=0D +#define _HDA_H_=0D +=0D +typedef enum {=0D + HdaVc0 =3D 0,=0D + HdaVc1 =3D 1=0D +} HDAUDIO_VC_TYPE;=0D +=0D +typedef enum {=0D + HdaDmicDisabled =3D 0,=0D + HdaDmic2chArray =3D 1,=0D + HdaDmic4chArray =3D 2,=0D + HdaDmic1chArray =3D 3=0D +} HDAUDIO_DMIC_TYPE;=0D +=0D +typedef enum {=0D + HdaLinkFreq6MHz =3D 0,=0D + HdaLinkFreq12MHz =3D 1,=0D + HdaLinkFreq24MHz =3D 2,=0D + HdaLinkFreq48MHz =3D 3,=0D + HdaLinkFreq96MHz =3D 4,=0D + HdaLinkFreqInvalid=0D +} HDAUDIO_LINK_FREQUENCY;=0D +=0D +typedef enum {=0D + HdaIDispMode2T =3D 0,=0D + HdaIDispMode1T =3D 1,=0D + HdaIDispMode4T =3D 2,=0D + HdaIDispMode8T =3D 3,=0D + HdaIDispMode16T =3D 4,=0D + HdaIDispTModeInvalid=0D +} HDAUDIO_IDISP_TMODE;=0D +=0D +typedef enum {=0D + HdaLink =3D 0,=0D + HdaIDispLink =3D 1,=0D + HdaDmic =3D 2,=0D + HdaSsp =3D 3,=0D + HdaSndw =3D 4,=0D + HdaLinkUnsupported=0D +} HDAUDIO_LINK_TYPE;=0D +=0D +typedef enum {=0D + HdaDmicClockSelectBoth =3D 0,=0D + HdaDmicClockSelectClkA =3D 1,=0D + HdaDmicClockSelectClkB =3D 2,=0D + HdaDmicClockSelectInvalid=0D +} HDAUDIO_DMIC_CLOCK_SELECT;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h b/S= ilicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h new file mode 100644 index 0000000000..023ba12daa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/MePolicyCommon.h @@ -0,0 +1,24 @@ +/** @file=0D + Definition for ME common policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _ME_POLICY_COMMON_H_=0D +#define _ME_POLICY_COMMON_H_=0D +=0D +#include =0D +=0D +#include =0D +=0D +#ifndef PLATFORM_POR=0D +#define PLATFORM_POR 0=0D +#endif=0D +#ifndef FORCE_ENABLE=0D +#define FORCE_ENABLE 1=0D +#endif=0D +#ifndef FORCE_DISABLE=0D +#define FORCE_DISABLE 2=0D +#endif=0D +=0D +#endif // _ME_POLICY_COMMON_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h b/Silicon= /Intel/TigerlakeSiliconPkg/Include/PcieRegs.h new file mode 100644 index 0000000000..d98019d1b4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/PcieRegs.h @@ -0,0 +1,155 @@ +/** @file=0D + Register names for PCIE standard register=0D +=0D + Conventions:=0D +=0D + - Prefixes:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register sizes=0D + Definitions beginning with "N_" are the bit position=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCIE_REGS_H_=0D +#define _PCIE_REGS_H_=0D +=0D +#include =0D +=0D +//=0D +// PCI type 0 Header=0D +//=0D +#define R_PCI_BCC_OFFSET 0x0B=0D +=0D +//=0D +// PCI type 1 Header=0D +//=0D +#define R_PCI_BRIDGE_BNUM 0x18 ///< Bus Number Reg= ister=0D +#define B_PCI_BRIDGE_BNUM_SBBN 0x00FF0000 ///< Subordin= ate Bus Number=0D +#define B_PCI_BRIDGE_BNUM_SCBN 0x0000FF00 ///< Secondar= y Bus Number=0D +=0D +//=0D +// PCI Express Capability List Register (CAPID:10h)=0D +//=0D +#define R_PCIE_XCAP_OFFSET 0x02 ///< PCI Express Ca= pabilities Register (Offset 02h)=0D +#define B_PCIE_XCAP_DT (BIT7 | BIT6 | BIT5 | BI= T4) ///< Device/Port Type=0D +#define N_PCIE_XCAP_DT 4=0D +=0D +#define R_PCIE_DCAP_OFFSET 0x04 ///< Device Capabil= ities Register (Offset 04h)=0D +#define B_PCIE_DCAP_RBER BIT15 ///< Role-Based Er= ror Reporting=0D +#define B_PCIE_DCAP_E1AL (BIT11 | BIT10 | BIT9) /= //< Endpoint L1 Acceptable Latency=0D +#define N_PCIE_DCAP_E1AL 9=0D +#define B_PCIE_DCAP_E0AL (BIT8 | BIT7 | BIT6) ///= < Endpoint L0s Acceptable Latency=0D +#define N_PCIE_DCAP_E0AL 6=0D +#define B_PCIE_DCAP_MPS (BIT2 | BIT1 | BIT0) ///= < Max_Payload_Size Supported=0D +=0D +#define R_PCIE_DCTL_OFFSET 0x08 ///< Device Control= Register (Offset 08h)=0D +#define B_PCIE_DCTL_MPS (BIT7 | BIT6 | BIT5) ///= < Max_Payload_Size=0D +#define N_PCIE_DCTL_MPS 5=0D +=0D +#define R_PCIE_LCAP_OFFSET 0x0C ///< Link Capabilit= ies Register (Offset 0Ch)=0D +#define B_PCIE_LCAP_CPM BIT18 ///< Clock Power M= anagement=0D +#define B_PCIE_LCAP_EL1 (BIT17 | BIT16 | BIT15) = ///< L1 Exit Latency=0D +#define N_PCIE_LCAP_EL1 15=0D +#define B_PCIE_LCAP_EL0 (BIT14 | BIT13 | BIT12) = ///< L0s Exit Latency=0D +#define N_PCIE_LCAP_EL0 12=0D +#define B_PCIE_LCAP_APMS_L0S BIT10=0D +#define B_PCIE_LCAP_APMS_L1 BIT11=0D +#define B_PCIE_LCAP_MLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Max Link Speed=0D +#define V_PCIE_LCAP_MLS_GEN3 3=0D +#define V_PCIE_LCAP_MLS_GEN4 4=0D +=0D +#define R_PCIE_LCTL_OFFSET 0x10 ///< Link Control R= egister (Offset 10h)=0D +#define B_PCIE_LCTL_ECPM BIT8 ///< Enable Clock P= ower Management=0D +#define B_PCIE_LCTL_CCC BIT6 ///< Common Clock C= onfiguration=0D +#define B_PCIE_LCTL_RL BIT5 ///< Retrain Link=0D +#define B_PCIE_LCTL_ASPM (BIT1 | BIT0) ///< Activ= e State Power Management (ASPM) Control=0D +#define V_PCIE_LCTL_ASPM_L0S 1=0D +#define V_PCIE_LCTL_ASPM_L1 2=0D +#define V_PCIE_LCTL_ASPM_L0S_L1 3=0D +=0D +#define R_PCIE_LSTS_OFFSET 0x12 ///< Link Status Re= gister (Offset 12h)=0D +#define B_PCIE_LSTS_LA BIT13 ///< Data Link Lay= er Link Active=0D +#define B_PCIE_LSTS_SCC BIT12 ///< Slot Clock Co= nfiguration=0D +#define B_PCIE_LSTS_LT BIT11 ///< Link Training= =0D +#define B_PCIE_LSTS_NLW 0x03F0 ///< Negotiated L= ink Width=0D +#define N_PCIE_LSTS_NLW 4=0D +#define B_PCIE_LSTS_CLS 0x000F ///< Current Link= Speed=0D +=0D +#define R_PCIE_SLCAP_OFFSET 0x14 ///< Slot Capabilit= ies Register (Offset 14h)=0D +#define B_PCIE_SLCAP_HPC BIT6 ///< Hot-Plug= Capable=0D +=0D +#define R_PCIE_SLSTS_OFFSET 0x1A ///< Slot Status Re= gister (Offset 1Ah)=0D +#define B_PCIE_SLSTS_PDS BIT6 ///< Presence Detec= t State=0D +=0D +#define R_PCIE_DCAP2_OFFSET 0x24 ///< Device Capabil= ities 2 Register (Offset 24h)=0D +#define B_PCIE_DCAP2_LTRMS BIT11 ///< LTR Mechanism= Supported=0D +=0D +#define R_PCIE_DCTL2_OFFSET 0x28 ///< Device Control= 2 Register (Offset 28h)=0D +#define B_PCIE_DCTL2_LTREN BIT10 ///< LTR Mechanism= Enable=0D +=0D +#define B_PCIE_LCTL2_TLS (BIT3 | BIT2 | BIT1 | BI= T0) ///< Target Link Speed=0D +=0D +//=0D +// Latency Tolerance Reporting Extended Capability Registers (CAPID:0018h)= =0D +//=0D +#define R_PCIE_LTRECH_CID 0x0018=0D +=0D +#define R_PCIE_LTRECH_MSLR_OFFSET 0x04=0D +#define N_PCIE_LTRECH_MSLR_VALUE 0=0D +#define N_PCIE_LTRECH_MSLR_SCALE 10=0D +=0D +#define R_PCIE_LTRECH_MNSLR_OFFSET 0x06=0D +#define N_PCIE_LTRECH_MNSLR_VALUE 0=0D +#define N_PCIE_LTRECH_MNSLR_SCALE 10=0D +=0D +//=0D +// Secondary PCI Express Extended Capability Header (CAPID:0019h)=0D +//=0D +#define R_PCIE_EX_LCTL3_OFFSET 0x04 ///< Link Control 3= Register=0D +#define B_PCIE_EX_LCTL3_PE BIT0 ///< Perform Equali= zation=0D +=0D +//=0D +// L1 Sub-States Extended Capability Register (CAPID:001Eh)=0D +//=0D +#define V_PCIE_EX_L1S_CID 0x001E ///< Capability ID= =0D +#define R_PCIE_EX_L1SCAP_OFFSET 0x04 ///< L1 Sub-States C= apabilities=0D +#define B_PCIE_EX_L1SCAP_PTV 0x00F80000 //< Port Tpowe= r_on value=0D +#define N_PCIE_EX_L1SCAP_PTV 19=0D +#define B_PCIE_EX_L1SCAP_PTPOS 0x00030000 //< Port Tpowe= r_on scale=0D +#define N_PCIE_EX_L1SCAP_PTPOS 16=0D +#define B_PCIE_EX_L1SCAP_CMRT 0x0000FF00 //< Common Mod= e Restore time=0D +#define N_PCIE_EX_L1SCAP_CMRT 8=0D +#define B_PCIE_EX_L1SCAP_L1PSS BIT4 ///< L1 PM substates= supported=0D +#define B_PCIE_EX_L1SCAP_AL1SS BIT3 ///< ASPM L1.1 suppo= rted=0D +#define B_PCIE_EX_L1SCAP_AL12S BIT2 ///< ASPM L1.2 suppo= rted=0D +#define B_PCIE_EX_L1SCAP_PPL11S BIT1 ///< PCI-PM L1.1 sup= ported=0D +#define B_PCIE_EX_L1SCAP_PPL12S BIT0 ///< PCI-PM L1.2 sup= ported=0D +#define R_PCIE_EX_L1SCTL1_OFFSET 0x08 ///< L1 Sub-States C= ontrol 1=0D +#define B_PCIE_EX_L1SCTL1_L1SSEIE BIT4=0D +#define N_PCIE_EX_L1SCTL1_L12LTRTLSV 29=0D +#define N_PCIE_EX_L1SCTL1_L12LTRTLV 16=0D +#define R_PCIE_EX_L1SCTL2_OFFSET 0x0C ///< L1 Sub-States C= ontrol 2=0D +#define N_PCIE_EX_L1SCTL2_POWT 3=0D +=0D +//=0D +// PTM Extended Capability Register (CAPID:001Fh)=0D +//=0D +#define V_PCIE_EX_PTM_CID 0x001F ///< Capability I= D=0D +#define R_PCIE_EX_PTMCAP_OFFSET 0x04 ///< PTM Capabiliti= es=0D +#define R_PCIE_EX_PTMCTL_OFFSET 0x08 ///< PTM Control Re= gister=0D +=0D +//=0D +// Base Address Offset=0D +//=0D +#define B_PCI_BAR_MEMORY_TYPE_MASK (BIT1 | BIT2)=0D +#define B_PCI_BAR_MEMORY_TYPE_64 BIT2=0D +=0D +//=0D +// PCI Express Extended Capability Header=0D +//=0D +#define R_PCIE_CFG_EXCAP_OFFSET 0x100=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.= h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h new file mode 100644 index 0000000000..ef94790985 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Pins/GpioPinsVer2Lp.h @@ -0,0 +1,110 @@ +/** @file=0D + GPIO pins for TGL-PCH-LP,=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_PINS_VER2_LP_H_=0D +#define _GPIO_PINS_VER2_LP_H_=0D +///=0D +/// This header file should be used together with=0D +/// PCH GPIO lib in C and ASL. All defines used=0D +/// must match both ASL/C syntax=0D +///=0D +=0D +///=0D +/// Unique ID used in GpioPad defines=0D +///=0D +#define GPIO_VER2_LP_CHIPSET_ID 0x9=0D +=0D +///=0D +/// TGL LP GPIO Groups=0D +/// Use below for functions from PCH GPIO Lib which=0D +/// require GpioGroup as argument=0D +///=0D +#define GPIO_VER2_LP_GROUP_GPP_B 0x0900=0D +#define GPIO_VER2_LP_GROUP_GPP_A 0x0902=0D +#define GPIO_VER2_LP_GROUP_GPP_R 0x0903=0D +#define GPIO_VER2_LP_GROUP_GPD 0x0905=0D +#define GPIO_VER2_LP_GROUP_GPP_S 0x0906=0D +#define GPIO_VER2_LP_GROUP_GPP_H 0x0907=0D +#define GPIO_VER2_LP_GROUP_GPP_D 0x0908=0D +#define GPIO_VER2_LP_GROUP_GPP_C 0x090B=0D +#define GPIO_VER2_LP_GROUP_GPP_F 0x090C=0D +#define GPIO_VER2_LP_GROUP_GPP_E 0x090E=0D +=0D +=0D +///=0D +/// TGL LP GPIO pins=0D +/// Use below for functions from PCH GPIO Lib which=0D +/// require GpioPad as argument. Encoding used here=0D +/// has all information required by library functions=0D +///=0D +#define GPIO_VER2_LP_GPP_B2 0x09000002=0D +#define GPIO_VER2_LP_GPP_B4 0x09000004=0D +#define GPIO_VER2_LP_GPP_B14 0x0900000E=0D +#define GPIO_VER2_LP_GPP_B15 0x0900000F=0D +#define GPIO_VER2_LP_GPP_B16 0x09000010=0D +#define GPIO_VER2_LP_GPP_B18 0x09000012=0D +#define GPIO_VER2_LP_GPP_B23 0x09000017=0D +#define GPIO_VER2_LP_GSPI0_CLK_LOOPBK 0x09000018=0D +=0D +#define GPIO_VER2_LP_GPP_A10 0x0902000A=0D +#define GPIO_VER2_LP_GPP_A11 0x0902000B=0D +#define GPIO_VER2_LP_GPP_A13 0x0902000D=0D +#define GPIO_VER2_LP_GPP_A14 0x0902000E=0D +#define GPIO_VER2_LP_GPP_A23 0x09020017=0D +#define GPIO_VER2_LP_ESPI_CLK_LOOPBK 0x09020018=0D +=0D +#define GPIO_VER2_LP_GPP_R5 0x09030005=0D +#define GPIO_VER2_LP_GPP_R6 0x09030006=0D +=0D +#define GPIO_VER2_LP_GPD7 0x09050007=0D +=0D +#define GPIO_VER2_LP_INPUT3VSEL 0x0905000C=0D +=0D +#define GPIO_VER2_LP_GPP_H0 0x09070000=0D +#define GPIO_VER2_LP_GPP_H1 0x09070001=0D +#define GPIO_VER2_LP_GPP_H12 0x0907000C=0D +#define GPIO_VER2_LP_GPP_H13 0x0907000D=0D +#define GPIO_VER2_LP_GPP_H15 0x0907000F=0D +#define GPIO_VER2_LP_GPP_H19 0x09070013=0D +=0D +#define GPIO_VER2_LP_GPP_D16 0x09080010=0D +#define GPIO_VER2_LP_GSPI2_CLK_LOOPBK 0x09080014=0D +=0D +#define GPIO_VER2_LP_GPP_C2 0x090B0002=0D +#define GPIO_VER2_LP_GPP_C5 0x090B0005=0D +#define GPIO_VER2_LP_GPP_C8 0x090B0008=0D +#define GPIO_VER2_LP_GPP_C12 0x090B000C=0D +#define GPIO_VER2_LP_GPP_C13 0x090B000D=0D +#define GPIO_VER2_LP_GPP_C14 0x090B000E=0D +#define GPIO_VER2_LP_GPP_C15 0x090B000F=0D +#define GPIO_VER2_LP_GPP_C22 0x090B0016=0D +#define GPIO_VER2_LP_GPP_C23 0x090B0017=0D +=0D +#define GPIO_VER2_LP_GPP_F4 0x090C0004=0D +#define GPIO_VER2_LP_GPP_F5 0x090C0005=0D +#define GPIO_VER2_LP_GPP_F9 0x090C0009=0D +#define GPIO_VER2_LP_GPP_F10 0x090C000A=0D +#define GPIO_VER2_LP_GPP_F20 0x090C0014=0D +#define GPIO_VER2_LP_GPP_F21 0x090C0015=0D +#define GPIO_VER2_LP_GPPF_CLK_LOOPBK 0x090C0018=0D +=0D +#define GPIO_VER2_LP_GPP_E3 0x090E0003=0D +#define GPIO_VER2_LP_GPP_E7 0x090E0007=0D +#define GPIO_VER2_LP_GPP_E8 0x090E0008=0D +#define GPIO_VER2_LP_GPP_E22 0x090E0016=0D +#define GPIO_VER2_LP_GPP_E23 0x090E0017=0D +#define GPIO_VER2_LP_GPPE_CLK_LOOPBK 0x090E0018=0D +=0D +//=0D +// GPIO Pin Muxing=0D +// Determines a selection of physical pad for a given signal.=0D +// Please refer to GPIO_NATIVE_PAD type.=0D +// If certain signal is not listed below it means that it can be enabled=0D +// only on a single pad and muxing setting is not needed.=0D +//=0D +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SDA_GPP_H8 0x1947CC08=0D +#define GPIO_VER2_LP_MUXING_SERIALIO_I2C4_SCL_GPP_H9 0x1947AC09=0D +#endif // _GPIO_PINS_VER2_LP_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h= b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h new file mode 100644 index 0000000000..215fd0407e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/FlashRegs.h @@ -0,0 +1,72 @@ +/** @file=0D + Register names for Flash registers=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _FLASH_REGS_H_=0D +#define _FLASH_REGS_H_=0D +=0D +//=0D +// Flash Descriptor Base Address Region (FDBAR) from Flash Region 0=0D +//=0D +#define R_FLASH_FDBAR_FLASH_MAP0 0x04=0D +#define B_FLASH_FDBAR_NC 0x00000300 //= /< Number Of Components=0D +#define N_FLASH_FDBAR_NC 8 //= /< Number Of Components=0D +#define R_FLASH_FDBAR_FLASH_MAP1 0x08=0D +#define B_FLASH_FDBAR_FPSBA 0x00FF0000 //= /< PCH Strap Base Address, [23:16] represents [11:4]=0D +#define N_FLASH_FDBAR_FPSBA 16 //= /< PCH Strap base Address bit position=0D +#define N_FLASH_FDBAR_FPSBA_REPR 4 //= /< PCH Strap base Address bit represents position=0D +#define B_FLASH_FDBAR_PCHSL 0xFF000000 //= /< PCH Strap Length, [31:24] represents number of Dwords=0D +#define N_FLASH_FDBAR_PCHSL 24 //= /< PCH Strap Length bit position=0D +#define R_FLASH_FDBAR_FLASH_MAP2 0x0C=0D +#define B_FLASH_FDBAR_FCPUSBA 0x00000FFC //= /< CPU Strap Base Address [11:2]=0D +#define N_FLASH_FDBAR_FCPUSBA 2 //= /< CPU Strap Base Address bit position=0D +#define B_FLASH_FDBAR_CPUSL 0x00FF0000 //= /< CPU Strap Length, [23:16] represents number of Dwords=0D +#define N_FLASH_FDBAR_CPUSL 16 //= /< CPU Strap Length bit position=0D +=0D +//=0D +// Flash Component Base Address (FCBA) from Flash Region 0=0D +//=0D +#define R_FLASH_FCBA_FLCOMP 0x00 //= /< Flash Components Register=0D +#define B_FLASH_FLCOMP_COMP1_MASK 0xF0 //= /< Flash Component 1 Size MASK=0D +#define N_FLASH_FLCOMP_COMP1 4 //= /< Flash Component 1 Size bit position=0D +#define B_FLASH_FLCOMP_COMP0_MASK 0x0F //= /< Flash Component 0 Size MASK=0D +#define V_FLASH_FLCOMP_COMP_512KB 0x80000=0D +//=0D +// Descriptor Upper Map Section from Flash Region 0=0D +//=0D +#define R_FLASH_UMAP1 0xEFC //= /< Flash Upper Map 1=0D +#define B_FLASH_UMAP1_MDTBA 0xFF000000 //= /< MIP Descriptor Table Base Address=0D +#define N_FLASH_UMAP1_MDTBA 24 //= /< MDTBA bits position=0D +#define N_FLASH_UMAP1_MDTBA_REPR 4 //= /< MDTBA address representation position=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h = b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h new file mode 100644 index 0000000000..e4bf2018b7 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegs.h @@ -0,0 +1,121 @@ +/** @file=0D + Register names for PCH GPIO=0D +=0D +Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_REGS_H_=0D +#define _GPIO_REGS_H_=0D +=0D +//=0D +// PADCFG register is split into multiple DW registers=0D +// S_GPIO_PCR_PADCFG refers to number of bytes used by all those registers= for one pad=0D +//=0D +#define S_GPIO_PCR_PADCFG 0x10=0D +=0D +//=0D +// Pad Configuration Register DW0=0D +//=0D +=0D +//Pad Reset Config=0D +#define B_GPIO_PCR_RST_CONF (BIT31 | BIT30)=0D +#define N_GPIO_PCR_RST_CONF 30=0D +#define V_GPIO_PCR_RST_CONF_POW_GOOD 0x00=0D +#define V_GPIO_PCR_RST_CONF_DEEP_RST 0x01=0D +#define V_GPIO_PCR_RST_CONF_GPIO_RST 0x02=0D +#define V_GPIO_PCR_RST_CONF_RESUME_RST 0x03 // Only for GPD Group=0D +=0D +//RX Raw Override to 1=0D +#define B_GPIO_PCR_RX_RAW1 BIT28=0D +#define N_GPIO_PCR_RX_RAW1 28=0D +=0D +//RX Level/Edge Configuration=0D +#define B_GPIO_PCR_RX_LVL_EDG (BIT26 | BIT25)=0D +#define N_GPIO_PCR_RX_LVL_EDG 25=0D +=0D +//RX Invert=0D +#define B_GPIO_PCR_RXINV BIT23=0D +#define N_GPIO_PCR_RXINV 23=0D +=0D +//GPIO Input Route IOxAPIC=0D +#define B_GPIO_PCR_RX_APIC_ROUTE BIT20=0D +=0D +//GPIO Input Route SCI=0D +#define B_GPIO_PCR_RX_SCI_ROUTE BIT19=0D +=0D +//GPIO Input Route SMI=0D +#define B_GPIO_PCR_RX_SMI_ROUTE BIT18=0D +=0D +//GPIO Input Route NMI=0D +#define B_GPIO_PCR_RX_NMI_ROUTE BIT17=0D +#define N_GPIO_PCR_RX_NMI_ROUTE 17=0D +=0D +//GPIO Pad Mode=0D +#define B_GPIO_PCR_PAD_MODE (BIT12 | BIT11 | BIT10)=0D +#define N_GPIO_PCR_PAD_MODE 10=0D +=0D +//GPIO RX Disable=0D +#define B_GPIO_PCR_RXDIS BIT9=0D +=0D +//GPIO TX Disable=0D +#define B_GPIO_PCR_TXDIS BIT8=0D +#define N_GPIO_PCR_TXDIS 8=0D +=0D +//GPIO RX State=0D +#define B_GPIO_PCR_RX_STATE BIT1=0D +#define N_GPIO_PCR_RX_STATE 1=0D +=0D +//GPIO TX State=0D +#define B_GPIO_PCR_TX_STATE BIT0=0D +#define N_GPIO_PCR_TX_STATE 0=0D +=0D +//Termination=0D +#define B_GPIO_PCR_TERM (BIT13 | BIT12 | BIT11 | BIT10)=0D +#define N_GPIO_PCR_TERM 10=0D +=0D +//Interrupt number=0D +#define B_GPIO_PCR_INTSEL 0x7F=0D +#define N_GPIO_PCR_INTSEL 0=0D +=0D +///=0D +/// GPIO SMI data used for EFI_SMM_GPI_DISPATCH2_PROTOCOL=0D +/// Below defines are to be used internally by PCH SMI dispatcher only=0D +///=0D +#define PCH_GPIO_NUM_SUPPORTED_GPIS 512=0D +#define S_GPIO_PCR_GP_SMI_STS 4=0D +=0D +///=0D +/// Groups mapped to 2-tier General Purpose Event will all be under=0D +/// one master GPE_111 (0x6F)=0D +///=0D +#define PCH_GPIO_2_TIER_MASTER_GPE_NUMBER 0x6F=0D +=0D +#endif // _GPIO_REGS_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer= 2.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h new file mode 100644 index 0000000000..1dc05869dd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/GpioRegsVer2.h @@ -0,0 +1,226 @@ +/** @file=0D + Register names for VER2 GPIO=0D +=0D +Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_REGS_VER2_H_=0D +#define _GPIO_REGS_VER2_H_=0D +=0D +//=0D +// PCH-LP GPIO=0D +//=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_B_PAD_MAX 26=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_A_PAD_MAX 25=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_R_PAD_MAX 8=0D +#define GPIO_VER2_PCH_LP_GPIO_GPD_PAD_MAX 17=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_S_PAD_MAX 8=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_H_PAD_MAX 24=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_D_PAD_MAX 21=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_F_PAD_MAX 25=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_C_PAD_MAX 24=0D +#define GPIO_VER2_PCH_LP_GPIO_GPP_E_PAD_MAX 25=0D +#define GPIO_VER2_PCH_LP_GPIO_CPU_PAD_MAX 15=0D +=0D +//=0D +// PCH-LP GPIO registers=0D +//=0D +=0D +//=0D +// GPIO Community 0 Private Configuration Registers=0D +//=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PAD_OWN 0x20=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PAD_OWN 0x38=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCK 0x80=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFGLOCKTX 0x84=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCK 0x90=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFGLOCKTX 0x94=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_HOSTSW_OWN 0xB0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_HOSTSW_OWN 0xB8=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IS 0x0100=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IS 0x0108=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_IE 0x0120=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_IE 0x0128=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_STS 0x0140=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_STS 0x0148=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_GPI_GPE_EN 0x0160=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_GPI_GPE_EN 0x0168=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_STS 0x0180=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_SMI_EN 0x01A0=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_STS 0x01C0=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_NMI_EN 0x01E0=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_B_PADCFG_OFFSET 0x700=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_A_PADCFG_OFFSET 0x9A0=0D +=0D +//=0D +// GPIO Community 1 Private Configuration Registers=0D +//=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PAD_OWN 0x20=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PAD_OWN 0x24=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PAD_OWN 0x30=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCK 0x80=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFGLOCKTX 0x84=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCK 0x88=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFGLOCKTX 0x8C=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCK 0x90=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFGLOCKTX 0x94=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_HOSTSW_OWN 0xB0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_HOSTSW_OWN 0xB4=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_HOSTSW_OWN 0xB8=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IS 0x0100=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IS 0x0104=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IS 0x0108=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_IE 0x0120=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_IE 0x0124=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_IE 0x0128=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_STS 0x0140=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_STS 0x0144=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_STS 0x0148=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_GPI_GPE_EN 0x0160=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_GPI_GPE_EN 0x0164=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_GPI_GPE_EN 0x0168=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_STS 0x0188=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_SMI_EN 0x01A8=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_STS 0x01C8=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_NMI_EN 0x01E8=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_S_PADCFG_OFFSET 0x700=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_H_PADCFG_OFFSET 0x780=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_D_PADCFG_OFFSET 0x900=0D +=0D +//=0D +// GPIO Community 2 Private Configuration Registers=0D +//=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PAD_OWN 0x20=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCK 0x80=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFGLOCKTX 0x84=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_HOSTSW_OWN 0xB0=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IS 0x0100=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_IE 0x0120=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_STS 0x0140=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_GPI_GPE_EN 0x0160=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPD_PADCFG_OFFSET 0x700=0D +=0D +//=0D +// GPIO Community 4 Private Configuration Registers=0D +//=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PAD_OWN 0x20=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PAD_OWN 0x2C=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PAD_OWN 0x40=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCK 0x80=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFGLOCKTX 0x84=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCK 0x88=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFGLOCKTX 0x8C=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCK 0x98=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFGLOCKTX 0x9C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_HOSTSW_OWN 0xB0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_HOSTSW_OWN 0xB4=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_HOSTSW_OWN 0xBC=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IS 0x0100=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IS 0x0104=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IS 0x010C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_IE 0x0120=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_IE 0x0124=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_IE 0x012C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_STS 0x0140=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_STS 0x0144=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_STS 0x014C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_GPI_GPE_EN 0x0160=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_GPI_GPE_EN 0x0164=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_GPI_GPE_EN 0x016C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_STS 0x0180=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_STS 0x018C=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_SMI_EN 0x01A0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_SMI_EN 0x01AC=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_STS 0x01C0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_STS 0x01CC=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_NMI_EN 0x01E0=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_NMI_EN 0x01EC=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_C_PADCFG_OFFSET 0x700=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_F_PADCFG_OFFSET 0x880=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_E_PADCFG_OFFSET 0xA70=0D +=0D +//=0D +// GPIO Community 5 Private Configuration Registers=0D +//=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PAD_OWN 0x20=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCK 0x80=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFGLOCKTX 0x84=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_HOSTSW_OWN 0xB0=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IS 0x0100=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_IE 0x0120=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_STS 0x0140=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_GPI_GPE_EN 0x0160=0D +=0D +#define R_GPIO_VER2_PCH_LP_GPIO_PCR_GPP_R_PADCFG_OFFSET 0x700=0D +=0D +#endif // _GPIO_REGS_VER2_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Reg= s.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h new file mode 100644 index 0000000000..5447fabccf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmi14Regs.h @@ -0,0 +1,16 @@ +/** @file=0D + Register names for PCH DMI SIP14=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_DMI14_REGS_H_=0D +#define _PCH_DMI14_REGS_H_=0D +=0D +//=0D +// DMI Control=0D +//=0D +#define R_PCH_DMI14_PCR_DMIC 0x2234 = ///< DMI Control=0D +#define B_PCH_DMI14_PCR_DMIC_SRL BIT31 = ///< Secured register lock=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.= h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h new file mode 100644 index 0000000000..e9e6f80327 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchDmiRegs.h @@ -0,0 +1,36 @@ +/** @file=0D + Register names for PCH DMI and OP-DMI=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_DMI_REGS_H_=0D +#define _PCH_DMI_REGS_H_=0D +=0D +//=0D +// PCH DMI Chipset Configuration Registers (PID:DMI)=0D +//=0D +=0D +//=0D +// PCH DMI Source Decode PCRs (Common)=0D +//=0D +#define R_PCH_DMI_PCR_LPCLGIR1 0x2730 = ///< LPC Generic I/O Range 1=0D +#define R_PCH_DMI_PCR_LPCGMR 0x2740 = ///< LPC Generic Memory Range=0D +#define R_PCH_DMI_PCR_SEGIR 0x27BC = ///< Second ESPI Generic I/O Range=0D +#define R_PCH_DMI_PCR_SEGMR 0x27C0 = ///< Second ESPI Generic Memory Range=0D +#define R_PCH_DMI_PCR_LPCBDE 0x2744 = ///< LPC BIOS Decode Enable=0D +#define R_PCH_DMI_PCR_UCPR 0x2748 = ///< uCode Patch Region=0D +#define B_PCH_DMI_PCR_UCPR_UPRE BIT0 = ///< uCode Patch Region Enable=0D +#define R_PCH_DMI_PCR_GCS 0x274C = ///< Generic Control and Status=0D +#define B_PCH_DMI_PCR_BBS BIT10 = ///< Boot BIOS Strap=0D +#define B_PCH_DMI_PCR_RPR BIT11 = ///< Reserved Page Route=0D +#define B_PCH_DMI_PCR_BILD BIT0 = ///< BIOS Interface Lock-Down=0D +#define R_PCH_DMI_PCR_IOT1 0x2750 = ///< I/O Trap Register 1=0D +#define R_PCH_DMI_PCR_LPCIOD 0x2770 = ///< LPC I/O Decode Ranges=0D +#define R_PCH_DMI_PCR_LPCIOE 0x2774 = ///< LPC I/O Enables=0D +#define R_PCH_DMI_PCR_TCOBASE 0x2778 = ///< TCO Base Address=0D +#define B_PCH_DMI_PCR_TCOBASE_TCOBA 0xFFE0 = ///< TCO Base Address Mask=0D +#define R_PCH_DMI_PCR_GPMR1 0x277C = ///< General Purpose Memory Range 1=0D +#define R_PCH_DMI_PCR_GPMR1DID 0x2780 = ///< General Purpose Memory Range 1 Destination ID=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRe= gs.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h new file mode 100644 index 0000000000..c3497b1013 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PchPcieRpRegs.h @@ -0,0 +1,93 @@ +/** @file=0D + Register names for PCH PCI-E root port devices=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PCIE_H_=0D +#define _PCH_REGS_PCIE_H_=0D +=0D +#define R_PCH_PCIE_CFG_CLIST 0x40=0D +#define R_PCH_PCIE_CFG_LCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LCAP_OFFSET)=0D +#define N_PCH_PCIE_CFG_LCAP_PN 24=0D +#define R_PCH_PCIE_CFG_LCTL (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LCTL_OFFSET)=0D +#define R_PCH_PCIE_CFG_LSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_LSTS_OFFSET)=0D +#define R_PCH_PCIE_CFG_SLCAP (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_SLCAP_OFFSET)=0D +#define R_PCH_PCIE_CFG_SLSTS (R_PCH_PCIE_CFG_CLIS= T + R_PCIE_SLSTS_OFFSET)=0D +=0D +#define R_PCH_PCIE_CFG_MPC2 0xD4=0D +#define B_PCH_PCIE_CFG_MPC2_EOIFD BIT1=0D +=0D +#define R_PCH_PCIE_CFG_MPC 0xD8=0D +#define S_PCH_PCIE_CFG_MPC 4=0D +#define B_PCH_PCIE_CFG_MPC_PMCE BIT31=0D +#define B_PCH_PCIE_CFG_MPC_HPME BIT1=0D +#define N_PCH_PCIE_CFG_MPC_HPME 1=0D +=0D +#define R_PCH_PCIE_CFG_SMSCS 0xDC=0D +#define S_PCH_PCIE_CFG_SMSCS 4=0D +#define B_PCH_PCIE_CFG_SMSCS_PMCS BIT31=0D +#define N_PCH_PCIE_CFG_SMSCS_LERSMIS 5=0D +#define N_PCH_PCIE_CFG_SMSCS_HPLAS 4=0D +#define N_PCH_PCIE_CFG_SMSCS_HPPDM 1=0D +=0D +//CES.RE, CES.BT, CES.BD=0D +=0D +#define R_PCH_PCIE_CFG_EX_SPEECH 0xA30 ///< Secondary= PCI Express Extended Capability Header=0D +#define R_PCH_PCIE_CFG_EX_LCTL3 (R_PCH_PCIE_CFG_EX_S= PEECH + R_PCIE_EX_LCTL3_OFFSET)=0D +=0D +#define R_PCH_PCIE_CFG_LTROVR 0x400=0D +#define B_PCH_PCIE_CFG_LTROVR_LTRNSROVR BIT31 ///< LTR Non-S= noop Requirement Bit Override=0D +#define B_PCH_PCIE_CFG_LTROVR_LTRSROVR BIT15 ///< LTR Snoop= Requirement Bit Override=0D +=0D +#define R_PCH_PCIE_CFG_LTROVR2 0x404=0D +#define B_PCH_PCIE_CFG_LTROVR2_FORCE_OVERRIDE BIT3 ///< LTR Force = Override Enable=0D +#define B_PCH_PCIE_CFG_LTROVR2_LOCK BIT2 ///< LTR Overri= de Lock=0D +#define B_PCH_PCIE_CFG_LTROVR2_LTRNSOVREN BIT1 ///< LTR Non-Sn= oop Override Enable=0D +#define B_PCH_PCIE_CFG_LTROVR2_LTRSOVREN BIT0 ///< LTR Snoop = Override Enable=0D +=0D +#define R_PCH_PCIE_CFG_PCIEPMECTL 0x420=0D +#define B_PCH_PCIE_CFG_PCIEPMECTL_DLSULPPGE BIT30=0D +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1LE BIT17=0D +#define B_PCH_PCIE_CFG_PCIEPMECTL_L1FSOE BIT0=0D +=0D +#define R_PCH_PCIE_CFG_EQCFG1 0x450=0D +#define S_PCH_PCIE_CFG_EQCFG1 4=0D +#define N_PCH_PCIE_CFG_EQCFG1_LERSMIE 21=0D +=0D +//=0D +// PCIE PCRs (PID:SPA SPB SPC SPD SPE SPF)=0D +//=0D +#define R_SPX_PCR_PCD 0 ///<= Port configuration and disable=0D +#define B_SPX_PCR_PCD_RP1FN (BIT2 | BIT1 | BIT0) ///<= Port 1 Function Number=0D +#define S_SPX_PCR_PCD_RP_FIELD 4 ///<= 4 bits for each RP FN=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h b= /Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h new file mode 100644 index 0000000000..fac1497773 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/PmcRegs.h @@ -0,0 +1,258 @@ +/** @file=0D + Register names for PCH PMC device=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PMC_H_=0D +#define _PCH_REGS_PMC_H_=0D +=0D +//=0D +// ACPI and legacy I/O register offsets from ACPIBASE=0D +//=0D +#define R_ACPI_IO_PM1_STS 0x00=0D +#define S_ACPI_IO_PM1_STS 2=0D +#define B_ACPI_IO_PM1_STS_WAK BIT15=0D +#define B_ACPI_IO_PM1_STS_PCIEXP_WAKE_STS BIT14=0D +#define B_ACPI_IO_PM1_STS_PRBTNOR BIT11=0D +#define B_ACPI_IO_PM1_STS_RTC BIT10=0D +#define B_ACPI_IO_PM1_STS_PWRBTN BIT8=0D +#define B_ACPI_IO_PM1_STS_GBL BIT5=0D +#define B_ACPI_IO_PM1_STS_TMROF BIT0=0D +#define N_ACPI_IO_PM1_STS_RTC 10=0D +#define N_ACPI_IO_PM1_STS_PWRBTN 8=0D +#define N_ACPI_IO_PM1_STS_TMROF 0=0D +=0D +#define R_ACPI_IO_PM1_EN 0x02=0D +#define S_ACPI_IO_PM1_EN 2=0D +#define B_ACPI_IO_PM1_EN_PWRBTN BIT8=0D +#define N_ACPI_IO_PM1_EN_RTC 10=0D +#define N_ACPI_IO_PM1_EN_PWRBTN 8=0D +#define N_ACPI_IO_PM1_EN_TMROF 0=0D +=0D +#define R_ACPI_IO_PM1_CNT 0x04=0D +#define B_ACPI_IO_PM1_CNT_SLP_EN BIT13=0D +#define B_ACPI_IO_PM1_CNT_SLP_TYP (BIT12 | BIT11 | BIT10)=0D +#define V_ACPI_IO_PM1_CNT_S0 0=0D +#define V_ACPI_IO_PM1_CNT_S1 BIT10=0D +#define V_ACPI_IO_PM1_CNT_S3 (BIT12 | BIT10)=0D +#define V_ACPI_IO_PM1_CNT_S4 (BIT12 | BIT11)=0D +#define V_ACPI_IO_PM1_CNT_S5 (BIT12 | BIT11 | BIT10)=0D +#define B_ACPI_IO_PM1_CNT_SCI_EN BIT0=0D +=0D +#define R_ACPI_IO_PM1_TMR 0x08=0D +#define B_ACPI_IO_PM1_TMR_VAL 0xFFFFFF=0D +#define V_ACPI_IO_PM1_TMR_MAX_VAL 0x1000000 ///< The = timer is 24 bit overflow=0D +=0D +#define R_ACPI_IO_SMI_EN 0x30=0D +#define S_ACPI_IO_SMI_EN 4=0D +#define B_ACPI_IO_SMI_EN_LEGACY_USB2 BIT17=0D +#define B_ACPI_IO_SMI_EN_TCO BIT13=0D +#define B_ACPI_IO_SMI_EN_BIOS_RLS BIT7=0D +#define B_ACPI_IO_SMI_EN_SWSMI_TMR BIT6=0D +#define B_ACPI_IO_SMI_EN_APMC BIT5=0D +#define B_ACPI_IO_SMI_EN_LEGACY_USB BIT3=0D +#define B_ACPI_IO_SMI_EN_BIOS BIT2=0D +#define B_ACPI_IO_SMI_EN_EOS BIT1=0D +#define B_ACPI_IO_SMI_EN_GBL_SMI BIT0=0D +#define N_ACPI_IO_SMI_EN_LEGACY_USB3 31=0D +#define N_ACPI_IO_SMI_EN_ESPI 28=0D +#define N_ACPI_IO_SMI_EN_PERIODIC 14=0D +#define N_ACPI_IO_SMI_EN_TCO 13=0D +#define N_ACPI_IO_SMI_EN_MCSMI 11=0D +#define N_ACPI_IO_SMI_EN_SWSMI_TMR 6=0D +#define N_ACPI_IO_SMI_EN_APMC 5=0D +#define N_ACPI_IO_SMI_EN_ON_SLP_EN 4=0D +#define N_ACPI_IO_SMI_EN_LEGACY_USB 3=0D +=0D +#define R_ACPI_IO_SMI_STS 0x34=0D +#define S_ACPI_IO_SMI_STS 4=0D +#define B_ACPI_IO_SMI_STS_GPIO_UNLOCK BIT27=0D +#define B_ACPI_IO_SMI_STS_SMBUS BIT16=0D +#define B_ACPI_IO_SMI_STS_PERIODIC BIT14=0D +#define B_ACPI_IO_SMI_STS_TCO BIT13=0D +#define B_ACPI_IO_SMI_STS_MCSMI BIT11=0D +#define B_ACPI_IO_SMI_STS_SWSMI_TMR BIT6=0D +#define B_ACPI_IO_SMI_STS_APM BIT5=0D +#define B_ACPI_IO_SMI_STS_ON_SLP_EN BIT4=0D +#define B_ACPI_IO_SMI_STS_BIOS BIT2=0D +#define N_ACPI_IO_SMI_STS_LEGACY_USB3 31=0D +#define N_ACPI_IO_SMI_STS_ESPI 28=0D +#define N_ACPI_IO_SMI_STS_SPI 26=0D +#define N_ACPI_IO_SMI_STS_MONITOR 21=0D +#define N_ACPI_IO_SMI_STS_PCI_EXP 20=0D +#define N_ACPI_IO_SMI_STS_SMBUS 16=0D +#define N_ACPI_IO_SMI_STS_SERIRQ 15=0D +#define N_ACPI_IO_SMI_STS_PERIODIC 14=0D +#define N_ACPI_IO_SMI_STS_TCO 13=0D +#define N_ACPI_IO_SMI_STS_MCSMI 11=0D +#define N_ACPI_IO_SMI_STS_GPIO_SMI 10=0D +#define N_ACPI_IO_SMI_STS_GPE0 9=0D +#define N_ACPI_IO_SMI_STS_PM1_STS_REG 8=0D +#define N_ACPI_IO_SMI_STS_SWSMI_TMR 6=0D +#define N_ACPI_IO_SMI_STS_APM 5=0D +#define N_ACPI_IO_SMI_STS_ON_SLP_EN 4=0D +#define N_ACPI_IO_SMI_STS_LEGACY_USB 3=0D +=0D +#define R_ACPI_IO_DEVACT_STS 0x44=0D +#define B_ACPI_IO_DEVACT_STS_KBC BIT12=0D +#define B_ACPI_IO_DEVACT_STS_PIRQDH BIT9=0D +#define B_ACPI_IO_DEVACT_STS_PIRQCG BIT8=0D +#define B_ACPI_IO_DEVACT_STS_PIRQBF BIT7=0D +#define B_ACPI_IO_DEVACT_STS_PIRQAE BIT6=0D +=0D +#define R_ACPI_IO_GPE0_STS_127_96 0x6C=0D +#define S_ACPI_IO_GPE0_STS_127_96 4=0D +#define B_ACPI_IO_GPE0_STS_127_96_WADT BIT18=0D +#define B_ACPI_IO_GPE0_STS_127_96_USB_CON_DSX_STS BIT17=0D +#define B_ACPI_IO_GPE0_STS_127_96_LAN_WAKE BIT16=0D +#define B_ACPI_IO_GPE0_STS_127_96_PME_B0 BIT13=0D +#define B_ACPI_IO_GPE0_STS_127_96_PME BIT11=0D +#define B_ACPI_IO_GPE0_STS_127_96_BATLOW BIT10=0D +#define B_ACPI_IO_GPE0_STS_127_96_RI BIT8=0D +#define B_ACPI_IO_GPE0_STS_127_96_SMB_WAK BIT7=0D +#define B_ACPI_IO_GPE0_STS_127_96_SWGPE BIT2=0D +#define N_ACPI_IO_GPE0_STS_127_96_PME_B0 13=0D +#define N_ACPI_IO_GPE0_STS_127_96_PME 11=0D +=0D +#define R_ACPI_IO_GPE0_EN_127_96 0x7C=0D +#define S_ACPI_IO_GPE0_EN_127_96 4=0D +#define B_ACPI_IO_GPE0_EN_127_96_WADT BIT18=0D +#define B_ACPI_IO_GPE0_EN_127_96_LAN_WAKE BIT16=0D +#define B_ACPI_IO_GPE0_EN_127_96_PME_B0 BIT13=0D +#define B_ACPI_IO_GPE0_EN_127_96_ME_SCI BIT12=0D +#define B_ACPI_IO_GPE0_EN_127_96_PME BIT11=0D +#define B_ACPI_IO_GPE0_EN_127_96_BATLOW BIT10=0D +#define B_ACPI_IO_GPE0_EN_127_96_RI BIT8=0D +#define B_ACPI_IO_GPE0_EN_127_96_SWGPE BIT2=0D +#define N_ACPI_IO_GPE0_EN_127_96_PME_B0 13=0D +#define N_ACPI_IO_GPE0_EN_127_96_PME 11=0D +=0D +//=0D +// TCO register I/O map=0D +//=0D +#define R_TCO_IO_TCO1_STS 0x04=0D +#define S_TCO_IO_TCO1_STS 2=0D +#define B_TCO_IO_TCO1_STS_DMISERR BIT12=0D +#define B_TCO_IO_TCO1_STS_DMISMI BIT10=0D +#define B_TCO_IO_TCO1_STS_DMISCI BIT9=0D +#define B_TCO_IO_TCO1_STS_BIOSWR BIT8=0D +#define B_TCO_IO_TCO1_STS_NEWCENTURY BIT7=0D +#define B_TCO_IO_TCO1_STS_TIMEOUT BIT3=0D +#define B_TCO_IO_TCO1_STS_TCO_INT BIT2=0D +#define B_TCO_IO_TCO1_STS_SW_TCO_SMI BIT1=0D +#define N_TCO_IO_TCO1_STS_DMISMI 10=0D +#define N_TCO_IO_TCO1_STS_BIOSWR 8=0D +#define N_TCO_IO_TCO1_STS_NEWCENTURY 7=0D +#define N_TCO_IO_TCO1_STS_TIMEOUT 3=0D +#define N_TCO_IO_TCO1_STS_SW_TCO_SMI 1=0D +#define N_TCO_IO_TCO1_STS_NMI2SMI 0=0D +=0D +#define R_TCO_IO_TCO2_STS 0x06=0D +#define S_TCO_IO_TCO2_STS 2=0D +#define B_TCO_IO_TCO2_STS_SECOND_TO BIT1=0D +#define B_TCO_IO_TCO2_STS_INTRD_DET BIT0=0D +#define N_TCO_IO_TCO2_STS_INTRD_DET 0=0D +=0D +#define R_TCO_IO_TCO1_CNT 0x08=0D +#define S_TCO_IO_TCO1_CNT 2=0D +#define B_TCO_IO_TCO1_CNT_LOCK BIT12=0D +#define N_TCO_IO_TCO1_CNT_NMI2SMI_EN 9=0D +=0D +#define R_TCO_IO_TCO2_CNT 0x0A=0D +#define S_TCO_IO_TCO2_CNT 2=0D +#define N_TCO_IO_TCO2_CNT_INTRD_SEL 2=0D +=0D +//=0D +// PWRM Registers=0D +//=0D +#define R_PMC_PWRM_GEN_PMCON_A 0x1020 = ///< in CNL located in PWRM=0D +#define B_PMC_PWRM_GEN_PMCON_A_GBL_RST_STS BIT24=0D +#define B_PMC_PWRM_GEN_PMCON_A_DISB BIT23=0D +#define B_PMC_PWRM_GEN_PMCON_A_ALLOW_L1LOW_C0 BIT19=0D +#define B_PMC_PWRM_GEN_PMCON_A_MS4V BIT18=0D +#define B_PMC_PWRM_GEN_PMCON_A_SUS_PWR_FLR BIT16=0D +#define B_PMC_PWRM_GEN_PMCON_A_PWR_FLR BIT14=0D +#define B_PMC_PWRM_GEN_PMCON_A_HOST_RST_STS BIT9=0D +#define B_PMC_PWRM_GEN_PMCON_A_ESPI_SMI_LOCK BIT8=0D +#define B_PMC_PWRM_GEN_PMCON_A_AFTERG3_EN BIT0=0D +#define B_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL 0xC0=0D +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_64MS 0xC0=0D +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_32MS 0x80=0D +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_16MS 0x40=0D +#define V_PMC_PWRM_GEN_PMCON_A_SWSMI_RTSL_1_5MS 0x00=0D +#define B_PMC_PWRM_GEN_PMCON_A_PER_SMI_SEL 0x6=0D +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_64S 0x0000=0D +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_32S 0x0002=0D +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_16S 0x0004=0D +#define V_PMC_PWRM_GEN_PMCON_A_PER_SMI_8S 0x0006=0D +=0D +#define R_PMC_PWRM_GEN_PMCON_B 0x1024=0D +#define B_PMC_PWRM_GEN_PMCON_B_SLPSX_STR_POL_LOCK BIT18 = ///< Lock down SLP_S3/SLP_S4 Minimum Assertion width=0D +#define B_PMC_PWRM_GEN_PMCON_B_PWRBTN_LVL BIT9=0D +#define B_PMC_PWRM_GEN_PMCON_B_SMI_LOCK BIT4=0D +#define B_PMC_PWRM_GEN_PMCON_B_RTC_PWR_STS BIT2=0D +=0D +#define R_PMC_PWRM_CRID 0x1030 = ///< Configured Revision ID=0D +#define V_PMC_PWRM_CRID_RID_SEL_CRID0 1=0D +#define B_PMC_PWRM_CRID_CRID_LK BIT31 = ///< CRID Lock=0D +=0D +#define R_PMC_PWRM_ETR3 0x1048 = ///< in CNL this is PWRM register=0D +#define B_PMC_PWRM_ETR3_CF9LOCK BIT31 = ///< CF9h Lockdown=0D +#define B_PMC_PWRM_ETR3_CF9GR BIT20 = ///< CF9h Global Reset=0D +#define B_PMC_PWRM_ETR3_CWORWRE BIT18=0D +=0D +#define R_PMC_PWRM_CFG 0x1818 = ///< Power Management Configuration=0D +#define B_PMC_PWRM_CFG_DBG_MODE_LOCK BIT27 = ///< Debug Mode Lock=0D +#define B_PMC_PWRM_CFG_PMCREAD_DISABLE BIT22 = ///< Disable Reads to PMC=0D +#define B_PMC_PWRM_CFG_TIMING_TPCH25 (BIT1 | BIT0) = ///< tPCH25 timing=0D +=0D +#define R_PMC_PWRM_DSX_CFG 0x1834 = ///< Deep SX Configuration=0D +#define B_PMC_PWRM_DSX_CFG_LAN_WAKE_EN BIT0 = ///< LAN_WAKE Pin DeepSx Enable=0D +=0D +#define R_PMC_PWRM_GPIO_CFG 0x1920=0D +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW2 (BIT11 | BIT10= | BIT9 | BIT8)=0D +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW2 8=0D +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW1 (BIT7 | BIT6 |= BIT5 | BIT4)=0D +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW1 4=0D +#define B_PMC_PWRM_GPIO_CFG_GPE0_DW0 (BIT3 | BIT2 |= BIT1 | BIT0)=0D +#define N_PMC_PWRM_GPIO_CFG_GPE0_DW0 0=0D +=0D +#define R_PMC_PWRM_HPR_CAUSE0 0x192C ///< = Host partition reset causes=0D +#define B_PMC_PWRM_HPR_CAUSE0_GBL_TO_HOST BIT15 ///< = Global reset converted to Host reset=0D +=0D +#define R_PMC_PWRM_ST_PG_FDIS_PMC_1 0x1E20 ///< St= atic PG Related Function Disable Register 1=0D +#define B_PMC_PWRM_ST_PG_FDIS_PMC_1_ST_FDIS_LK BIT31 ///< Sta= tic Function Disable Lock (ST_FDIS_LK)=0D +=0D +#define R_PMC_PWRM_FUSE_DIS_RD_2 0x1E44 ///< Fu= se Disable Read 2 Register=0D +#define B_PMC_PWRM_FUSE_DIS_RD_2_GBE_FUSE_SS_DIS BIT0 ///< GBE= Fuse or Soft Strap Disable=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h b= /Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h new file mode 100644 index 0000000000..5824663d22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/RtcRegs.h @@ -0,0 +1,45 @@ +/** @file=0D + Register names for RTC device=0D +=0D +Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _REGS_RTC_H_=0D +#define _REGS_RTC_H_=0D +=0D +#define R_RTC_IO_INDEX 0x70=0D +#define R_RTC_IO_TARGET 0x71=0D +#define R_RTC_IO_INDEX_ALT 0x74=0D +#define R_RTC_IO_TARGET_ALT 0x75=0D +#define R_RTC_IO_EXT_INDEX_ALT 0x76=0D +#define R_RTC_IO_REGD 0x0D=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h = b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h new file mode 100644 index 0000000000..2037bb003d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SataRegs.h @@ -0,0 +1,56 @@ +/** @file=0D + Register names for SATA controllers=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SATA_REGS_H_=0D +#define _SATA_REGS_H_=0D +=0D +//=0D +// SATA Controller Common Registers=0D +//=0D +#define R_SATA_CFG_AHCI_BAR 0x24=0D +#define R_SATA_CFG_MAP 0x90=0D +#define N_SATA_CFG_MAP_SPD 16=0D +#define R_SATA_CFG_PCS 0x94=0D +#define B_SATA_CFG_PCS_P0P BIT16=0D +#define R_SATA_CFG_SATAGC 0x9C=0D +#define B_SATA_CFG_SATAGC_ASSEL (BIT2 | BIT1 | BIT0)=0D +#define V_SATA_CFG_SATAGC_ASSEL_2K 0x0=0D +#define V_SATA_CFG_SATAGC_ASSEL_16K 0x1=0D +#define V_SATA_CFG_SATAGC_ASSEL_32K 0x2=0D +#define V_SATA_CFG_SATAGC_ASSEL_64K 0x3=0D +#define V_SATA_CFG_SATAGC_ASSEL_128K 0x4=0D +#define V_SATA_CFG_SATAGC_ASSEL_256K 0x5=0D +#define V_SATA_CFG_SATAGC_ASSEL_512K 0x6=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoReg= s.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h new file mode 100644 index 0000000000..9864dd872d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/SerialIoRegs.h @@ -0,0 +1,47 @@ +/** @file=0D + Register names for Serial IO Controllers=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_REGS_H_=0D +#define _SERIAL_IO_REGS_H_=0D +=0D +//=0D +// Serial IO Controllers PCI Configuration Registers=0D +// registers accessed using PciD21FxRegBase + offset=0D +//=0D +#define R_SERIAL_IO_CFG_BAR0_LOW 0x10=0D +#define R_SERIAL_IO_CFG_BAR0_HIGH 0x14=0D +=0D +#define R_SERIAL_IO_CFG_PME_CTRL_STS 0x84=0D +=0D +#endif //_SERIAL_IO_REGS_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h b= /Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h new file mode 100644 index 0000000000..ea832873bf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/Register/UsbRegs.h @@ -0,0 +1,51 @@ +/** @file=0D + Register names for USB Host and device controller=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _USB_REGS_H_=0D +#define _USB_REGS_H_=0D +=0D +//=0D +// XHCI PCI Config Space registers=0D +//=0D +#define R_XHCI_CFG_PWR_CNTL_STS 0x74=0D +#define B_XHCI_CFG_PWR_CNTL_STS_PWR_STS (BIT1 | BIT0)=0D +#define V_XHCI_CFG_PWR_CNTL_STS_PWR_STS_D3 (BIT1 | BIT0)=0D +=0D +//=0D +// xDCI (OTG) MMIO registers=0D +//=0D +#define R_XDCI_MEM_GCTL 0xC110 ///< Xdci Global Ctr= l=0D +=0D +#endif // _USB_REGS_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h b/= Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h new file mode 100644 index 0000000000..e2e1cf2ad2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SerialIoDevices.h @@ -0,0 +1,213 @@ +/** @file=0D + Serial IO policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_DEVICES_H_=0D +#define _SERIAL_IO_DEVICES_H_=0D +=0D +#include =0D +#include =0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + Available working modes for SerialIo SPI Host Controller=0D +=0D + 0: SerialIoSpiDisabled;=0D + - Device is placed in D3=0D + - Gpio configuration is skipped=0D + - PSF:=0D + !important! If given device is Function 0 and other higher funct= ions on given device=0D + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible.=0D + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device.=0D + 1: SerialIoSpiPci;=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device will be enabled in PSF=0D + - Only BAR0 will be enabled=0D + 2: SerialIoSpiHidden;=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device disabled in the PSF=0D + - Both BARs are enabled, BAR1 becomes devices Pci Config Space=0D + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC=0D + @note=0D + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space.=0D +**/=0D +typedef enum {=0D + SerialIoSpiDisabled,=0D + SerialIoSpiPci,=0D + SerialIoSpiHidden=0D +} SERIAL_IO_SPI_MODE;=0D +=0D +/**=0D + Used to set Inactive/Idle polarity of Spi Chip Select=0D +**/=0D +typedef enum {=0D + SerialIoSpiCsActiveLow =3D 0,=0D + SerialIoSpiCsActiveHigh =3D 1=0D +} SERIAL_IO_CS_POLARITY;=0D +=0D +/**=0D + The SERIAL_IO_SPI_CONFIG provides the configurations to set the Serial I= O SPI controller=0D +**/=0D +typedef struct {=0D + UINT8 Mode; ///< SerialIoSpi= Pci see SERIAL_IO_SPI_MODE=0D + UINT8 DefaultCsOutput; ///< 0 =3D CS0 CS1, CS2, CS3. Default CS used by the SPI HC=0D + UINT8 CsPolarity[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< Selects SPI Ch= ipSelect signal polarity, 0 =3D low 1 =3D High=0D + UINT8 CsEnable[PCH_MAX_SERIALIO_SPI_CHIP_SELECTS]; ///< 0 =3D Enabl= e 1 =3D Disable. Based on this setting GPIO for given SPIx CSx will be = configured in Native mode=0D + UINT8 CsMode; ///< 0 =3D HW Co= ntrol 1 =3D SW Control. Sets Chip Select Control mode Hardware or Softw= are.=0D + UINT8 CsState; ///< 0 =3D CS is= set to low 1 =3D CS is set to high=0D +} SERIAL_IO_SPI_CONFIG;=0D +=0D +/**=0D + Available working modes for SerialIo UART Host Controller=0D +=0D + 0: SerialIoUartDisabled;=0D + - Device is placed in D3=0D + - Gpio configuration is skipped=0D + - PSF:=0D + !important! If given device is Function 0 and other higher funct= ions on given device=0D + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible.=0D + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device.=0D + 1: SerialIoUartPci;=0D + - Designated for Serial IO UART OS driver usage=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device will be enabled in PSF=0D + - Only BAR0 will be enabled=0D + 2: SerialIoUartHidden;=0D + - Designated for BIOS and/or DBG2 OS kernel debug=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device disabled in the PSF=0D + - Both BARs are enabled, BAR1 becomes devices Pci Config Space=0D + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC=0D + @note=0D + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space.=0D + 3: SerialIoUartCom;=0D + - Designated for 16550/PNP0501 compatible COM device=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device disabled in the PSF=0D + - Both BARs are enabled, BAR1 becomes devices Pci Config Space=0D + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC=0D + 4: SerialIoUartSkipInit;=0D + - Gpio configuration is skipped=0D + - PSF configuration is skipped=0D + - BAR assignemnt is skipped=0D + - D-satate setting is skipped=0D +=0D +**/=0D +typedef enum {=0D + SerialIoUartDisabled,=0D + SerialIoUartPci,=0D + SerialIoUartHidden,=0D + SerialIoUartCom,=0D + SerialIoUartSkipInit=0D +} SERIAL_IO_UART_MODE;=0D +=0D +/**=0D + UART Settings=0D +**/=0D +typedef struct {=0D + UINT32 BaudRate; ///< 115200 Max 6000000 MdePkg.dec P= cdUartDefaultBaudRate=0D + UINT8 Parity; ///< 1 - No Parity see EFI_PARITY_TYPE = MdePkg.dec PcdUartDefaultParity=0D + UINT8 DataBits; ///< 8 MdePkg.dec PcdUartDefaultDataBits= =0D + UINT8 StopBits; ///< 1 - One Stop Bit see EFI_STOP_BITS_= TYPE MdePkg.dec PcdUartDefaultStopBits=0D + UINT8 AutoFlow; ///< FALSE IntelFrameworkModulePkg.dsc = PcdIsaBusSerialUseHalfHandshake=0D +} SERIAL_IO_UART_ATTRIBUTES;=0D +=0D +/**=0D + UART signals pin muxing settings. If signal can be enable only on a sing= le pin=0D + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_UA= RTx_* in GpioPins*.h=0D + for supported settings on a given platform=0D +**/=0D +typedef struct {=0D + UINT32 Rx; ///< RXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_RXD_*=0D + UINT32 Tx; ///< TXD Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_TXD_*=0D + UINT32 Rts; ///< RTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_RTS_*=0D + UINT32 Cts; ///< CTS Pin mux configuration. Refer to GPIO_*_MUXING_SERIA= LIO_UARTx_CTS_*=0D +} UART_PIN_MUX;=0D +=0D +/**=0D + Serial IO UART Controller Configuration=0D +**/=0D +typedef struct {=0D + SERIAL_IO_UART_ATTRIBUTES Attributes; ///< see SERIAL_IO_UART_ATTRIBUTE= S=0D + UART_PIN_MUX PinMux; ///< UART pin mux configuration=0D + UINT8 Mode; ///< SerialIoUartPci see= SERIAL_IO_UART_MODE=0D + UINT8 DBG2; ///< FALSE If TRUE adds = UART to DBG2 table and overrides UartPg to SerialIoUartPgDisabled=0D + UINT8 PowerGating; ///< SerialIoUartPgAuto = Applies to Hidden/COM/SkipInit see SERIAL_IO_UART_PG=0D + UINT8 DmaEnable; ///< TRUE Applies to Ser= ialIoUartPci only. Informs OS driver to use DMA, if false it will run in PI= O mode=0D +} SERIAL_IO_UART_CONFIG;=0D +=0D +typedef enum {=0D + SerialIoUartPgDisabled, ///< No _PS0/_PS3 support, device left in D0, a= fter initialization=0D +/**=0D + In mode: SerialIoUartCom;=0D + _PS0/_PS3 that supports getting device out of reset=0D + In mode: SerialIoUartPci=0D + Keeps UART in D0 and assigns Fixed MMIO for SEC/PEI usage only= =0D +**/=0D + SerialIoUartPgEnabled,=0D + SerialIoUartPgAuto ///< _PS0 and _PS3, detection through ACPI if d= evice was initialized prior to first PG. If it was used (DBG2) PG is disabl= ed,=0D +} SERIAL_IO_UART_PG;=0D +=0D +/**=0D + Available working modes for SerialIo I2C Host Controller=0D +=0D + 0: SerialIoI2cDisabled;=0D + - Device is placed in D3=0D + - Gpio configuration is skipped=0D + - PSF:=0D + !important! If given device is Function 0 and other higher funct= ions on given device=0D + are enabled, PSF disabling is skipped. PSF default w= ill remain and device PCI CFG Space will still be visible.=0D + This is needed to allow PCI enumerator access functi= ons above 0 in a multifunction device.=0D + 1: SerialIoI2cPci;=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device will be enabled in PSF=0D + - Only BAR0 will be enabled=0D + 2: SerialIoI2cHidden;=0D + - Gpio pin configuration in native mode for each assigned pin=0D + - Device disabled in the PSF=0D + - Both BARs are enabled, BAR1 becomes devices Pci Config Space=0D + - BAR0 assigned from the global PCH reserved memory range, repor= ted as motherboard resource by SIRC=0D + @note=0D + If this controller is located at function 0 and it's mode is se= t to hidden it will not be visible in the PCI space.=0D +**/=0D +typedef enum {=0D + SerialIoI2cDisabled,=0D + SerialIoI2cPci,=0D + SerialIoI2cHidden=0D +} SERIAL_IO_I2C_MODE;=0D +=0D +/**=0D + I2C signals pin muxing settings. If signal can be enable only on a singl= e pin=0D + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_SERIALIO_I2= Cx_* in GpioPins*.h=0D + for supported settings on a given platform=0D +**/=0D +typedef struct {=0D + UINT32 Sda; ///< SDA Pin mux configuration. Refer to GPIO_*_MUXING_S= ERIALIO_I2Cx_SDA_*=0D + UINT32 Scl; ///< SCL Pin mux configuration. Refer to GPIO_*_MUXING_S= ERIALIO_I2Cx_SCL_*=0D +} I2C_PIN_MUX;=0D +=0D +/**=0D + Serial IO I2C Controller Configuration=0D +**/=0D +typedef struct {=0D + UINT8 Mode; /// SerialIoI2cPci see SERIAL_IO_I2C_MO= DE=0D + /**=0D + I2C Pads Internal Termination.=0D + For more information please see Platform Design Guide.=0D + Supported values (check GPIO_ELECTRICAL_CONFIG for reference):=0D + GpioTermNone: No termination,=0D + GpioTermWpu1K: 1kOhm weak pull-up,=0D + GpioTermWpu5K: 5kOhm weak pull-up,=0D + GpioTermWpu20K: 20kOhm weak pull-up=0D + **/=0D + UINT8 PadTermination;=0D + UINT8 Reserved[2];=0D + I2C_PIN_MUX PinMux; ///< I2C pin mux configuration=0D +} SERIAL_IO_I2C_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SERIAL_IO_DEVICES_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h b/Sili= con/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h new file mode 100644 index 0000000000..191bd815a1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiConfigHob.h @@ -0,0 +1,17 @@ +/** @file=0D + Silicon Config HOB is used for gathering platform=0D + related Intel silicon information and config setting.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_CONFIG_HOB_H_=0D +#define _SI_CONFIG_HOB_H_=0D +=0D +#include =0D +=0D +extern EFI_GUID gSiConfigHobGuid;=0D +=0D +// Rename SI_CONFIG_HOB into SI_CONFIG_HOB_DATA for it does not follow HOB= structure.=0D +typedef CONST SI_CONFIG SI_CONFIG_HOB_DATA;=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h b/S= ilicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h new file mode 100644 index 0000000000..7b646d8972 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/SiPolicyStruct.h @@ -0,0 +1,64 @@ +/** @file=0D + Intel reference code configuration policies.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_POLICY_STRUCT_H_=0D +#define _SI_POLICY_STRUCT_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Silicon Policy revision number=0D + Any change to this structure will result in an update in the revision nu= mber=0D +=0D + This member specifies the revision of the Silicon Policy. This field is = used to indicate change=0D + to the policy structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +#define SI_POLICY_REVISION 1=0D +=0D +/**=0D + Silicon pre-memory Policy revision number=0D + Any change to this structure will result in an update in the revision nu= mber=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +#define SI_PREMEM_POLICY_REVISION 1=0D +=0D +=0D +/**=0D + SI Policy PPI in Pre-Mem\n=0D + All SI config block change history will be listed here\n\n=0D +=0D + - Revision 1:=0D + - Initial version.\n=0D +**/=0D +struct _SI_PREMEM_POLICY_STRUCT {=0D + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table He= ader=0D +/*=0D + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock()=0D +*/=0D +};=0D +=0D +/**=0D + SI Policy PPI\n=0D + All SI config block change history will be listed here\n\n=0D +=0D + - Revision 1:=0D + - Initial version.\n=0D +**/=0D +struct _SI_POLICY_STRUCT {=0D + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Config Block Table He= ader=0D +/*=0D + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock()=0D +*/=0D +};=0D +=0D +#endif=0D --=20 2.24.0.windows.2