From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com []) by mx.groups.io with SMTP id smtpd.web11.5283.1612428700646076160 for ; Thu, 04 Feb 2021 00:51:41 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: RZONj1L+wHailxXqX+QLvl4lgYli4PRB/hCkp92yqJRIVLfxN9X5S3Gly6StxLewIuom8Uh89D 1MPwElA8NyQQ== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="180425535" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="180425535" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:40 -0800 IronPort-SDR: rKrIQnc90hPDIwqrLzZm55QqpSeUaYSfntNOP4ZZ/kfT/uEvonvLtx3DYBFiZEINJeX93C2FaH RbQ4/THX+iRg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062383" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:38 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 32/40] TigerlakeSiliconPkg/Pch: Add Pch common library instances Date: Thu, 4 Feb 2021 16:49:11 +0800 Message-Id: <20210204084919.3603-32-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * Pch/Library/BasePchPciBdfLib * Pch/Library/BaseResetSystemLib * Pch/Library/DxePchPolicyLib * Pch/Library/PeiDxeSmmPchCycleDecodingLib * Pch/Library/PeiDxeSmmPchInfoLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePchPciB= dfLib.inf | 33 +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPciBdfLi= b.c | 1092 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset= SystemLib.c | 158 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/BaseReset= SystemLib.inf | 38 +++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicy= Lib.c | 198 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchPolicy= Lib.inf | 43 +++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib= /PchCycleDecodingLib.c | 587 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib= /PeiDxeSmmPchCycleDecodingLib.inf | 42 ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoL= ib.c | 127 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoL= ibPrivate.h | 58 ++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PchInfoL= ibTgl.c | 715 ++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeSm= mPchInfoLibTgl.inf | 43 +++++++++++++++++++++++++++++++++++ 12 files changed, 3134 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib= /BasePchPciBdfLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseP= chPciBdfLib/BasePchPciBdfLib.inf new file mode 100644 index 0000000000..4f4096a409 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/BasePc= hPciBdfLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# PCH PCIe Bus Device Function Library.=0D +#=0D +# All functions from this library are available in PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchPciBdfLib=0D +FILE_GUID =3D ED0C4241-40FA-4A74-B061-2E45E7AAD7BA=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PchPciBdfLib=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PchInfoLib=0D +PchPcieRpLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +PchPciBdfLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib= /PchPciBdfLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciB= dfLib/PchPciBdfLib.c new file mode 100644 index 0000000000..0db8cea4bb --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BasePchPciBdfLib/PchPci= BdfLib.c @@ -0,0 +1,1092 @@ +/** @file=0D + PCH PCIe Bus Device Function Library.=0D + All functions from this library are available in PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Check if a Device is present for PCH FRU=0D + If the data is defined for PCH RFU return it=0D + If the data is not defined (Device is NOT present) assert.=0D +=0D + @param[in] DataToCheck Device or Function number to check=0D +=0D + @retval Device or Function number value if defined for PCH FRU=0D + 0xFF if not present in PCH FRU=0D +**/=0D +UINT8=0D +CheckAndReturn (=0D + UINT8 DataToCheck=0D + )=0D +{=0D + if (DataToCheck =3D=3D NOT_PRESENT) {=0D + ASSERT (FALSE);=0D + }=0D + return DataToCheck;=0D +}=0D +=0D +/**=0D + Get eSPI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval eSPI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +EspiPciCfgBase (=0D + VOID=0D + )=0D +{=0D + ASSERT (PCI_DEVICE_NUMBER_PCH_ESPI !=3D NOT_PRESENT);=0D +=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PCI_DEVICE_NUMBER_PCH_ESPI,=0D + PCI_FUNCTION_NUMBER_PCH_ESPI,=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Device Number=0D +=0D + @retval GbE device number=0D +**/=0D +UINT8=0D +GbeDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_GBE);=0D +}=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Function Number=0D +=0D + @retval GbE function number=0D +**/=0D +UINT8=0D +GbeFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_GBE);=0D +}=0D +=0D +/**=0D + Get GbE controller address that can be passed to the PCI Segment Library= functions.=0D +=0D + @retval GbE controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +GbePciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + GbeDevNumber (),=0D + GbeFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get HDA PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +HdaDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HDA);=0D +}=0D +=0D +/**=0D + Get HDA PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +HdaFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HDA);=0D +}=0D +=0D +/**=0D + Get HDA controller address that can be passed to the PCI Segment Library= functions.=0D +=0D + @retval HDA controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +HdaPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + HdaDevNumber (),=0D + HdaFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get P2SB PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +P2sbDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_P2SB);=0D +}=0D +=0D +/**=0D + Get P2SB PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +P2sbFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_P2SB);=0D +}=0D +=0D +/**=0D + Get P2SB controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval P2SB controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +P2sbPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + P2sbDevNumber (),=0D + P2sbFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Returns PCH SPI Device number=0D +=0D + @retval UINT8 PCH SPI Device number=0D +**/=0D +UINT8=0D +SpiDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SPI);=0D +}=0D +=0D +/**=0D + Returns PCH SPI Function number=0D +=0D + @retval UINT8 PCH SPI Function number=0D +**/=0D +UINT8=0D +SpiFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SPI);=0D +}=0D +=0D +/**=0D + Returns PCH SPI PCI Config Space base address=0D +=0D + @retval UINT64 PCH SPI Config Space base address=0D +**/=0D +UINT64=0D +SpiPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SpiDevNumber (),=0D + SpiFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get XHCI controller PCIe Device Number=0D +=0D + @retval XHCI controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchXhciDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XHCI);=0D +}=0D +=0D +/**=0D + Get XHCI controller PCIe Function Number=0D +=0D + @retval XHCI controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchXhciFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XHCI);=0D +}=0D +=0D +/**=0D + Get XHCI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval XHCI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchXhciPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PchXhciDevNumber (),=0D + PchXhciFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get XDCI controller PCIe Device Number=0D +=0D + @retval XDCI controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchXdciDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_XDCI);=0D +}=0D +=0D +/**=0D + Get XDCI controller PCIe Function Number=0D +=0D + @retval XDCI controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchXdciFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_XDCI);=0D +}=0D +=0D +/**=0D + Get XDCI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval XDCI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchXdciPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PchXdciDevNumber (),=0D + PchXdciFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Return Smbus Device Number=0D +=0D + @retval Smbus Device Number=0D +**/=0D +UINT8=0D +SmbusDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SMBUS);=0D +}=0D +=0D +/**=0D + Return Smbus Function Number=0D +=0D + @retval Smbus Function Number=0D +**/=0D +UINT8=0D +SmbusFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SMBUS);=0D +}=0D +=0D +/**=0D + Get SMBUS controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval SMBUS controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +SmbusPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SmbusDevNumber (),=0D + SmbusFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Return DMA Smbus Device Number=0D +=0D + @retval DMA Smbus Device Number=0D +**/=0D +UINT8=0D +SmbusDmaDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_DMA_SMBUS);=0D +}=0D +=0D +/**=0D + Return DMA Smbus Function Number=0D +=0D + @retval DMA Smbus Function Number=0D +**/=0D +UINT8=0D +SmbusDmaFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS);=0D +}=0D +=0D +/**=0D + Get DMA SMBUS controller address that can be passed to the PCI Segment L= ibrary functions.=0D +=0D + @retval DMA SMBUS controller address in PCI Segment Library representati= on=0D +**/=0D +UINT64=0D +SmbusDmaPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SmbusDmaDevNumber (),=0D + SmbusDmaFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get SATA controller PCIe Device Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller PCIe Device Number=0D +**/=0D +UINT8=0D +SataDevNumber (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER);=0D +=0D + if (SataCtrlIndex =3D=3D 0) {=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_1);=0D + } else if (SataCtrlIndex =3D=3D 1) {=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_2);=0D + } else if (SataCtrlIndex =3D=3D 2) {=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SATA_3);=0D + } else {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get SATA controller PCIe Function Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller PCIe Function Number=0D +**/=0D +UINT8=0D +SataFuncNumber (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MAX_SATA_CONTROLLER);=0D +=0D + if (SataCtrlIndex =3D=3D 0) {=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_1);=0D + } else if (SataCtrlIndex =3D=3D 1) {=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_2);=0D + } else if (SataCtrlIndex =3D=3D 2) {=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SATA_3);=0D + } else {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get SATA controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +SataPciCfgBase (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SataDevNumber (SataCtrlIndex),=0D + SataFuncNumber (SataCtrlIndex),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get LPC controller PCIe Device Number=0D +=0D + @retval LPC controller PCIe Device Number=0D +**/=0D +UINT8=0D +LpcDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_LPC);=0D +}=0D +=0D +/**=0D + Get LPC controller PCIe Function Number=0D +=0D + @retval LPC controller PCIe Function Number=0D +**/=0D +UINT8=0D +LpcFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_LPC);=0D +}=0D +=0D +/**=0D + Returns PCH LPC device PCI base address.=0D +=0D + @retval PCH LPC PCI base address.=0D +**/=0D +UINT64=0D +LpcPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + LpcDevNumber (),=0D + LpcFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get Thermal Device PCIe Device Number=0D +=0D + @retval Thermal Device PCIe Device Number=0D +**/=0D +UINT8=0D +ThermalDevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_THERMAL);=0D +}=0D +=0D +/**=0D + Get Thermal Device PCIe Function Number=0D +=0D + @retval Thermal Device PCIe Function Number=0D +**/=0D +UINT8=0D +ThermalFuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_THERMAL);=0D +}=0D +=0D +/**=0D + Returns Thermal Device PCI base address.=0D +=0D + @retval Thermal Device PCI base address.=0D +**/=0D +UINT64=0D +ThermalPciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + ThermalDevNumber (),=0D + ThermalFuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get Serial IO I2C controller PCIe Device Number=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoI2cDevNumber (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoI2cControllersNum () <=3D I2cNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D + switch (I2cNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0);=0D + case 1:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1);=0D + case 2:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2);=0D + case 3:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3);=0D + case 4:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4);=0D + case 5:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5);=0D + case 6:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6);=0D + case 7:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO I2C controller PCIe Function Number=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoI2cFuncNumber (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoI2cControllersNum () <=3D I2cNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D + switch (I2cNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0);=0D + case 1:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1);=0D + case 2:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2);=0D + case 3:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3);=0D + case 4:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4);=0D + case 5:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5);=0D + case 6:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6);=0D + case 7:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO I2C controller address that can be passed to the PCI Segme= nt Library functions.=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller address in PCI Segment Library represen= tation=0D +**/=0D +UINT64=0D +SerialIoI2cPciCfgBase (=0D + IN UINT8 I2cNumber=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoI2cDevNumber (I2cNumber),=0D + SerialIoI2cFuncNumber (I2cNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get Serial IO SPI controller PCIe Device Number=0D +=0D + @param[in] I2cNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoSpiDevNumber (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoSpiControllersNum () <=3D SpiNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +=0D + switch (SpiNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0);=0D + case 1:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1);=0D + case 2:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2);=0D + case 3:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3);=0D + case 4:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4);=0D + case 5:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5);=0D + case 6:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO SPI controller PCIe Function Number=0D +=0D + @param[in] SpiNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoSpiFuncNumber (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoSpiControllersNum () <=3D SpiNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +=0D + switch (SpiNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0);=0D + case 1:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1);=0D + case 2:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2);=0D + case 3:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3);=0D + case 4:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4);=0D + case 5:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5);=0D + case 6:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO SPI controller address that can be passed to the PCI Segme= nt Library functions.=0D +=0D + @param[in] SpiNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller address in PCI Segment Library represen= tation=0D +**/=0D +UINT64=0D +SerialIoSpiPciCfgBase (=0D + IN UINT8 SpiNumber=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoSpiDevNumber (SpiNumber),=0D + SerialIoSpiFuncNumber (SpiNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get Serial IO UART controller PCIe Device Number=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoUartDevNumber (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoUartControllersNum () <=3D UartNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D + switch (UartNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0);=0D + case 1:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1);=0D + case 2:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2);=0D + case 3:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3);=0D + case 4:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4);=0D + case 5:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5);=0D + case 6:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO UART controller PCIe Function Number=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoUartFuncNumber (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + if (GetPchMaxSerialIoUartControllersNum () <=3D UartNumber) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D + switch (UartNumber) {=0D + case 0:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0);=0D + case 1:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1);=0D + case 2:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2);=0D + case 3:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3);=0D + case 4:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4);=0D + case 5:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5);=0D + case 6:=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6);=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get Serial IO UART controller address that can be passed to the PCI Segm= ent Library functions.=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller address in PCI Segment Library represe= ntation=0D +**/=0D +UINT64=0D +SerialIoUartPciCfgBase (=0D + IN UINT8 UartNumber=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + SerialIoUartDevNumber (UartNumber),=0D + SerialIoUartFuncNumber (UartNumber),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get PCH PCIe controller PCIe Device Number=0D +=0D + @param[in] RpIndex Root port physical number. (0-based)=0D +=0D + @retval PCH PCIe controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchPcieRpDevNumber (=0D + IN UINTN RpIndex=0D + )=0D +{=0D + if (RpIndex >=3D GetPchMaxPciePortNum ()) {=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D + switch (RpIndex) {=0D + case 0:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1);=0D + case 1:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2);=0D + case 2:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3);=0D + case 3:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4);=0D + case 4:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5);=0D + case 5:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6);=0D + case 6:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7);=0D + case 7:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8);=0D + case 8:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9);=0D + case 9:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10);=0D + case 10:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11);=0D + case 11:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12);=0D + case 12:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13);=0D + case 13:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14);=0D + case 14:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15);=0D + case 15:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16);=0D + case 16:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17);=0D + case 17:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18);=0D + case 18:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19);=0D + case 19:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20);=0D + case 20:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21);=0D + case 21:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22);=0D + case 22:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23);=0D + case 23:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24);=0D + case 24:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25);=0D + case 25:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26);=0D + case 26:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27);=0D + case 27:=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28);=0D +=0D + default:=0D + ASSERT (FALSE);=0D + return 0xFF;=0D + }=0D +}=0D +=0D +/**=0D + Get PCH PCIe controller PCIe Function Number=0D + Note:=0D + For Client PCH generations Function Number can be various=0D + depending on "Root Port Function Swapping". For such cases=0D + Function Number MUST be obtain from proper register.=0D + For Server PCHs we have no "Root Port Function Swapping"=0D + and we can return fixed Function Number.=0D + To address this difference in this, PCH generation independent,=0D + library we should call specific function in PchPcieRpLib.=0D +=0D + @param[in] RpIndex Root port physical number. (0-based)=0D +=0D + @retval PCH PCIe controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchPcieRpFuncNumber (=0D + IN UINTN RpIndex=0D + )=0D +{=0D + UINTN Device;=0D + UINTN Function;=0D +=0D + GetPchPcieRpDevFun (RpIndex, &Device, &Function);=0D +=0D + return (UINT8)Function;=0D +}=0D +=0D +/**=0D + Get PCH PCIe controller address that can be passed to the PCI Segment Li= brary functions.=0D +=0D + @param[in] RpIndex PCH PCIe Root Port physical number. (0-based)= =0D +=0D + @retval PCH PCIe controller address in PCI Segment Library representatio= n=0D +**/=0D +UINT64=0D +PchPcieRpPciCfgBase (=0D + IN UINT32 RpIndex=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PchPcieRpDevNumber (RpIndex),=0D + PchPcieRpFuncNumber (RpIndex),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get HECI1 PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +PchHeci1DevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI1);=0D +}=0D +=0D +/**=0D + Get HECI1 PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +PchHeci1FuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI1);=0D +}=0D +=0D +/**=0D + Get HECI1 controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval HECI1 controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchHeci1PciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PchHeci1DevNumber (),=0D + PchHeci1FuncNumber (),=0D + 0=0D + );=0D +}=0D +=0D +/**=0D + Get HECI3 PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +PchHeci3DevNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_DEVICE_NUMBER_PCH_HECI3);=0D +}=0D +=0D +/**=0D + Get HECI3 PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +PchHeci3FuncNumber (=0D + VOID=0D + )=0D +{=0D + return CheckAndReturn (PCI_FUNCTION_NUMBER_PCH_HECI3);=0D +}=0D +=0D +/**=0D + Get HECI3 controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval HECI3 controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchHeci3PciCfgBase (=0D + VOID=0D + )=0D +{=0D + return PCI_SEGMENT_LIB_ADDRESS (=0D + DEFAULT_PCI_SEGMENT_NUMBER_PCH,=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + PchHeci3DevNumber (),=0D + PchHeci3FuncNumber (),=0D + 0=0D + );=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemL= ib/BaseResetSystemLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/Bas= eResetSystemLib/BaseResetSystemLib.c new file mode 100644 index 0000000000..2ede8e0021 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/Base= ResetSystemLib.c @@ -0,0 +1,158 @@ +/** @file=0D + System reset library services.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT16 mBaseResetSystemABase;=0D +=0D +/**=0D + Calling this function causes a system-wide reset. This sets=0D + all circuitry within the system to its initial state. This type of reset= =0D + is asynchronous to system operation and operates without regard to=0D + cycle boundaries.=0D +=0D + System reset should not return, if it returns, it means the system does= =0D + not support cold reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetCold (=0D + VOID=0D + )=0D +{=0D + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);=0D +}=0D +=0D +/**=0D + Calling this function causes a system-wide initialization. The processor= s=0D + are set to their initial state, and pending cycles are not corrupted.=0D +=0D + System reset should not return, if it returns, it means the system does= =0D + not support warm reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetWarm (=0D + VOID=0D + )=0D +{=0D + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_HARDRESET);=0D +}=0D +=0D +/**=0D + Calling this function causes the system to enter a power state equivalen= t=0D + to the ACPI G2/S5 or G3 states.=0D +=0D + System shutdown should not return, if it returns, it means the system do= es=0D + not support shut down reset.=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetShutdown (=0D + VOID=0D + )=0D +{=0D + UINT16 ABase;=0D + UINT32 Data32;=0D +=0D + ABase =3D mBaseResetSystemABase;=0D + if (ABase =3D=3D 0) {=0D + ABase =3D PmcGetAcpiBase ();=0D + }=0D + ///=0D + /// Firstly, GPE0_EN should be disabled to avoid any GPI waking up the s= ystem from S5=0D + ///=0D + IoWrite32 (ABase + R_ACPI_IO_GPE0_EN_127_96, 0);=0D +=0D + ///=0D + /// Secondly, PwrSts register must be cleared=0D + ///=0D + /// Write a "1" to bit[8] of power button status register at=0D + /// (PM_BASE + PM1_STS_OFFSET) to clear this bit=0D + ///=0D + IoWrite16 (ABase + R_ACPI_IO_PM1_STS, B_ACPI_IO_PM1_STS_PWRBTN);=0D +=0D + ///=0D + /// Finally, transform system into S5 sleep state=0D + ///=0D + Data32 =3D IoRead32 (ABase + R_ACPI_IO_PM1_CNT);=0D +=0D + Data32 =3D (UINT32) ((Data32 &~(B_ACPI_IO_PM1_CNT_SLP_TYP + B_ACPI_IO_PM= 1_CNT_SLP_EN)) | V_ACPI_IO_PM1_CNT_S5);=0D +=0D + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32);=0D +=0D + Data32 =3D Data32 | B_ACPI_IO_PM1_CNT_SLP_EN;=0D +=0D + IoWrite32 (ABase + R_ACPI_IO_PM1_CNT, Data32);=0D +=0D + return;=0D +}=0D +=0D +/**=0D + Calling this function causes the system to enter a power state for platf= orm specific.=0D +=0D + @param[in] DataSize The size of ResetData in bytes.=0D + @param[in] ResetData Optional element used to introduce a pla= tform specific reset.=0D + The exact type of the reset is defined b= y the EFI_GUID that follows=0D + the Null-terminated Unicode string.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +ResetPlatformSpecific (=0D + IN UINTN DataSize,=0D + IN VOID *ResetData OPTIONAL=0D + )=0D +{=0D + IoWrite8 (R_PCH_IO_RST_CNT, V_PCH_IO_RST_CNT_FULLRESET);=0D +}=0D +=0D +/**=0D + Calling this function causes the system to enter a power state for capsu= le update.=0D +=0D + Reset update should not return, if it returns, it means the system does= =0D + not support capsule update.=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +EnterS3WithImmediateWake (=0D + VOID=0D + )=0D +{=0D + //=0D + // In case there are pending capsules to process, need to flush the cach= e.=0D + //=0D + AsmWbinvd ();=0D +=0D + ResetWarm ();=0D + ASSERT (FALSE);=0D +}=0D +=0D +/**=0D + The library constructuor.=0D +=0D + The function does the necessary initialization work for this library ins= tance.=0D +=0D + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +BaseResetSystemLibConstructor (=0D + VOID=0D + )=0D +{=0D + mBaseResetSystemABase =3D PmcGetAcpiBase ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemL= ib/BaseResetSystemLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/B= aseResetSystemLib/BaseResetSystemLib.inf new file mode 100644 index 0000000000..a4f805035a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/BaseResetSystemLib/Base= ResetSystemLib.inf @@ -0,0 +1,38 @@ +## @file=0D +# Component description file for Intel Ich7 Reset System Library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D BaseResetSystemLib=0D +FILE_GUID =3D D4FF05AA-3C7D-4B8A-A1EE-AA5EFA0B1732=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +UEFI_SPECIFICATION_VERSION =3D 2.00=0D +LIBRARY_CLASS =3D ResetSystemLib=0D +CONSTRUCTOR =3D BaseResetSystemLibConstructor=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF=0D +#=0D +=0D +[LibraryClasses]=0D +IoLib=0D +BaseLib=0D +DebugLib=0D +PmcLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +BaseResetSystemLib.c=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/= DxePchPolicyLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPol= icyLib/DxePchPolicyLib.c new file mode 100644 index 0000000000..90aea8f420 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchP= olicyLib.c @@ -0,0 +1,198 @@ +/** @file=0D + This file provide services for DXE phase policy default initialization=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Load DXE Config block default for eMMC=0D +=0D + @param[in] ConfigBlockPointer Pointer to config block=0D +**/=0D +VOID=0D +LoadEmmcDxeConfigDefault (=0D + IN VOID *ConfigBlockPointer=0D + )=0D +{=0D + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig;=0D + EmmcDxeConfig =3D ConfigBlockPointer;=0D +=0D + DEBUG ((DEBUG_INFO, "EmmcDxeConfig->Header.GuidHob.Name =3D %g\n", &Emmc= DxeConfig->Header.GuidHob.Name));=0D + DEBUG ((DEBUG_INFO, "EmmcDxeConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", EmmcDxeConfig->Header.GuidHob.Header.HobLength));=0D +=0D + EmmcDxeConfig->DriverStrength =3D DriverStrength40Ohm;=0D +}=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mPchDxeIpBlocks [] = =3D {=0D + {&gEmmcDxeConfigGuid, sizeof (SCS_EMMC_DXE_CONFIG), SCS_EMMC_DXE_CONF= IG_REVISION, LoadEmmcDxeConfigDefault}=0D +};=0D +=0D +/**=0D + Print SCS_EMMC_DXE_CONFIG.=0D +=0D + @param[in] EmmcDxeConfig Pointer to a SCS_EMMC_DXE_CONFIG that p= rovides the eMMC settings=0D +**/=0D +VOID=0D +PchPrintEmmcDxeConfig (=0D + IN CONST SCS_EMMC_DXE_CONFIG *EmmcDxeConfig=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "------------------ PCH eMMC DXE Config ------------= ------\n"));=0D + DEBUG ((DEBUG_INFO, " DriverStrength : %d\n", EmmcDxeConfig->DriverStren= gth));=0D + DEBUG ((DEBUG_INFO, " EnableSoftwareHs400Tuning: %d\n", EmmcDxeConfig->E= nableSoftwareHs400Tuning));=0D + DEBUG ((DEBUG_INFO, " TuningLba : %X\n", EmmcDxeConfig->TuningLba));=0D + DEBUG ((DEBUG_INFO, " Previous tuning success : %d\n", EmmcDxeConfig->Pr= eviousTuningResults.TuningSuccessful));=0D + if (EmmcDxeConfig->PreviousTuningResults.TuningSuccessful) {=0D + DEBUG ((DEBUG_INFO, " Hs400 Rx DLL value : %X\n", EmmcDxeConfig->Prev= iousTuningResults.Hs400RxValue));=0D + DEBUG ((DEBUG_INFO, " Hs400 Tx DLL value : %X\n", EmmcDxeConfig->Prev= iousTuningResults.Hs400TxValue));=0D + }=0D +}=0D +=0D +/**=0D + This function prints the PCH DXE phase policy.=0D +=0D + @param[in] PchPolicy - PCH DXE Policy protocol=0D +**/=0D +VOID=0D +PchPrintPolicyProtocol (=0D + IN PCH_POLICY_PROTOCOL *PchPolicy=0D + )=0D +{=0D + DEBUG_CODE_BEGIN();=0D + EFI_STATUS Status;=0D + SCS_EMMC_DXE_CONFIG *EmmcDxeConfig;=0D +=0D + //=0D + // Get requisite IP Config Blocks which needs to be used here=0D + //=0D + Status =3D GetConfigBlock ((VOID *) PchPolicy, &gEmmcDxeConfigGuid, (VOI= D *)&EmmcDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print Sta= rt ------------------------\n"));=0D + DEBUG ((DEBUG_INFO, " Revision : %x\n", PchPolicy->TableHeader.Header.Re= vision));=0D +=0D + PchPrintEmmcDxeConfig (EmmcDxeConfig);=0D + GpioDxePrintConfig (PchPolicy);=0D + HdaDxePrintConfig (PchPolicy);=0D + PchPcieRpDxePrintConfig (PchPolicy);=0D +=0D + DEBUG ((DEBUG_INFO, "------------------------ PCH Policy (DXE) Print End= --------------------------\n"));=0D + DEBUG_CODE_END();=0D +}=0D +=0D +/**=0D + CreatePchDxeConfigBlocks generates the config blocksg of PCH DXE Policy.= =0D + It allocates and zero out buffer, and fills in the Intel default setting= s.=0D +=0D + @param[out] PchPolicy The pointer to get PCH DXE Protoco= l instance=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CreatePchDxeConfigBlocks (=0D + IN OUT PCH_POLICY_PROTOCOL **DxePchPolicy=0D + )=0D +{=0D + UINT16 TotalBlockSize;=0D + EFI_STATUS Status;=0D + PCH_POLICY_PROTOCOL *PchPolicyInit;=0D + UINT16 RequiredSize;=0D +=0D +=0D + DEBUG ((DEBUG_INFO, "PCH Create Dxe Config Blocks\n"));=0D +=0D + PchPolicyInit =3D NULL;=0D +=0D + TotalBlockSize =3D GetComponentConfigBlockTotalSize (&mPchDxeIpBlocks[0]= , sizeof (mPchDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));=0D + TotalBlockSize +=3D GpioDxeGetConfigBlockTotalSize();=0D + TotalBlockSize +=3D HdaDxeGetConfigBlockTotalSize();=0D + TotalBlockSize +=3D PchPcieRpDxeGetConfigBlockTotalSize();=0D +=0D + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize));=0D +=0D + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;=0D +=0D + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &PchPolicyInit= );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // General initialization=0D + //=0D + PchPolicyInit->TableHeader.Header.Revision =3D PCH_POLICY_PROTOCOL_REVIS= ION;=0D + //=0D + // Add config blocks.=0D + //=0D + Status =3D AddComponentConfigBlocks ((VOID *) PchPolicyInit, &mPchDxeIp= Blocks[0], sizeof (mPchDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GpioDxeAddConfigBlock ((VOID *) PchPolicyInit);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D HdaDxeAddConfigBlock ((VOID *) PchPolicyInit);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D PchPcieRpDxeAddConfigBlock ((VOID *) PchPolicyInit);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Assignment for returning SaInitPolicy config block base address=0D + //=0D + *DxePchPolicy =3D PchPolicyInit;=0D + return Status;=0D +}=0D +=0D +/**=0D + PchInstallPolicyProtocol installs PCH Policy.=0D + While installed, RC assumes the Policy is ready and finalized. So please= update and override=0D + any setting before calling this function.=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D + @param[in] SaPolicy The pointer to SA Policy Protocol = instance=0D +=0D + @retval EFI_SUCCESS The policy is installed.=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PchInstallPolicyProtocol (=0D + IN EFI_HANDLE ImageHandle,=0D + IN PCH_POLICY_PROTOCOL *PchPolicy=0D + )=0D +{=0D +=0D + EFI_STATUS Status;=0D +=0D + ///=0D + /// Print PCH DXE Policy=0D + ///=0D + PchPrintPolicyProtocol (PchPolicy);=0D +=0D + ///=0D + /// Install protocol to to allow access to this Policy.=0D + ///=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &ImageHandle,=0D + &gPchPolicyProtocolGuid,=0D + PchPolicy,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/= DxePchPolicyLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchP= olicyLib/DxePchPolicyLib.inf new file mode 100644 index 0000000000..50e5cdacfd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/DxePchPolicyLib/DxePchP= olicyLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# Component description file for the PeiPchPolicy library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxePchPolicyLib=0D +FILE_GUID =3D E2179D04-7026-48A5-9475-309CEA2F21A3=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D DxePchPolicyLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseMemoryLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +ConfigBlockLib=0D +SiConfigBlockLib=0D +PchInfoLib=0D +DxeGpioPolicyLib=0D +DxeHdaPolicyLib=0D +DxePchPcieRpPolicyLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +DxePchPolicyLib.c=0D +=0D +=0D +[Guids]=0D +gEmmcDxeConfigGuid=0D +=0D +[Protocols]=0D +gPchPolicyProtocolGuid ## PRODUCES=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycl= eDecodingLib/PchCycleDecodingLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/= Library/PeiDxeSmmPchCycleDecodingLib/PchCycleDecodingLib.c new file mode 100644 index 0000000000..0927cd1ced --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodi= ngLib/PchCycleDecodingLib.c @@ -0,0 +1,587 @@ +/** @file=0D + PCH cycle decoding configuration and query library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +typedef enum {=0D + SlaveLpcEspiCS0,=0D + SlaveEspiCS1,=0D + SlaveId_Max=0D +} SLAVE_ID_INDEX;=0D +=0D +/**=0D + Get PCH TCO base address.=0D +=0D + @param[out] Address Address of TCO base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid pointer passed.=0D +**/=0D +EFI_STATUS=0D +PchTcoBaseGet (=0D + OUT UINT16 *Address=0D + )=0D +{=0D + if (Address =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "PchTcoBaseGet Error. Invalid pointer.\n"));=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + //=0D + // Read "TCO Base Address" from DMI=0D + // Don't read TCO base address from SMBUS PCI register since SMBUS might= be disabled.=0D + //=0D + *Address =3D PchDmiGetTcoBase ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI and eSPI CS1# generic IO range decoding.=0D +=0D + Steps of programming generic IO range:=0D + 1. Program LPC/eSPI PCI Offset 84h ~ 93h (LPC, eSPI CS0#) or A4h (eSPI C= S1#) of Mask, Address, and Enable.=0D + 2. Program LPC/eSPI Generic IO Range in DMI=0D +=0D + @param[in] Address Address for generic IO range decod= ing.=0D + @param[in] Length Length of generic IO range.=0D + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_OUT_OF_RESOURCES No more generic range available.=0D + @retval EFI_UNSUPPORTED DMI configuration is locked,=0D + GenIO range conflicting with other= eSPI CS=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +LpcEspiGenIoRangeSetHelper (=0D + IN UINT32 Address,=0D + IN UINT32 Length,=0D + IN SLAVE_ID_INDEX SlaveId=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI generic IO range.=0D + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2=0D + and less than or equal to 256. Moreover, the address must be length alig= ned.=0D + This function basically checks the address and length, which should not = overlap with all other generic ranges.=0D + If no more generic range register available, it returns out of resource = error.=0D + This cycle decoding is also required on DMI side=0D + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB=0D + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges:=0D + 0x00-0x1F,=0D + 0x44-0x4B,=0D + 0x54-0x5F,=0D + 0x68-0x6F,=0D + 0x80-0x8F,=0D + 0xC0-0xFF=0D + Steps of programming generic IO range:=0D + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.=0D + 2. Program LPC/eSPI Generic IO Range in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_OUT_OF_RESOURCES No more generic range available.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcGenIoRangeSet (=0D + IN UINT16 Address,=0D + IN UINTN Length=0D + )=0D +{=0D + return LpcEspiGenIoRangeSetHelper ((UINT32)Address, (UINT32)Length, Slav= eLpcEspiCS0);=0D +}=0D +=0D +=0D +/**=0D + Set PCH LPC/eSPI and eSPI CS1# memory range decoding.=0D + This cycle decoding is required to be set on DMI side=0D + Programming steps:=0D + 1. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 0] to [0] to disable memory decoding first before changing base address.=0D + 2. Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 31:16, 0] to [Address, 1].=0D + 3. Program LPC/eSPI Memory Range in DMI=0D +=0D + @param[in] Address Address for memory for decoding.=0D + @param[in] RangeIndex Slave ID (refer to SLAVE_ID_INDEX)= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D +**/=0D +STATIC=0D +EFI_STATUS=0D +LpcEspiMemRangeSetHelper (=0D + IN UINT32 Address,=0D + IN SLAVE_ID_INDEX SlaveId=0D + )=0D +{=0D + UINT64 LpcBase;=0D + EFI_STATUS Status;=0D + UINT32 GenMemReg;=0D + UINT32 MemRangeAddr;=0D +=0D + if (((Address & (~B_LPC_CFG_LGMR_MA)) !=3D 0) || (SlaveId >=3D SlaveId_M= ax)) {=0D + DEBUG ((DEBUG_ERROR, "%a Error. Invalid Address: %x or invalid SlaveId= \n", __FUNCTION__, Address));=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + LpcBase =3D LpcPciCfgBase ();=0D +=0D + MemRangeAddr =3D ~Address;=0D + if (SlaveId =3D=3D SlaveEspiCS1) {=0D + GenMemReg =3D R_ESPI_CFG_CS1GMR1;=0D + // Memory Range already decoded for LPC/eSPI?=0D + Status =3D PchLpcMemRangeGet (&MemRangeAddr);=0D + if (MemRangeAddr !=3D Address) {=0D + Status =3D PchDmiSetEspiCs1MemRange (Address);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D + }=0D + } else {=0D + GenMemReg =3D R_LPC_CFG_LGMR;=0D + // Memory Range already decoded for eSPI CS1?=0D + Status =3D PchEspiCs1MemRangeGet (&MemRangeAddr);=0D + if (MemRangeAddr !=3D Address) {=0D + Status =3D PchDmiSetLpcMemRange (Address);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D + }=0D + }=0D +=0D + //=0D + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 0] to [0] to disable memory decoding first before changing base address.=0D + //=0D + PciSegmentAnd32 (=0D + LpcBase + GenMemReg,=0D + (UINT32) ~B_LPC_CFG_LGMR_LMRD_EN=0D + );=0D + //=0D + // Program LPC/eSPI PCI Offset 98h (LPC, eSPI CS0#) or A8h (eSPI CS1#) [= 31:16, 0] to [Address, 1].=0D + //=0D + PciSegmentWrite32 (=0D + LpcBase + GenMemReg,=0D + (Address | B_LPC_CFG_LGMR_LMRD_EN)=0D + );=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI memory range decoding.=0D + This cycle decoding is required to be set on DMI side=0D + Programming steps:=0D + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding firs= t before changing base address.=0D + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].=0D + 3. Program LPC Memory Range in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_OUT_OF_RESOURCES No more generic range available.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcMemRangeSet (=0D + IN UINT32 Address=0D + )=0D +{=0D + return LpcEspiMemRangeSetHelper (Address, SlaveLpcEspiCS0);=0D +}=0D +=0D +/**=0D + Set PCH eSPI CS1# memory range decoding.=0D + This cycle decoding is required to be set on DMI side=0D + Programming steps:=0D + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory = decoding first before changing base address.=0D + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].=0D + 3. Program eSPI Memory Range in DMI=0D +=0D + @param[in] Address Address for memory for decoding.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_UNSUPPORTED eSPI secondary slave not supported= =0D +**/=0D +EFI_STATUS=0D +PchEspiCs1MemRangeSet (=0D + IN UINT32 Address=0D + )=0D +{=0D + if (!IsEspiSecondSlaveSupported ()) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + return LpcEspiMemRangeSetHelper (Address, SlaveEspiCS1);=0D +}=0D +=0D +/**=0D + Get PCH LPC/eSPI and eSPI CS1# memory range decoding address.=0D +=0D + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)= =0D + @param[out] Address Address of LPC/eSPI or eSPI CS1# m= emory decoding base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address passed.=0D + @retval EFI_UNSUPPORTED eSPI secondary slave not supported= =0D +**/=0D +STATIC=0D +EFI_STATUS=0D +LpcEspiMemRangeGetHelper (=0D + IN SLAVE_ID_INDEX SlaveId,=0D + OUT UINT32 *Address=0D + )=0D +{=0D + UINT32 GenMemReg;=0D +=0D + if ((Address =3D=3D NULL) || (SlaveId >=3D SlaveId_Max)) {=0D + DEBUG ((DEBUG_ERROR, "%a Error. Invalid pointer or SlaveId.\n", __FUNC= TION__));=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + if (SlaveId =3D=3D SlaveEspiCS1) {=0D + GenMemReg =3D R_ESPI_CFG_CS1GMR1;=0D + } else {=0D + GenMemReg =3D R_LPC_CFG_LGMR;=0D + }=0D + *Address =3D PciSegmentRead32 (LpcPciCfgBase () + GenMemReg) & B_LPC_CFG= _LGMR_MA;=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Get PCH LPC/eSPI memory range decoding address.=0D +=0D + @param[out] Address Address of LPC/eSPI memory decodin= g base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address passed.=0D +**/=0D +EFI_STATUS=0D +PchLpcMemRangeGet (=0D + OUT UINT32 *Address=0D + )=0D +{=0D + return LpcEspiMemRangeGetHelper (SlaveLpcEspiCS0, Address);=0D +}=0D +=0D +/**=0D + Get PCH eSPI CS1# memory range decoding address.=0D +=0D + @param[out] Address Address of eSPI CS1# memory decodi= ng base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address passed.=0D + @retval EFI_UNSUPPORTED eSPI secondary slave not supported= =0D +**/=0D +EFI_STATUS=0D +PchEspiCs1MemRangeGet (=0D + OUT UINT32 *Address=0D + )=0D +{=0D + if (!IsEspiSecondSlaveSupported ()) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + return LpcEspiMemRangeGetHelper (SlaveEspiCS1, Address);=0D +}=0D +=0D +/**=0D + Set PCH BIOS range deocding.=0D + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly.=0D + Please check EDS for detail of BiosDecodeEnable bit definition.=0D + bit 15: F8-FF Enable=0D + bit 14: F0-F8 Enable=0D + bit 13: E8-EF Enable=0D + bit 12: E0-E8 Enable=0D + bit 11: D8-DF Enable=0D + bit 10: D0-D7 Enable=0D + bit 9: C8-CF Enable=0D + bit 8: C0-C7 Enable=0D + bit 7: Legacy F Segment Enable=0D + bit 6: Legacy E Segment Enable=0D + bit 5: Reserved=0D + bit 4: Reserved=0D + bit 3: 70-7F Enable=0D + bit 2: 60-6F Enable=0D + bit 1: 50-5F Enable=0D + bit 0: 40-4F Enable=0D + This cycle decoding is also required in DMI=0D + Programming steps:=0D + 1. if GCS.BBS is 0 (SPI), program SPI offset D8h to BiosDecodeEnable.=0D + if GCS.BBS is 1 (LPC/eSPi), program LPC offset D8h to BiosDecodeEnabl= e.=0D + 2. program LPC BIOS Decode Enable in DMI=0D +=0D + @param[in] BiosDecodeEnable Bios decode enable setting.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchBiosDecodeEnableSet (=0D + IN UINT16 BiosDecodeEnable=0D + )=0D +{=0D + UINT64 BaseAddr;=0D + EFI_STATUS Status;=0D +=0D + Status =3D PchDmiSetBiosDecodeEnable (BiosDecodeEnable);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D +=0D + //=0D + // Check Boot BIOS Strap in DMI=0D + //=0D + if (PchDmiIsBootBiosStrapSetForSpi ()) {=0D + BaseAddr =3D SpiPciCfgBase ();=0D + //=0D + // If SPI, Program SPI offset D8h to BiosDecodeEnable.=0D + //=0D + PciSegmentWrite16 (BaseAddr + R_SPI_CFG_BDE, BiosDecodeEnable);=0D + } else {=0D + BaseAddr =3D LpcPciCfgBase ();=0D + //=0D + // If LPC/eSPi, program LPC offset D8h to BiosDecodeEnable.=0D + //=0D + PciSegmentWrite16 (BaseAddr + R_LPC_CFG_BDE, BiosDecodeEnable);=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI IO decode ranges.=0D + Program LPC/eSPI I/O Decode Ranges in DMI to the same value programmed i= n LPC/eSPI PCI offset 80h.=0D + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.= =0D + Bit 12: FDD range=0D + Bit 9:8: LPT range=0D + Bit 6:4: ComB range=0D + Bit 2:0: ComA range=0D +=0D + @param[in] LpcIoDecodeRanges LPC/eSPI IO decode ranges bit sett= ings.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcIoDecodeRangesSet (=0D + IN UINT16 LpcIoDecodeRanges=0D + )=0D +{=0D + UINT64 LpcBaseAddr;=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Note: Inside this function, don't use debug print since it's could us= ed before debug print ready.=0D + //=0D +=0D + LpcBaseAddr =3D LpcPciCfgBase ();=0D +=0D + //=0D + // check if setting is identical=0D + //=0D + if (LpcIoDecodeRanges =3D=3D PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_I= OD)) {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + Status =3D PchDmiSetLpcIoDecodeRanges (LpcIoDecodeRanges);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D +=0D + //=0D + // program LPC/eSPI PCI offset 80h.=0D + //=0D + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOD, LpcIoDecodeRanges);=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Set PCH LPC/eSPI and eSPI CS1# IO enable decoding.=0D + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h (LPC, eSPI CS0#) or A0h (eSPI CS1#).=0D + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field=0D + in LPC/eSPI PCI offset 82h[13:10] or A0h[13:10] is always forwarded by D= MI to subtractive agent for handling.=0D + Please check EDS for detail of Lpc/eSPI IO decode ranges bit definition.= =0D +=0D + @param[in] IoEnableDecoding LPC/eSPI IO enable decoding bit se= ttings.=0D + @param[in] SlaveId Slave ID (refer to SLAVE_ID_INDEX)= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMI configuration is locked=0D +**/=0D +EFI_STATUS=0D +LpcEspiIoEnableDecodingSetHelper (=0D + IN UINT16 IoEnableDecoding,=0D + IN SLAVE_ID_INDEX SlaveId=0D + )=0D +{=0D + UINT64 LpcBaseAddr;=0D + EFI_STATUS Status;=0D + UINT16 Cs1IoEnableDecodingOrg;=0D + UINT16 Cs0IoEnableDecodingOrg;=0D + UINT16 IoEnableDecodingMerged;=0D +=0D + LpcBaseAddr =3D LpcPciCfgBase ();=0D +=0D + Cs0IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + R_LPC_CFG_IOE= );=0D +=0D + if (IsEspiSecondSlaveSupported ()) {=0D + Cs1IoEnableDecodingOrg =3D PciSegmentRead16 (LpcBaseAddr + R_ESPI_CFG_= CS1IORE);=0D + } else {=0D + Cs1IoEnableDecodingOrg =3D 0;=0D + }=0D +=0D + if (SlaveId =3D=3D SlaveEspiCS1) {=0D + if (IoEnableDecoding =3D=3D Cs1IoEnableDecodingOrg) {=0D + return EFI_SUCCESS;=0D + } else {=0D + IoEnableDecodingMerged =3D (Cs0IoEnableDecodingOrg | IoEnableDecodin= g);=0D + }=0D + } else {=0D + if ((IoEnableDecoding | Cs1IoEnableDecodingOrg) =3D=3D Cs0IoEnableDeco= dingOrg) {=0D + return EFI_SUCCESS;=0D + } else {=0D + IoEnableDecodingMerged =3D (Cs1IoEnableDecodingOrg | IoEnableDecodin= g);=0D + }=0D + }=0D +=0D + Status =3D PchDmiSetLpcIoEnable (IoEnableDecodingMerged);=0D + if (EFI_ERROR (Status)) {=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D +=0D + //=0D + // program PCI offset 82h for LPC/eSPI.=0D + //=0D + PciSegmentWrite16 (LpcBaseAddr + R_LPC_CFG_IOE, IoEnableDecodingMerged);= =0D +=0D + if (SlaveId =3D=3D SlaveEspiCS1) {=0D + //=0D + // For eSPI CS1# device program eSPI PCI offset A0h.=0D + //=0D + PciSegmentWrite16 (LpcBaseAddr + R_ESPI_CFG_CS1IORE, IoEnableDecoding)= ;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Set PCH LPC and eSPI CS0# IO enable decoding.=0D + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h.=0D + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field=0D + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling.=0D + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.= =0D +=0D + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setting= s.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcIoEnableDecodingSet (=0D + IN UINT16 LpcIoEnableDecoding=0D + )=0D +{=0D + return LpcEspiIoEnableDecodingSetHelper (LpcIoEnableDecoding, SlaveLpcEs= piCS0);=0D +}=0D +=0D +/**=0D + Set PCH eSPI CS1# IO enable decoding.=0D + Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0= h (eSPI CS1#).=0D + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field=0D + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive = agent for handling.=0D + Please check EDS for detail of eSPI IO decode ranges bit definition.=0D +=0D + @param[in] IoEnableDecoding eSPI IO enable decoding bit settin= gs.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMI configuration is locked=0D +**/=0D +EFI_STATUS=0D +PchEspiCs1IoEnableDecodingSet (=0D + IN UINT16 IoEnableDecoding=0D + )=0D +{=0D + if (!IsEspiSecondSlaveSupported ()) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + return LpcEspiIoEnableDecodingSetHelper (IoEnableDecoding, SlaveEspiCS1)= ;=0D +}=0D +=0D +=0D +/**=0D + Get IO APIC regsiters base address.=0D +=0D + @param[out] IoApicBase Buffer of IO APIC regsiter address= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D +**/=0D +EFI_STATUS=0D +PchIoApicBaseGet (=0D + OUT UINT32 *IoApicBase=0D + )=0D +{=0D + *IoApicBase =3D PcdGet32 (PcdSiIoApicBaseAddress);=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Get HPET base address.=0D +=0D + @param[out] HpetBase Buffer of HPET base address=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid offset passed.=0D +**/=0D +EFI_STATUS=0D +PchHpetBaseGet (=0D + OUT UINT32 *HpetBase=0D + )=0D +{=0D + if (HpetBase =3D=3D NULL) {=0D + DEBUG ((DEBUG_ERROR, "PchHpetBaseGet Error. Invalid pointer.\n"));=0D + ASSERT (FALSE);=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + *HpetBase =3D PcdGet32 (PcdSiHpetBaseAddress);=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycl= eDecodingLib/PeiDxeSmmPchCycleDecodingLib.inf b/Silicon/Intel/TigerlakeSili= conPkg/Pch/Library/PeiDxeSmmPchCycleDecodingLib/PeiDxeSmmPchCycleDecodingLi= b.inf new file mode 100644 index 0000000000..ea6b434f29 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchCycleDecodi= ngLib/PeiDxeSmmPchCycleDecodingLib.inf @@ -0,0 +1,42 @@ +## @file=0D +# PCH cycle decoding Lib.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchCycleDecodingLib=0D +FILE_GUID =3D 676C749F-9CD1-46B7-BAFD-4B1BC36B4C8E=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PchCycleDecodingLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PciSegmentLib=0D +PchInfoLib=0D +PchPcrLib=0D +PchDmiLib=0D +EspiLib=0D +PchPciBdfLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +PchCycleDecodingLib.c=0D +=0D +[Pcd]=0D +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress ## CONSUMES=0D +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress ## CONSUMES=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfo= Lib/PchInfoLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmP= chInfoLib/PchInfoLib.c new file mode 100644 index 0000000000..df8a23d5a3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pch= InfoLib.c @@ -0,0 +1,127 @@ +/** @file=0D + Pch information library.=0D +=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "PchInfoLibPrivate.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Return Pch Series=0D +=0D + @retval PCH_SERIES Pch Series=0D +**/=0D +PCH_SERIES=0D +PchSeries (=0D + VOID=0D + )=0D +{=0D + return PCH_LP;=0D +}=0D +=0D +/**=0D + Return Pch stepping type=0D +=0D + @retval PCH_STEPPING Pch stepping type=0D +**/=0D +PCH_STEPPING=0D +PchStepping (=0D + VOID=0D + )=0D +{=0D + return 0;=0D +}=0D +=0D +/**=0D + Check if this is TGL PCH generation=0D +=0D + @retval TRUE It's TGL PCH=0D + @retval FALSE It's not TGL PCH=0D +**/=0D +BOOLEAN=0D +IsTglPch (=0D + VOID=0D + )=0D +{=0D + return (PchGeneration () =3D=3D TGL_PCH);=0D +}=0D +=0D +/**=0D + Get PCH stepping ASCII string.=0D + Function determines major and minor stepping versions and writes them in= to a buffer.=0D + The return string is zero terminated=0D +=0D + @param [out] Buffer Output buffer of string=0D + @param [in] BufferSize Buffer size.=0D + Must not be less then PCH_STEPPING= _STR_LENGTH_MAX=0D +=0D + @retval EFI_SUCCESS String copied successfully=0D + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL=0D + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small=0D +**/=0D +EFI_STATUS=0D +PchGetSteppingStr (=0D + OUT CHAR8 *Buffer,=0D + IN UINT32 BufferSize=0D + )=0D +{=0D + PCH_STEPPING PchStep;=0D +=0D + PchStep =3D PchStepping ();=0D +=0D + if ((Buffer =3D=3D NULL) || (BufferSize =3D=3D 0)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D + if (BufferSize < PCH_STEPPING_STR_LENGTH_MAX) {=0D + return EFI_BUFFER_TOO_SMALL;=0D + }=0D +=0D + PchPrintSteppingStr (Buffer, BufferSize, PchStep);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Pcie Controller Number=0D +=0D + @retval Pch Maximum Pcie Root Port Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieControllerNum (=0D + VOID=0D + )=0D +{=0D + return GetPchMaxPciePortNum () / PCH_PCIE_CONTROLLER_PORTS;=0D +}=0D +=0D +/**=0D + return support status for P2SB PCR 20-bit addressing=0D +=0D + @retval TRUE=0D + @retval FALSE=0D +**/=0D +BOOLEAN=0D +IsP2sb20bPcrSupported (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfo= Lib/PchInfoLibPrivate.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/Pei= DxeSmmPchInfoLib/PchInfoLibPrivate.h new file mode 100644 index 0000000000..a93c3dbafd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pch= InfoLibPrivate.h @@ -0,0 +1,58 @@ +/** @file=0D + Private header for PCH Info Lib.=0D +=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +/**=0D + Structure for PCH SKU string mapping=0D +**/=0D +struct PCH_SKU_STRING {=0D + UINT16 Id;=0D + CHAR8 *String;=0D +};=0D +=0D +/**=0D + Determine Pch Series based on Device Id=0D +=0D + @param[in] LpcDeviceId Lpc Device Id=0D +=0D + @retval PCH_SERIES Pch Series=0D +**/=0D +PCH_SERIES=0D +PchSeriesFromLpcDid (=0D + IN UINT16 LpcDeviceId=0D + );=0D +=0D +/**=0D +Determine Pch Generation based on Device Id=0D +=0D +@param[in] LpcDeviceId Lpc Device Id=0D +=0D +@retval PCH_GENERATION Pch Generation=0D +**/=0D +PCH_GENERATION=0D +PchGenerationFromDid (=0D + IN UINT16 LpcDeviceId=0D + );=0D +=0D +/**=0D + Print Pch Stepping String=0D +=0D + @param[out] Buffer Output buffer of string=0D + @param[in] BufferSize Buffer Size=0D + @param[in] PchStep Pch Stepping Type=0D +=0D + @retval VOID=0D +**/=0D +VOID=0D +PchPrintSteppingStr (=0D + OUT CHAR8 *Buffer,=0D + IN UINT32 BufferSize,=0D + IN PCH_STEPPING PchStep=0D + );=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfo= Lib/PchInfoLibTgl.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeS= mmPchInfoLib/PchInfoLibTgl.c new file mode 100644 index 0000000000..bb3c7975e8 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pch= InfoLibTgl.c @@ -0,0 +1,715 @@ +/** @file=0D + Pch information library for TGL.=0D +=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include "PchInfoLibPrivate.h"=0D +#include =0D +#include =0D +=0D +/**=0D + Print Pch Stepping String=0D +=0D + @param[out] Buffer Output buffer of string=0D + @param[in] BufferSize Buffer Size=0D + @param[in] PchStep Pch Stepping Type=0D +=0D + @retval VOID=0D +**/=0D +VOID=0D +PchPrintSteppingStr (=0D + OUT CHAR8 *Buffer,=0D + IN UINT32 BufferSize,=0D + IN PCH_STEPPING PchStep=0D + )=0D +{=0D + AsciiSPrint (Buffer, BufferSize, "%c%c", 'A' + (PchStep >> 4), '0' + (Pc= hStep & 0xF));=0D +}=0D +=0D +/**=0D + Return Pch Generation=0D +=0D + @retval PCH_GENERATION Pch Generation=0D +**/=0D +PCH_GENERATION=0D +PchGeneration (=0D + VOID=0D + )=0D +{=0D + return TGL_PCH;=0D +}=0D +=0D +=0D +/**=0D + Get PCH series ASCII string.=0D +=0D + @retval PCH Series string=0D +**/=0D +CHAR8*=0D +PchGetSeriesStr (=0D + VOID=0D + )=0D +{=0D + switch (PchSeries ()) {=0D +=0D + case PCH_LP:=0D + return "TGL PCH-LP";=0D +=0D + default:=0D + return NULL;=0D + }=0D +}=0D +=0D +/**=0D + Get Pch Maximum Pcie Clock Number=0D +=0D + @retval Pch Maximum Pcie Clock Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieClockNum (=0D + VOID=0D + )=0D +{=0D + return 7;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Pcie ClockReq Number=0D +=0D + @retval Pch Maximum Pcie ClockReq Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieClockReqNum (=0D + VOID=0D + )=0D +{=0D + return GetPchMaxPcieClockNum ();=0D +}=0D +=0D +/**=0D + Get Pch Maximum Type C Port Number=0D +=0D + @retval Pch Maximum Type C Port Number=0D +**/=0D +UINT8=0D +GetPchMaxTypeCPortNum (=0D + VOID=0D + )=0D +{=0D + switch (PchSeries ()) {=0D + case PCH_LP:=0D + return 4;=0D + default:=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D + Check whether integrated LAN controller is supported by PCH Series.=0D +=0D + @retval TRUE GbE is supported in current PCH=0D + @retval FALSE GbE is not supported on current PCH=0D +**/=0D +BOOLEAN=0D +PchIsGbeSupported (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Check whether integrated TSN is supported by PCH Series.=0D +=0D + @retval TRUE TSN is supported in current PCH=0D + @retval FALSE TSN is not supported on current PCH=0D +**/=0D +BOOLEAN=0D +PchIsTsnSupported (=0D + VOID=0D + )=0D +{=0D +#if FixedPcdGet8(PcdEmbeddedEnable) =3D=3D 0x1=0D + return TRUE;=0D +#else=0D + return FALSE;=0D +#endif=0D +}=0D +=0D +/**=0D + Check whether ISH is supported by PCH Series.=0D +=0D + @retval TRUE ISH is supported in current PCH=0D + @retval FALSE ISH is not supported on current PCH=0D +**/=0D +BOOLEAN=0D +PchIsIshSupported (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Pcie Root Port Number=0D +=0D + @retval Pch Maximum Pcie Root Port Number=0D +**/=0D +UINT8=0D +GetPchMaxPciePortNum (=0D + VOID=0D + )=0D +{=0D + switch (PchSeries ()) {=0D + case PCH_LP:=0D + return 12;=0D + default:=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D + Get Pch Maximum Hda Dmic Link=0D +=0D + @retval Pch Maximum Hda Dmic Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxDmicLinkNum (=0D + VOID=0D + )=0D +{=0D + return 2;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Hda Sndw Link=0D +=0D + @retval Pch Maximum Hda Sndw Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxSndwLinkNum (=0D + VOID=0D + )=0D +{=0D + return 4;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Hda Ssp Link=0D +=0D + @retval Pch Maximum Hda Ssp Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxSspLinkNum (=0D + VOID=0D + )=0D +{=0D + return 3;=0D +}=0D +=0D +/**=0D + Check if given Audio Interface is supported=0D +=0D + @param[in] AudioLinkType Link type support to be checked=0D + @param[in] AudioLinkIndex Link number=0D +=0D + @retval TRUE Link supported=0D + @retval FALSE Link not supported=0D +**/=0D +BOOLEAN=0D +IsAudioInterfaceSupported (=0D + IN HDAUDIO_LINK_TYPE AudioLinkType,=0D + IN UINT32 AudioLinkIndex=0D + )=0D +{=0D + //=0D + // Interfaces supported:=0D + // 1. HDA Link (SDI0/SDI1)=0D + // 2. Display Audio Link (SDI2)=0D + // 3. SSP[0-5]=0D + // 4. SNDW[1-4]=0D + //=0D + switch (AudioLinkType) {=0D + case HdaLink:=0D + case HdaIDispLink:=0D + return TRUE;=0D + case HdaDmic:=0D + if (AudioLinkIndex < 2) {=0D + return TRUE;=0D + } else {=0D + return FALSE;=0D + }=0D + case HdaSsp:=0D + if (AudioLinkIndex < 6) {=0D + return TRUE;=0D + } else {=0D + return FALSE;=0D + }=0D + case HdaSndw:=0D + if (AudioLinkIndex < 1) {=0D + return TRUE;=0D + } else if (AudioLinkIndex < 4) {=0D + return TRUE;=0D + } else {=0D + return FALSE;=0D + }=0D + default:=0D + return FALSE;=0D + }=0D +}=0D +=0D +/**=0D + Check if given Display Audio Link T-Mode is supported=0D +=0D + @param[in] Tmode T-mode support to be checked=0D +=0D + @retval TRUE T-mode supported=0D + @retval FALSE T-mode not supported=0D +**/=0D +BOOLEAN=0D +IsAudioIDispTmodeSupported (=0D + IN HDAUDIO_IDISP_TMODE Tmode=0D + )=0D +{=0D + //=0D + // iDisplay Audio Link T-mode support per PCH Generation/Series:=0D + // 1. 2T - TGL-LP/H/N=0D + // 2. 4T - TGL-LP (default), TGL-H, TGL-N=0D + // 3. 8T - TGL-H, TGL-N (default)=0D + // 4. 16T - TGL-H, TGL-N (not-POR)=0D + //=0D + switch (Tmode) {=0D + case HdaIDispMode1T:=0D + return FALSE;=0D + case HdaIDispMode2T:=0D + case HdaIDispMode4T:=0D + case HdaIDispMode8T:=0D + return TRUE;=0D + case HdaIDispMode16T:=0D + return FALSE;=0D + default:=0D + return FALSE;=0D + }=0D +}=0D +=0D +/**=0D +Get Pch Usb2 Maximum Physical Port Number=0D +=0D +@retval Pch Usb2 Maximum Physical Port Number=0D +**/=0D +UINT8=0D +GetPchUsb2MaxPhysicalPortNum(=0D + VOID=0D + )=0D +{=0D + switch (PchSeries()) {=0D + case PCH_LP:=0D + return 10;=0D + default:=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D +Get Pch Maximum Usb2 Port Number of XHCI Controller=0D +=0D +@retval Pch Maximum Usb2 Port Number of XHCI Controller=0D +**/=0D +UINT8=0D +GetPchXhciMaxUsb2PortNum(=0D + VOID=0D + )=0D +{=0D + switch (PchSeries()) {=0D + case PCH_LP:=0D + return 12;=0D + default:=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D +Get Pch Maximum Usb3 Port Number of XHCI Controller=0D +=0D +@retval Pch Maximum Usb3 Port Number of XHCI Controller=0D +**/=0D +UINT8=0D +GetPchXhciMaxUsb3PortNum(=0D + VOID=0D + )=0D +{=0D + switch (PchSeries()) {=0D + case PCH_LP:=0D + return 4;=0D + default:=0D + return 0;=0D + }=0D +}=0D +=0D +/**=0D + Gets the maximum number of UFS controller supported by this chipset.=0D +=0D + @return Number of supported UFS controllers=0D +**/=0D +UINT8=0D +PchGetMaxUfsNum (=0D + VOID=0D + )=0D +{=0D + return 2;=0D +}=0D +=0D +/**=0D + Check if this chipset supports eMMC controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchEmmcSupported (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Check if this chipset supports SD controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchSdCardSupported (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Check if this chipset supports THC controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchThcSupported (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Check if this chipset supports HSIO BIOS Sync=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchChipsetInitSyncSupported (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Check if link between PCH and CPU is an P-DMI=0D +=0D + @retval TRUE P-DMI link=0D + @retval FALSE Not an P-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithPdmi (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Check whether ATX Shutdown (PS_ON) is supported.=0D +=0D + @retval TRUE ATX Shutdown (PS_ON) is supported in PCH=0D + @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH=0D +**/=0D +BOOLEAN=0D +IsPchPSOnSupported (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Check if link between PCH and CPU is an OP-DMI=0D +=0D + @retval TRUE OP-DMI link=0D + @retval FALSE Not an OP-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithOpdmi (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Check if link between PCH and CPU is an F-DMI=0D +=0D + @retval TRUE F-DMI link=0D + @retval FALSE Not an F-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithFdmi (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +/**=0D + Get Pch Maximum ISH UART Controller number=0D +=0D + @retval Pch Maximum ISH UART controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshUartControllersNum (=0D + VOID=0D + )=0D +{=0D + return 2;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ISH I2C Controller number=0D +=0D + @retval Pch Maximum ISH I2C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshI2cControllersNum (=0D + VOID=0D + )=0D +{=0D + return 3;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ISH I3C Controller number=0D +=0D + @retval Pch Maximum ISH I3C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshI3cControllersNum (=0D + VOID=0D + )=0D +{=0D + return 0;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ISH SPI Controller number=0D +=0D + @retval Pch Maximum ISH SPI controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshSpiControllersNum (=0D + VOID=0D + )=0D +{=0D + return 1;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ISH SPI Controller Cs pins number=0D +=0D + @retval Pch Maximum ISH SPI controller Cs pins number=0D +**/=0D +UINT8=0D +GetPchMaxIshSpiControllerCsPinsNum (=0D + VOID=0D + )=0D +{=0D + return 1;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ISH GP number=0D +=0D + @retval Pch Maximum ISH GP number=0D +**/=0D +UINT8=0D +GetPchMaxIshGpNum (=0D + VOID=0D + )=0D +{=0D + return 8;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Serial IO I2C controllers number=0D +=0D + @retval Pch Maximum Serial IO I2C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoI2cControllersNum (=0D + VOID=0D + )=0D +{=0D + return 6;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Serial IO SPI controllers number=0D +=0D + @retval Pch Maximum Serial IO SPI controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoSpiControllersNum (=0D + VOID=0D + )=0D +{=0D + return 4;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Serial IO UART controllers number=0D +=0D + @retval Pch Maximum Serial IO UART controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoUartControllersNum (=0D + VOID=0D + )=0D +{=0D + return 4;=0D +}=0D +=0D +/**=0D + Get Pch Maximum Serial IO SPI Chip Selects count=0D +=0D + @retval Pch Maximum Serial IO SPI Chip Selects number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoSpiChipSelectsNum (=0D + VOID=0D + )=0D +{=0D + return 2;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ME Applet count=0D +=0D + @retval Pch Maximum ME Applet number=0D +**/=0D +UINT8=0D +GetPchMaxMeAppletCount (=0D + VOID=0D + )=0D +{=0D + return 31;=0D +}=0D +=0D +/**=0D + Get Pch Maximum ME Session count=0D +=0D + @retval Pch Maximum ME Sesion number=0D +**/=0D +UINT8=0D +GetPchMaxMeSessionCount (=0D + VOID=0D + )=0D +{=0D + return 16;=0D +}=0D +=0D +/**=0D + Get Pch Maximum THC count=0D +=0D + @retval Pch Maximum THC count number=0D +**/=0D +UINT8=0D +GetPchMaxThcCount (=0D + VOID=0D + )=0D +{=0D + return 2;=0D +}=0D +=0D +/**=0D + Returns a frequency of the sosc_clk signal.=0D + All SATA controllers on the system are assumed to=0D + work on the same sosc_clk frequency.=0D +=0D + @retval Frequency of the sosc_clk signal.=0D +**/=0D +SATA_SOSC_CLK_FREQ=0D +GetSataSoscClkFreq (=0D + VOID=0D + )=0D +{=0D + return SataSosc100Mhz;=0D +}=0D +=0D +/**=0D + Check if SATA support should be awake after function disable=0D +=0D + @retval TRUE=0D + @retval FALSE=0D +**/=0D +BOOLEAN=0D +IsSataSupportWakeAfterFunctionDisable (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +/**=0D + Returns USB2 PHY Reference Clock frequency value used by PCH=0D + This defines what electrical tuning parameters shall be used=0D + during USB2 PHY initialization programming=0D +=0D + @retval Frequency reference clock for USB2 PHY=0D +**/=0D +USB2_PHY_REF_FREQ=0D +GetUsb2PhyRefFreq (=0D + VOID=0D + )=0D +{=0D + return FREQ_19_2;=0D +}=0D +=0D +/**=0D + Check if SPI in a given PCH generation supports an Extended BIOS Range D= ecode=0D +=0D + @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode=0D +**/=0D +BOOLEAN=0D +IsExtendedBiosRangeDecodeSupported (=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +#define SPI_PCH_LP_DMI_TARGET 0x23A8=0D +=0D +/**=0D + Returns DMI target for current PCH SPI=0D +=0D + @retval PCH SPI DMI target value=0D +**/=0D +UINT16=0D +GetPchSpiDmiTarget (=0D + VOID=0D + )=0D +{=0D + return SPI_PCH_LP_DMI_TARGET;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfo= Lib/PeiDxeSmmPchInfoLibTgl.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Libr= ary/PeiDxeSmmPchInfoLib/PeiDxeSmmPchInfoLibTgl.inf new file mode 100644 index 0000000000..4b3fb988d2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Library/PeiDxeSmmPchInfoLib/Pei= DxeSmmPchInfoLibTgl.inf @@ -0,0 +1,43 @@ +## @file=0D +# PCH information library for TigerLake PCH.=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchInfoLibTgl=0D +FILE_GUID =3D 253B9BFC-026F-4BB4-AC2C-AC167BC0F43C=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PchInfoLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +PrintLib=0D +PciSegmentLib=0D +PchPcrLib=0D +PcdLib=0D +PchPciBdfLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +PchInfoLib.c=0D +PchInfoLibTgl.c=0D +=0D +[Pcd]=0D +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable ## CONSUMES= =0D --=20 2.24.0.windows.2