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04 Feb 2021 00:51:41 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and library instances Date: Thu, 4 Feb 2021 16:49:13 +0800 Message-Id: <20210204084919.3603-34-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * SystemAgent/AcpiTables * SystemAgent/Library/DxeSaPolicyLib * SystemAgent/Library/PeiDxeSmmSaPlatformLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRp.= asl | 252 ++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPcieRpC= ommon.asl | 289 ++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCommon.= asl | 1344 ++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRtd3.as= l | 124 ++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl = | 26 ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.asl= | 20 ++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf= | 22 +++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSa= PolicyLib.c | 254 ++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSa= PolicyLib.inf | 48 ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/DxeSa= PolicyLibrary.h | 33 ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformL= ib/PeiDxeSmmSaPlatformLib.inf | 32 ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformL= ib/SaPlatformLibrary.c | 68 ++++++++++++++++++++++++++++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlatformL= ib/SaPlatformLibrary.h | 21 ++++++++++++++ 13 files changed, 2533 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/CpuPcieRp.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/= SaSsdt/CpuPcieRp.asl new file mode 100644 index 0000000000..0babf047ed --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPc= ieRp.asl @@ -0,0 +1,252 @@ +/** @file=0D + This file contains the CPU PCIe Root Port configuration=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +External(LTRX) // CPU PCIe Root Port 0 Latency Tolerance Reporting Enable= =0D +External(LTRY) // CPU PCIe Root Port 1 Latency Tolerance Reporting Enable= =0D +External(LTRZ) // CPU PCIe Root Port 2 Latency Tolerance Reporting Enable= =0D +External(LTRW) // CPU PCIe Root Port 3 Latency Tolerance Reporting Enable= =0D +External(SMSL) // CPU PCIe Root Port Latency Tolerance Reporting Max Snoop= Latency=0D +External(SNSL) // CPU PCIe Root Port Latency Tolerance Reporting Max No Sn= oop Latency=0D +External(PG0E) // CpuPcieRp0Enable 0: Disable; 1: Enable=0D +External(PG1E) // CpuPcieRp1Enable 0: Disable; 1: Enable=0D +External(PG2E) // CpuPcieRp2Enable 0: Disable; 1: Enable=0D +External(PG3E) // CpuPcieRp3Enable 0: Disable; 1: Enable=0D +External(\_SB.PC00.PEG0, DeviceObj)=0D +External(\_SB.PC00.PEG1, DeviceObj)=0D +External(\_SB.PC00.PEG2, DeviceObj)=0D +External(\_SB.PC00.PEG3, DeviceObj)=0D +External(\_SB.PC00.PEG0.PEGP, DeviceObj)=0D +External(\_SB.PC00.PEG1.PEGP, DeviceObj)=0D +External(\_SB.PC00.PEG2.PEGP, DeviceObj)=0D +External(\_SB.PC00.PEG3.PEGP, DeviceObj)=0D +External(\AR02)=0D +External(\PD02)=0D +External(\AR0A)=0D +External(\PD0A)=0D +External(\AR0B)=0D +External(\PD0B)=0D +External(\AR0C)=0D +External(\PD0C)=0D +External(VMDE)=0D +External(VMCP)=0D +External(MPGN)=0D +External(PBR1)=0D +External(PBR2)=0D +External(PBR3)=0D +=0D +Scope (\_SB.PC00.PEG0) {=0D +=0D + Name(SLOT, 0) // CPU PCIe root port index 0 corresponds to PEG60 (0/6/0)= =0D +=0D + Method (_STA, 0x0, NotSerialized) {=0D + if(PG0E =3D=3D 1) { // If CPU PCIe RP0 enabled?=0D + Return(0x0F)=0D + }=0D + Return(0x00)=0D + }=0D +=0D + Name(LTEN, 0)=0D + Name(LMSL, 0)=0D + Name(LNSL, 0)=0D +=0D + Method(_INI)=0D + {=0D + Store (LTRX, LTEN)=0D + Store (SMSL, LMSL)=0D + Store (SNSL, LNSL)=0D + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {=0D + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x8),0))) {=0D + Store (1, CPMV)=0D + }=0D + }=0D + }=0D +=0D + Method(_PRT,0) {=0D + If(PICM) {=0D + Return(AR02)=0D + } // APIC mode=0D + Return (PD02) // PIC Mode=0D + } // end _PRT=0D +=0D + Include("CpuPcieRpCommon.asl")=0D +} // PEG0 scope end=0D +=0D +Scope (\_SB.PC00.PEG1) {=0D +=0D + Name(SLOT, 1) // CPU PCIe root port index 1 corresponds to PEG10 (0/1/0)= =0D +=0D + Method (_STA, 0x0, NotSerialized) {=0D + if(PG1E =3D=3D 1) { // If CPU PCIe RP1 enabled?=0D + Return(0x0F)=0D + }=0D + Return(0x00)=0D + }=0D +=0D + Name(LTEN, 0)=0D + Name(LMSL, 0)=0D + Name(LNSL, 0)=0D +=0D + Method(_INI)=0D + {=0D + Store (LTRY, LTEN)=0D + Store (SMSL, LMSL)=0D + Store (SNSL, LNSL)=0D + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {=0D + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x1),0))) {=0D + Store (1, CPMV)=0D + }=0D + }=0D + }=0D +=0D + Method(_PRT,0) {=0D + If(PICM) {=0D + Return(AR0A)=0D + } // APIC mode=0D + Return (PD0A) // PIC Mode=0D + } // end _PRT=0D +=0D + Include("CpuPcieRpCommon.asl")=0D +} // PEG1 scope end=0D +=0D +Scope (\_SB.PC00.PEG2) {=0D +=0D + Name(SLOT, 2) // CPU PCIe root port index 2 corresponds to PEG11 (0/1/1)= =0D +=0D + Method (_STA, 0x0, NotSerialized) {=0D + if(PG2E =3D=3D 1) { // If CPU PCIe RP2 enabled?=0D + Return(0x0F)=0D + }=0D + Return(0x00)=0D + }=0D +=0D + Name(LTEN, 0)=0D + Name(LMSL, 0)=0D + Name(LNSL, 0)=0D +=0D + Method(_INI)=0D + {=0D + Store (LTRZ, LTEN)=0D + Store (SMSL, LMSL)=0D + Store (SNSL, LNSL)=0D + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {=0D + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x2),0))) {=0D + Store (1, CPMV)=0D + }=0D + }=0D + }=0D +=0D + Method(_PRT,0) {=0D + If(PICM) {=0D + Return(AR0B)=0D + } // APIC mode=0D + Return (PD0B) // PIC Mode=0D + } // end _PRT=0D +=0D + Include("CpuPcieRpCommon.asl")=0D +} // PEG2 scope end=0D +=0D +If (CondRefOf(\_SB.PC00.PEG3)) {=0D + Scope (\_SB.PC00.PEG3) {=0D +=0D + Name(SLOT, 3) // CPU PCIe root port index 3 corresponds to PEG12 (0/1/= 2)=0D +=0D + Method (_STA, 0x0, NotSerialized) {=0D + if(PG3E =3D=3D 1) { // If CPU PCIe RP3 enabled?=0D + Return(0x0F)=0D + }=0D + Return(0x00)=0D + }=0D +=0D + Name(LTEN, 0)=0D + Name(LMSL, 0)=0D + Name(LNSL, 0)=0D +=0D + Method(_INI)=0D + {=0D + Store (LTRW, LTEN)=0D + Store (SMSL, LMSL)=0D + Store (SNSL, LNSL)=0D + If(LAnd(CondRefOf(VMCP),CondRefOf(VMDE))) {=0D + If(LAnd(LEqual(VMDE,1),LNotEqual(And(VMCP,0x4),0))) {=0D + Store (1, CPMV)=0D + }=0D + }=0D + }=0D +=0D + Method(_PRT,0) {=0D + If(PICM) {=0D + Return(AR0C)=0D + } // APIC mode=0D + Return (PD0C) // PIC Mode=0D + } // end _PRT=0D +=0D + Include("CpuPcieRpCommon.asl")=0D + } // PEG3 scope end=0D +}=0D +=0D +Scope(\_SB.PC00.PEG0.PEGP) {=0D + Method(_PRW, 0) {=0D + Return(GPRW(0x69, 4)) // can wakeup from S4 state=0D + }=0D +}=0D +=0D +=0D +If (PBR1) {=0D + Scope(\_SB.PC00.PEG1.PEGP) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D +=0D + Device (PEGD) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D + Name(_ADR, 0x00000000)=0D + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 stat= e=0D + }=0D + } // end "P.E.G. Port Slot x16"=0D +}=0D +=0D +Scope(\_SB.PC00.PEG1.PEGP) {=0D + Method(_PRW, 0) {=0D + Return(GPRW(0x69, 4)) // can wakeup from S4 state=0D + }=0D +}=0D +=0D +=0D +If (PBR2) {=0D + Scope(\_SB.PC00.PEG2.PEGP) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D +=0D + Device (PEGD) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D + Name(_ADR, 0x00000000)=0D + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 stat= e=0D + }=0D + } // end "P.E.G. Port Slot 2x8"=0D +}=0D +=0D +Scope(\_SB.PC00.PEG2.PEGP) {=0D + Method(_PRW, 0) {=0D + Return(GPRW(0x69, 4)) // can wakeup from S4 state=0D + }=0D +}=0D +=0D +If (PBR3) {=0D + Scope(\_SB.PC00.PEG3.PEGP) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D +=0D + Device (PEGD) {=0D + Method(_S0W, 0) { Return(4)} //D3cold is supported=0D + Name(_ADR, 0x00000000)=0D + Method(_PRW, 0) { Return(GPRW(0x69, 4)) } // can wakeup from S4 stat= e=0D + }=0D + } // end "P.E.G. Port Slot 1x8 - 2x4"=0D +}=0D +=0D +If (CondRefOf(\_SB.PC00.PEG3)) {=0D + Scope(\_SB.PC00.PEG3.PEGP) {=0D + Method(_PRW, 0) {=0D + Return(GPRW(0x69, 4)) // can wakeup from S4 state=0D + }=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/CpuPcieRpCommon.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiT= ables/SaSsdt/CpuPcieRpCommon.asl new file mode 100644 index 0000000000..81f785dfc5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/CpuPc= ieRpCommon.asl @@ -0,0 +1,289 @@ +/** @file=0D + This file contains the CPU PCIe Root Port configuration=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D + External(ECR1)=0D + External(GPRW, MethodObj)=0D + External(PICM)=0D + External(\_SB.PC00.PC2M, MethodObj)=0D + External(_ADR, IntObj)=0D +=0D +=0D + OperationRegion(PXCS,SystemMemory,\_SB.PC00.PC2M(_ADR),0x480)=0D + Field(PXCS, AnyAcc, NoLock, Preserve)=0D + {=0D + Offset(0),=0D + VDID, 32,=0D + Offset(0x50), // LCTL - Link Control Register=0D + L0SE, 1, // 0, L0s Entry Enabled=0D + , 3,=0D + LDIS, 1,=0D + , 3,=0D + Offset(0x52), // LSTS - Link Status Register=0D + , 13,=0D + LASX, 1, // 0, Link Active Status=0D + Offset(0x5A), // SLSTS[7:0] - Slot Status Register=0D + ABPX, 1, // 0, Attention Button Pressed=0D + , 2,=0D + PDCX, 1, // 3, Presence Detect Changed=0D + , 2,=0D + PDSX, 1, // 6, Presence Detect State=0D + , 1,=0D + Offset(0x60), // RSTS - Root Status Register=0D + , 16,=0D + PSPX, 1, // 16, PME Status=0D + Offset(0xA4),=0D + D3HT, 2, // Power State=0D + Offset(0xD8), // 0xD8, MPC - Miscellaneous Port Configuration Register= =0D + , 30,=0D + HPEX, 1, // 30, Hot Plug SCI Enable=0D + PMEX, 1, // 31, Power Management SCI Enable=0D + Offset(0xE0), // 0xE0, SPR - Scratch Pad Register=0D + , 0,=0D + SCB0, 1, // Sticky Scratch Pad Bit SCB0=0D + Offset(0xE2), // 0xE2, RPPGEN - Root Port Power Gating Enable=0D + , 2,=0D + L23E, 1, // 2, L23_Rdy Entry Request (L23ER)=0D + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)=0D + Offset(0x324), // 0x324 - PCIEDBG=0D + , 3,=0D + LEDM, 1, // PCIEDBG.DMIL1EDM=0D + Offset(0x328), // 0x328 - PCIESTS1=0D + , 24,=0D + LTSM, 8,=0D + }=0D + Field(PXCS,AnyAcc, NoLock, WriteAsZeros)=0D + {=0D + Offset(0xDC), // 0xDC, SMSCS - SMI/SCI Status Register=0D + , 30,=0D + HPSX, 1, // 30, Hot Plug SCI Status=0D + PMSX, 1 // 31, Power Management SCI Status=0D + }=0D +=0D + //=0D + // L23D method recovers link from L2 or L3 state. Used for RTD3 flows, r= ight after endpoint is powered up and exits reset.=0D + // This flow is implemented in ASL because rootport registers used for L= 2/L3 entry/exit=0D + // are proprietary and OS drivers don't know about them.=0D + //=0D + Method (L23D, 0, Serialized) {=0D + If(LNotEqual(SCB0,0x1)) {=0D + Return()=0D + }=0D +=0D + /// Set L23_Rdy to Detect Transition (L23R2DT)=0D + Store(1, L23R)=0D + Store(0, Local0)=0D + /// Wait for transition to Detect=0D + While(L23R) {=0D + If(Lgreater(Local0, 4))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + Store(0,SCB0)=0D +=0D + /// Once in Detect, wait up to 124 ms for Link Active (typically happe= ns in under 70ms)=0D + /// Worst case per PCIe spec from Detect to Link Active is:=0D + /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config (2= 4+2+2+2+2)=0D + Store(0, Local0)=0D + While(LEqual(LASX,0)) {=0D + If(Lgreater(Local0, 8))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + }=0D +=0D + //=0D + // DL23 method puts link to L2 or L3 state. Used for RTD3 flows, before = endpoint is powered down.=0D + // This flow is implemented in ASL because rootport registers used for L= 2/L3 entry/exit=0D + // are proprietary and OS drivers don't know about them.=0D + //=0D + Method (DL23, 0, Serialized) {=0D + Store(1, L23E)=0D + Sleep(16)=0D + Store(0, Local0)=0D + While(L23E) {=0D + If(Lgreater(Local0, 4))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + Store(1,SCB0)=0D + }=0D +=0D + Name(LTRV, Package(){0,0,0,0})=0D + Name(CPMV, 0) // CPU Rp Mapped under VMD=0D +=0D + //=0D + // _DSM Device Specific Method=0D + //=0D + // Arg0: UUID Unique function identifier=0D + // Arg1: Integer Revision Level=0D + // Arg2: Integer Function Index (0 =3D Return Supported Functions)=0D + // Arg3: Package Parameters=0D + Method(_DSM, 4, Serialized) {=0D + //=0D + // Switch based on which unique function identifier was passed in=0D + //=0D + If (LEqual(Arg0, ToUUID ("E5C937D0-3553-4d7a-9117-EA4D19C3434D"))) {=0D + //=0D + // _DSM Definitions for Latency Tolerance Reporting=0D + //=0D + // Arguments:=0D + // Arg0: UUID: E5C937D0-3553-4d7a-9117-EA4D19C3434D=0D + // Arg1: Revision ID: 3=0D + // Arg2: Function Index: 0, 6, 8, 9=0D + // Arg3: Empty Package=0D + //=0D + // Switch by function index=0D + //=0D + Switch(ToInteger(Arg2)) {=0D + //=0D + // Function Index:0=0D + // Standard query - A bitmask of functions supported=0D + //=0D + Case (0) {=0D + Name(OPTS,Buffer(2){0,0})=0D + CreateBitField(OPTS,0,FUN0)=0D + CreateBitField(OPTS,6,FUN6)=0D + CreateBitField(OPTS,8,FUN8)=0D + CreateBitField(OPTS,9,FUN9)=0D +=0D + Store(1,FUN0)=0D + if(LEqual(LTEN,1)) {=0D + Store(1,Fun6)=0D + }=0D +=0D + If (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2=0D + If(CondRefOf(ECR1)) {=0D + if(LEqual(ECR1,1)){=0D + if (LGreaterEqual(Arg1, 3)){ // test Arg1 for Revision ID:= 3=0D + Store(1,Fun8)=0D + Store(1,Fun9)=0D + }=0D + }=0D + }=0D + }=0D + Return (OPTS)=0D + }=0D +=0D + //=0D + // Function Index: 6=0D + // LTR Extended Capability Structure=0D + //=0D + Case(6) {=0D + if (LGreaterEqual(Arg1, 2)){ // test Arg1 for Revision ID: 2=0D + Store(And(ShiftRight(LMSL,10),7), Index(LTRV, 0))=0D + Store(And(LMSL,0x3FF), Index(LTRV, 1))=0D + Store(And(ShiftRight(LNSL,10),7), Index(LTRV, 2))=0D + Store(And(LNSL,0x3FF), Index(LTRV, 3))=0D + Return (LTRV)=0D + }=0D + }=0D + Case(8) { //ECR ACPI additions for FW latency optimizations, DSM f= or Avoiding Power-On Reset Delay Duplication on Sx Resume=0D + If(CondRefOf(ECR1)) {=0D + if(LEqual(ECR1,1)){=0D + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: = 3=0D + return (1)=0D + }=0D + }=0D + }=0D + }=0D + Case(9) { //ECR ACPI additions for FW latency optimizations, DSM f= or Specifying Device Readiness Durations=0D + If(CondRefOf(ECR1)) {=0D + if(LEqual(ECR1,1)){=0D + if (LGreaterEqual(Arg1, 3)) { // test Arg1 for Revision ID: = 3=0D + return(Package(5){50000,Ones,Ones,50000,Ones})=0D + }=0D + }=0D + }=0D + }=0D + } // End of switch(Arg2)=0D + } // End of if=0D + return (Buffer() {0x00})=0D + } // End of _DSM=0D +=0D + Method(_PRW, 0) {=0D + Return(GPRW(0x69, 4)) // can wakeup from S4 state=0D + }=0D +=0D + Method(_PS0,0,Serialized)=0D + {=0D + If (LEqual(HPEX, 1)) {=0D + Store(0, HPEX) // Disable Hot Plug SCI=0D + Store(1, HPSX) // Clear Hot Plug SCI status=0D + }=0D + If (LEqual (PMEX, 1)) {=0D + Store(0, PMEX) // Disable Power Management SCI=0D + Store(1, PMSX) // Clear Power Management SCI status=0D + }=0D + }=0D + Method(_PS3,0,Serialized)=0D + {=0D + If (LEqual (HPEX, 0)) {=0D + Store(1, HPEX) // Enable Hot Plug SCI=0D + Store(1, HPSX) // Clear Hot Plug SCI status=0D + }=0D + If (LEqual(PMEX, 0)) {=0D + Store(1, PMEX) // Enable Power Management SCI=0D + Store(1, PMSX) // Clear Power Management SCI status=0D + }=0D + }=0D +=0D + Method (_DSD, 0) {=0D + Return (=0D + Package () {=0D + ToUUID("FDF06FAD-F744-4451-BB64-ECD792215B10"),=0D + Package () {=0D + Package (2) {"FundamentalDeviceResetTriggeredOnD3ToD0", 1},=0D + }=0D + }=0D + ) // End of Return ()=0D + }=0D +=0D + //=0D + // PCI_EXP_STS Handler for PCIE Root Port=0D + //=0D + Method(HPME,0,Serialized) {=0D + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), LEqual(PMSX,1))) { //if port exist= s and has PME SCI Status set...=0D + Store(1,PMSX) // clear rootport's PME SCI status=0D + Store(1,PSPX) // consume one pending PME status to prevent it from b= locking the queue=0D + Return(0x01)=0D + }=0D + Return(0x00)=0D + }=0D +=0D + //=0D + // Sub-Method of _L61 Hot-Plug event=0D + // _L61 event handler should invoke this method to support HotPlug wake = event from PEG RP=0D + //=0D + Method(HPEV,0,Serialized) {=0D + If(LAnd(LNotEqual(VDID,0xFFFFFFFF), HPSX)) {=0D + // Clear HotPlug SCI event status=0D + Store(1, HPSX)=0D +=0D + If(LEqual(PDCX, 1)) {=0D + // Clear Presence Detect Changed=0D + Store(1,PDCX)=0D +=0D + If(LEqual(PDSX, 0)) {=0D + // The PCI Express slot is empty, so disable L0s on hot unplug=0D + //=0D + Store(0,L0SE)=0D + }=0D + // Perform proper notification=0D + // to the OS.=0D + Notify(^,0)=0D + }=0D + }=0D + }=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/PegCommon.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/= SaSsdt/PegCommon.asl new file mode 100644 index 0000000000..68b10309d4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegCo= mmon.asl @@ -0,0 +1,1344 @@ +/** @file=0D + This file contains the device definitions of the SystemAgent=0D + PCIE ACPI Reference Code.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +External(\_SB.ISME, MethodObj)=0D +External(\_SB.SHPO, MethodObj)=0D +External(\_SB.CAGS, MethodObj)=0D +External(\_SB.GGOV, MethodObj)=0D +External(\_SB.SGOV, MethodObj)=0D +External(\_SB.PC00.PEG0, DeviceObj)=0D +External(\_SB.PC00.PEG1, DeviceObj)=0D +External(\_SB.PC00.PEG2, DeviceObj)=0D +External(\_SB.PC00.PEG3, DeviceObj)=0D +External(\_SB.PC00.PEG0.PPRW, MethodObj)=0D +External(\_SB.PC00.PEG1.PPRW, MethodObj)=0D +External(\_SB.PC00.PEG2.PPRW, MethodObj)=0D +External(\_SB.PC00.PEG3.PPRW, MethodObj)=0D +External(\_SB.PC00.PC2M, MethodObj)=0D +External(P8XH, MethodObj)=0D +External(SPCO, MethodObj)=0D +External(PINI, MethodObj) // Platform specific PCIe root port initializati= on=0D +External(PRES, MethodObj)=0D +External(GPRW, MethodObj)=0D +External(\SLOT)=0D +External(\P0WK)=0D +External(\P1WK)=0D +External(\P2WK)=0D +External(\P3WK)=0D +External(\XBAS)=0D +External(\SBN0)=0D +External(\SBN1)=0D +External(\SBN2)=0D +External(\SBN3)=0D +External(\EECP)=0D +External(\EEC1)=0D +External(\EEC2)=0D +External(\EEC3)=0D +External(\SGGP)=0D +External(\HRE0)=0D +External(\HRG0)=0D +External(\HRA0)=0D +External(\PWE0)=0D +External(\PWG0)=0D +External(\PWA0)=0D +External(\P1GP)=0D +External(\HRE1)=0D +External(\HRG1)=0D +External(\HRA1)=0D +External(\PWE1)=0D +External(\PWG1)=0D +External(\PWA1)=0D +External(\P2GP)=0D +External(\HRE2)=0D +External(\HRG2)=0D +External(\HRA2)=0D +External(\PWE2)=0D +External(\PWG2)=0D +External(\PWA2)=0D +External(\P3GP)=0D +External(\HRE3)=0D +External(\HRG3)=0D +External(\HRA3)=0D +External(\PWE3)=0D +External(\PWG3)=0D +External(\PWA3)=0D +External(\P0SC)=0D +External(\P1SC)=0D +External(\P2SC)=0D +External(\P3SC)=0D +External(\DLPW)=0D +External(\DLHR)=0D +External(\OBFX)=0D +External(\OBFY)=0D +External(\OBFZ)=0D +External(\OBFA)=0D +External(\OSYS)=0D +=0D +//GPE Event handling - Start=0D +Scope(\_GPE) {=0D + //=0D + // _L6F Method call for PEG0/1/2/3 ports to handle 2-tier RTD3 GPE event= s=0D + //=0D + Method(P0L6,0)=0D + {=0D + // PEG0 Device Wake Event=0D + If (\_SB.ISME(P0WK))=0D + {=0D + \_SB.SHPO(P0WK, 1) // set gpio ownership to driver(0=3DA= CPI mode, 1=3DGPIO mode)=0D + Notify(\_SB.PC00.PEG0, 0x02) // device wake=0D + \_SB.CAGS(P0WK) // Clear GPE status bit for PEG0 WAKE= =0D + }=0D + }=0D +=0D + Method(P1L6,0)=0D + {=0D + // PEG1 Device Wake Event=0D + If (\_SB.ISME(P1WK))=0D + {=0D + \_SB.SHPO(P1WK, 1) // set gpio ownership to driver(0=3DA= CPI mode, 1=3DGPIO mode)=0D + Notify(\_SB.PC00.PEG1, 0x02) // device wake=0D + \_SB.CAGS(P1WK) // Clear GPE status bit for PEG1 WAKE= =0D + }=0D + }=0D +=0D + Method(P2L6,0)=0D + {=0D + // PEG2 Device Wake Event=0D + If (\_SB.ISME(P2WK))=0D + {=0D + \_SB.SHPO(P2WK, 1) // set gpio ownership to driver(0=3DA= CPI mode, 1=3DGPIO mode)=0D + Notify(\_SB.PC00.PEG2, 0x02) // device wake=0D + \_SB.CAGS(P2WK) // Clear GPE status bit for PEG2 WAKE= =0D + }=0D + }=0D +=0D + If (CondRefOf(\_SB.PC00.PEG3)) {=0D + Method(P3L6,0)=0D + {=0D + // PEG2 Device Wake Event=0D + If (\_SB.ISME(P3WK))=0D + {=0D + \_SB.SHPO(P3WK, 1) // set gpio ownership to driver(0= =3DACPI mode, 1=3DGPIO mode)=0D + Notify(\_SB.PC00.PEG3, 0x02) // device wake=0D + \_SB.CAGS(P3WK) // Clear GPE status bit for PEG2 WA= KE=0D + }=0D + }=0D + }=0D +} //Scope(\_GPE)=0D +=0D +If(LAnd((LEqual(HGMD,2)), (LEqual(HGST,1)))) {=0D +///=0D +/// P.E.G. Root Port D6F0=0D +///=0D +Scope(\_SB.PC00.PEG0) {=0D + Name(WKEN, 0)=0D +=0D + PowerResource(PG00, 0, 0) {=0D + Name(_STA, One)=0D + Method(_ON, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGON(0)=0D + Store(One, _STA)=0D + }=0D + }=0D + Method(_OFF, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGOF(0)=0D + Store(Zero, _STA)=0D + }=0D + }=0D + } //End of PowerResource(PG00, 0, 0)=0D +=0D + Name(_PR0,Package(){PG00})=0D + Name(_PR3,Package(){PG00})=0D +=0D + ///=0D + /// This method is used to enable/disable wake from PEG60 (WKEN)=0D + ///=0D + Method(_DSW, 3)=0D + {=0D + If(Arg1)=0D + {=0D + Store(0, WKEN) /// If entering Sx, need to disable WAKE# from= generating runtime PME=0D + }=0D + Else=0D + { /// If Staying in S0=0D + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake=0D + {=0D + Store(1, WKEN) ///- Set PME=0D + } Else {=0D + Store(0, WKEN) ///- Disable runtime PME, either because staying= in D0 or disabling wake=0D + }=0D + }=0D + } // End _DSW=0D +=0D + ///=0D + /// This method is used to change the GPIO ownership back to ACPI and wi= ll be called in PEG OFF Method=0D + ///=0D + Method(P0EW, 0)=0D + {=0D + If(WKEN)=0D + {=0D + If(LNotEqual(SGGP, 0x0))=0D + {=0D + If(LEqual(SGGP, 0x1)) // GPIO mode=0D + {=0D + \_SB.SGOV(P0WK, 0x1)=0D + \_SB.SHPO(P0WK, 0x0) // set gpio ownership to ACPI(0=3DACPI = mode, 1=3DGPIO mode)=0D + }=0D + }=0D + }=0D + } // End P0EW=0D +=0D + Method(_S0W, 0) {=0D + Return(4) //D3cold is supported=0D + }=0D +}// end "P.E.G. Root Port D6F0"=0D +=0D +///=0D +/// P.E.G. Root Port D1F0=0D +///=0D +Scope(\_SB.PC00.PEG1) {=0D + Name(WKEN, 0)=0D +=0D + PowerResource(PG01, 0, 0) {=0D + Name(_STA, One)=0D + Method(_ON, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGON(1)=0D + Store(One, _STA)=0D + }=0D + }=0D + Method(_OFF, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGOF(1)=0D + Store(Zero, _STA)=0D + }=0D + }=0D + } //End of PowerResource(PG01, 0, 0)=0D +=0D + Name(_PR0,Package(){PG01})=0D + Name(_PR3,Package(){PG01})=0D +=0D + ///=0D + /// This method is used to enable/disable wake from PEG10 (WKEN)=0D + ///=0D + Method(_DSW, 3)=0D + {=0D + If(Arg1)=0D + {=0D + Store(0, WKEN) /// If entering Sx, need to disable WAKE# from= generating runtime PME=0D + }=0D + Else=0D + { /// If Staying in S0=0D + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake=0D + {=0D + Store(1, WKEN) ///- Set PME=0D + } Else {=0D + Store(0, WKEN) ///- Disable runtime PME, either because staying= in D0 or disabling wake=0D + }=0D + }=0D + } // End _DSW=0D +=0D + ///=0D + /// This method is used to change the GPIO ownership back to ACPI and wi= ll be called in PEG OFF Method=0D + ///=0D + Method(P1EW, 0)=0D + {=0D + If(WKEN)=0D + {=0D + If(LNotEqual(P1GP, 0x0))=0D + {=0D + If(LEqual(P1GP, 0x1)) // GPIO mode=0D + {=0D + \_SB.SGOV(P1WK, 0x1)=0D + \_SB.SHPO(P1WK, 0x0) // set gpio ownership to ACPI(0=3DACPI = mode, 1=3DGPIO mode)=0D + }=0D + }=0D + }=0D + } // End P1EW=0D +}// end "P.E.G. Root Port D1F0"=0D +=0D +///=0D +/// P.E.G. Root Port D1F1=0D +///=0D +Scope(\_SB.PC00.PEG2) {=0D + Name(WKEN, 0)=0D +=0D + PowerResource(PG02, 0, 0) {=0D + Name(_STA, One)=0D + Method(_ON, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGON(2)=0D + Store(One, _STA)=0D + }=0D + }=0D + Method(_OFF, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGOF(2)=0D + Store(Zero, _STA)=0D + }=0D + }=0D + } //End of PowerResource(PG02, 0, 0)=0D +=0D + Name(_PR0,Package(){PG02})=0D +=0D + Name(_PR3,Package(){PG02})=0D +=0D + ///=0D + /// This method is used to enable/disable wake from PEG11 (WKEN)=0D + ///=0D + Method(_DSW, 3)=0D + {=0D + If(Arg1)=0D + {=0D + Store(0, WKEN) /// If entering Sx, need to disable WAKE# from= generating runtime PME=0D + }=0D + Else=0D + { /// If Staying in S0=0D + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake=0D + {=0D + Store(1, WKEN) ///- Set PME=0D + } Else {=0D + Store(0, WKEN) ///- Disable runtime PME, either because staying= in D0 or disabling wake=0D + }=0D + }=0D + } // End _DSW=0D +=0D + ///=0D + /// This method is used to change the GPIO ownership back to ACPI and wi= ll be called in PEG OFF Method=0D + ///=0D + Method(P2EW, 0)=0D + {=0D + If(WKEN)=0D + {=0D + If(LNotEqual(P2GP, 0x0))=0D + {=0D + If(LEqual(P2GP, 0x1)) // GPIO mode=0D + {=0D + \_SB.SGOV(P2WK, 0x1)=0D + \_SB.SHPO(P2WK, 0x0) // set gpio ownership to ACPI(0=3DACPI = mode, 1=3DGPIO mode)=0D + }=0D + }=0D + }=0D + } // End P2EW=0D +}// end "P.E.G. Root Port D1F1"=0D +=0D +///=0D +/// P.E.G. Root Port D1F2=0D +///=0D +Scope(\_SB.PC00.PEG3) {=0D + Name(WKEN, 0)=0D +=0D + PowerResource(PG03, 0, 0) {=0D + Name(_STA, One)=0D + Method(_ON, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGON(3)=0D + Store(One, _STA)=0D + }=0D + }=0D + Method(_OFF, 0, Serialized) {=0D + If(LGreater(OSYS,2009)) {=0D + PGOF(3)=0D + Store(Zero, _STA)=0D + }=0D + }=0D + } //End of PowerResource(PG03, 0, 0)=0D +=0D + Name(_PR0,Package(){PG03})=0D + Name(_PR3,Package(){PG03})=0D +=0D + ///=0D + /// This method is used to enable/disable wake from PEG12 (WKEN)=0D + ///=0D + Method(_DSW, 3)=0D + {=0D + If(Arg1)=0D + {=0D + Store(0, WKEN) /// If entering Sx, need to disable WAKE# from= generating runtime PME=0D + }=0D + Else=0D + { /// If Staying in S0=0D + If(LAnd(Arg0, Arg2)) ///- Check if Exiting D0 and arming for wake=0D + {=0D + Store(1, WKEN) ///- Set PME=0D + } Else {=0D + Store(0, WKEN) ///- Disable runtime PME, either because staying= in D0 or disabling wake=0D + }=0D + }=0D + } // End _DSW=0D +=0D + ///=0D + /// This method is used to change the GPIO ownership back to ACPI and wi= ll be called in PEG OFF Method=0D + ///=0D + Method(P3EW, 0)=0D + {=0D + If(WKEN)=0D + {=0D + If(LNotEqual(P3GP, 0x0))=0D + {=0D + If(LEqual(P3GP, 0x1)) // GPIO mode=0D + {=0D + \_SB.SGOV(P3WK, 0x1)=0D + \_SB.SHPO(P3WK, 0x0) // set gpio ownership to ACPI(0=3DACPI = mode, 1=3DGPIO mode)=0D + }=0D + }=0D + }=0D + } // End P3EW=0D +}// end "P.E.G. Root Port D1F2"=0D +=0D +Scope (\_SB.PC00) {=0D +=0D + Name(IVID, 0xFFFF) //Invalid Vendor ID=0D +=0D + Name(PEBA, 0) //PCIE base address=0D +=0D + Name(PION, 0) //PEG index for ON Method=0D + Name(PIOF, 0) //PEG index for OFF Method=0D +=0D + Name(PBUS, 0) //PEG Rootport bus no=0D + Name(PDEV, 0) //PEG Rootport device no=0D + Name(PFUN, 0) //PEG Rootport function no=0D +=0D + Name(EBUS, 0) //Endpoint bus no=0D + Name(EDEV, 0) //Endpoint device no=0D + Name(EFN0, 0) //Endpoint function no 0=0D + Name(EFN1, 1) //Endpoint function no 1=0D +=0D + Name(LTRS, 0)=0D + Name(OBFS, 0)=0D +=0D + Name(DSOF, 0x06) //Device status PCI offset=0D + Name(CPOF, 0x34) //Capabilities pointer PCI offset=0D + Name(SBOF, 0x19) //PCI-2-PCI Secondary Bus number=0D +=0D + // PEG0 Endpoint variable to save/restore Link Capability, Link contro= l, Subsytem VendorId and Device Id=0D + Name (ELC0, 0x00000000)=0D + Name (ECP0, 0xffffffff)=0D + Name (H0VI, 0x0000)=0D + Name (H0DI, 0x0000)=0D +=0D + // PEG1 Endpoint variable to save/restore Link Capability, Link contro= l, Subsytem VendorId and Device Id=0D + Name (ELC1, 0x00000000)=0D + Name (ECP1, 0xffffffff)=0D + Name (H1VI, 0x0000)=0D + Name (H1DI, 0x0000)=0D +=0D + // PEG2 Endpoint variable to save/restore Link Capability, Link contro= l, Subsytem VendorId and Device Id=0D + Name (ELC2, 0x00000000)=0D + Name (ECP2, 0xffffffff)=0D + Name (H2VI, 0x0000)=0D + Name (H2DI, 0x0000)=0D +=0D + // PEG3 Endpoint variable to save/restore Link Capability, Link contro= l, Subsytem VendorId and Device Id=0D + Name (ELC3, 0x00000000)=0D + Name (ECP3, 0xffffffff)=0D + Name (H3VI, 0x0000)=0D + Name (H3DI, 0x0000)=0D +=0D + // PEG_AFELN[15:0]VMTX2_OFFSET variables=0D + Name(AFL0, 0)=0D + Name(AFL1, 0)=0D + Name(AFL2, 0)=0D + Name(AFL3, 0)=0D + Name(AFL4, 0)=0D + Name(AFL5, 0)=0D + Name(AFL6, 0)=0D + Name(AFL7, 0)=0D + Name(AFL8, 0)=0D + Name(AFL9, 0)=0D + Name(AFLA, 0)=0D + Name(AFLB, 0)=0D + Name(AFLC, 0)=0D + Name(AFLD, 0)=0D + Name(AFLE, 0)=0D + Name(AFLF, 0)=0D +=0D + //=0D + // Define a Memory Region for PEG60 root port that will allow access t= o its=0D + // Register Block.=0D + //=0D + OperationRegion(OPG0, SystemMemory, Add(XBAS,0x30000), 0x1000)=0D + Field(OPG0, AnyAcc,NoLock,Preserve)=0D + {=0D + Offset(0),=0D + P0VI, 16, //Vendor ID PCI offset=0D + P0DI, 16, //Device ID PCI offset=0D + Offset(0x06),=0D + DSO0, 16, //Device status PCI offset=0D + Offset(0x34),=0D + CPO0, 8, //Capabilities pointer PCI offset=0D + Offset(0x0B0),=0D + , 4,=0D + P0LD, 1, //Link Disable=0D + Offset(0x11A),=0D + , 1,=0D + P0VC, 1, //VC0RSTS.VC0NP=0D + Offset(0x214),=0D + , 16,=0D + P0LS, 4, //PEGSTS.LKS=0D + Offset(0x248),=0D + , 7,=0D + Q0L2, 1, //L23_Rdy Entry Request for RTD3=0D + Q0L0, 1, //L23 to Detect Transition for RTD3=0D + Offset(0x504),=0D + HST0, 32,=0D + Offset(0x508),=0D + P0TR, 1, //TRNEN.TREN=0D + Offset(0xC74),=0D + P0LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS=0D + Offset(0xD0C),=0D + LRV0, 32,=0D + }=0D +=0D + //=0D + // Define a Memory Region for Endpoint on PEG60 root port=0D + //=0D + OperationRegion (PCS0, SystemMemory, Add(XBAS,ShiftLeft(SBN0,20)), 0xF= 0)=0D + Field(PCS0, DWordAcc, Lock, Preserve)=0D + {=0D + Offset(0x0),=0D + D0VI, 16,=0D + Offset(0x2C),=0D + S0VI, 16,=0D + S0DI, 16,=0D + }=0D +=0D + OperationRegion(CAP0, SystemMemory, Add(Add(XBAS,ShiftLeft(SBN0,20)),E= ECP),0x14)=0D + Field(CAP0,DWordAcc, NoLock,Preserve)=0D + {=0D + Offset(0x0C), // Link Capabilities Register=0D + LCP0, 32, // Link Capabilities Register Dat= a=0D + Offset(0x10),=0D + LCT0, 16, // Link Control register=0D + }=0D +=0D + //=0D + // Define a Memory Region for PEG10 root port that will allow access t= o its=0D + // Register Block.=0D + //=0D + OperationRegion(OPG1, SystemMemory, Add(XBAS,0x8000), 0x1000)=0D + Field(OPG1, AnyAcc,NoLock,Preserve)=0D + {=0D + Offset(0),=0D + P1VI, 16, //Vendor ID PCI offset=0D + P1DI, 16, //Device ID PCI offset=0D + Offset(0x06),=0D + DSO1, 16, //Device status PCI offset=0D + Offset(0x34),=0D + CPO1, 8, //Capabilities pointer PCI offset=0D + Offset(0x0B0),=0D + , 4,=0D + P1LD, 1, //Link Disable=0D + Offset(0x11A),=0D + , 1,=0D + P1VC, 1, //VC0RSTS.VC0NP=0D + Offset(0x214),=0D + , 16,=0D + P1LS, 4, //PEGSTS.LKS=0D + Offset(0x248),=0D + , 7,=0D + Q1L2, 1, //L23_Rdy Entry Request for RTD3=0D + Q1L0, 1, //L23 to Detect Transition for RTD3=0D + Offset(0x504),=0D + HST1, 32,=0D + Offset(0x508),=0D + P1TR, 1, //TRNEN.TREN=0D + Offset(0x70C),=0D + PA0V, 32, //PEG_AFELN0VMTX2_OFFSET=0D + Offset(0x71C),=0D + PA1V, 32, //PEG_AFELN1VMTX2_OFFSET=0D + Offset(0x72C),=0D + PA2V, 32, //PEG_AFELN2VMTX2_OFFSET=0D + Offset(0x73C),=0D + PA3V, 32, //PEG_AFELN3VMTX2_OFFSET=0D + Offset(0x74C),=0D + PA4V, 32, //PEG_AFELN4VMTX2_OFFSET=0D + Offset(0x75C),=0D + PA5V, 32, //PEG_AFELN5VMTX2_OFFSET=0D + Offset(0x76C),=0D + PA6V, 32, //PEG_AFELN6VMTX2_OFFSET=0D + Offset(0x77C),=0D + PA7V, 32, //PEG_AFELN7VMTX2_OFFSET=0D + Offset(0x78C),=0D + PA8V, 32, //PEG_AFELN8VMTX2_OFFSET=0D + Offset(0x79C),=0D + PA9V, 32, //PEG_AFELN9VMTX2_OFFSET=0D + Offset(0x7AC),=0D + PAAV, 32, //PEG_AFELNAVMTX2_OFFSET=0D + Offset(0x7BC),=0D + PABV, 32, //PEG_AFELNBVMTX2_OFFSET=0D + Offset(0x7CC),=0D + PACV, 32, //PEG_AFELNCVMTX2_OFFSET=0D + Offset(0x7DC),=0D + PADV, 32, //PEG_AFELNDVMTX2_OFFSET=0D + Offset(0x7EC),=0D + PAEV, 32, //PEG_AFELNEVMTX2_OFFSET=0D + Offset(0x7FC),=0D + PAFV, 32, //PEG_AFELNFVMTX2_OFFSET=0D + Offset(0x91C),=0D + , 31,=0D + BSP1, 1,=0D + Offset(0x93C),=0D + , 31,=0D + BSP2, 1,=0D + Offset(0x95C),=0D + , 31,=0D + BSP3, 1,=0D + Offset(0x97C),=0D + , 31,=0D + BSP4, 1,=0D + Offset(0x99C),=0D + , 31,=0D + BSP5, 1,=0D + Offset(0x9BC),=0D + , 31,=0D + BSP6, 1,=0D + Offset(0x9DC),=0D + , 31,=0D + BSP7, 1,=0D + Offset(0x9FC),=0D + , 31,=0D + BSP8, 1,=0D + Offset(0xC20),=0D + , 4,=0D + P1AP, 2, //AFEOVR.RXSQDETOVR=0D + Offset(0xC38),=0D + , 3,=0D + P1RM, 1, //CMNSPARE.PCUNOTL1=0D + Offset(0xC3C),=0D + , 31,=0D + PRST, 1,=0D + Offset(0xC74),=0D + P1LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS=0D + Offset(0xD0C),=0D + LRV1, 32,=0D + }=0D +=0D + //=0D + // Define a Memory Region for Endpoint on PEG10 root port=0D + //=0D + OperationRegion (PCS1, SystemMemory, Add(XBAS,ShiftLeft(SBN1,20)), 0xF= 0)=0D + Field(PCS0, DWordAcc, Lock, Preserve)=0D + {=0D + Offset(0x0),=0D + D1VI, 16,=0D + Offset(0x2C),=0D + S1VI, 16,=0D + S1DI, 16,=0D + }=0D +=0D + OperationRegion(CAP1, SystemMemory, Add(Add(XBAS,ShiftLeft(SBN1,20)),E= EC1),0x14)=0D + Field(CAP0,DWordAcc, NoLock,Preserve)=0D + {=0D + Offset(0x0C), // Link Capabilities Register=0D + LCP1, 32, // Link Capabilities Register Dat= a=0D + Offset(0x10),=0D + LCT1, 16, // Link Control register=0D + }=0D +=0D + //=0D + // Define a Memory Region for PEG11 root port that will allow access t= o its=0D + // Register Block.=0D + //=0D + OperationRegion(OPG2, SystemMemory, Add(XBAS,0x9000), 0x1000)=0D + Field(OPG2, AnyAcc,NoLock,Preserve)=0D + {=0D + Offset(0),=0D + P2VI, 16, //Vendor ID PCI offset=0D + P2DI, 16, //Device ID PCI offset=0D + Offset(0x06),=0D + DSO2, 16, //Device status PCI offset=0D + Offset(0x34),=0D + CPO2, 8, //Capabilities pointer PCI offset=0D + Offset(0x0B0),=0D + , 4,=0D + P2LD, 1, //Link Disable=0D + Offset(0x11A),=0D + , 1,=0D + P2VC, 1, //VC0RSTS.VC0NP=0D + Offset(0x214),=0D + , 16,=0D + P2LS, 4, //PEGSTS.LKS=0D + Offset(0x248),=0D + , 7,=0D + Q2L2, 1, //L23_Rdy Entry Request for RTD3=0D + Q2L0, 1, //L23 to Detect Transition for RTD3=0D + Offset(0x504),=0D + HST2, 32,=0D + Offset(0x508),=0D + P2TR, 1, //TRNEN.TREN=0D + Offset(0xC20),=0D + , 4,=0D + P2AP, 2, //AFEOVR.RXSQDETOVR=0D + Offset(0xC38),=0D + , 3,=0D + P2RM, 1, //CMNSPARE.PCUNOTL1=0D + Offset(0xC74),=0D + P2LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS=0D + Offset(0xD0C),=0D + LRV2, 32,=0D + }=0D +=0D + //=0D + // Define a Memory Region for Endpoint on PEG11 root port=0D + //=0D + OperationRegion (PCS2, SystemMemory, Add(XBAS,ShiftLeft(SBN2,20)), 0xF= 0)=0D + Field(PCS2, DWordAcc, Lock, Preserve)=0D + {=0D + Offset(0x0),=0D + D2VI, 16,=0D + Offset(0x2C),=0D + S2VI, 16,=0D + S2DI, 16,=0D + }=0D +=0D + OperationRegion(CAP2, SystemMemory, Add(Add(XBAS,ShiftLeft(SBN2,20)),E= EC2),0x14)=0D + Field(CAP2,DWordAcc, NoLock,Preserve)=0D + {=0D + Offset(0x0C), // Link Capabilities Register=0D + LCP2, 32, // Link Capabilities Register Data=0D + Offset(0x10),=0D + LCT2, 16, // Link Control register=0D + }=0D +=0D +=0D + //=0D + // Define a Memory Region for PEG12 root port that will allow access t= o its=0D + // Register Block.=0D + //=0D + OperationRegion(OPG3, SystemMemory, Add(XBAS,0xA000), 0x1000)=0D + Field(OPG3, AnyAcc,NoLock,Preserve)=0D + {=0D + Offset(0),=0D + P3VI, 16, //Vendor ID PCI offset=0D + P3DI, 16, //Device ID PCI offset=0D + Offset(0x06),=0D + DSO3, 16, //Device status PCI offset=0D + Offset(0x34),=0D + CPO3, 8, //Capabilities pointer PCI offset=0D + Offset(0x0B0),=0D + , 4,=0D + P3LD, 1, //Link Disable=0D + Offset(0x11A),=0D + , 1,=0D + P3VC, 1, //VC0RSTS.VC0NP=0D + Offset(0x214),=0D + , 16,=0D + P3LS, 4, //PEGSTS.LKS=0D + Offset(0x248),=0D + , 7,=0D + Q3L2, 1, //L23_Rdy Entry Request for RTD3=0D + Q3L0, 1, //L23 to Detect Transition for RTD3=0D + Offset(0x504),=0D + HST3, 32,=0D + Offset(0x508),=0D + P3TR, 1, //TRNEN.TREN=0D + Offset(0xC20),=0D + , 4,=0D + P3AP, 2, //AFEOVR.RXSQDETOVR=0D + Offset(0xC38),=0D + , 3,=0D + P3RM, 1, //CMNSPARE.PCUNOTL1=0D + Offset(0xC74),=0D + P3LT, 4, //LTSSM_FSM_RESTORE.LTSSM_FSM_PS=0D + Offset(0xD0C),=0D + LRV3, 32,=0D + }=0D +=0D + //=0D + // Define a Memory Region for Endpoint on PEG2 root port=0D + //=0D + OperationRegion (PCS3, SystemMemory, Add(XBAS,ShiftLeft(SBN3,20)), 0xF= 0)=0D + Field(PCS2, DWordAcc, Lock, Preserve)=0D + {=0D + Offset(0x0),=0D + D3VI, 16,=0D + Offset(0x2C),=0D + S3VI, 16,=0D + S3DI, 16,=0D + }=0D +=0D + OperationRegion(CAP3, SystemMemory, Add(Add(XBAS,ShiftLeft(SBN3,20)),E= EC3),0x14)=0D + Field(CAP3,DWordAcc, NoLock,Preserve)=0D + {=0D + Offset(0x0C), // Link Capabilities Register=0D + LCP3, 32, // Link Capabilities Register Data=0D + Offset(0x10),=0D + LCT3, 16, // Link Control register=0D + }=0D +=0D + //=0D + // Name: PGON=0D + // Description: Function to put the Pcie Endpoint in ON state=0D + // Input: Arg0 -> PEG index=0D + // Return: Nothing=0D + //=0D + Method(PGON,1,Serialized)=0D + {=0D + Store(Arg0, PION)=0D +=0D + //=0D + // Check for the GPIO support on PEG0/1/2/3 Configuration and Return= if it is not supported.=0D + //=0D + If (LEqual(PION, 0))=0D + {=0D + If (LEqual(SGGP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PION, 1))=0D + {=0D + If (LEqual(P1GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PION, 2))=0D + {=0D + If (LEqual(P2GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PION, 3))=0D + {=0D + If (LEqual(P3GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + Store(\XBAS, PEBA)=0D + Store(GDEV(PIOF), PDEV)=0D + Store(GFUN(PIOF), PFUN)=0D +=0D + /// de-assert CLK_REQ MSK=0D + PGSC(Arg0, 1)=0D +=0D + If (LEqual(CCHK(PION, 1), 0))=0D + {=0D + Return ()=0D + }=0D +=0D + //Power on the Endpoint=0D + GPPR(PION, 1)=0D +=0D + // Restore PEG Recipe before program L23R2DT=0D + //\_SB.PC00.PEG1.RAVR()=0D +=0D + // Enable link for RTD3=0D + RTEN()=0D +=0D + // Re-store the DGPU Subsystem VendorID, DeviceID & Link control reg= ister data=0D + If (LEqual(PION, 0))=0D + {=0D + Store(H0VI, S0VI)=0D + Store(H0DI, S0DI)=0D + Or(And(ELC0,0x0043),And(LCT0,0xFFBC),LCT0)=0D + }=0D + ElseIf (LEqual(PION, 1))=0D + {=0D + Store(H1VI, S1VI)=0D + Store(H1DI, S1DI)=0D + Or(And(ELC1,0x0043),And(LCT1,0xFFBC),LCT1)=0D + }=0D + ElseIf (LEqual(PION, 2))=0D + {=0D + Store(H2VI, S2VI)=0D + Store(H2DI, S2DI)=0D + Or(And(ELC2,0x0043),And(LCT2,0xFFBC),LCT2)=0D + }=0D + ElseIf (LEqual(PION, 3))=0D + {=0D + Store(H3VI, S3VI)=0D + Store(H3DI, S3DI)=0D + Or(And(ELC3,0x0043),And(LCT3,0xFFBC),LCT3)=0D + }=0D + Return ()=0D + } // End of Method(PGON,1,Serialized)=0D +=0D + //=0D + // Name: PGOF=0D + // Description: Function to put the Pcie Endpoint in OFF state=0D + // Input: Arg0 -> PEG index=0D + // Return: Nothing=0D + //=0D + Method(PGOF,1,Serialized)=0D + {=0D +=0D + Store(Arg0, PIOF)=0D + //=0D + // Check for the GPIO support on PEG0/1/2 Configuration and Return i= f it is not supported.=0D + //=0D + If (LEqual(PIOF, 0))=0D + {=0D + If (LEqual(SGGP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PIOF, 1))=0D + {=0D + If (LEqual(P1GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PIOF, 2))=0D + {=0D + If (LEqual(P2GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D + ElseIf (LEqual(PIOF, 3))=0D + {=0D + If (LEqual(P3GP, 0x0))=0D + {=0D + Return ()=0D + }=0D + }=0D +=0D + Store(\XBAS, PEBA)=0D + Store(GDEV(PIOF), PDEV)=0D + Store(GFUN(PIOF), PFUN)=0D +=0D + If (LEqual(CCHK(PIOF, 0), 0))=0D + {=0D + Return ()=0D + }=0D +=0D + // Save Endpoint Link Control register, Subsystem VendorID & Device = ID, Link capability Data=0D + If (LEqual(Arg0, 0)) //PEG60=0D + {=0D + Store(LCT0, ELC0)=0D + Store(S0VI, H0VI)=0D + Store(S0DI, H0DI)=0D + Store(LCP0, ECP0)=0D + }=0D + ElseIf (LEqual(Arg0, 1)) //PEG10=0D + {=0D + Store(LCT1, ELC1)=0D + Store(S1VI, H1VI)=0D + Store(S1DI, H1DI)=0D + Store(LCP1, ECP1)=0D + }=0D + ElseIf (LEqual(Arg0, 2)) //PEG11=0D + {=0D + Store(LCT2, ELC2)=0D + Store(S2VI, H2VI)=0D + Store(S2DI, H2DI)=0D + Store(LCP2, ECP2)=0D + }=0D + ElseIf (LEqual(Arg0, 3)) //PEG12=0D + {=0D + Store(LCT3, ELC3)=0D + Store(S3VI, H3VI)=0D + Store(S3DI, H3DI)=0D + Store(LCP3, ECP3)=0D + }=0D +=0D + //\_SB.PC00.PEG0.SAVR()=0D +=0D + // Put link in L2=0D + RTDS()=0D +=0D + /// assert CLK_REQ MSK=0D + ///=0D + /// On RTD3 entry, BIOS will instruct the PMC to disable source cloc= ks.=0D + /// This is done through sending a PMC IPC command.=0D + ///=0D + PGSC(Arg0, 0)=0D +=0D + //Power-off the Endpoint=0D + GPPR(PIOF, 0)=0D + //Method to set Wake GPIO ownership from GPIO to ACPI for Device Ini= tiated RTD3=0D + DIWK(PIOF)=0D +=0D + Return ()=0D + } // End of Method(PGOF,1,Serialized)=0D +=0D +=0D + //=0D + // Name: GDEV=0D + // Description: Function to return the PEG device no for the given PEG= index=0D + // Input: Arg0 -> PEG index=0D + // Return: PEG device no for the given PEG index=0D + //=0D + Method(GDEV,1)=0D + {=0D + If(LEqual(Arg0, 0))=0D + {=0D + Store(0x6, Local0) //Device6-Function0 =3D 00110.000=0D + }=0D + ElseIf(LEqual(Arg0, 1))=0D + {=0D + Store(0x1, Local0) //Device1-Function0 =3D 00001.000=0D + }=0D + ElseIf(LEqual(Arg0, 2))=0D + {=0D + Store(0x1, Local0) //Device1-Function2 =3D 00001.001=0D + }=0D + ElseIf(LEqual(Arg0, 3))=0D + {=0D + Store(0x1, Local0) //Device1-Function3 =3D 00001.010=0D + }=0D +=0D + Return(Local0)=0D + } // End of Method(GDEV,1)=0D +=0D + //=0D + // Name: GFUN=0D + // Description: Function to return the PEG function no for the given P= EG index=0D + // Input: Arg0 -> PEG index=0D + // Return: PEG function no for the given PEG index=0D + //=0D + Method(GFUN,1)=0D + {=0D + If(LEqual(Arg0, 0))=0D + {=0D + Store(0x0, Local0) //Device6-Function0 =3D 00110.000=0D + }=0D + ElseIf(LEqual(Arg0, 1))=0D + {=0D + Store(0x0, Local0) //Device1-Function0 =3D 00001.000=0D + }=0D + ElseIf(LEqual(Arg0, 2))=0D + {=0D + Store(0x1, Local0) //Device1-Function1 =3D 00001.001=0D + }=0D + ElseIf(LEqual(Arg0, 2))=0D + {=0D + Store(0x2, Local0) //Device1-Function2 =3D 00001.010=0D + }=0D +=0D + Return(Local0)=0D + } // End of Method(GFUN,1)=0D +=0D + //=0D + // Name: CCHK=0D + // Description: Function to check whether _ON/_OFF sequence is allowed= to execute for the given PEG controller or not=0D + // Input: Arg0 -> PEG index=0D + // Arg1 -> 0 means _OFF sequence, 1 means _ON sequence=0D + // Return: 0 - Don't execute the flow, 1 - Execute the flow=0D + //=0D + Method(CCHK,2)=0D + {=0D +=0D + //Check for Referenced PEG controller is present or not=0D + If(LEqual(Arg0, 0))=0D + {=0D + Store(P0VI, Local7)=0D + }=0D + ElseIf(LEqual(Arg0, 1))=0D + {=0D + Store(P1VI, Local7)=0D + }=0D + ElseIf(LEqual(Arg0, 2))=0D + {=0D + Store(P2VI, Local7)=0D + }=0D + ElseIf(LEqual(Arg0, 3))=0D + {=0D + Store(P3VI, Local7)=0D + }=0D +=0D + If(LEqual(Local7, IVID))=0D + {=0D + Return(0)=0D + }=0D +=0D + If(LNotEqual(Arg0, 1))=0D + {=0D + //Check for PEG10 controller presence=0D + Store(P1VI, Local7)=0D + If(LEqual(Local7, IVID))=0D + {=0D + Return(0)=0D + }=0D + }=0D +=0D + //If Endpoint is not present[already disabled] before executing PGOF= then don't call the PGOF method=0D + //If Endpoint is present[already enabled] before executing PGON then= don't call the PGON method=0D + If(LEqual(Arg1, 0))=0D + {=0D + //_OFF sequence condition check=0D + If(LEqual(Arg0, 0))=0D + {=0D + If(LEqual(SGPI(SGGP, PWE0, PWG0, PWA0), 0))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 1))=0D + {=0D + If(LEqual(SGPI(P1GP, PWE1, PWG1, PWA1), 0))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 2))=0D + {=0D + If(LEqual(SGPI(P2GP, PWE2, PWG2, PWA2), 0))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 3))=0D + {=0D + If(LEqual(SGPI(P3GP, PWE3, PWG3, PWA3), 0))=0D + {=0D + Return(0)=0D + }=0D + }=0D + }=0D + ElseIf(LEqual(Arg1, 1))=0D + {=0D + //_ON sequence condition check=0D + If(LEqual(Arg0, 0))=0D + {=0D + If(LEqual(SGPI(SGGP, PWE0, PWG0, PWA0), 1))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 1))=0D + {=0D + If(LEqual(SGPI(P1GP, PWE1, PWG1, PWA1), 1))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 2))=0D + {=0D + If(LEqual(SGPI(P2GP, PWE2, PWG2, PWA2), 1))=0D + {=0D + Return(0)=0D + }=0D + }=0D + If(LEqual(Arg0, 3))=0D + {=0D + If(LEqual(SGPI(P3GP, PWE3, PWG3, PWA3), 1))=0D + {=0D + Return(0)=0D + }=0D + }=0D + }=0D +=0D + Return(1)=0D + }=0D +=0D +=0D + //=0D + // Name: SGPI [PCIe GPIO Read]=0D + // Description: Function to Read from PCIe GPIO=0D + // Input: Arg0 -> Gpio Support=0D + // Arg1 -> Expander Number=0D + // Arg2 -> Gpio Number=0D + // Arg3 -> Active Information=0D + // Return: GPIO value=0D + //=0D + Method(SGPI, 4, Serialized)=0D + {=0D + If (LEqual(Arg0, 0x01))=0D + {=0D + //=0D + // PCH based GPIO=0D + //=0D + If (CondRefOf(\_SB.GGOV))=0D + {=0D + Store(\_SB.GGOV(Arg2), Local0)=0D + }=0D + }=0D + //=0D + // Invert if Active Low=0D + //=0D + If (LEqual(Arg3,0))=0D + {=0D + Not(Local0, Local0)=0D + And (Local0, 0x01, Local0)=0D + }=0D +=0D + Return(Local0)=0D + }// End of Method(SGPI)=0D +=0D + // Name: PGSC [PEG port source clock control]=0D + // Description: Function to enable/disable PEG port source clocks=0D + // Input: Arg0 -> PEG index=0D + // Arg1 -> Enable/Disable Clock (0 =3D Disable, 1 =3D Enable)=0D + // Return: Nothing=0D + //=0D +=0D + Method(PGSC, 2, Serialized)=0D + {=0D + If(LEqual(Arg0, 0)) { // PEG0=0D + Store (P0SC, Local0)=0D + } ElseIf(LEqual(Arg0, 1)) { // PEG1=0D + Store (P1SC, Local0)=0D + } ElseIf(LEqual(Arg0, 2)) { // PEG2=0D + Store (P2SC, Local0)=0D + } ElseIf(LEqual(Arg0, 3)) {// PEG3=0D + Store (P3SC, Local0)=0D + } Else {=0D + Return()=0D + }=0D +=0D + SPCO (Local0, Arg1)=0D + }// End of Method(PGSC)=0D +=0D + //=0D + // Name: GPPR=0D + // Description: Function to do Endpoint ON/OFF using GPIOs=0D + // There are two GPIOs currently used to control Third Pa= rty Vendor[TPV] DGPU Endpoint devices:=0D + // (1) DGPU_PWR_EN [used for Power control]=0D + // (2) DGPU_HOLD_RST[used for Reset control]=0D + // Input: Arg0 -> PEG index=0D + // Arg1 -> 0 means _OFF sequence, 1 means _ON sequence=0D + // Return: Nothing=0D + //=0D + Method(GPPR,2)=0D + {=0D +=0D + If(LEqual(Arg1, 0))=0D + {=0D + //_OFF sequence GPIO programming=0D + If(LEqual(Arg0, 0))=0D + {=0D + SGPO(SGGP, HRE0, HRG0, HRA0, 1) // Assert PCIe0/dGPU_HOLD_RST# (= PERST#)=0D + //Sleep(DLHR) // As per the PCIe spec, Wait = for 'given'ms after Assert the Reset=0D + SGPO(SGGP, PWE0, PWG0, PWA0, 0) // Deassert PCIe0/dGPU_PWR_EN#=0D + }=0D +=0D + If(LEqual(Arg0, 1))=0D + {=0D + SGPO(P1GP, HRE1, HRG1, HRA1, 1) // Assert PCIe1_HOLD_RST# (PERST= #)=0D + //Sleep(DLHR) // As per the PCIe spec, Wait = for 'given'ms after Assert the Reset=0D + SGPO(P1GP, PWE1, PWG1, PWA1, 0) // Deassert PCIe1_PWR_EN#=0D + }=0D +=0D + If(LEqual(Arg0, 2))=0D + {=0D + SGPO(P2GP, HRE2, HRG2, HRA2, 1) // Assert PCIe2_HOLD_RST# (PERST= #)=0D + //Sleep(DLHR) // As per the PCIe spec, Wait = for 'given'ms after Assert the Reset=0D + SGPO(P2GP, PWE2, PWG2, PWA2, 0) // Deassert PCIe2_PWR_EN#=0D + }=0D +=0D + If(LEqual(Arg0, 3))=0D + {=0D + SGPO(P3GP, HRE3, HRG3, HRA3, 1) // Assert PCIe3_HOLD_RST# (PERST= #)=0D + //Sleep(DLHR) // As per the PCIe spec, Wait = for 'given'ms after Assert the Reset=0D + SGPO(P3GP, PWE3, PWG3, PWA3, 0) // Deassert PCIe2_PWR_EN#=0D + }=0D + }=0D + ElseIf(LEqual(Arg1, 1))=0D + {=0D + //_ON sequence GPIO programming=0D + If(LEqual(Arg0, 0))=0D + {=0D + SGPO(SGGP, PWE0, PWG0, PWA0, 1) //Assert dGPU_PWR_EN#=0D +=0D + //Sleep(DLPW) // Wait for 'given'ms for power to get stable=0D + SGPO(SGGP, HRE0, HRG0, HRA0, 0) //Deassert dGPU_HOLD_RST# as per= the PCIe spec=0D +=0D + //Sleep(DLHR) // Wait for 'given'ms after Deassert=0D + }=0D +=0D + If(LEqual(Arg0, 1))=0D + {=0D + SGPO(P1GP, PWE1, PWG1, PWA1, 1) //Assert dGPU_PWR_EN#=0D +=0D + //Sleep(DLPW) // Wait for 'given'ms for power to get stable=0D + SGPO(P1GP, HRE1, HRG1, HRA1, 0) //Deassert dGPU_HOLD_RST# as per= the PCIe spec=0D +=0D + //Sleep(DLHR) // Wait for 'given'ms after Deassert=0D + }=0D +=0D + If(LEqual(Arg0, 2))=0D + {=0D + SGPO(P2GP, PWE2, PWG2, PWA2, 1) //Assert dGPU_PWR_EN#=0D +=0D + //Sleep(DLPW) // Wait for 'given'ms for power to get stable=0D + SGPO(P2GP, HRE2, HRG2, HRA2, 0) //Deassert dGPU_HOLD_RST# as per= the PCIe spec=0D +=0D + //Sleep(DLHR) // Wait for 'given'ms after Deassert=0D + }=0D +=0D + If(LEqual(Arg0, 3))=0D + {=0D + SGPO(P3GP, PWE3, PWG3, PWA3, 1) //Assert dGPU_PWR_EN#=0D +=0D + //Sleep(DLPW) // Wait for 'given'ms for power to get stable=0D + SGPO(P3GP, HRE3, HRG3, HRA3, 0) //Deassert dGPU_HOLD_RST# as per= the PCIe spec=0D +=0D + //Sleep(DLHR) // Wait for 'given'ms after Deassert=0D + }=0D + }=0D + } // End of Method(GPPR,2)=0D +=0D + //=0D + // Name: SGPO [PCIe GPIO Write]=0D + // Description: Function to write into PCIe GPIO=0D + // Input: Arg0 -> Gpio Support=0D + // Arg1 -> Expander Number=0D + // Arg2 -> Gpio Number=0D + // Arg3 -> Active Information=0D + // Arg4 -> Value to write=0D + // Return: Nothing=0D + //=0D +=0D + Method(SGPO, 5, Serialized)=0D + {=0D + //=0D + // Invert if Active Low=0D + //=0D + If (LEqual(Arg3,0))=0D + {=0D + Not(Arg4, Arg4)=0D + And(Arg4, 0x01, Arg4)=0D + }=0D + If (LEqual(Arg0, 0x01))=0D + {=0D + //=0D + // PCH based GPIO=0D + //=0D + If (CondRefOf(\_SB.SGOV))=0D + {=0D + \_SB.SGOV(Arg2, Arg4)=0D + }=0D + }=0D + } // End of Method(SGPO)=0D +=0D + //=0D + // Name: DIWK=0D + // Description: Function which set the GPIO ownership to ACPI for devi= ce initiated RTD3=0D + // Input: PEG Index=0D + // Return: Nothing=0D + //=0D + Method(DIWK,1)=0D + {=0D + If (LEqual(Arg0, 0))=0D + {=0D + \_SB.PC00.PEG0.P0EW()=0D + }=0D + ElseIf (LEqual(Arg0, 1))=0D + {=0D + \_SB.PC00.PEG1.P1EW()=0D + }=0D + ElseIf (LEqual(Arg0, 2))=0D + {=0D + \_SB.PC00.PEG2.P2EW()=0D + }=0D + ElseIf (LEqual(Arg0, 3))=0D + {=0D + \_SB.PC00.PEG3.P3EW()=0D + }=0D + }=0D + }// End of Scope (\_SB.PC00)=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/PegRtd3.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/Sa= Ssdt/PegRtd3.asl new file mode 100644 index 0000000000..b5d1a4e35e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/PegRt= d3.asl @@ -0,0 +1,124 @@ +/** @file=0D + This file contains the device definitions of the SystemAgent=0D + PCIE ACPI Reference Code.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +Scope (\_SB.PC00) {=0D +=0D + OperationRegion(PXCS,PCI_Config,0x00,0x480)=0D + Field(PXCS,AnyAcc, NoLock, Preserve)=0D + {=0D + Offset(0),=0D + VDID, 32,=0D + Offset(0x50), // LCTL - Link Control Register=0D + L0SE, 1, // 0, L0s Entry Enabled=0D + , 3,=0D + LDIS, 1,=0D + , 3,=0D + Offset(0x52), // LSTS - Link Status Register=0D + , 13,=0D + LASX, 1, // 0, Link Active Status=0D + Offset(0x5A), // SLSTS[7:0] - Slot Status Register=0D + ABPX, 1, // 0, Attention Button Pressed=0D + , 2,=0D + PDCX, 1, // 3, Presence Detect Changed=0D + , 2,=0D + PDSX, 1, // 6, Presence Detect State=0D + , 1,=0D + Offset(0x60), // RSTS - Root Status Register=0D + , 16,=0D + PSPX, 1, // 16, PME Status=0D + Offset(0xA4),=0D + D3HT, 2, // Power State=0D + Offset(0xD8), // 0xD8, MPC - Miscellaneous Port Configuration Register= =0D + , 30,=0D + HPEX, 1, // 30, Hot Plug SCI Enable=0D + PMEX, 1, // 31, Power Management SCI Enable=0D + Offset(0xE0), // 0xE0, SPR - Scratch Pad Register=0D + , 0,=0D + SCB0, 1, // Sticky Scratch Pad Bit SCB0=0D + Offset(0xE2), // 0xE2, RPPGEN - Root Port Power Gating Enable=0D + , 2,=0D + L23E, 1, // 2, L23_Rdy Entry Request (L23ER)=0D + L23R, 1, // 3, L23_Rdy to Detect Transition (L23R2DT)=0D + Offset(0x324), // 0x324 - PCIEDBG=0D + , 3,=0D + LEDM, 1, // PCIEDBG.DMIL1EDM=0D + Offset(0x328), // 0x328 - PCIESTS1=0D + , 24,=0D + LTSM, 8,=0D + }=0D + Field(PXCS,AnyAcc, NoLock, WriteAsZeros)=0D + {=0D + Offset(0xDC), // 0xDC, SMSCS - SMI/SCI Status Register=0D + , 30,=0D + HPSX, 1, // 30, Hot Plug SCI Status=0D + PMSX, 1 // 31, Power Management SCI Status=0D + }=0D +=0D + //=0D + // Name: RTEN=0D + // Description: Function to Enable the link for RTD3 [RCTL.L22DT]=0D + // Input: PEG Index=0D + // Return: Nothing=0D + //=0D + Method(RTEN, 0, Serialized)=0D + {=0D + If (LNotEqual (SCB0,0x1)) {=0D + Return ()=0D + }=0D +=0D + /// Set L23_Rdy to Detect Transition (L23R2DT)=0D + Store(1, L23R)=0D + Store(0, Local0)=0D + /// Wait for transition to Detect=0D + While(L23R) {=0D + If(Lgreater(Local0, 4))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + Store(0,SCB0)=0D +=0D + /// Once in Detect, wait up to 124 ms for Link Active (typically hap= pens in under 70ms)=0D + /// Worst case per PCIe spec from Detect to Link Active is:=0D + /// 24ms in Detect (12+12), 72ms in Polling (24+48), 28ms in Config = (24+2+2+2+2)=0D + Store(0, Local0)=0D + While(LEqual(LASX,0)) {=0D + If(Lgreater(Local0, 8))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + }=0D +=0D + //=0D + // Name: RTDS=0D + // Description: Function to Disable link for RTD3 [RCTL.L23ER]=0D + // Input: PEG Index=0D + // Return: Nothing=0D + //=0D + Method(RTDS, 0, Serialized)=0D + {=0D + Store(1, L23E)=0D + Sleep(16)=0D + Store(0, Local0)=0D + While(L23E) {=0D + If(Lgreater(Local0, 4))=0D + {=0D + Break=0D + }=0D + Sleep(16)=0D + Increment(Local0)=0D + }=0D + Store(1,SCB0)=0D + }=0D +=0D +} // End of Scope (\_SB.PC00)=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/Sa.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/= Sa.asl new file mode 100644 index 0000000000..5228d9d753 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/Sa.asl @@ -0,0 +1,26 @@ +/** @file=0D + This file contains the device definition of the System Agent=0D + ACPI reference code.=0D + Currently defines the device objects for the=0D + System Agent PCI Express* ports (PEG), iGfx and other devices.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +External(\HGMD)=0D +External(\HGST)=0D +External(\_SB.PC00, DeviceObj)=0D +External(\_SB.PC00.GFX0, DeviceObj)=0D +External(\_SB.PC00.IPU0, DeviceObj)=0D +External(\_SB.PC00.B0D3, DeviceObj)=0D +External(\_SB.PC00.PCIC, MethodObj)=0D +External(\_SB.PC00.PCID, MethodObj)=0D +///=0D +/// CPU PCIe Root Port=0D +///=0D +include("CpuPcieRp.asl")=0D +include("PegCommon.asl")=0D +If(LAnd((LEqual(HGMD,2)), (LEqual(HGST,1)))) {=0D + include("PegRtd3.asl")=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/SaSsdt.asl b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaS= sdt/SaSsdt.asl new file mode 100644 index 0000000000..0494c659e0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsd= t.asl @@ -0,0 +1,20 @@ +/** @file=0D + This file contains the SystemAgent SSDT Table ASL code.=0D + It defines a Global NVS table which exchanges datas between OS=0D + and BIOS.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +DefinitionBlock (=0D + "SaSsdt.aml",=0D + "SSDT",=0D + 0x02,=0D + "SaSsdt",=0D + "SaSsdt ",=0D + 0x3000=0D + )=0D +{=0D + Include ("Sa.asl")=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsd= t/SaSsdt.inf b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaS= sdt/SaSsdt.inf new file mode 100644 index 0000000000..d0d1494b99 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/AcpiTables/SaSsdt/SaSsd= t.inf @@ -0,0 +1,22 @@ +## @file=0D +# Component description file for the ACPI tables=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010005=0D +BASE_NAME =3D SaSsdt=0D +FILE_GUID =3D ca89914d-2317-452e-b245-36c6fb77a9c6=0D +MODULE_TYPE =3D USER_DEFINED=0D +VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + SaSsdt.asl=0D +=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLib.c b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Lib= rary/DxeSaPolicyLib/DxeSaPolicyLib.c new file mode 100644 index 0000000000..e1569e7f32 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= DxeSaPolicyLib.c @@ -0,0 +1,254 @@ +/** @file=0D + This file provide services for DXE phase policy default initialization=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "DxeSaPolicyLibrary.h"=0D +#include =0D +#include =0D +#include =0D +=0D +extern EFI_GUID gMemoryDxeConfigGuid;=0D +extern EFI_GUID gPcieDxeConfigGuid;=0D +=0D +/**=0D + This function prints the SA DXE phase policy.=0D +=0D + @param[in] SaPolicy - SA DXE Policy protocol=0D +**/=0D +VOID=0D +SaPrintPolicyProtocol (=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + PCIE_DXE_CONFIG *PcieDxeConfig;=0D + MEMORY_DXE_CONFIG *MemoryDxeConfig;=0D +=0D + //=0D + // Get requisite IP Config Blocks which needs to be used here=0D + //=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gPcieDxeConfigGuid, (VOID= *)&PcieDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gMemoryDxeConfigGuid, (VO= ID *)&MemoryDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D +=0D + DEBUG_CODE_BEGIN ();=0D + INTN i;=0D +=0D + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print BE= GIN -----------------\n"));=0D + DEBUG ((DEBUG_INFO, "Revision : %x\n", SaPolicy->TableHeader.Header.Revi= sion));=0D + ASSERT (SaPolicy->TableHeader.Header.Revision =3D=3D SA_POLICY_PROTOCOL_= REVISION);=0D +=0D + DEBUG ((DEBUG_INFO, "------------------------ SA_MEMORY_CONFIGURATION --= ---------------\n"));=0D +=0D + DEBUG ((DEBUG_INFO, " SpdAddressTable[%d] :", 4));=0D + for (i =3D 0; i < 4; i++) {=0D + DEBUG ((DEBUG_INFO, " %x", MemoryDxeConfig->SpdAddressTable[i]));=0D + }=0D + DEBUG ((DEBUG_INFO, "\n"));=0D +=0D + DEBUG ((DEBUG_INFO, " ChannelASlotMap : %x\n", MemoryDxeConfig->ChannelA= SlotMap));=0D + DEBUG ((DEBUG_INFO, " ChannelBSlotMap : %x\n", MemoryDxeConfig->ChannelB= SlotMap));=0D + DEBUG ((DEBUG_INFO, " MrcTimeMeasure : %x\n", MemoryDxeConfig->MrcTimeM= easure));=0D + DEBUG ((DEBUG_INFO, " MrcFastBoot : %x\n", MemoryDxeConfig->MrcFastB= oot));=0D +=0D + DEBUG ((DEBUG_INFO, "------------------------ CPU_PCIE_CONFIGURATION ---= --------------\n"));=0D + DEBUG ((DEBUG_INFO, " PegAspm[%d] :", SA_PEG_MAX_FUN));=0D + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) {=0D + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegAspm[i]));=0D + }=0D + DEBUG ((DEBUG_INFO, "\n"));=0D +=0D + DEBUG ((DEBUG_INFO, " PegRootPortHPE[%d] :", SA_PEG_MAX_FUN));=0D + for (i =3D 0; i < SA_PEG_MAX_FUN; i++) {=0D + DEBUG ((DEBUG_INFO, " %x", PcieDxeConfig->PegRootPortHPE[i]));=0D + }=0D + DEBUG ((DEBUG_INFO, "\n"));=0D +=0D +=0D + DEBUG ((DEBUG_INFO, "\n------------------------ SA Policy (DXE) print EN= D -----------------\n"));=0D + DEBUG_CODE_END ();=0D +=0D + return;=0D +}=0D +=0D +/**=0D + Load DXE Config block default for PCIe=0D +=0D + @param[in] ConfigBlockPointer Pointer to config block=0D +**/=0D +VOID=0D +LoadPcieDxeDefault (=0D + IN VOID *ConfigBlockPointer=0D + )=0D +{=0D + UINT8 Index;=0D + PCIE_DXE_CONFIG *PcieDxeConfig;=0D +=0D + PcieDxeConfig =3D ConfigBlockPointer;=0D + DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Name =3D %g\n", &Pcie= DxeConfig->Header.GuidHob.Name));=0D + DEBUG ((DEBUG_INFO, "PcieDxeConfig->Header.GuidHob.Header.HobLength =3D = 0x%x\n", PcieDxeConfig->Header.GuidHob.Header.HobLength));=0D + ///=0D + /// Initialize the PCIE Configuration=0D + /// PEG ASPM per port configuration. 4 PEG controllers i.e. 0,1,2,3=0D + ///=0D + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) {=0D + PcieDxeConfig->PegAspm[Index] =3D CpuPcieAspmAutoConfig;=0D + }=0D +=0D + for (Index =3D 0; Index < SA_PEG_MAX_FUN; Index++) {=0D + PcieDxeConfig->PegPwrOpt[Index].LtrEnable =3D 1;=0D + PcieDxeConfig->PegPwrOpt[Index].LtrMaxSnoopLatency =3D V_SA_LTR_MAX_= SNOOP_LATENCY_VALUE;=0D + PcieDxeConfig->PegPwrOpt[Index].LtrMaxNoSnoopLatency =3D V_SA_LTR_MAX_= NON_SNOOP_LATENCY_VALUE;=0D + PcieDxeConfig->PegPwrOpt[Index].ObffEnable =3D 1;=0D + }=0D +}=0D +=0D +=0D +/**=0D + Load DXE Config block default=0D +=0D + @param[in] ConfigBlockPointer Pointer to config block=0D +**/=0D +VOID=0D +LoadMemoryDxeDefault (=0D + IN VOID *ConfigBlockPointer=0D + )=0D +{=0D + MEMORY_DXE_CONFIG *MemoryDxeConfig;=0D +=0D + MemoryDxeConfig =3D ConfigBlockPointer;=0D + DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Name =3D %g\n", &Me= moryDxeConfig->Header.GuidHob.Name));=0D + DEBUG ((DEBUG_INFO, "MemoryDxeConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", MemoryDxeConfig->Header.GuidHob.Header.HobLength));=0D + ///=0D + /// Initialize the Memory Configuration=0D + ///=0D + ///=0D + /// DIMM SMBus addresses info=0D + /// Refer to the SpdAddressTable[] mapping rule in DxeSaPolicyLibrary.h= =0D + ///=0D + MemoryDxeConfig->SpdAddressTable =3D AllocateZeroPool (sizeof (UINT8) * = 4);=0D + ASSERT (MemoryDxeConfig->SpdAddressTable !=3D NULL);=0D + if (MemoryDxeConfig->SpdAddressTable !=3D NULL) {=0D + MemoryDxeConfig->SpdAddressTable[0] =3D DIMM_SMB_SPD_P0C0D0;=0D + MemoryDxeConfig->SpdAddressTable[1] =3D DIMM_SMB_SPD_P0C0D1;=0D + MemoryDxeConfig->SpdAddressTable[2] =3D DIMM_SMB_SPD_P0C1D0;=0D + MemoryDxeConfig->SpdAddressTable[3] =3D DIMM_SMB_SPD_P0C1D1;=0D + }=0D + MemoryDxeConfig->ChannelASlotMap =3D 0x01;=0D + MemoryDxeConfig->ChannelBSlotMap =3D 0x01;=0D +}=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED COMPONENT_BLOCK_ENTRY mSaDxeIpBlocks [] =3D= {=0D + {&gPcieDxeConfigGuid, sizeof (PCIE_DXE_CONFIG), PCIE_DXE_CONFIG_= REVISION, LoadPcieDxeDefault},=0D + {&gMemoryDxeConfigGuid, sizeof (MEMORY_DXE_CONFIG), MEMORY_DXE_CONFI= G_REVISION, LoadMemoryDxeDefault}=0D +};=0D +=0D +=0D +/**=0D + CreateSaDxeConfigBlocks generates the config blocks of SA DXE Policy.=0D + It allocates and zero out buffer, and fills in the Intel default setting= s.=0D +=0D + @param[out] SaPolicy The pointer to get SA DXE Protocol i= nstance=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +CreateSaDxeConfigBlocks (=0D + IN OUT SA_POLICY_PROTOCOL **SaPolicy=0D + )=0D +{=0D + UINT16 TotalBlockSize;=0D + EFI_STATUS Status;=0D + SA_POLICY_PROTOCOL *SaInitPolicy;=0D + UINT16 RequiredSize;=0D +=0D + DEBUG ((DEBUG_INFO, "SA Create Dxe Config Blocks\n"));=0D +=0D + SaInitPolicy =3D NULL;=0D +=0D + TotalBlockSize =3D GetComponentConfigBlockTotalSize (&mSaDxeIpBlocks[0],= sizeof (mSaDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));=0D + TotalBlockSize +=3D VtdGetConfigBlockTotalSizeDxe ();=0D + TotalBlockSize +=3D GraphicsGetConfigBlockTotalSizeDxe ();=0D + DEBUG ((DEBUG_INFO, "TotalBlockSize =3D 0x%x\n", TotalBlockSize));=0D +=0D + RequiredSize =3D sizeof (CONFIG_BLOCK_TABLE_HEADER) + TotalBlockSize;=0D +=0D + Status =3D CreateConfigBlockTable (RequiredSize, (VOID *) &SaInitPolicy)= ;=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Initialize Policy Revision=0D + //=0D + SaInitPolicy->TableHeader.Header.Revision =3D SA_POLICY_PROTOCOL_REVISIO= N;=0D + //=0D + // Add config blocks.=0D + //=0D + Status =3D AddComponentConfigBlocks ((VOID *) SaInitPolicy, &mSaDxeIpBl= ocks[0], sizeof (mSaDxeIpBlocks) / sizeof (COMPONENT_BLOCK_ENTRY));=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + // Vtd=0D + Status =3D VtdAddConfigBlocksDxe((VOID *) SaInitPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + // Gfx=0D + Status =3D GraphicsAddConfigBlocksDxe ((VOID *) SaInitPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Assignment for returning SaInitPolicy config block base address=0D + //=0D + *SaPolicy =3D SaInitPolicy;=0D + return Status;=0D +}=0D +=0D +=0D +/**=0D + SaInstallPolicyProtocol installs SA Policy.=0D + While installed, RC assumes the Policy is ready and finalized. So please= update and override=0D + any setting before calling this function.=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D + @param[in] SaPolicy The pointer to SA Policy Protocol = instance=0D +=0D + @retval EFI_SUCCESS The policy is installed.=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SaInstallPolicyProtocol (=0D + IN EFI_HANDLE ImageHandle,=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + ///=0D + /// Print SA DXE Policy=0D + ///=0D + SaPrintPolicyProtocol (SaPolicy);=0D + GraphicsDxePolicyPrint (SaPolicy);=0D + VtdPrintPolicyDxe (SaPolicy);=0D +=0D + ///=0D + /// Install protocol to to allow access to this Policy.=0D + ///=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &ImageHandle,=0D + &gSaPolicyProtocolGuid,=0D + SaPolicy,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/L= ibrary/DxeSaPolicyLib/DxeSaPolicyLib.inf new file mode 100644 index 0000000000..8af3d09b80 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= DxeSaPolicyLib.inf @@ -0,0 +1,48 @@ +## @file=0D +# Component description file for the PeiSaPolicy library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeSaPolicyLib=0D +FILE_GUID =3D B402A3A4-4B82-410E-B79C-5914880A05E7=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D DxeSaPolicyLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseMemoryLib=0D +UefiRuntimeServicesTableLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +PostCodeLib=0D +ConfigBlockLib=0D +HobLib=0D +DxeGraphicsPolicyLib=0D +DxeVtdPolicyLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +DxeSaPolicyLib.c=0D +DxeSaPolicyLibrary.h=0D +=0D +=0D +[Guids]=0D +gPcieDxeConfigGuid=0D +gMemoryDxeConfigGuid=0D +=0D +=0D +[Protocols]=0D +gSaPolicyProtocolGuid ## PRODUCES=0D +=0D +[Pcd]=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPol= icyLib/DxeSaPolicyLibrary.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent= /Library/DxeSaPolicyLib/DxeSaPolicyLibrary.h new file mode 100644 index 0000000000..2f64e6eb0d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/DxeSaPolicyLib/= DxeSaPolicyLibrary.h @@ -0,0 +1,33 @@ +/** @file=0D + Header file for the DxeSaPolicy library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DXE_SA_POLICY_LIBRARY_H_=0D +#define _DXE_SA_POLICY_LIBRARY_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define WORD_FIELD_VALID_BIT BIT15=0D +#define MAX_PCIE_ASPM_OVERRIDE 500=0D +#define MAX_PCIE_LTR_OVERRIDE 500=0D +///=0D +/// DIMM SMBus addresses=0D +///=0D +#define DIMM_SMB_SPD_P0C0D0 0xA0=0D +#define DIMM_SMB_SPD_P0C0D1 0xA2=0D +#define DIMM_SMB_SPD_P0C1D0 0xA4=0D +#define DIMM_SMB_SPD_P0C1D1 0xA6=0D +#define DIMM_SMB_SPD_P0C0D2 0xA8=0D +#define DIMM_SMB_SPD_P0C1D2 0xAA=0D +=0D +#endif // _DXE_SA_POLICY_LIBRARY_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSm= mSaPlatformLib/PeiDxeSmmSaPlatformLib.inf b/Silicon/Intel/TigerlakeSiliconP= kg/SystemAgent/Library/PeiDxeSmmSaPlatformLib/PeiDxeSmmSaPlatformLib.inf new file mode 100644 index 0000000000..0a632fc81a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlat= formLib/PeiDxeSmmSaPlatformLib.inf @@ -0,0 +1,32 @@ +## @file=0D +# Component description file for SA Platform Lib=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmSaPlatformLib=0D +FILE_GUID =3D 9DB5ACB4-DB23-43AE-A283-2ABEF365CBE0=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D SaPlatformLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +BaseMemoryLib=0D +DebugLib=0D +IoLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +SaPlatformLibrary.h=0D +SaPlatformLibrary.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSm= mSaPlatformLib/SaPlatformLibrary.c b/Silicon/Intel/TigerlakeSiliconPkg/Syst= emAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.c new file mode 100644 index 0000000000..42902d795c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlat= formLib/SaPlatformLibrary.c @@ -0,0 +1,68 @@ +/** @file=0D + SA Platform Lib implementation.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include "SaPlatformLibrary.h"=0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + Checks if SKU is Mobile=0D +=0D + @retval FALSE SKU is not Mobile=0D + @retval TRUE SKU is Mobile=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsMobileSku (=0D + VOID=0D + )=0D +{=0D + UINT16 DeviceId;=0D +=0D + DeviceId =3D PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_M= C_BUS, SA_MC_DEV, SA_MC_FUN, R_SA_MC_DEVICE_ID));=0D + if (=0D + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULT_1) || \=0D + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULT_2) || \=0D + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULX_1) || \=0D + (DeviceId =3D=3D V_SA_DEVICE_ID_MB_ULX_2) \=0D + ) {=0D + return TRUE;=0D + }=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if SKU is Desktop=0D +=0D + @retval FALSE SKU is not Desktop=0D + @retval TRUE SKU is Desktop=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsDesktopSku (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if SKU is Server=0D +=0D + @retval FALSE SKU is not Server=0D + @retval TRUE SKU is Server=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsServerSku (=0D + VOID=0D + )=0D +{=0D + return FALSE;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSm= mSaPlatformLib/SaPlatformLibrary.h b/Silicon/Intel/TigerlakeSiliconPkg/Syst= emAgent/Library/PeiDxeSmmSaPlatformLib/SaPlatformLibrary.h new file mode 100644 index 0000000000..10513d0ea0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Library/PeiDxeSmmSaPlat= formLib/SaPlatformLibrary.h @@ -0,0 +1,21 @@ +/** @file=0D + Header file for SA Platform Lib implementation.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_=0D +#define _SA_PLATFORM_LIBRARY_IMPLEMENTATION_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#endif=0D --=20 2.24.0.windows.2