From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [Patch V2 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files
Date: Thu, 4 Feb 2021 16:49:17 +0800 [thread overview]
Message-ID: <20210204084919.3603-38-heng.luo@intel.com> (raw)
In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following DSC files:
* Fru/TglCpu
* Fru/TglPch
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc | 11 +++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc | 9 +++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc | 20 ++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc | 8 ++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc | 7 +++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc | 30 ++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc | 9 +++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc | 13 +++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc | 8 ++++++++
Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc | 10 ++++++++++
10 files changed, 125 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc
new file mode 100644
index 0000000000..99ee0eccac
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/CommonLib.dsc
@@ -0,0 +1,11 @@
+## @file
+# Component description file for the TigerLake CPU Common FRU libraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+VtdInfoLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/Library/PeiDxeSmmVtdInfoLib/PeiDxeSmmVtdInfoLib.inf
+CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDxeSmmCpuPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf
+CpuPcieInfoFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CpuPcieRp/Library/PeiDxeSmmCpuPcieInfoFruLib/PeiDxeSmmCpuPcieInfoFruLib.inf
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc
new file mode 100644
index 0000000000..874e4cbaad
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Dxe.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the Tigerlake CPU DXE FRU drivers.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc
new file mode 100644
index 0000000000..5c72c2ac61
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/DxeLib.dsc
@@ -0,0 +1,20 @@
+## @file
+# Component description file for the Tigerlake CPU DXE FRU libraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+DxeGraphicsPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf
+DxeGraphicsInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeGraphicsInitLib/DxeGraphicsInitLib.inf
+DxeIgdOpRegionInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf
+DxeVtdInitLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitLib.inf
+DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdPolicyLib/DxeVtdPolicyLib.inf
+DxeVtdInitFruLib|$(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Vtd/LibraryPrivate/DxeVtdInitLib/DxeVtdInitFruLib.inf
+
+
+#
+# CPU PCIe IpBlock
+#
+DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryPrivate/DxeCpuPcieRpLib/DxeCpuPcieRpLib.inf
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc
new file mode 100644
index 0000000000..de8288364a
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Pei.dsc
@@ -0,0 +1,8 @@
+## @file
+# Component description file for the Tigerlake CPU PEI FRU drivers.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc
new file mode 100644
index 0000000000..5355ecb288
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/PeiLib.dsc
@@ -0,0 +1,7 @@
+## @file
+# Component description file for the Tigerlake CPU PEI FRU ibraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc
new file mode 100644
index 0000000000..b7ba1f752c
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/CommonLib.dsc
@@ -0,0 +1,30 @@
+## @file
+# Component description file for the Tigerlake PCH Common FRU libraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+ PsfLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxeSmmPsfLibVer2.inf
+ PchPcrLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmPchPcrLib/PeiDxeSmmPchPcrLib.inf
+ PchSbiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/LibraryPrivate/PeiDxeSmmPchSbiAccessLib/PeiDxeSmmPchSbiAccessLib.inf
+ GbeMdiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gbe/LibraryPrivate/PeiDxeSmmGbeMdiLib/PeiDxeSmmGbeMdiLib.inf
+ GbeLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gbe/Library/PeiDxeSmmGbeLib/PeiDxeSmmGbeLib.inf
+ EspiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Espi/Library/PeiDxeSmmEspiLib/PeiDxeSmmEspiLib.inf
+ PmcLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/Library/PeiDxeSmmPmcLib/PeiDxeSmmPmcLib.inf
+ PmcPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibVer2.inf
+ PmcPrivateLibWithS3|$(PLATFORM_SI_PACKAGE)/IpBlock/Pmc/LibraryPrivate/PeiDxeSmmPmcPrivateLib/PeiDxeSmmPmcPrivateLibWithS3.inf
+ SpiCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/BaseSpiCommonLib/BaseSpiCommonLib.inf
+ GpioLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/PeiDxeSmmGpioLib/PeiDxeSmmGpioLib.inf
+ GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxeSmmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf
+ GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpioCheckConflictLib/BaseGpioCheckConflictLib.inf
+ PchDmiLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiLib.inf
+ PchDmiWithS3Lib|$(PLATFORM_SI_PACKAGE)/IpBlock/PchDmi/LibraryPrivate/PeiDxeSmmPchDmiLib/PeiDxeSmmPchDmiWithS3Lib.inf
+ SataLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf
+ SpiAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Library/PeiDxeSmmSpiAccessLib/PeiDxeSmmSpiAccessLib.inf
+ SpiAccessPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/LibraryPrivate/PeiDxeSmmSpiAccessPrivateLib/PeiDxeSmmSpiAccessPrivateLib.inf
+ PchPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/PeiDxeSmmPchPcieRpLib/PeiDxeSmmPchPcieRpLibVer2.inf
+ PcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PcieClientRpLib/PcieClientRpLib.inf
+ PciExpressHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PciExpressHelpersLibrary/PeiDxeSmmPciExpressHelpersLib.inf
+ BasePcieHelperLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/Library/BasePcieHelperLib/BasePcieHelperLib.inf
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc
new file mode 100644
index 0000000000..9fefc6b4c9
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Dxe.dsc
@@ -0,0 +1,9 @@
+## @file
+# Component description file for the Tigerlake PCH DXE FRU drivers.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+$(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc
new file mode 100644
index 0000000000..e9be448baa
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/DxeLib.dsc
@@ -0,0 +1,13 @@
+## @file
+# Component description file for the Tigerlake PCH DXE FRU libraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+ DxeHdaNhltLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Hda/Library/DxeHdaNhltLib/DxeHdaNhltLib.inf
+ DxeHdaPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Hda/LibraryPrivate/DxeHdaPolicyLib/DxeHdaPolicyLib.inf
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseGpioHelpersLibNull/BaseGpioHelpersLibNull.inf
+ GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/DxeGpioNameBufferLib/DxeGpioNameBufferLib.inf
+ DxeGpioPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/DxeGpioPolicyLib/DxeGpioPolicyLib.inf
+ DxePchPcieRpPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.inf
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc
new file mode 100644
index 0000000000..2eacbe905c
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Pei.dsc
@@ -0,0 +1,8 @@
+## @file
+# Component description file for the Tigerlake PCH PEI FRU drivers.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc
new file mode 100644
index 0000000000..d8e6313084
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/PeiLib.dsc
@@ -0,0 +1,10 @@
+## @file
+# Component description file for the Tigerlake PCH PEI FRU libraries.
+#
+# Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+ GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpioHelpersLib/PeiGpioHelpersLib.inf
+ GpioNameBufferLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiGpioNameBufferLib/PeiGpioNameBufferLib.inf
--
2.24.0.windows.2
next prev parent reply other threads:[~2021-02-04 8:52 UTC|newest]
Thread overview: 47+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-04 8:48 [Patch V2 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-04 8:48 ` [Patch V2 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-05 5:52 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-05 5:53 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-05 5:56 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-05 5:59 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-05 6:21 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-05 7:40 ` Chaganty, Rangasai V
2021-02-04 8:48 ` [Patch V2 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-04 8:48 ` [Patch V2 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-04 8:48 ` [Patch V2 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-04 8:48 ` [Patch V2 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-04 8:48 ` [Patch V2 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-04 8:48 ` [Patch V2 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-04 8:48 ` [Patch V2 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-04 8:48 ` [Patch V2 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-04 8:48 ` [Patch V2 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-04 8:48 ` [Patch V2 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-04 8:48 ` [Patch V2 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-04 8:49 ` [Patch V2 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-04 8:49 ` [Patch V2 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-04 8:49 ` [Patch V2 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-04 8:49 ` [Patch V2 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-04 8:49 ` [Patch V2 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-04 8:49 ` [Patch V2 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-04 8:49 ` [Patch V2 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-04 8:49 ` [Patch V2 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-04 8:49 ` [Patch V2 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-04 8:49 ` [Patch V2 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-04 8:49 ` [Patch V2 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-04 8:49 ` [Patch V2 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-04 8:49 ` [Patch V2 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-04 8:49 ` [Patch V2 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-04 8:49 ` [Patch V2 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-04 8:49 ` [Patch V2 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-04 8:49 ` [Patch V2 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-04 8:49 ` Heng Luo [this message]
2021-02-04 8:49 ` [Patch V2 39/40] TigerlakeSiliconPkg: Add package DSC files Heng Luo
[not found] ` <20210204084919.3603-40-heng.luo@intel.com>
2021-02-04 20:09 ` [Patch V2 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Nate DeSimone
2021-02-05 3:51 ` [Patch V2 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Chaganty, Rangasai V
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