From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga17.intel.com (mga17.intel.com []) by mx.groups.io with SMTP id smtpd.web08.5236.1612428733029241268 for ; Thu, 04 Feb 2021 00:52:13 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: GXkRj7dZWUWc83KpwyBCsA7VqYoMvPbJcXfcjgmU8avyo7yZ17d96EreeLg1MUApzFPuOKuF4r 3SYIEXkoNKWA== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="160957580" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="160957580" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga107.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:50 -0800 IronPort-SDR: K9R/+T/O+hHMLthuLg38JqqY9L5b4NzMWpyHYkiSbO9Cp2gKtK4lrlk4azCWP1U/cEzX1/0cTF dTxMRYXDh0Ig== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062460" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:49 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 39/40] TigerlakeSiliconPkg: Add package DSC files Date: Thu, 4 Feb 2021 16:49:18 +0800 Message-Id: <20210204084919.3603-39-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc | 122 ++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc | 43 ++++++++++= +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc | 47 ++++++++++= +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc | 40 ++++++++++= ++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc | 20 ++++++++++= ++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc | 20 ++++++++++= ++++++++++ Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc | 229 ++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 521 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc b/Silic= on/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc new file mode 100644 index 0000000000..51c40812ea --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgBuildOption.dsc @@ -0,0 +1,122 @@ +## @file=0D +# Silicon build option configuration file.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[BuildOptions]=0D +# Define Build Options both for EDK and EDKII drivers.=0D +=0D + DEFINE PCH_BUILD_OPTIONS =3D -DPCH_TGL=0D +#=0D +# SA=0D +#=0D +!if gSiPkgTokenSpaceGuid.PcdBdatEnable =3D=3D TRUE=0D + DEFINE BDAT_BUILD_OPTION =3D -DBDAT_SUPPORT=3D1=0D +!else=0D + DEFINE BDAT_BUILD_OPTION =3D=0D +!endif=0D +=0D + DEFINE SLE_BUILD_OPTIONS =3D=0D +!if $(TARGET) =3D=3D RELEASE=0D +!if gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable =3D=3D TRUE=0D + DEFINE DEBUG_BUILD_OPTIONS =3D=0D +!else=0D + # MDEPKG_NDEBUG is introduced for the intention=0D + # of size reduction when compiler optimization is disabled. If MDEPKG_ND= EBUG is=0D + # defined, then debug and assert related macros wrapped by it are the NU= LL implementations.=0D + DEFINE DEBUG_BUILD_OPTIONS =3D -DMDEPKG_NDEBUG=0D +!endif=0D +!else=0D + DEFINE DEBUG_BUILD_OPTIONS =3D=0D +!endif=0D +=0D +!if ($(TARGET) =3D=3D RELEASE) AND (gSiPkgTokenSpaceGuid.PcdSiCatalogDebug= Enable =3D=3D TRUE)=0D + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D -DRELEASE_CATALOG=0D +!else=0D + DEFINE RELEASE_CATALOG_BUILD_OPTIONS =3D=0D +!endif=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL-=0D +!else=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D=0D +!endif=0D +=0D + DEFINE HSLE_BUILD_OPTIONS =3D=0D +=0D +=0D + DEFINE CPU_FLAGS =3D -DCPU_ICL -DCPU_TGL=0D +=0D +=0D + DEFINE RESTRICTED_OPTION =3D=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported =3D=3D FALSE=0D + *_*_*_MRC_NDEBUG =3D -DMDEPKG_NDEBUG=0D +!endif=0D +=0D +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(BDAT_BUILD_OPTION) $(DEBUG_BU= ILD_OPTIONS)=0D +DEFINE DSC_SIPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIO= NS) $(PCH_BUILD_OPTIONS) $(CPU_FLAGS) $(HSLE_BUILD_OPTIONS)=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdSourceDebugEnable =3D=3D TRUE=0D + *_*_X64_GENFW_FLAGS =3D --keepexceptiontable=0D +!endif=0D +=0D +[BuildOptions.Common.EDKII]=0D +=0D +#=0D +# For IA32 Global Build Flag=0D +#=0D + *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI=0D + *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +#=0D +# For IA32 Specific Build Flag=0D +#=0D +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI /= w34668=0D +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +=0D +#=0D +# For X64 Global Build Flag=0D +#=0D + *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) -D PI= _SPECIFICATION_VERSION=3D0x00010015=0D + *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +#=0D +# For X64 Specific Build Flag=0D +#=0D +GCC: *_*_X64_PP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 /w34668=0D +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS) $(OPT= IMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +#=0D +# For Xcode Specific Build Flag=0D +#=0D +# Override assembly code build order=0D +*_XCODE5_*_*_BUILDRULEORDER =3D nasm S s=0D +# Align 47bfbd7f8069e523798ef973c8eb0abd5c6b0746 to fix the usage of VA_ST= ART in undefined way=0D +*_XCODE5_*_CC_FLAGS =3D -Wno-varargs=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection of runtime modules=0D +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]=0D + MSFT: *_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + GCC: *_GCC*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc b/Silicon= /Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc new file mode 100644 index 0000000000..16f148f1e7 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgCommonLib.dsc @@ -0,0 +1,43 @@ +## @file=0D +# Component description file for the TigerLake silicon package both Pei a= nd Dxe libraries DSC file.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=0D +# FRUs=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/CommonLib.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/CommonLib.dsc=0D +=0D +#=0D +# Common=0D +#=0D + MmPciLib|$(PLATFORM_SI_PACKAGE)/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPciL= ib.inf=0D + PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPci= /BasePciSegmentMultiSegLibPci.inf=0D +=0D +#=0D +# Pch=0D +#=0D + PchCycleDecodingLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchCycleD= ecodingLib/PeiDxeSmmPchCycleDecodingLib.inf=0D + PchInfoLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/PeiDxeSmmPchInfoLib/PeiDxeS= mmPchInfoLibTgl.inf=0D + CpuPcieInitCommonLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/Pei= DxeSmmCpuPcieInitCommonLib/PeiDxeSmmCpuPcieInitCommonLib.inf=0D + CpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/Library/PeiDxeSmmCp= uPcieRpLib/PeiDxeSmmCpuPcieRpLib.inf=0D +=0D + SerialIoAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/Library/PeiDxeS= mmSerialIoAccessLib/PeiDxeSmmSerialIoAccessLib.inf=0D + SerialIoPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/SerialIo/LibraryPrivate= /PeiDxeSmmSerialIoPrivateLib/PeiDxeSmmSerialIoPrivateLibVer2.inf=0D + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/Base= ResetSystemLib.inf=0D + #private=0D + GpioPrivateLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/PeiDxeS= mmGpioPrivateLib/PeiDxeSmmGpioPrivateLibVer2.inf=0D +=0D + SiScheduleResetLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/BaseSiSchedu= leResetLib/BaseSiScheduleResetLib.inf=0D + PchPciBdfLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BasePchPciBdfLib/BasePchP= ciBdfLib.inf=0D + PcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/PcieRp/LibraryPrivate/PcieClient= RpLib/PcieClientRpLib.inf=0D +=0D +#=0D +# SA=0D +#=0D + SaPlatformLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/PeiDxeSmmSaPlatf= ormLib/PeiDxeSmmSaPlatformLib.inf=0D + CpuRegbarAccessLib|$(PLATFORM_SI_PACKAGE)/IpBlock/P2sb/Library/PeiDxeSmmC= puRegbarAccessLib/PeiDxeSmmCpuRegbarAccessLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc b/Silicon/Intel= /TigerlakeSiliconPkg/SiPkgDxe.dsc new file mode 100644 index 0000000000..1a08fbc24c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxe.dsc @@ -0,0 +1,47 @@ +## @file=0D +# Component description file for the TigerLake silicon package DXE driver= s.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=0D +# FRUs=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/Dxe.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/Dxe.dsc=0D +=0D +#=0D +# Common=0D +#=0D +=0D +#=0D +# Pch=0D +#=0D + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeTgl.inf=0D + $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmControl.inf=0D +=0D + $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSmiDispatcher.inf{=0D + =0D + #SmiHandlerProfileLib|MdeModulePkg/Library/SmmSmiHandlerProfileLib/S= mmSmiHandlerProfileLib.inf=0D + SmiHandlerProfileLib|MdePkg/Library/SmiHandlerProfileLibNull/SmiHand= lerProfileLibNull.inf=0D + }=0D + $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf=0D +=0D +#=0D +# SystemAgent=0D +#=0D +=0D + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitDxe.inf=0D +=0D + $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Smm/SaLateInitSmm.inf {=0D + =0D + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScr= iptLibNull.inf=0D + }=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE=0D + $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTables/SaSsdt/SaSsdt.inf=0D + $(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/AcpiTables/IgfxSsdt.inf=0D +!endif=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc b/Silicon/In= tel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc new file mode 100644 index 0000000000..210fb37332 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgDxeLib.dsc @@ -0,0 +1,40 @@ +## @file=0D +# Component description file for the TigerLake silicon package DXE librar= ies.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=0D +# Silicon Init Dxe Library=0D +#=0D +=0D +#=0D +# FRUs=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/DxeLib.dsc=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/DxeLib.dsc=0D +=0D +#=0D +# Common=0D +#=0D +SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/BaseS= iConfigBlockLib.inf=0D +=0D +#=0D +# Pch=0D +#=0D +DxePchPolicyLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/DxePchPolicyLib/DxePchP= olicyLib.inf=0D +SmmPchPrivateLib|$(PLATFORM_SI_PACKAGE)/Pch/LibraryPrivate/SmmPchPrivateLi= b/SmmPchPrivateLib.inf=0D +=0D +#=0D +# SystemAgent=0D +#=0D +DxeSaPolicyLib|$(PLATFORM_SI_PACKAGE)/SystemAgent/Library/DxeSaPolicyLib/D= xeSaPolicyLib.inf=0D +DxeVtdPolicyLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Vtd/LibraryPrivate/DxeVtdPo= licyLib/DxeVtdPolicyLib.inf=0D +=0D +#=0D +# CPU PCIe IpBlock=0D +#=0D +=0D +DxeCpuPcieRpLib|$(PLATFORM_SI_PACKAGE)/IpBlock/CpuPcieRp/LibraryPrivate/Dx= eCpuPcieRpLib/DxeCpuPcieRpLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc b/Silicon/Intel= /TigerlakeSiliconPkg/SiPkgPei.dsc new file mode 100644 index 0000000000..15fc5685a5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPei.dsc @@ -0,0 +1,20 @@ +## @file=0D +# Component description file for the TigerLake silicon package PEI driver= s.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=0D +# Common=0D +#=0D +=0D +#=0D +# SystemAgent=0D +#=0D +=0D +#=0D +# Cpu=0D +#=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc b/Silicon/In= tel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc new file mode 100644 index 0000000000..6f90ff02bb --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkgPeiLib.dsc @@ -0,0 +1,20 @@ +## @file=0D +# Component description file for the TigerLake silicon package PEI librar= ies.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=0D +# Silicon Init Pei Library=0D +#=0D +=0D +#=0D +# FRUs=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglCpu/PeiLib.dsc=0D +=0D +!include $(PLATFORM_SI_PACKAGE)/Fru/TglPch/PeiLib.dsc=0D +=0D + SiConfigBlockLib|$(PLATFORM_SI_PACKAGE)/Library/BaseSiConfigBlockLib/Base= SiConfigBlockLib.inf=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc b/Si= licon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc new file mode 100644 index 0000000000..73a2594887 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/TigerlakeSiliconPkg.dsc @@ -0,0 +1,229 @@ +## @file=0D +# Component description file for the TigerLake silicon package DSC file.= =0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +UefiCpuPkg/UefiCpuPkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[PcdsFixedAtBuild]=0D +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE=0D +=0D +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdBdatEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable |FALSE #BiosGuardMod= ule.bin=0D +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE=0D +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE=0D +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |TRUE=0D +=0D +gSiPkgTokenSpaceGuid.PcdThcEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdPpamEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable |0x0=0D +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE=0D +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport |TRUE=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdPpamEnable =3D=3D TRUE=0D +#=0D +# PCD for State Save Support on DGR=0D +# TRUE - SMM State Save region access is protected=0D +# FALSE - SMM can have Read/Write access to SMM State Save region=0D +#=0D +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable |FALSE=0D +#=0D +# PCD to enable SPA Support on DGR=0D +# Note: This PCD is mainly used for Debugging purpose. Not recommended to = set for End Product.=0D +#=0D +gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE=0D +!endif=0D +=0D +[PcdsFixedAtBuild.common]=0D +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress |0xC0000000=0D +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |gEfiMdePkgTokenSp= aceGuid.PcdPciExpressBaseAddress=0D +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength |0x10000000=0D +=0D +[PcdsDynamicDefault.common]=0D +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength |0x10000000=0D +## Specifies the AP wait loop state during POST phase.=0D +# The value is defined as below.=0D +# 1: Place AP in the Hlt-Loop state.=0D +# 2: Place AP in the Mwait-Loop state.=0D +# 3: Place AP in the Run-Loop state.=0D +# @Prompt The AP wait loop state.=0D +gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2=0D +## Specifies the AP target C-state for Mwait during POST phase.=0D +# The default value 0 means C1 state.=0D +# The value is defined as below.

=0D +# @Prompt The specified AP target C-state for Mwait.=0D +gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0=0D +=0D +[Defines]=0D + PLATFORM_NAME =3D TigerlakeSiliconPkg=0D + PLATFORM_GUID =3D CCD38CA7-61D3-4185-9CDA-A9FDF209CB31=0D + PLATFORM_VERSION =3D 0.4=0D + DSC_SPECIFICATION =3D 0x00010005=0D + OUTPUT_DIRECTORY =3D Build/TigerlakeSiliconPkg=0D + SUPPORTED_ARCHITECTURES =3D IA32|X64=0D + BUILD_TARGETS =3D DEBUG|RELEASE=0D + SKUID_IDENTIFIER =3D DEFAULT=0D +=0D + DEFINE PLATFORM_SI_PACKAGE =3D TigerlakeSiliconPkg=0D + #=0D + # Definition for Build Flag=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc=0D +=0D +[LibraryClasses.common]=0D + #=0D + # Entry point=0D + #=0D + PeiCoreEntryPoint|MdePkg/Library/PeiCoreEntryPoint/PeiCoreEntryPoint.inf= =0D + PeimEntryPoint|MdePkg/Library/PeimEntryPoint/PeimEntryPoint.inf=0D + DxeCoreEntryPoint|MdePkg/Library/DxeCoreEntryPoint/DxeCoreEntryPoint.inf= =0D + UefiDriverEntryPoint|MdePkg/Library/UefiDriverEntryPoint/UefiDriverEntry= Point.inf=0D + UefiApplicationEntryPoint|MdePkg/Library/UefiApplicationEntryPoint/UefiA= pplicationEntryPoint.inf=0D + PeCoffExtraActionLib|MdePkg/Library/BasePeCoffExtraActionLibNull/BasePeC= offExtraActionLibNull.inf=0D +=0D + #=0D + # Basic=0D + #=0D + BaseLib|MdePkg/Library/BaseLib/BaseLib.inf=0D + BaseMemoryLib|MdePkg/Library/BaseMemoryLibRepStr/BaseMemoryLibRepStr.inf= =0D + PrintLib|MdePkg/Library/BasePrintLib/BasePrintLib.inf=0D + CpuLib|MdePkg/Library/BaseCpuLib/BaseCpuLib.inf=0D + IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf=0D + PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPc= i/BasePciSegmentMultiSegLibPci.inf=0D + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D + PciCf8Lib|MdePkg/Library/BasePciCf8Lib/BasePciCf8Lib.inf=0D + CacheMaintenanceLib|MdePkg/Library/BaseCacheMaintenanceLib/BaseCacheMain= tenanceLib.inf=0D + PeCoffLib|MdePkg/Library/BasePeCoffLib/BasePeCoffLib.inf=0D + PeCoffGetEntryPointLib|MdePkg/Library/BasePeCoffGetEntryPointLib/BasePeC= offGetEntryPointLib.inf=0D + PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf=0D + PostCodeLib|MdePkg/Library/BasePostCodeLibPort80/BasePostCodeLibPort80.i= nf=0D +=0D + #=0D + # UEFI & PI=0D + #=0D + UefiBootServicesTableLib|MdePkg/Library/UefiBootServicesTableLib/UefiBoo= tServicesTableLib.inf=0D + UefiRuntimeServicesTableLib|MdePkg/Library/UefiRuntimeServicesTableLib/U= efiRuntimeServicesTableLib.inf=0D + UefiRuntimeLib|MdePkg/Library/UefiRuntimeLib/UefiRuntimeLib.inf=0D + UefiLib|MdePkg/Library/UefiLib/UefiLib.inf=0D + DevicePathLib|MdePkg/Library/UefiDevicePathLib/UefiDevicePathLib.inf=0D + PeiServicesTablePointerLib|MdePkg/Library/PeiServicesTablePointerLibIdt/= PeiServicesTablePointerLibIdt.inf=0D + PeiServicesLib|MdePkg/Library/PeiServicesLib/PeiServicesLib.inf=0D + DxeServicesLib|MdePkg/Library/DxeServicesLib/DxeServicesLib.inf=0D + DxeServicesTableLib|MdePkg/Library/DxeServicesTableLib/DxeServicesTableL= ib.inf=0D +=0D + S3BootScriptLib|MdePkg/Library/BaseS3BootScriptLibNull/BaseS3BootScriptL= ibNull.inf=0D + S3IoLib|MdePkg/Library/BaseS3IoLib/BaseS3IoLib.inf=0D + S3PciLib|MdePkg/Library/BaseS3PciLib/BaseS3PciLib.inf=0D +=0D + UefiUsbLib|MdePkg/Library/UefiUsbLib/UefiUsbLib.inf=0D + UefiScsiLib|MdePkg/Library/UefiScsiLib/UefiScsiLib.inf=0D + SynchronizationLib|MdePkg/Library/BaseSynchronizationLib/BaseSynchroniza= tionLib.inf=0D +=0D + DebugPrintErrorLevelLib|MdePkg/Library/BaseDebugPrintErrorLevelLib/BaseD= ebugPrintErrorLevelLib.inf=0D +=0D + #=0D + # Misc=0D + #=0D + DebugLib|MdePkg/Library/BaseDebugLibNull/BaseDebugLibNull.inf=0D + PerformanceLib|MdePkg/Library/BasePerformanceLibNull/BasePerformanceLibN= ull.inf=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D + TimerLib|MdePkg/Library/BaseTimerLibNullTemplate/BaseTimerLibNullTemplat= e.inf=0D + ReportStatusCodeLib|MdePkg/Library/BaseReportStatusCodeLibNull/BaseRepor= tStatusCodeLibNull.inf=0D + MtrrLib|UefiCpuPkg/Library/MtrrLib/MtrrLib.inf=0D + RngLib|MdePkg/Library/BaseRngLib/BaseRngLib.inf=0D +=0D +##########################################################################= ###########################=0D +=0D +#=0D +# Silicon Init Common Library=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc=0D +ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBlockL= ib.inf=0D +=0D +[LibraryClasses.IA32]=0D +#=0D +# PEI phase common=0D +#=0D + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D + HobLib|MdePkg/Library/PeiHobLib/PeiHobLib.inf=0D + MemoryAllocationLib|MdePkg/Library/PeiMemoryAllocationLib/PeiMemoryAlloc= ationLib.inf=0D + ExtractGuidedSectionLib|MdePkg/Library/PeiExtractGuidedSectionLib/PeiExt= ractGuidedSectionLib.inf=0D + PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLi= b/PeiGetVtdPmrAlignmentLib.inf=0D +=0D +##########################################################################= ###########################################################=0D +=0D +#=0D +# Silicon Init Pei Library=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc=0D +=0D +[LibraryClasses.IA32.SEC]=0D + GpioHelpersLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/LibraryPrivate/BaseGp= ioHelpersLibNull/BaseGpioHelpersLibNull.inf=0D +=0D +[LibraryClasses.X64]=0D + #=0D + # DXE phase common=0D + #=0D + HobLib|MdePkg/Library/DxeHobLib/DxeHobLib.inf=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D + MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAll= ocationLib.inf=0D + ExtractGuidedSectionLib|MdePkg/Library/DxeExtractGuidedSectionLib/DxeExt= ractGuidedSectionLib.inf=0D +=0D +#=0D +# Hsti=0D +#=0D + HstiLib|MdePkg/Library/DxeHstiLib/DxeHstiLib.inf=0D +=0D +##########################################################################= #########################=0D +#=0D +# Silicon Init Dxe Library=0D +#=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc=0D +=0D +[LibraryClasses.X64.PEIM]=0D +=0D +[LibraryClasses.X64.DXE_CORE]=0D + HobLib|MdePkg/Library/DxeCoreHobLib/DxeCoreHobLib.inf=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +=0D +[LibraryClasses.X64.DXE_SMM_DRIVER]=0D + SmmServicesTableLib|MdePkg/Library/SmmServicesTableLib/SmmServicesTableL= ib.inf=0D + MemoryAllocationLib|MdePkg/Library/SmmMemoryAllocationLib/SmmMemoryAlloc= ationLib.inf=0D + SmmIoLib|MdePkg/Library/SmmIoLib/SmmIoLib.inf=0D + SmmMemLib|MdePkg/Library/SmmMemLib/SmmMemLib.inf=0D +=0D +[LibraryClasses.X64.SMM_CORE]=0D +=0D +[LibraryClasses.X64.UEFI_DRIVER]=0D + PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf=0D +=0D +[LibraryClasses.X64.UEFI_APPLICATION]=0D + PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf=0D +=0D +[Components.IA32]=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc=0D +=0D +[Components.X64]=0D +!include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc=0D --=20 2.24.0.windows.2