From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by mx.groups.io with SMTP id smtpd.web09.5257.1612428667935408713 for ; Thu, 04 Feb 2021 00:51:08 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.31, mailfrom: heng.luo@intel.com) IronPort-SDR: OxK4LB7x0R8oNKJW9pup+Yxl5dCWVkEl8SxnqmbjYWvzqLVdnW2EUbQ+fVhpNc4bpZqai5aCwA 0eihRhJXO9Fw== X-IronPort-AV: E=McAfee;i="6000,8403,9884"; a="242707117" X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="242707117" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 00:51:04 -0800 IronPort-SDR: 77b9gjXMK8yNhuoj6MjOb/7HxkyicVuj/+Ffgowh3K+KktG0R4AJm7TDLB1RqKmFjFx2mHgIn1 owA3bprVnlrQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.79,400,1602572400"; d="scan'208";a="393062051" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 04 Feb 2021 00:51:02 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V2 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Date: Thu, 4 Feb 2021 16:48:48 +0800 Message-Id: <20210204084919.3603-9-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210204084919.3603-1-heng.luo@intel.com> References: <20210204084919.3603-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Fru/TglCpu/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieInfoFr= uLib.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsHostBr= idge.h | 145 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h = | 12 ++++++++++++ 3 files changed, 214 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/C= puPcieInfoFruLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/L= ibrary/CpuPcieInfoFruLib.h new file mode 100644 index 0000000000..89cf952717 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Library/CpuPcieI= nfoFruLib.h @@ -0,0 +1,57 @@ +/** @file=0D + Header file for CpuPcieInfoFruLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PCIE_INFO_FRU_LIB_H_=0D +#define _CPU_PCIE_INFO_FRU_LIB_H_=0D +=0D +#include =0D +=0D +#define CPU_PCIE_MAX_ROOT_PORTS 4=0D +=0D +#define CPU_PCIE_ULT_ULX_MAX_ROOT_PORT 1=0D +=0D +#include =0D +=0D +/**=0D + Get CPU Maximum Pcie Root Port Number=0D +=0D + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number=0D +**/=0D +UINT8=0D +GetMaxCpuPciePortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get CPU Pcie Root Port Device and Function Number by Root Port physical = Number=0D +=0D + @param[in] RpNumber Root port physical number. (0-based)=0D + @param[out] RpDev Return corresponding root port device = number.=0D + @param[out] RpFun Return corresponding root port functio= n number.=0D +=0D + @retval EFI_SUCCESS Root port device and function is retri= eved=0D + @retval EFI_INVALID_PARAMETER RpNumber is invalid=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetCpuPcieRpDevFun (=0D + IN UINTN RpNumber,=0D + OUT UINTN *RpDev,=0D + OUT UINTN *RpFun=0D + );=0D +=0D +/**=0D + Gets pci segment base address of PCIe root port.=0D +=0D + @param RpIndex Root Port Index (0 based)=0D + @return PCIe port base address.=0D +**/=0D +UINT64=0D +CpuPcieBase (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +#endif // _CPU_PCIE_INFO_FRU_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/= SaRegsHostBridge.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/R= egister/SaRegsHostBridge.h new file mode 100644 index 0000000000..32e38fa072 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/Register/SaRegsH= ostBridge.h @@ -0,0 +1,145 @@ +/** @file=0D + Register names for Host Bridge block=0D + Conventions:=0D + - Prefixes:=0D + - Definitions beginning with "R_" are registers=0D + - Definitions beginning with "B_" are bits within registers=0D + - Definitions beginning with "V_" are meaningful values of bits within= the registers=0D + - Definitions beginning with "S_" are register sizes=0D + - Definitions beginning with "N_" are the bit position=0D + - In general, SA registers are denoted by "_SA_" in register names=0D + - Registers / bits that are different between SA generations are denoted= by=0D + "_SA_[generation_name]_" in register/bit names. e.g., "_SA_HSW_"=0D + - Registers / bits that are different between SKUs are denoted by "_[SKU= _name]"=0D + at the end of the register/bit names=0D + - Registers / bits of new devices introduced in a SA generation will be = just named=0D + as "_SA_" without [generation_name] inserted.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_REGS_HOST_BRIDGE_H_=0D +#define _SA_REGS_HOST_BRIDGE_H_=0D +=0D +#define SA_SEG_NUM 0x00=0D +#define V_SA_DEVICE_ID_INVALID 0xFFFF=0D +//=0D +// DEVICE 0 (Memory Controller Hub)=0D +//=0D +#define SA_MC_BUS 0x00=0D +#define SA_MC_DEV 0x00=0D +#define SA_MC_FUN 0x00=0D +#define V_SA_MC_VID 0x8086=0D +#define R_SA_MC_DEVICE_ID 0x02=0D +#define R_SA_MC_CAPID0_B 0xE8=0D +=0D +//=0D +// SA DMI configuration=0D +//=0D +=0D +//=0D +// Maximum DMI lanes and bundles supported (x8 and 4 lanes)=0D +//=0D +#define SA_DMI_MAX_LANE 0x08=0D +#define SA_DMI_MAX_BUNDLE 0x04=0D +#define SA_DMI_MAX_LANE_VER1 0x04=0D +#define SA_DMI_MAX_BUNDLE_VER1 0x02=0D +=0D +=0D +//=0D +// TigerLake Mobile SA Device IDs B0:D0:F0=0D +//=0D +#define V_SA_DEVICE_ID_MB_ULT_1 0x9A14 ///< TigerLake Ult (TGL-U 4+2)=0D +#define V_SA_DEVICE_ID_MB_ULT_2 0x9A04 ///< TigerLake Ult (TGL-U 2+2)=0D +=0D +#define V_SA_DEVICE_ID_MB_ULX_1 0x9A12 ///< TigerLake Ulx (TGL-Y 4+2)=0D +#define V_SA_DEVICE_ID_MB_ULX_2 0x9A02 ///< TigerLake Ulx (TGL-Y 2+2)=0D +=0D +/**=0D + Description:=0D + - This is the base address for the Host Memory Mapped Configuration space= . There is no physical memory within this 32KB window that can be addresse= d. The 32KB reserved by this register does not alias to any PCI 2.3 compli= ant memory mapped space. On reset, the Host MMIO Memory Mapped Configuatio= n space is disabled and must be enabled by writing a 1 to MCHBAREN [Dev 0, = offset48h, bit 0].=0D + - All the bits in this register are locked in LT mode.=0D + - The register space contains memory control, initialization, timing, and= buffer strength registers; clocking registers; and power and thermal manag= ement registers.=0D +**/=0D +#define R_SA_MCHBAR (0x48)=0D +=0D +/**=0D + Description:=0D + - All the bits in this register are LT lockable.=0D +**/=0D +#define R_SA_GGC (0x50)=0D +=0D +/**=0D + Description of GMS (8:15)=0D + - This field is used to select the amount of Main Memory that is pre-allo= cated to support the Internal Graphics device in VGA (non-linear) and Nativ= e (linear) modes. The BIOS ensures that memory is pre-allocated only when = Internal graphics is enabled.=0D + - This register is also LT lockable.=0D + - Valid options are 0 (0x0) to 2048MB (0x40) in multiples of 32 MB=0D + - All other values are reserved=0D + - Hardware does not clear or set any of these bits automatically based on= IGD being disabled/enabled.=0D + - BIOS Requirement: BIOS must not set this field to 0h if IVD (bit 1 of t= his register) is 0.=0D +**/=0D +#define N_SA_GGC_GMS_OFFSET (0x8)=0D +#define B_SA_GGC_GMS_MASK (0xff00)=0D +=0D +/**=0D + Description of GGMS (6:7)=0D + - This field is used to select the amount of Main Memory that is pre-allo= cated to support the Internal Graphics Translation Table. The BIOS ensures= that memory is pre-allocated only when Internal graphics is enabled.=0D + - GSM is assumed to be a contiguous physical DRAM space with DSM, and BIO= S needs to allocate a contiguous memory chunk. Hardware will derive the ba= se of GSM from DSM only using the GSM size programmed in the register.=0D + - Valid options:=0D + - 0h: 0 MB of memory pre-allocated for GTT.=0D + - 1h: 2 MB of memory pre-allocated for GTT.=0D + - 2h: 4 MB of memory pre-allocated for GTT.=0D + - 3h: 8 MB of memory pre-allocated for GTT.=0D + - Others: Reserved=0D + - Hardware functionality in case of programming this value to Reserved is= not guaranteed.=0D +**/=0D +#define N_SA_GGC_GGMS_OFFSET (0x6)=0D +#define B_SA_GGC_GGMS_MASK (0xc0)=0D +#define V_SA_GGC_GGMS_8MB 3=0D +=0D +/**=0D + Description:=0D + - Allows for enabling/disabling of PCI devices and functions that are wit= hin the CPU package. The table below the bit definitions describes the beha= vior of all combinations of transactions to devices controlled by this regi= ster.=0D + All the bits in this register are LT Lockable.=0D +**/=0D +#define R_SA_DEVEN (0x54)=0D +=0D +/**=0D + Description of D2EN (4:4)=0D + - 0: Bus 0 Device 2 is disabled and hidden=0D + - 1: Bus 0 Device 2 is enabled and visible=0D + - This bit will remain 0 if Device 2 capability is disabled.=0D +**/=0D +#define B_SA_DEVEN_D2EN_MASK (0x10)=0D +=0D +=0D +///=0D +/// Description:=0D +/// The SMRAMC register controls how accesses to Compatible SMRAM spaces = are treated. The Open, Close and Lock bits function only when G_SMRAME bit= is set to 1. Also, the Open bit must be reset before the Lock bit is set.= =0D +///=0D +#define R_SA_SMRAMC (0x88)=0D +=0D +///=0D +/// Description:=0D +/// This register contains the base address of stolen DRAM memory for the= GTT. BIOS determines the base of GTT stolen memory by subtracting the GTT = graphics stolen memory size (PCI Device 0 offset 52 bits 9:8) from the Grap= hics Base of Data Stolen Memory (PCI Device 0 offset B0 bits 31:20).=0D +///=0D +#define R_SA_BGSM (0xb4)=0D +=0D +=0D +///=0D +/// Description:=0D +/// This register contains the Top of low memory address.=0D +///=0D +#define R_SA_TOLUD (0xbc)=0D +=0D +///=0D +/// Description of TOLUD (20:31)=0D +/// This register contains bits 31 to 20 of an address one byte above the= maximum DRAM memory below 4G that is usable by the operating system. Addre= ss bits 31 down to 20 programmed to 01h implies a minimum memory size of 1M= B. Configuration software must set this value to the smaller of the followi= ng 2 choices: maximum amount memory in the system minus ME stolen memory pl= us one byte or the minimum address allocated for PCI memory. Address bits 1= 9:0 are assumed to be 0_0000h for the purposes of address comparison. The H= ost interface positively decodes an address towards DRAM if the incoming ad= dress is less than the value programmed in this register.=0D +/// The Top of Low Usable DRAM is the lowest address above both Graphics = Stolen memory and Tseg. BIOS determines the base of Graphics Stolen Memory = by subtracting the Graphics Stolen Memory Size from TOLUD and further decre= ments by Tseg size to determine base of Tseg. All the Bits in this register= are locked in LT mode.=0D +/// This register must be 1MB aligned when reclaim is enabled.=0D +///=0D +#define B_SA_TOLUD_TOLUD_MASK (0xfff00000)=0D +#define R_SA_MC_CAPID0_A_OFFSET 0xE4=0D +#define V_SA_LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Snoop Latency (70us)=0D +#define V_SA_LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel reco= mmended maximum value for Non-Snoop Latency (70us)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.= h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h new file mode 100644 index 0000000000..cd8d57d948 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglCpu/Include/TcssInfo.h @@ -0,0 +1,12 @@ +/** @file=0D + Register names for TCSS USB devices=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _TCSS_INFO_H_=0D +#define _TCSS_INFO_H_=0D +=0D +#define MAX_ITBT_PCIE_PORT 4=0D +=0D +#endif=0D --=20 2.24.0.windows.2