From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.5212.1612510881323892522 for ; Thu, 04 Feb 2021 23:41:21 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: heng.luo@intel.com) IronPort-SDR: 3ZNMg9DOCWuR9vu7Cz3PV0t/YqrCYdpq4945qSuA1JT18HV9bad8Q9P4t43+zLRvCG0XL5OBHZ G4W6UG23Sufg== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543590" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543590" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:19 -0800 IronPort-SDR: jWwMpydXgi76cUULA02I6vhGzc2ALBI6OptLhd2sinGhgAO39h9hBxiaPrv/Un8+KxHUr07G67 BgkWcrovV+AQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260199" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:15 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Date: Fri, 5 Feb 2021 15:40:06 +0800 Message-Id: <20210205074045.3916-1-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Create the TigerlakeSiliconPkg to provide an initial package for silicon initialization code for Tiger Lake (TGL) products. * Major areas of functionality are categorized into CPU, IpBlock, Fru, Platform Controller Hub (PCH), and System Agent subdirectories. * Common libraries and headers are kept at the root of the package. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig.h = | 67 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPreMemC= onfig.h | 86 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/CpuPc= ieConfig.h | 498 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h = | 72 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig.h = | 61 ++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig.h = | 170 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h = | 33 +++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h = | 31 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevConfig.h= | 37 ++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/Graph= icsConfig.h | 211 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConfig.h = | 227 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/HostBridg= eConfig.h | 62 +++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/Hybri= dGraphicsConfig.h | 66 +++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/Hybrid= StorageConfig.h | 36 +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h = | 34 ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h = | 134 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptConfig= .h | 58 ++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConfig.h = | 60 +++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h = | 117 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/MemoryCo= nfig.h | 478 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Overclo= ckingConfig.h | 236 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig.h = | 34 ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiConfig.= h | 44 +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieRp/Pch= PcieRpConfig.h | 368 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConfig.h = | 217 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h = | 86 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h = | 391 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h = | 32 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h = | 82 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h = | 38 +++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig.h = | 168 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h = | 139 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/SerialIoCon= fig.h | 32 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h = | 152 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h = | 67 ++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConfig.h = | 50 ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h = | 43 ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiConfig.h= | 145 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h = | 73 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/ThermalConfi= g.h | 153 ++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceHubCon= fig.h | 101 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConfig.h = | 81 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioConfig.h= | 138 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h = | 149 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulator/Cpu= PowerMgmtVrConfig.h | 114 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h = | 64 ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogConfig.h= | 31 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec = | 1207 ++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ 48 files changed, 6973 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/Cnv= iConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/Cnvi= Config.h new file mode 100644 index 0000000000..de1f4159f0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Cnvi/CnviConfig= .h @@ -0,0 +1,67 @@ +/** @file=0D + CNVi policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CNVI_CONFIG_H_=0D +#define _CNVI_CONFIG_H_=0D +=0D +#define CNVI_CONFIG_REVISION 1=0D +extern EFI_GUID gCnviConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CNVi Mode options=0D +**/=0D +typedef enum {=0D + CnviModeDisabled =3D 0,=0D + CnviModeAuto=0D +} CNVI_MODE;=0D +=0D +=0D +/**=0D + CNVi signals pin muxing settings. If signal can be enable only on a sing= le pin=0D + then this parameter is ignored by RC. Refer to GPIO_*_MUXING_CNVI_* in G= pioPins*.h=0D + for supported settings on a given platform=0D +**/=0D +typedef struct {=0D + UINT32 RfReset; ///< RF_RESET# Pin mux configuration. Refer to GPIO_*_MU= XING_CNVI_RF_RESET_*=0D + UINT32 Clkreq; ///< CLKREQ Pin mux configuration. Refer to GPIO_*_MUXIN= G_CNVI_*_CLKREQ_*=0D +} CNVI_PIN_MUX;=0D +=0D +/**=0D + The CNVI_CONFIG block describes the expected configuration of the CNVi I= P.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + This option allows for automatic detection of Connectivity Solution.=0D + Auto Detection assumes that CNVi will be enabled when available;=0D + Disable allows for disabling CNVi.=0D + CnviModeDisabled =3D Disabled,=0D + CnviModeAuto =3D Auto Detection=0D + **/=0D + UINT32 Mode : 1;=0D + UINT32 BtCore : 1; ///< The option to turn ON or OFF the= BT Core. 0: Disabled, 1: Enabled=0D + /**=0D + The option to enable or disable BT Audio Offload.=0D + 0: Disabled, 1: Enabled=0D + @note This feature only support with Intel(R) Wireless-AX 22560=0D + **/=0D + UINT32 BtAudioOffload : 1;=0D + UINT32 RsvdBits : 29;=0D + /**=0D + CNVi PinMux Configuration=0D + RESET#/CLKREQ to CRF, can have two alternative mappings, depending on = board routing requirements.=0D + **/=0D + CNVI_PIN_MUX PinMux;=0D +} CNVI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CNVI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/C= puDmiPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock= /CpuDmi/CpuDmiPreMemConfig.h new file mode 100644 index 0000000000..527febb0a4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuDmi/CpuDmiPr= eMemConfig.h @@ -0,0 +1,86 @@ +/** @file=0D + DMI policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_DMI_PREMEM_CONFIG_H_=0D +#define _CPU_DMI_PREMEM_CONFIG_H_=0D +=0D +#include =0D +#include =0D +=0D +#define DMI_CONFIG_REVISION 1=0D +=0D +#define CPU_DMI_HWEQ_COEFFS_MAX 8=0D +=0D +#pragma pack (push,1)=0D +///=0D +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature=0D +///=0D +typedef enum {=0D + DmiAspmDisabled,=0D + DmiAspmL0s,=0D + DmiAspmL1,=0D + DmiAspmL0sL1,=0D + DmiAspmAutoConfig,=0D + DmiAspmMax=0D +} DMI_ASPM;=0D +=0D +=0D +/**=0D + The CPU_DMI_CONFIG block describes the expected configuration of the CPU= for DMI.=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D +=0D +/**=0D + - Auto (0x0) : Maximum possible link speed (Default)=0D + - Gen1 (0x1) : Limit Link to Gen1 Speed=0D + - Gen2 (0x2) : Limit Link to Gen2 Speed CpuDmiPreMemConfig=0D + - Gen3 (0x3) : Limit Link to Gen3 Speed=0D + **/=0D + UINT8 DmiMaxLinkSpeed;=0D + /**=0D + (Test) DMI Equalization Phase 2 Enable Control=0D + - Disabled (0x0) : Disable phase 2=0D + - Enabled (0x1) : Enable phase 2=0D + - Auto (0x2) : Use the current default method (Default)=0D + **/=0D + UINT8 DmiGen3EqPh2Enable;=0D + /**=0D + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI=0D + - Auto (0x0) : Use the current default method (Default)=0D + - HwEq (0x1) : Use Adaptive Hardware Equalization=0D + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code)=0D + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1)=0D + - Disabled (0x4) : Bypass Equalization Phase 3=0D + **/=0D + UINT8 DmiGen3EqPh3Method;=0D + /**=0D + (Test) Program DMI Gen3 EQ Phase1 Static Presets=0D + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming= =0D + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default)=0D + **/=0D + UINT8 DmiGen3ProgramStaticEq;=0D + UINT8 DmiDeEmphasis; ///<= DeEmphasis control for DMI (-6 dB and -3.5 dB are the options)=0D + UINT8 DmiAspm;=0D + UINT8 DmiAspmCtrl; ///<= ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiA= spmAutoConfig=0D + UINT8 DmiAspmL1ExitLatency; ///<= ASPM configuration on the CPU side of the DMI/OPI Link. Default is DmiA= spmAutoConfig=0D + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Used for programming DMI Gen3 preset values per lane. Range: 0-9, 8 is def= ault for each lane=0D + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Used for programming DMI Gen3 preset values per lane. Range: 0-9, 7 is def= ault for each lane=0D + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2 is default f= or each lane=0D +=0D + /**=0D + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting=0D + has to be specified based upon platform design and must follow the guid= eline. Default is 12.=0D + **/=0D +=0D + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];=0D +} CPU_DMI_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_DMI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieR= p/Gen4/CpuPcieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBl= ock/CpuPcieRp/Gen4/CpuPcieConfig.h new file mode 100644 index 0000000000..f18cd0352a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/CpuPcieRp/Gen4/= CpuPcieConfig.h @@ -0,0 +1,498 @@ +/** @file=0D + Pcie root port policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _CPU_PCIE_CONFIG_H_=0D +#define _CPU_PCIE_CONFIG_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#pragma pack(push, 1)=0D +=0D +#define CPU_PCIE_PEI_PREMEM_CONFIG_REVISION 1=0D +#define CPU_PCIE_RP_PREMEM_CONFIG_REVISION 4=0D +=0D +/**=0D + Making any setup structure change after code frozen=0D + will need to maintain backward compatibility, bump up=0D + structure revision and update below history table\n=0D + Revision 1: - Initial version.=0D + Revision 2: - Add Gen3TxOverride and Gen4TxOverride=0D + Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable= =0D + Revision 4: - Add FOMS Control Policy Setup Variable=0D + Revision 5: - Add Gen3HwEqOverride and Gen4HwEqOverride=0D + Revision 6: - Align revision with CPU_PCIE_RP_CONFIG_REVISION va= lue=0D +**/=0D +=0D +#define CPU_PCIE_RP_CONFIG_REVISION 6=0D +=0D +#define L0_SET BIT0=0D +#define L1_SET BIT1=0D +=0D +=0D +=0D +=0D +/**=0D + PCI Express and DMI controller configuration\n=0D + @note Optional. These policies will be ignored if there is no PEG = port present on board.=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///<= Offset 0-27 Config Block Header=0D + /**=0D + Offset 28:0 :=0D + (Test) DMI Link Speed Control=0D + - Auto (0x0) : Maximum possible link speed (Default)=0D + - Gen1 (0x1) : Limit Link to Gen1 Speed=0D + - Gen2 (0x2) : Limit Link to Gen2 Speed=0D + - Gen3 (0x3) : Limit Link to Gen3 Speed=0D + **/=0D + UINT32 DmiMaxLinkSpeed : 2;=0D + /**=0D + Offset 28:2 :=0D + (Test) DMI Equalization Phase 2 Enable Control=0D + - Disabled (0x0) : Disable phase 2=0D + - Enabled (0x1) : Enable phase 2=0D + - Auto (0x2) : Use the current default method (Default)=0D + **/=0D + UINT32 DmiGen3EqPh2Enable : 2;=0D + /**=0D + Offset 28:4 :=0D + (Test) Selects the method for performing Phase3 of Gen3 Equaliza= tion on DMI=0D + - Auto (0x0) : Use the current default method (Default)=0D + - HwEq (0x1) : Use Adaptive Hardware Equalization=0D + - SwEq (0x2) : Use Adaptive Software Equalization (Implemented i= n BIOS Reference Code)=0D + - Static (0x3) : Use the Static EQs provided in DmiGen3EndPointPre= set array for Phase1 AND Phase3 (Instead of just Phase1)=0D + - Disabled (0x4) : Bypass Equalization Phase 3=0D + **/=0D + UINT32 DmiGen3EqPh3Method : 3;=0D + /**=0D + Offset 28:7 :=0D + (Test) Program DMI Gen3 EQ Phase1 Static Presets=0D + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming= =0D + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default)=0D + **/=0D + UINT32 DmiGen3ProgramStaticEq : 1;=0D + UINT32 RsvdBits0 : 24; ///= < Offset 28:8 :Reserved for future use=0D +=0D + /**=0D + Offset 32:0 :=0D + Select when PCIe ASPM programming will happen in relation to the Oprom=0D + - Before (0x0) : Do PCIe ASPM programming before Oprom. (Default)= =0D + - After (0x1) : Do PCIe ASPM programming after Oprom. This will = require an SMI handler to save/restore ASPM settings.=0D + **/=0D + UINT32 InitPcieAspmAfterOprom : 1;=0D + UINT32 RsvdBits1 : 31; ///< Offset 32:1 :Reserved= for future use=0D +=0D + UINT8 DmiGen3RootPortPreset[SA_DMI_MAX_LANE]; ///<= Offset 36 Used for programming DMI Gen3 preset values per lane. Range: 0-9= , 8 is default for each lane=0D + UINT8 DmiGen3EndPointPreset[SA_DMI_MAX_LANE]; ///<= Offset 40/44 Used for programming DMI Gen3 preset values per lane. Range: = 0-9, 7 is default for each lane=0D + UINT8 DmiGen3EndPointHint[SA_DMI_MAX_LANE]; ///<= Offset 44/52 Hint value per lane for the DMI Gen3 End Point. Range: 0-6, 2= is default for each lane=0D + /**=0D + Offset 48/60 :=0D + DMI Gen3 RxCTLEp per-Bundle control. The range of the setting is (0-15)= . This setting=0D + has to be specified based upon platform design and must follow the guid= eline. Default is 12.=0D + **/=0D +=0D + UINT8 DmiGen3RxCtlePeaking[SA_DMI_MAX_BUNDLE];=0D +=0D + UINT8 DmiDeEmphasis; ///<= Offset 64 This field is used to describe the DeEmphasis control for DMI (-= 6 dB and -3.5 dB are the options)=0D + UINT8 Rsvd0[3]; ///<= Offset 65=0D +} PCIE_PEI_PREMEM_CONFIG;=0D +=0D +=0D +/**=0D + CPU PCIe Root Port Pre-Memory Configuration=0D + Contains Root Port settings and capabilities=0D + Revision 1: - Initial version.=0D + Revision 2: - Adding Dekel Suqelch Workaround Setup Variable=0D + Revision 3: - Deprecate Dekel Suqelch Workaround Setup Variable= =0D + Revision 4: - Adding CDR Relock Setup Variable=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header=0D + /**=0D + Root Port enabling mask.=0D + Bit0 presents RP1, Bit1 presents RP2, and so on.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 RpEnabledMask;=0D + /**=0D + Assertion on Link Down GPIOs=0D + - Disabled (0x0) : Disable assertion on Link Down GPIOs(Default)= =0D + - Enabled (0x1) : Enable assertion on Link Down GPIOs=0D + **/=0D + UINT8 LinkDownGpios;=0D + /**=0D + Enable ClockReq Messaging=0D + - Disabled (0x0) : Disable ClockReq Messaging(Default)=0D + - Enabled (0x1) : Enable ClockReq Messaging=0D + **/=0D + UINT8 ClkReqMsgEnable;=0D + /**=0D + Dekel Recipe Workaround=0D + 2=0D + 1=3DMinimal, 9=3DMaximum,=0D + **/=0D + UINT8 DekelSquelchWa; // Deprecated variable=0D + UINT8 Rsvd0[1];=0D + /**=0D + Determines each PCIE Port speed capability.=0D + 0: Auto; 1: Gen1; 2: Gen2; 3: Gen3; 4: Gen4 (see: CPU_PCIE_SPEED)= =0D + **/=0D + UINT8 PcieSpeed[CPU_PCIE_MAX_ROOT_PORTS];=0D + /**=0D + To Enable/Disable CDR Relock=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT8 CdrRelock[CPU_PCIE_MAX_ROOT_PORTS];=0D + /**=0D + This policy is used while programming DEKEL Recipe=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT8 Xl1el[CPU_PCIE_MAX_ROOT_PORTS];=0D +=0D +} CPU_PCIE_RP_PREMEM_CONFIG;=0D +=0D +typedef enum {=0D + CpuPcieOverrideDisabled =3D 0,=0D + CpuPcieL1L2Override =3D 0x01,=0D + CpuPcieL1SubstatesOverride =3D 0x02,=0D + CpuPcieL1L2AndL1SubstatesOverride =3D 0x03,=0D + CpuPcieLtrOverride =3D 0x04=0D +} CPU_PCIE_OVERRIDE_CONFIG;=0D +=0D +/**=0D + PCIe device table entry entry=0D +=0D + The PCIe device table is being used to override PCIe device ASPM setting= s.=0D + To take effect table consisting of such entries must be instelled as PPI= =0D + on gPchPcieDeviceTablePpiGuid.=0D + Last entry VendorId must be 0.=0D +**/=0D +typedef struct {=0D + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID=0D + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID=0D + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings=0D + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class=0D + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class=0D + UINT8 EndPointAspm; ///< Override device ASPM (see: CPU= _PCIE_ASPM_CONTROL)=0D + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect=0D + UINT16 OverrideConfig; ///< The override config bitmap (se= e: CPU_PCIE_OVERRIDE_CONFIG).=0D + /**=0D + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig)=0D + This field can be zero if only the L1 Substate value is going to be ov= erride.=0D + **/=0D + UINT16 L1SubstatesCapOffset;=0D + /**=0D + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig)=0D + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override.=0D + Only bit [3:0] are applicable. Other bits are ignored.=0D + **/=0D + UINT8 L1SubstatesCapMask;=0D + /**=0D + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sCommonModeRestoreTime;=0D + /**=0D + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sTpowerOnScale;=0D + /**=0D + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sTpowerOnValue;=0D +=0D + /**=0D + SnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid=0D + When clear values in bits 9:0 will be ignored=0D + BITS[14:13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with=0D + the scale in bits 12:10=0D +=0D + This field takes effect only if bit 3 is set in OverrideConfig.=0D + **/=0D + UINT16 SnoopLatency;=0D + /**=0D + NonSnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid=0D + When clear values in bits 9:0 will be ignored=0D + BITS[14:13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with=0D + the scale in bits 12:10=0D +=0D + This field takes effect only if bit 3 is set in OverrideConfig.=0D + **/=0D + UINT16 NonSnoopLatency;=0D +=0D + /**=0D + Forces LTR override to be permanent=0D + The default way LTR override works is:=0D + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message=0D + This settings allows force override of LTR mechanism. If it's enabled,= then:=0D + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored=0D + **/=0D + UINT8 ForceLtrOverride;=0D + UINT8 Reserved[3];=0D +} CPU_PCIE_DEVICE_OVERRIDE;=0D +=0D +enum CPU_PCIE_SPEED {=0D + CpuPcieAuto,=0D + CpuPcieGen1,=0D + CpuPcieGen2,=0D + CpuPcieGen3,=0D + CpuPcieGen4,=0D + CpuPcieGen5=0D +};=0D +=0D +///=0D +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature=0D +///=0D +typedef enum {=0D + CpuPcieAspmDisabled,=0D + CpuPcieAspmL0s,=0D + CpuPcieAspmL1,=0D + CpuPcieAspmL0sL1,=0D + CpuPcieAspmAutoConfig,=0D + CpuPcieAspmMax=0D +} CPU_PCIE_ASPM_CONTROL;=0D +=0D +/**=0D + Refer to SA EDS for the SA implementation values corresponding=0D + to below PCI-E spec defined ranges=0D +**/=0D +typedef enum {=0D + CpuPcieL1SubstatesDisabled,=0D + CpuPcieL1SubstatesL1_1,=0D + CpuPcieL1SubstatesL1_1_2,=0D + CpuPcieL1SubstatesMax=0D +} CPU_PCIE_L1SUBSTATES_CONTROL;=0D +=0D +enum CPU_PCIE_MAX_PAYLOAD {=0D + CpuPcieMaxPayload128 =3D 0,=0D + CpuPcieMaxPayload256,=0D + CpuPcieMaxPayload512,=0D + CpuPcieMaxPayloadMax=0D +};=0D +=0D +enum CPU_PCIE_COMPLETION_TIMEOUT {=0D + CpuPcieCompletionTO_Default,=0D + CpuPcieCompletionTO_50_100us,=0D + CpuPcieCompletionTO_1_10ms,=0D + CpuPcieCompletionTO_16_55ms,=0D + CpuPcieCompletionTO_65_210ms,=0D + CpuPcieCompletionTO_260_900ms,=0D + CpuPcieCompletionTO_1_3P5s,=0D + CpuPcieCompletionTO_4_13s,=0D + CpuPcieCompletionTO_17_64s,=0D + CpuPcieCompletionTO_Disabled=0D +};=0D +=0D +=0D +enum CPU_PCIE_GEN3_PRESET_COEFF_SELECTION {=0D + CpuPcieGen3PresetSelection,=0D + CpuPcieGen3CoefficientSelection=0D +};=0D +=0D +enum CPU_PCIE_GEN4_PRESET_COEFF_SELECTION {=0D + CpuPcieGen4PresetSelection,=0D + CpuPcieGen4CoefficientSelection=0D +};=0D +=0D +typedef enum {=0D + CpuPcieEqDefault =3D 0, ///< @deprecated since revision 3. Behaves= as PchPcieEqHardware.=0D + CpuPcieEqHardware =3D 1, ///< Hardware equalization=0D + CpuPcieEqStaticCoeff =3D 4 ///< Fixed equalization (requires Coeffici= ent settings per lane)=0D +} CPU_PCIE_EQ_METHOD;=0D +=0D +=0D +/**=0D + Represent lane specific PCIe Gen3 equalization parameters.=0D +**/=0D +typedef struct {=0D + UINT8 Cm; ///< Coefficient C-1=0D + UINT8 Cp; ///< Coefficient C+1=0D + UINT8 PegGen3RootPortPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 8 is defaul= t for each lane=0D + UINT8 PegGen3EndPointPreset; ///< (Test) Us= ed for programming PEG Gen3 preset values per lane. Range: 0-9, 7 is defaul= t for each lane=0D + UINT8 PegGen3EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen3 End Point. Range: 0-6, 2 is default for = each lane=0D + UINT8 PegGen4RootPortPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 8 is defaul= t for each lane=0D + UINT8 PegGen4EndPointPreset; ///< (Test) Us= ed for programming PEG Gen4 preset values per lane. Range: 0-9, 7 is defaul= t for each lane=0D + UINT8 PegGen4EndPointHint; ///< (Test) Hi= nt value per lane for the PEG Gen4 End Point. Range: 0-6, 2 is default for = each lane=0D +} CPU_PCIE_EQ_LANE_PARAM;=0D +=0D +/**=0D + The CPU_PCI_ROOT_PORT_CONFIG describe the feature and capability of each= CPU PCIe root port.=0D +**/=0D +typedef struct {=0D +=0D + UINT32 ExtSync : 1; ///< Indicate whether th= e extended synch is enabled. 0: Disable; 1: Enable.=0D + UINT32 VcEnabled : 1; ///< Virtual Channel. 0:= Disable; 1: Enable=0D + UINT32 MultiVcEnabled : 1; ///< Multiple Virtual Ch= annel. 0: Disable; 1: Enable=0D + UINT32 PeerToPeer : 1; ///< Peer to Peer Mode. = 0: Disable; 1: Enable.=0D + UINT32 RsvdBits0 : 28; ///< Reserved bits=0D + /**=0D + PCIe Gen4 Equalization Method=0D + - HwEq (0x1) : Hardware Equalization (Default)=0D + - StaticEq (0x2) : Static Equalization=0D + **/=0D + UINT8 Gen4EqPh3Method;=0D + UINT8 FomsCp; ///< FOM Score Board Con= trol Policy=0D + UINT8 RsvdBytes0[2]; ///< Reserved bytes=0D +=0D + //=0D + // Gen3 Equalization settings=0D + //=0D + UINT32 Gen3Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen3 Link Equalization. Used for al= l lanes. Default is 7.=0D + UINT32 Gen3Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen3 Link Equalization. Used for a= ll lanes. Default is 7.=0D + //=0D + // Gen4 Equalization settings=0D + //=0D + UINT32 Gen4Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen4 Link Equalization. Used for al= l lanes. Default is 7.=0D + UINT32 Gen4Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen4 Link Equalization. Used for a= ll lanes. Default is 7.=0D + //=0D + // Gen5 Equalization settings=0D + //=0D + UINT32 Gen5Uptp : 4; ///< (Test) Upstr= eam Port Transmitter Preset used during Gen5 Link Equalization. Used for al= l lanes. Default is 7.=0D + UINT32 Gen5Dptp : 4; ///< (Test) Downs= tream Port Transmiter Preset used during Gen5 Link Equalization. Used for a= ll lanes. Default is 7.=0D + UINT32 RsvdBits1 : 8; ///< Reserved Bits=0D +=0D + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; = ///< (Test) Includes policies which are common to = both SA and PCH RootPort=0D +=0D +} CPU_PCIE_ROOT_PORT_CONFIG;=0D +=0D +typedef struct {=0D + UINT8 PcieGen3PresetCoeffSelection; ///Revision 1< / b>:=0D + -Initial version.=0D + Revision 2:=0D + - SlotSelection policy added=0D + Revision 3=0D + - Deprecate PegGen3ProgramStaticEq and PegGen4ProgramStaticEq=0D + Revision 4:=0D + - Deprecating SetSecuredRegisterLock=0D + Revision 5:=0D + - Adding Serl=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config = Block Header=0D + ///=0D + /// These members describe the configuration of each SA PCIe root port.= =0D + ///=0D + CPU_PCIE_ROOT_PORT_CONFIG RootPort[CPU_PCIE_MAX_ROOT_PORTS];=0D + ///=0D + /// Gen3 Equalization settings for physical PCIe lane, index 0 represent= s PCIe lane 1, etc.=0D + /// Corresponding entries are used when root port EqPh3Method is PchPcie= EqStaticCoeff (default).=0D + ///=0D + CPU_PCIE_EQ_LANE_PARAM EqPh3LaneParam[SA_PEG_MAX_LANE];=0D + ///=0D + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ)=0D + ///=0D + PCIE_EQ_PARAM HwEqGen4CoeffList[PCIE_HWEQ_COEFFS_MAX= ]; // Deprecated Policy=0D +=0D + PCIE_COMMON_CONFIG PcieCommonConfig; /// < (Test) Includes policies which are common to both SA and PCH PCIe=0D +=0D + UINT32 FiaProgramming : 1; /// < Skip Fia Conf= iguration and lock if enable=0D + ///=0D + /// This member describes whether the PCI Express Clock Gating for each = root port=0D + /// is enabled by platform modules. 0: Disable; 1: Enable.=0D + ///=0D + UINT32 ClockGating : 1;=0D + ///=0D + /// This member describes whether the PCI Express Power Gating for each = root port=0D + /// is enabled by platform modules. 0: Disable; 1: Enable.=0D + ///=0D + UINT32 PowerGating : 1;=0D + // Deprecated Policy=0D + /**=0D + (Test) Program PEG Gen3 EQ Phase1 Static Presets=0D + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming= =0D + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default)=0D + **/=0D + UINT32 PegGen3ProgramStaticEq : 1;=0D +=0D + // Deprecated Policy=0D + /**=0D + (Test) Program PEG Gen4 EQ Phase1 Static Presets=0D + - Disabled (0x0) : Disable EQ Phase1 Static Presets Programming= =0D + - Enabled (0x1) : Enable EQ Phase1 Static Presets Programming = (Default)=0D + **/=0D + UINT32 PegGen4ProgramStaticEq : 1;=0D + /**=0D + (Test) Cpu Pcie Secure Register Lock=0D + - Disabled (0x0)=0D + - Enabled (0x1)=0D + **/=0D + UINT32 SetSecuredRegisterLock : 1; // Deprecated Policy=0D + ///=0D + /// This member allows to select between the PCI Express M2 or CEMx4 slo= t 1: PCIe M2; 0: CEMx4 slot.=0D + ///=0D + UINT32 SlotSelection : 1;=0D + ///=0D + /// Set/Clear Serl(Secure Equalization Register Lock)=0D + ///=0D + UINT32 Serl : 1;=0D +=0D + UINT32 RsvdBits0 : 24;=0D +=0D + /**=0D + PCIe device override table=0D + The PCIe device table is being used to override PCIe device ASPM setti= ngs.=0D + This is a pointer points to a 32bit address. And it's only used in Pos= tMem phase.=0D + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.=0D + Last entry VendorId must be 0.=0D + The prototype of this policy is:=0D + CPU_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;=0D + **/=0D + UINT32 PcieDeviceOverrideTablePtr;=0D + CPU_PCIE_ROOT_PORT_CONFIG2 RootPort2[CPU_PCIE_MAX_ROOT_PORTS];=0D + PCIE_COMMON_CONFIG2 PcieCommonConfig2;=0D +} CPU_PCIE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_PCIE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConf= ig.h new file mode 100644 index 0000000000..445642da1f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Dci/DciConfig.h @@ -0,0 +1,72 @@ +/** @file=0D + Dci policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DCI_CONFIG_H_=0D +#define _DCI_CONFIG_H_=0D +=0D +#define DCI_PREMEM_CONFIG_REVISION 2=0D +extern EFI_GUID gDciPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef enum {=0D + DciDbcDisabled =3D 0x0,=0D + DciDbcUsb2 =3D 0x1,=0D + DciDbcUsb3 =3D 0x2,=0D + DciDbcBoth =3D 0x3,=0D + DciDbcNoChange =3D 0x4,=0D + DciDbcMax=0D +} DCI_DBC_MODE;=0D +=0D +typedef enum {=0D + Usb3TcDbgDisabled =3D 0x0,=0D + Usb3TcDbgEnabled =3D 0x1,=0D + Usb3TcDbgNoChange =3D 0x2,=0D + Usb3TcDbgMax=0D +} DCI_USB3_TYPE_C_DEBUG_MODE;=0D +=0D +/**=0D + The PCH_DCI_PREMEM_CONFIG block describes policies related to Direct Con= nection Interface (DCI)=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Added DciModphyPg=0D + - change to use data in byte unit rather than bit-field=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + DCI enable.=0D + Determine if to enable DCI debug from host.=0D + 0:Disabled; 1:Enabled=0D + **/=0D + UINT8 DciEn;=0D + /**=0D + USB DbC enable mode.=0D + Disabled: Clear both USB2/3DBCEN; USB2: Set USB2DBCEN; USB3: Set USB3D= BCEN; Both: Set both USB2/3DBCEN; No Change: Comply with HW value=0D + Refer to definition of DCI_USB_DBC_MODE for supported settings.=0D + 0:Disabled; 1:USB2; 2:USB3; 3:Both; 4:No Change=0D + **/=0D + UINT8 DciDbcMode;=0D + /**=0D + Enable Modphy power gate when DCI is enable. It must be disabled for 4= -wire DCI OOB. Set default to HW default : Disabled=0D + 0:Disabled; 1:Enabled=0D + **/=0D + UINT8 DciModphyPg;=0D + /**=0D + USB3 Type-C UFP2DFP kenel / platform debug support. No change will do = nothing to UFP2DFP configuration.=0D + When enabled, USB3 Type C UFP (upstream-facing port) may switch to DFP= (downstream-facing port) for first connection.=0D + It must be enabled for USB3 kernel(kernel mode debug) and platform deb= ug(DFx, DMA, Trace) over UFP Type-C receptacle.=0D + Refer to definition of DCI_USB_TYPE_C_DEBUG_MODE for supported setting= s.=0D + 0:Disabled; 1:Enabled; 2:No Change=0D + **/=0D + UINT8 DciUsb3TypecUfpDbg;=0D +} PCH_DCI_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _DCI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/Esp= iConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/Espi= Config.h new file mode 100644 index 0000000000..260b582702 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Espi/EspiConfig= .h @@ -0,0 +1,61 @@ +/** @file=0D + Espi policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _ESPI_CONFIG_H_=0D +#define _ESPI_CONFIG_H_=0D +=0D +#define ESPI_CONFIG_REVISION 2=0D +extern EFI_GUID gEspiConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure contains the policies which are related to ESPI.=0D +=0D + Revision 1:=0D + - Initial revision=0D + Revision 2:=0D + - Added LockLinkConfiguration field to config block=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + LPC (eSPI) Memory Range Decode Enable. When TRUE, then the range=0D + specified in PCLGMR[31:16] is enabled for decoding to LPC (eSPI).=0D + 0: FALSE, 1: TRUE=0D + **/=0D + UINT32 LgmrEnable : 1;=0D + /**=0D + eSPI Master and Slave BME settings.=0D + When TRUE, then the BME bit enabled in eSPI Master and Slave.=0D + 0: FALSE, 1: TRUE =0D + **/=0D + UINT32 BmeMasterSlaveEnabled : 1;=0D + /**=0D + Master HOST_C10 (Virtual Wire) to Slave Enable (VWHC10OE)=0D + 0b: Disable HOST_C10 reporting (HOST_C10 indication from PMC is ign= ored)=0D + 1b: Enable HOST_C10 reporting to Slave via eSPI Virtual Wire (upon rec= eiving a HOST_C10 indication from PMC)=0D + **/=0D + UINT32 HostC10ReportEnable : 1;=0D + /**=0D + eSPI Link Configuration Lock (SBLCL)=0D + If set to TRUE then communication through SET_CONFIG/GET_CONFIG=0D + to eSPI slaves addresses from range 0x0 - 0x7FF=0D + 1: TRUE, 0: FALSE=0D + **/=0D + UINT32 LockLinkConfiguration : 1;=0D + /**=0D + Hardware Autonomous Enable (HAE)=0D + If set to TRUE, then the IP may request a PG whenever it is idle=0D + **/=0D + UINT32 EspiPmHAE : 1;=0D + UINT32 RsvdBits : 27; ///< Reserved bits=0D +} PCH_ESPI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _ESPI_CONFIG_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/Fiv= rConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/Fivr= Config.h new file mode 100644 index 0000000000..0df2755280 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Fivr/FivrConfig= .h @@ -0,0 +1,170 @@ +/** @file=0D + PCH FIVR policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _FIVR_CONFIG_H_=0D +#define _FIVR_CONFIG_H_=0D +=0D +#define FIVR_CONFIG_REVISION 1=0D +extern EFI_GUID gFivrConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + Rail support in S0ix and Sx=0D + Settings other than FivrRailDisabled can be OR'ed=0D +**/=0D +typedef enum {=0D + FivrRailDisabled =3D 0,=0D + FivrRailInS0i1S0i2 =3D BIT0,=0D + FivrRailInS0i3 =3D BIT1,=0D + FivrRailInS3 =3D BIT2,=0D + FivrRailInS4 =3D BIT3,=0D + FivrRailInS5 =3D BIT4,=0D + FivrRailInS0ix =3D FivrRailInS0i1S0i2 | FivrRailInS0i3,=0D + FivrRailInSx =3D FivrRailInS3 | FivrRailInS4 | FivrRailInS5,=0D + FivrRailAlwaysOn =3D FivrRailInS0ix | FivrRailInSx=0D +} FIVR_RAIL_SX_STATE;=0D +=0D +typedef enum {=0D + FivrRetentionActive =3D BIT0,=0D + FivrNormActive =3D BIT1,=0D + FivrMinActive =3D BIT2,=0D + FivrMinRetention =3D BIT3=0D +} FIVR_RAIL_SUPPORTED_VOLTAGE;=0D +=0D +/**=0D + Structure for V1p05/Vnn VR rail configuration=0D +**/=0D +typedef struct {=0D + /**=0D + Mask to enable the usage of external VR rail in specific S0ix or Sx st= ates=0D + Use values from FIVR_RAIL_SX_STATE=0D + The default is FivrRailDisabled.=0D + **/=0D + UINT32 EnabledStates : 5;=0D +=0D + /**=0D + VR rail voltage value that will be used in S0i2/S0i3 states.=0D + This value is given in 2.5mV increments (0=3D0mV, 1=3D2.5mV, 2=3D5mV..= .)=0D + The default for Vnn is set to 420 - 1050 mV.=0D + **/=0D + UINT32 Voltage : 11;=0D + /**=0D + @deprecated=0D + THIS POLICY IS DEPRECATED, PLEASE USE IccMaximum INSTEAD=0D + VR rail Icc Max Value=0D + Granularity of this setting is 1mA and maximal possible value is 500mA= =0D + The default is 0mA .=0D + **/=0D + UINT32 IccMax : 8;=0D +=0D + /**=0D + This register holds the control hold off values to be used when=0D + changing the rail control for external bypass value in us=0D + **/=0D + UINT32 CtrlRampTmr : 8;=0D +=0D + /**=0D + Mask to set the supported configuration in VR rail.=0D + Use values from FIVR_RAIL_SUPPORTED_VOLTAGE=0D + **/=0D + UINT32 SupportedVoltageStates : 4;=0D +=0D + /**=0D + VR rail Icc Maximum Value=0D + Granularity of this setting is 1mA and maximal possible value is 500mA= =0D + The default is 0mA .=0D + **/=0D + UINT32 IccMaximum : 16;=0D +=0D + UINT32 RsvdBits1 : 12;=0D +=0D +} FIVR_EXT_RAIL_CONFIG;=0D +=0D +=0D +/**=0D + Structure for VCCIN_AUX voltage rail configuration=0D +**/=0D +typedef struct {=0D + /**=0D + Transition time in microseconds from Low Current Mode Voltage to High Cu= rrent Mode Voltage.=0D + Voltage transition time required by motherboard voltage regulator when P= CH changes=0D + the VCCIN_AUX regulator set point from the low current mode voltage and = high current mode voltage.=0D + This field has 1us resolution.=0D + When value is 0 PCH will not transition VCCIN_AUX to low current mode vo= ltage.=0D + The default is 0xC .=0D + **/=0D + UINT8 LowToHighCurModeVolTranTime;=0D +=0D + /**=0D + Transition time in microseconds from Retention Mode Voltage to High Curr= ent Mode Voltage.=0D + Voltage transition time required by motherboard voltage regulator when P= CH changes=0D + the VCCIN_AUX regulator set point from the retention mode voltage to hig= h current mode voltage.=0D + This field has 1us resolution.=0D + When value is 0 PCH will not transition VCCIN_AUX to retention voltage.= =0D + The default is 0x36 .=0D + **/=0D + UINT8 RetToHighCurModeVolTranTime;=0D +=0D + /**=0D + Transition time in microseconds from Retention Mode Voltage to Low Curre= nt Mode Voltage.=0D + Voltage transition time required by motherboard voltage regulator when P= CH changes=0D + the VCCIN_AUX regulator set point from the retention mode voltage to low= current mode voltage.=0D + This field has 1us resolution.=0D + When value is 0 PCH will not transition VCCIN_AUX to retention voltage.= =0D + The default is 0x2B .=0D + **/=0D + UINT8 RetToLowCurModeVolTranTime;=0D + UINT8 RsvdByte1;=0D + /**=0D + Transition time in microseconds from Off (0V) to High Current Mode Volta= ge.=0D + Voltage transition time required by motherboard voltage regulator when P= CH changes=0D + the VCCIN_AUX regulator set point from 0V to the high current mode volta= ge.=0D + This field has 1us resolution.=0D + 0 =3D Transition to 0V is disabled=0D + Setting this field to 0 sets VCCIN_AUX as a fixed rail that stays on=0D + in all S0 & Sx power states after initial start up on G3 exit=0D + The default is 0x96 .=0D + **/=0D + UINT32 OffToHighCurModeVolTranTime : 11;=0D + UINT32 RsvdBits1 : 21;=0D +} FIVR_VCCIN_AUX_CONFIG;=0D +=0D +/**=0D + The PCH_FIVR_CONFIG block describes FIVR settings.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + External V1P05 VR rail configuration.=0D + **/=0D + FIVR_EXT_RAIL_CONFIG ExtV1p05Rail;=0D + /**=0D + External Vnn VR rail configuration.=0D + **/=0D + FIVR_EXT_RAIL_CONFIG ExtVnnRail;=0D + /**=0D + Additional External Vnn VR rail configuration that will get applied=0D + in Sx entry SMI callback. Required only if External Vnn VR=0D + needs different settings for Sx than those specified in ExtVnnRail.=0D + **/=0D + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;=0D + /**=0D + VCCIN_AUX voltage rail configuration.=0D + **/=0D + FIVR_VCCIN_AUX_CONFIG VccinAux;=0D +=0D + /**=0D + Enable/Disable FIVR Dynamic Power Management=0D + Default is 1 .=0D + **/=0D + UINT32 FivrDynPm : 1;=0D + UINT32 RsvdBits2 : 31;=0D +} PCH_FIVR_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _FIVR_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConf= ig.h new file mode 100644 index 0000000000..cb9411f9e8 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gbe/GbeConfig.h @@ -0,0 +1,33 @@ +/** @file=0D + Gigabit Ethernet policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GBE_CONFIG_H_=0D +#define _GBE_CONFIG_H_=0D +=0D +#define GBE_CONFIG_REVISION 1=0D +extern EFI_GUID gGbeConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + PCH intergrated GBE controller configuration settings.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + Determines if enable PCH internal GBE, 0: Disable; 1: Enable.=0D + When Enable is changed (from disabled to enabled or from enabled to di= sabled),=0D + it needs to set LAN Disable regsiter, which might be locked by FDSWL r= egister.=0D + So it's recommendated to issue a global reset when changing the status= for PCH Internal LAN.=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 LtrEnable : 1; ///< 0: Disable; 1: Enable LTR cap= abilty of PCH internal LAN.=0D + UINT32 RsvdBits0 : 30; ///< Reserved bits=0D +} GBE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _GBE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConf= ig.h new file mode 100644 index 0000000000..87649253c6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gna/GnaConfig.h @@ -0,0 +1,31 @@ +/** @file=0D + Policy definition for GNA Config Block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GNA_CONFIG_H_=0D +#define _GNA_CONFIG_H_=0D +#pragma pack(push, 1)=0D +=0D +#define GNA_CONFIG_REVISION 1=0D +/**=0D + GNA config block for configuring GNA.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 C= onfig Block Header=0D + /**=0D + Offset 28:0=0D + This policy enables the GNA Device (SA Device 8) if supported.=0D + If FALSE, all other policies in this config block will be ignored.=0D + 1=3DTRUE;=0D + 0=3DFALSE.=0D + **/=0D + UINT32 GnaEnable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Offset 28:1 :Reserved f= or future use=0D +} GNA_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _GNA_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/Gpi= oDevConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/G= pioDevConfig.h new file mode 100644 index 0000000000..1a724f14da --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Gpio/GpioDevCon= fig.h @@ -0,0 +1,37 @@ +/** @file=0D + GPIO device policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GPIO_DEV_CONFIG_H_=0D +#define _GPIO_DEV_CONFIG_H_=0D +=0D +extern EFI_GUID gGpioDxeConfigGuid;=0D +=0D +#define GPIO_DXE_CONFIG_REVISION 1=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure contains the DXE policies which are related to GPIO devic= e.=0D +=0D + Revision 1:=0D + - Inital version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + If GPIO ACPI device is not used by OS it can be hidden. In such case=0D + no other device exposed to the system can reference GPIO device in one= =0D + of its resources through GpioIo(..) or GpioInt(..) ACPI descriptors.=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT32 HideGpioAcpiDevice : 1;=0D + UINT32 RsvdBits : 31; ///< Reserved bits=0D +=0D +} GPIO_DXE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _GPIO_DEV_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics= /Gen12/GraphicsConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigB= lock/Graphics/Gen12/GraphicsConfig.h new file mode 100644 index 0000000000..c3b134b830 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Graphics/Gen12/= GraphicsConfig.h @@ -0,0 +1,211 @@ +/** @file=0D + Policy definition for Internal Graphics Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _GRAPHICS_CONFIG_H_=0D +#define _GRAPHICS_CONFIG_H_=0D +#pragma pack(push, 1)=0D +=0D +#define GRAPHICS_PEI_PREMEM_CONFIG_REVISION 3=0D +#define GRAPHICS_PEI_CONFIG_REVISION 7=0D +#define GRAPHICS_DXE_CONFIG_REVISION 1=0D +=0D +#define DDI_DEVICE_NUMBER 4=0D +#define MAX_BCLM_ENTRIES 20=0D +=0D +=0D +//=0D +// DDI defines=0D +//=0D +typedef enum {=0D + DdiDisable =3D 0x00,=0D + DdiDdcEnable =3D 0x01,=0D +} DDI_DDC_TBT_VAL;=0D +=0D +typedef enum {=0D + DdiHpdDisable =3D 0x00,=0D + DdiHpdEnable =3D 0x01,=0D +} DDI_HPD_VAL;=0D +=0D +typedef enum {=0D + DdiPortDisabled =3D 0x00,=0D + DdiPortEdp =3D 0x01,=0D + DdiPortMipiDsi =3D 0x02,=0D +} DDI_PORT_SETTINGS;=0D +=0D +/**=0D + This structure configures the Native GPIOs for DDI port per VBT settings= .=0D +**/=0D +typedef struct {=0D + UINT8 DdiPortAConfig; /// The Configuration of DDI port A, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tA, DdiPortEdp - Set DdiPortA to eDP, DdiPortMipiDsi - Set DdiPortA = to MIPI DSI=0D + UINT8 DdiPortBConfig; /// The Configuration of DDI port B, this settings= must match VBT's settings. DdiPortDisabled - No LFP is connected on DdiPor= tB, DdiPortEdp - Set DdiPortB to eDP, DdiPortMipiDsi - Set DdiPortB = to MIPI DSI=0D + UINT8 DdiPortAHpd; /// The HPD setting of DDI Port A, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPortBHpd; /// The HPD setting of DDI Port B, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable - En= able HPD=0D + UINT8 DdiPortCHpd; /// The HPD setting of DDI Port C, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPort1Hpd; /// The HPD setting of DDI Port 1, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPort2Hpd; /// The HPD setting of DDI Port 2, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPort3Hpd; /// The HPD setting of DDI Port 3, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPort4Hpd; /// The HPD setting of DDI Port 4, this settings m= ust match VBT's settings. DdiHpdDisable - Disable HPD, DdiHpdEnable = - Enable HPD=0D + UINT8 DdiPortADdc; /// The DDC setting of DDI Port A, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D + UINT8 DdiPortBDdc; /// The DDC setting of DDI Port B, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - Enabl= e DDC =0D + UINT8 DdiPortCDdc; /// The DDC setting of DDI Port C, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D + UINT8 DdiPort1Ddc; /// The DDC setting of DDI Port 1, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D + UINT8 DdiPort2Ddc; /// The DDC setting of DDI Port 2, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D + UINT8 DdiPort3Ddc; /// The DDC setting of DDI Port 3, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D + UINT8 DdiPort4Ddc; /// The DDC setting of DDI Port 4, this settings m= ust match VBT's settings. DdiDisable - Disable DDC, DdiDdcEnable - E= nable DDC=0D +} DDI_CONFIGURATION;=0D +=0D +/**=0D + This Configuration block is to configure GT related PreMem data/variable= s.\n=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Added DfdRestoreEnable.=0D + Revision 3:=0D + - Added DdiConfiguration.=0D + Revision 4:=0D + - Added GmAdr64 and made GmAdr obselete=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config = Block Header=0D + /**=0D + Offset 28=0D + Selection of the primary display device: 0=3DiGFX, 1=3DPEG, 2=3DPCIe G= raphics on PCH, 3=3DAUTO, 4=3DSwitchable Graphics\n=0D + When AUTO mode selected, the priority of display devices is: PCIe Grap= hics on PCH > PEG > iGFX=0D + **/=0D + UINT8 PrimaryDisplay;=0D + /**=0D + Offset 29=0D + Intel Gfx Support. It controls enabling/disabling iGfx device.=0D + When AUTO mode selected, iGFX will be turned off when external graphic= s detected.=0D + If FALSE, all other polices can be ignored.=0D + 2 =3D AUTO;=0D + 0 =3D FALSE;=0D + 1 =3D TRUE.=0D + **/=0D + UINT8 InternalGraphics;=0D + /**=0D + Offset 30=0D + Pre-allocated memory for iGFX\n=0D + 0 =3D 0MB,1 or 247 =3D 32MB,\n=0D + 2 =3D 64MB,\n=0D + 240 =3D 4MB, 241 =3D 8MB,\n=0D + 242 =3D 12MB, 243 =3D 16MB,\n=0D + 244 =3D 20MB, 245 =3D 24MB,\n=0D + 246 =3D 28MB, 248 =3D 36MB,\n=0D + 249 =3D 40MB, 250 =3D 44MB,\n=0D + 251 =3D 48MB, 252 =3D 52MB,\n=0D + 253 =3D 56MB, 254 =3D 60MB,\n=0D + Note: enlarging pre-allocated memory for iGFX may need to reduce Mm= ioSize because of 4GB boundary limitation=0D + **/=0D + UINT16 IgdDvmt50PreAlloc;=0D + UINT8 PanelPowerEnable; ///< Offset 32 :(Test) = Control for enabling/disabling VDD force bit (Required only for early enabl= ing of eDP panel): 0=3DFALSE, 1=3DTRUE=0D + UINT8 ApertureSize; ///< Offset 33 :Graphics apert= ure size (256MB is the recommended size as per BWG) : 0=3D128MB, 1=3D256= MB, 3=3D512MB, 7=3D1024MB, 15=3D2048MB.=0D + UINT8 GtPsmiSupport; ///< Offset 34 :PSMI support O= n/Off: 0=3DFALSE, 1=3DTRUE=0D + UINT8 PsmiRegionSize; ///< Offset 35 :Psmi region si= ze: 0=3D32MB, 1=3D288MB, 2=3D544MB, 3=3D800MB, 4=3D1056MB=0D + UINT8 DismSize; ///< Offset 36 :DiSM Size for = 2LM Sku: 0=3D0GB, 1=3D1GB, 2=3D2GB, 3=3D3GB, 4=3D4GB, 5=3D5GB, 6=3D6= GB, 7=3D7GB=0D + UINT8 DfdRestoreEnable; ///< Offset 37 :Display memory= map programming for DFD Restore 0- Disable, 1- Enable=0D + UINT16 GttSize; ///< Offset 38 :Selection of i= GFX GTT Memory size: 1=3D2MB, 2=3D4MB, 3=3D8MB=0D + /**=0D + Offset 40=0D + Temp Address of System Agent GTTMMADR: Default is 0xAF000000=0D + **/=0D + UINT32 GttMmAdr;=0D + UINT32 GmAdr; ///< Offset 44 Obsolete not to= be used, use GmAdr64=0D + DDI_CONFIGURATION DdiConfiguration; ///< Offset 48 DDI configurati= on, need to match with VBT settings.=0D +=0D + UINT8 GtClosEnable; ///< Offset 50 Gt ClOS=0D + UINT8 Rsvd0[7]; ///< Offset 51 Reserved for 4 = bytes of alignment=0D + /**=0D + Offset 58=0D + Temp Address of System Agent GMADR: Default is 0xB0000000=0D + **/=0D + UINT64 GmAdr64;=0D +} GRAPHICS_PEI_PREMEM_CONFIG;=0D +=0D +/**=0D + This configuration block is to configure IGD related variables used in P= ostMem PEI.=0D + If Intel Gfx Device is not supported, all policies can be ignored.=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Removed DfdRestoreEnable.=0D + Revision 3:=0D + - Removed DdiConfiguration.=0D + Revision 4:=0D + - Added new CdClock frequency=0D + Revision 5:=0D + - Added GT Chicket bits=0D + Revision 6:=0D + - Added LogoPixelHeight and LogoPixelWidth=0D + Revision 7:=0D + - Added SkipFspGop=0D +=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D + UINT8 RenderStandby; ///< Offset 28 :(Test)= This field is used to enable or disable RC6 (Render Standby): 0=3DFALSE, <= b>1=3DTRUE=0D + UINT8 PmSupport; ///< Offset 29 :(Test)= IGD PM Support TRUE/FALSE: 0=3DFALSE, 1=3DTRUE=0D + /**=0D + Offset 30=0D + CdClock Frequency select\n=0D + 0xFF =3D Auto. Max CdClock freq based on Reference Clk \n=0D + 0: 192 Mhz, 1: 307.2 Mhz, 2: 312 Mhz, 3: 324 Mhz, 4: 326.4 Mhz, 5: 55= 2 Mhz, 6: 556.8 Mhz, 7: 648 Mhz, 8: 652.8 Mhz=0D +=0D + **/=0D + UINT16 CdClock;=0D + UINT8 PeiGraphicsPeimInit; ///< Offset 32 : This policy = is used to enable/disable Intel Gfx PEIM.0- Disable, 1- Enable=0D + UINT8 CdynmaxClampEnable; ///< Offset 33 : This policy = is used to enable/disable CDynmax Clamping Feature (CCF) 1- Enable, = 0- Disable=0D + UINT16 GtFreqMax; ///< Offset 34 : (Test) Max GT frequency limited by user in multiples of 50MHz: Default value whi= ch indicates normal frequency is 0xFF=0D + UINT8 DisableTurboGt; ///< Offset 36 : This policy = is used to enable/disable DisableTurboGt 0- Disable, 1- Enable=0D + UINT8 SkipCdClockInit; ///< Offset 37 : SKip full CD= clock initialization. 0- Disable, 1- Enable=0D + UINT8 RC1pFreqEnable; ///< Offset 38 : This policy = is used to enable/disable RC1p Frequency. 0- Disable, 1- Enable=0D + UINT8 PavpEnable; ///< Offset 39 :IGD PAVP TRUE= /FALSE: 0=3DFALSE, 1=3DTRUE=0D + VOID* LogoPtr; ///< Offset 40 Address of Int= el Gfx PEIM Logo to be displayed=0D + UINT32 LogoSize; ///< Offset 44 Intel Gfx PEIM= Logo Size=0D + VOID* GraphicsConfigPtr; ///< Offset 48 Address of the= Graphics Configuration Table=0D + VOID* BltBufferAddress; ///< Offset 52 Address of Blt= buffer for PEIM Logo use=0D + UINT32 BltBufferSize; ///< Offset 56 The size for B= lt Buffer, calculating by PixelWidth * PixelHeight * 4 bytes (the size of E= FI_GRAPHICS_OUTPUT_BLT_PIXEL)=0D + UINT8 ProgramGtChickenBits; ///< Offset 60 Program GT Chi= cket bits in GTTMMADR + 0xD00 BITS [3:1].=0D + UINT8 SkipFspGop; ///< Offset 61 This policy is= used to skip PEIM GOP in FSP.0- Use FSP provided GOP driver, 1- Ski= p FSP provided GOP driver=0D + UINT8 Rsvd1[2]; ///< Offset 62 Reserved for 4= bytes alignment=0D + UINT32 LogoPixelHeight; ///< Offset 64 Address of Log= oPixelHeight for PEIM Logo use=0D + UINT32 LogoPixelWidth; ///< Offset 68 Address of Log= oPixelWidth for PEIM Logo use=0D +} GRAPHICS_PEI_CONFIG;=0D +=0D +/**=0D + This configuration block is to configure IGD related variables used in D= XE.=0D + If Intel Gfx Device is not supported or disabled, all policies will be i= gnored.=0D + The data elements should be initialized by a Platform Module.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header=0D + UINT32 Size; ///< Offset 28 - 31: Thi= s field gives the size of the GOP VBT Data buffer=0D + EFI_PHYSICAL_ADDRESS VbtAddress; ///< Offset 32 - 39: Thi= s field points to the GOP VBT data buffer=0D + UINT8 PlatformConfig; ///< Offset 40: This fie= ld gives the Platform Configuration Information (0=3DPlatform is S0ix Capab= le for ULT SKUs only, 1=3DPlatform is not S0ix Capable, 2=3DForce Pl= atform is S0ix Capable for All SKUs)=0D + UINT8 AlsEnable; ///< Offset 41: Ambient = Light Sensor Enable: 0=3DDisable, 2=3DEnable=0D + UINT8 BacklightControlSupport; ///< Offset 42: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal=0D + UINT8 IgdBootType; ///< Offset 43: IGD Boot= Type CMOS option: 0=3DDefault, 0x01=3DCRT, 0x04=3DEFP, 0x08=3DLFP, = 0x20=3DEFP3, 0x40=3DEFP2, 0x80=3DLFP2=0D + UINT32 IuerStatusVal; ///< Offset 44 - 47: Off= set 16 This field holds the current status of all the supported Ultrabook e= vents (Intel(R) Ultrabook Event Status bits)=0D + CHAR16 GopVersion[0x10]; ///< Offset 48 - 79:This= field holds the GOP Driver Version. It is an Output Protocol and updated b= y the Silicon code=0D + /**=0D + Offset 80: IGD Panel Type CMOS option\n=0D + 0=3DDefault, 1=3D640X480LVDS, 2=3D800X600LVDS, 3=3D1024X768LVDS= , 4=3D1280X1024LVDS, 5=3D1400X1050LVDS1\n=0D + 6=3D1400X1050LVDS2, 7=3D1600X1200LVDS, 8=3D1280X768LVDS, 9=3D1680X1050= LVDS, 10=3D1920X1200LVDS, 13=3D1600X900LVDS\n=0D + 14=3D1280X800LVDS, 15=3D1280X600LVDS, 16=3D2048X1536LVDS, 17=3D1366X76= 8LVDS=0D + **/=0D + UINT8 IgdPanelType;=0D + UINT8 IgdPanelScaling; ///< Offset 81: IGD Pane= l Scaling: 0=3DAUTO, 1=3DOFF, 6=3DForce scaling=0D + UINT8 IgdBlcConfig; ///< Offset 82: Backligh= t Control Support: 0=3DPWM Inverted, 2=3DPWM Normal=0D + UINT8 IgdDvmtMemSize; ///< Offset 83: IGD DVMT= Memory Size: 1=3D128MB, 2=3D256MB, 3=3DMAX=0D + UINT8 GfxTurboIMON; ///< Offset 84: IMON Cur= rent Value: 14=3DMinimal, 31=3DMaximum=0D + UINT8 Reserved[3]; ///< Offset 85: Reserved= for DWORD alignment.=0D + UINT16 BCLM[MAX_BCLM_ENTRIES]; ///< Offset 88: IGD Back= light Brightness Level Duty cycle Mapping Table.=0D +} GRAPHICS_DXE_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _GRAPHICS_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAu= dioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdA= udioConfig.h new file mode 100644 index 0000000000..a2e0a65e45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Hda/HdAudioConf= ig.h @@ -0,0 +1,227 @@ +/** @file=0D + HDAUDIO policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HDAUDIO_CONFIG_H_=0D +#define _HDAUDIO_CONFIG_H_=0D +=0D +#include =0D +#include =0D +=0D +#define HDAUDIO_PREMEM_CONFIG_REVISION 2=0D +#define HDAUDIO_CONFIG_REVISION 1=0D +#define HDAUDIO_DXE_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gHdAudioPreMemConfigGuid;=0D +extern EFI_GUID gHdAudioConfigGuid;=0D +extern EFI_GUID gHdAudioDxeConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +///=0D +/// The PCH_HDAUDIO_CONFIG block describes the expected configuration of t= he Intel HD Audio feature.=0D +///=0D +=0D +#define HDAUDIO_VERB_TABLE_VIDDID(Vid,Did) (UINT32)((= UINT16)Vid | ((UINT16)Did << 16))=0D +#define HDAUDIO_VERB_TABLE_RID_SDI_SIZE(Rid,Sdi,VerbTableSize) (UINT32)((= UINT8)Rid | ((UINT8)Sdi << 8) | ((UINT16)VerbTableSize << 16))=0D +#define HDAUDIO_VERB_TABLE_CMD_SIZE(VerbTable) ((sizeof (= VerbTable) - sizeof (HDA_VERB_TABLE_HEADER)) / (sizeof (UINT32)))=0D +=0D +///=0D +/// Use this macro to create HDAUDIO_VERB_TABLE and populate size automati= cally=0D +///=0D +#define HDAUDIO_VERB_TABLE_INIT(Vid,Did,Rid,Sdi,...) \=0D +{ \=0D + { Vid, Did, Rid, Sdi, (sizeof((UINT32[]){__VA_ARGS__})/sizeof(UINT32)) }= , \=0D + { __VA_ARGS__ } \=0D +}=0D +=0D +=0D +/**=0D + Azalia verb table header=0D + Every verb table should contain this defined header and followed by azal= ia verb commands.=0D +**/=0D +typedef struct {=0D + UINT16 VendorId; ///< Codec Vendor ID=0D + UINT16 DeviceId; ///< Codec Device ID=0D + UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matche= s any revision.=0D + UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.=0D + UINT16 DataDwords; ///< Number of data DWORDs following the h= eader.=0D +} HDA_VERB_TABLE_HEADER;=0D +=0D +#ifdef _MSC_VER=0D +//=0D +// Disable "zero-sized array in struct/union" extension warning.=0D +// Used for neater verb table definitions.=0D +//=0D +#pragma warning (push)=0D +#pragma warning (disable: 4200)=0D +#endif=0D +typedef struct {=0D + HDA_VERB_TABLE_HEADER Header;=0D + UINT32 Data[];=0D +} HDAUDIO_VERB_TABLE;=0D +#ifdef _MSC_VER=0D +#pragma warning (pop)=0D +#endif=0D +=0D +typedef struct {=0D + UINT32 ClkA; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_CLKA_*=0D + UINT32 ClkB; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_CLKB_*=0D + UINT32 Data; ///< Pin mux configuration. Refer to GPIO_*_M= UXING_DMIC*_DATA_*=0D +} HDA_DMIC_PIN_MUX;=0D +=0D +/**=0D + HD Audio Link Policies=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< HDA interface enable. When enabled related= pins will be switched to native mode: 0: Disable; 1: Enable.=0D + UINT32 RsvdBits0 : 31;=0D + UINT8 SdiEnable[PCH_MAX_HDA_SDI]; ///< HDA SDI signal enable. When en= abled related SDI pins will be switched to appropriate native mode: 0: D= isable; 1: Enable=0D + UINT8 Reserved[(4 - (PCH_MAX_HDA_SDI % 4)) % 4]; ///< Padding for SDI= enable table.=0D +} HDA_LINK_HDA;=0D +=0D +/**=0D + HD Audio DMIC Interface Policies=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< HDA DMIC interface enable= . When enabled related pins will be switched to native mode: 0: Disable<= /b>; 1: Enable.=0D + UINT32 DmicClockSelect : 2; ///< DMIC link clock select: <= b>0: Both, 1: ClkA, 2: ClkB; default is "Both"=0D + UINT32 RsvdBits0 : 29;=0D + HDA_DMIC_PIN_MUX PinMux; ///< Pin mux configuration.=0D +} HDA_LINK_DMIC;=0D +=0D +/**=0D + HD Audio SSP Interface Policies=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< HDA SSP interface enable. When = enabled related pins will be switched to native mode: 0: Disable; 1:= Enable.=0D + UINT32 RsvdBits0 : 31;=0D +} HDA_LINK_SSP;=0D +=0D +/**=0D + HD Audio SNDW Interface Policies=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< HDA SNDW interface enable. When= enabled related pins will be switched to native mode: 0: Disable; 1= : Enable.=0D + UINT32 RsvdBits0 : 31;=0D +} HDA_LINK_SNDW;=0D +=0D +=0D +/**=0D + This structure contains the policies which are related to HD Audio devic= e (cAVS).=0D +=0D + Revision 1:=0D + - Inital version.=0D +=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: D= isable; 1: Enable=0D + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake in= itiated by a codec in Sx (eg by modem codec), 0: Disable; 1: Enable= =0D + UINT32 HdAudioLinkFrequency : 4; ///< HDA-Link frequency (PCH_HDAU= DIO_LINK_FREQUENCY enum): 2: 24MHz, 1: 12MHz, 0: 6MHz=0D + UINT32 RsvdBits0 : 26; ///< Reserved bits 0=0D + /**=0D + Number of the verb table entry defined in VerbTablePtr.=0D + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks.=0D + **/=0D + UINT8 VerbTableEntryNum;=0D + UINT8 Rsvd0[3]; ///< Reserved bytes, align to = multiple 4=0D + /**=0D + Pointer to a verb table array.=0D + This pointer points to 32bits address, and is only eligible and consum= ed in post mem phase.=0D + Each entry points to a verb table which contains HDAUDIO_VERB_TABLE st= ructure and verb command blocks.=0D + The prototype of this is:=0D + HDAUDIO_VERB_TABLE **VerbTablePtr;=0D + **/=0D + UINT32 VerbTablePtr;=0D +} HDAUDIO_CONFIG;=0D +=0D +/**=0D + This structure contains the premem policies which are related to HD Audi= o device (cAVS).=0D +=0D + Revision 1:=0D + - Inital version.=0D + Revision 2:=0D + - Add DmicClockSelect=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 Enable : 1; ///< Intel HD Audio (Azalia) enab= lement: 0: Disable, 1: Enable=0D + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; = 1: Enable=0D + UINT32 VcType : 1; ///< Virtual Channel Type Select:= 0: VC0, 1: VC1=0D + /**=0D + Universal Audio Architecture compliance for DSP enabled system:=0D + 0: Not-UAA Compliant (Intel SST driver supported only),=0D + 1: UAA Compliant (HDA Inbox driver or SST driver supported)=0D + **/=0D + UINT32 DspUaaCompliance : 1;=0D + UINT32 IDispLinkFrequency : 4; ///< iDisp-Link frequency (PCH_HD= AUDIO_LINK_FREQUENCY enum): 4: 96MHz, 3: 48MHz=0D + UINT32 IDispLinkTmode : 3; ///< iDisp-Link T-Mode (PCH_HDAUD= IO_IDISP_TMODE enum): 0: 2T, 1: 1T, 2: 4T, 3: 8T, 4: 16T=0D + UINT32 IDispCodecDisconnect : 1; ///< iDisplay Audio Codec disconn= ection, 0: Not disconnected, enumerable; 1: Disconnected SDI, not en= umerable=0D + UINT32 PowerGatingSupported : 1; ///< Power Gating supported: 0= : Not supported, 1: Supported=0D + UINT32 RsvdBits : 19; ///< Reserved bits 0=0D +=0D + /**=0D + Audio Link Mode configuration bitmask.=0D + Allows to configure enablement of the following interfaces: HDA-Link, = DMIC, SSP, SoundWire.=0D + **/=0D +=0D + HDA_LINK_HDA AudioLinkHda; ///< HDA-Link enablement: 0: Disa= ble; 1: Enable.=0D + /**=0D + DMIC link enablement: 0: Disable; 1: Enable.=0D + DMIC0 LKF: Muxed with SNDW2/SNDW4.=0D + **/=0D + HDA_LINK_DMIC AudioLinkDmic [2];=0D + /**=0D + I2S/SSP link enablement: 0: Disable; 1: Enable.=0D + SSP0/1 LKF: Muxed with HDA.=0D + @note Since the I2S/SSP2 pin set contains pads which are also used for= CNVi purpose, enabling AudioLinkSsp2=0D + is exclusive with CNVi is present.=0D + **/=0D + HDA_LINK_SSP AudioLinkSsp [PCH_MAX_HDA_SSP_LINK_NUM];=0D + /**=0D + SoundWire link enablement: 0: Disable; 1: Enable.=0D + SNDW2 LKF: Muxed with DMIC0/DMIC1.=0D + SNDW3 LKF: Muxed with DMIC1.=0D + SNDW4 LKF: Muxed with DMIC0.=0D + **/=0D + HDA_LINK_SNDW AudioLinkSndw [PCH_MAX_HDA_SNDW_LINK_NUM];=0D +=0D +=0D + UINT16 ResetWaitTimer; ///< (Test) The delay t= imer after Azalia reset, the value is number of microseconds. Default is 600.=0D + UINT8 Rsvd0[2]; ///< Reserved bytes, align to = multiple 4=0D +=0D +} HDAUDIO_PREMEM_CONFIG;=0D +=0D +typedef struct {=0D + UINT32 AutonomousClockStop : 1; ///< SoundWire1 link autonom= ous clock stop capability: 0: Disable; 1: Enable=0D + UINT32 DataOnActiveIntervalSelect : 2; ///< SoundWire1 link data on= active interval select 0: 3 clock periods; 1: 4 clock periods; 2: 5= clock periods; 3: 6 clock periods=0D + UINT32 DataOnDelaySelect : 1; ///< SoundWire1 link data on= delay select 0: 2 clock periods; 1: 3 clock periods=0D + UINT32 RsvdBits1 : 28; ///< Reserved bits 1=0D +} HDAUDIO_SNDW_CONFIG;=0D +=0D +/**=0D + This structure contains the DXE policies which are related to HD Audio d= evice (cAVS).=0D + Revision 1:=0D + - Inital version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + SNDW configuration for exposed via SNDW ACPI tables:=0D + **/=0D + HDAUDIO_SNDW_CONFIG SndwConfig[PCH_MAX_HDA_SNDW_LINK_NUM];=0D + /**=0D + Bitmask of supported DSP features:=0D + [BIT0] - WoV; [BIT1] - BT Sideband; [BIT2] - Codec VAD; [BIT5] - BT In= tel HFP; [BIT6] - BT Intel A2DP=0D + [BIT7] - DSP based speech pre-processing disabled; [BIT8] - 0: Intel W= oV, 1: Windows Voice Activation=0D + Default is zero.=0D + **/=0D + UINT32 DspFeatureMask;=0D +} HDAUDIO_DXE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _HDAUDIO_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBrid= ge/HostBridgeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlo= ck/HostBridge/HostBridgeConfig.h new file mode 100644 index 0000000000..67335be92e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HostBridge/Host= BridgeConfig.h @@ -0,0 +1,62 @@ +/** @file=0D + Configurations for HostBridge=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HOST_BRIDGE_CONFIG_H_=0D +#define _HOST_BRIDGE_CONFIG_H_=0D +=0D +#include =0D +=0D +#define HOST_BRIDGE_PREMEM_CONFIG_REVISION 1=0D +#define HOST_BRIDGE_PEI_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gHostBridgePeiPreMemConfigGuid;=0D +extern EFI_GUID gHostBridgePeiConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This configuration block describes HostBridge settings in PreMem.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D + UINT32 MchBar; ///< Offset 28 Address of Sys= tem Agent MCHBAR: 0xFEDC0000(TGL)/0xFED10000(RKL)/0xFEA80000(JSL)=0D + UINT32 DmiBar; ///< Offset 32 Address of Sys= tem Agent DMIBAR: 0xFEDA0000=0D + UINT32 EpBar; ///< Offset 36 Address of Sys= tem Agent EPBAR: 0xFEDA1000=0D + UINT32 GdxcBar; ///< Offset 40 Address of Sys= tem Agent GDXCBAR: 0xFED84000=0D + UINT32 RegBar; ///< Offset 44 Address of Sys= tem Agent REGBAR: 0xFB000000=0D + UINT32 EdramBar; ///< Offset 48 Address of Sys= tem Agent EDRAMBAR: 0xFED80000=0D + /**=0D + Offset 52 :=0D + Size of reserved MMIO space for PCI devices\n=0D + 0=3DAUTO, 512=3D512MB, 768=3D768MB, 1024=3D1024MB, 1280=3D1280M= B, 1536=3D1536MB, 1792=3D1792MB,=0D + 2048=3D2048MB, 2304=3D2304MB, 2560=3D2560MB, 2816=3D2816MB, 3072=3D307= 2MB\n=0D + When AUTO mode selected, the MMIO size will be calculated by required = MMIO size from PCIe devices detected.=0D + **/=0D + UINT32 MmioSize;=0D + UINT32 MmioSizeAdjustment; ///< Offset 56 Increase (give= n positive value) or Decrease (given negative value) the Reserved MMIO size= when Dynamic Tolud/AUTO mode enabled (in MBs): 0=3Dno adjustment=0D + UINT8 EnableAbove4GBMmio; ///< Offset 60 Enable/disable= above 4GB MMIO resource support: 0=3DDisable, 1=3DEnable=0D + UINT8 Reserved[3]; ///< Offset 61 Reserved for f= uture use.=0D +} HOST_BRIDGE_PREMEM_CONFIG;=0D +=0D +=0D +/**=0D + This configuration block describes HostBridge settings in Post-Mem.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D + UINT8 Device4Enable; ///< Offser 28 :This policy i= s used to control enable or disable System Agent Thermal device (0,4,0). 0=3DFALSE, 1=3DTRUE.=0D + UINT8 ChapDeviceEnable; ///< Offset 29 :(Test)= This policy is used to control enable or disable System Agent Chap device (= 0,7,0). 0=3DFALSE, 1=3DTRUE.=0D + UINT8 SkipPamLock; ///< Offset 30 :To skip PAM r= egister locking. @note It is still recommended to set PCI Config space B0: = D0: F0: Offset 80h[0]=3D1 in platform code even Silicon code skipped this.\= n 0=3DAll PAM registers will be locked in Silicon code, 1=3DSkip loc= k PAM registers in Silicon code.=0D + UINT8 EdramTestMode; ///< Offset 28 :EDRAM Test Mo= de. For EDRAM stepping - 0- EDRAM SW Disable, 1- EDRAM SW Enable, 2- ED= RAM HW Mode=0D +} HOST_BRIDGE_PEI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGr= aphics/HybridGraphicsConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/C= onfigBlock/HybridGraphics/HybridGraphicsConfig.h new file mode 100644 index 0000000000..3f420aed48 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridGraphics/= HybridGraphicsConfig.h @@ -0,0 +1,66 @@ +/** @file=0D + Hybrid Graphics policy definitions=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HYBRID_GRAPHICS_CONFIG_H_=0D +#define _HYBRID_GRAPHICS_CONFIG_H_=0D +=0D +#define HYBRID_GRAPHICS_CONFIG_REVISION 2=0D +=0D +#pragma pack(push, 1)=0D +///=0D +/// GPIO Support=0D +///=0D +typedef enum {=0D + NotSupported =3D 0,=0D + PchGpio,=0D + I2CGpio,=0D +} GPIO_SUPPORT;=0D +=0D +///=0D +/// CPU PCIe GPIO Data Structure=0D +///=0D +typedef struct {=0D + UINT8 ExpanderNo; ///< Offset 0 Expander No For I2C based GPIO=0D + BOOLEAN Active; ///< Offset 1 0=3DActive Low; 1=3DActive High=0D + UINT8 Rsvd0[2]; ///< Offset 2 Reserved=0D + UINT32 GpioNo; ///< Offset 4 GPIO pad=0D +} CPU_PCIE_GPIO_INFO;=0D +=0D +/**=0D + CPU PCIE RTD3 GPIO Data Structure=0D +**/=0D +typedef struct {=0D + CPU_PCIE_GPIO_INFO HoldRst; ///< Offset 0 This field contain PCIe = HLD RESET GPIO value and level information=0D + CPU_PCIE_GPIO_INFO PwrEnable; ///< Offset 8 This field contain PCIe = PWR Enable GPIO value and level information=0D + UINT32 WakeGpioNo; ///< Offset 16 This field contain PCIe= RTD3 Device Wake GPIO Number=0D + UINT8 GpioSupport; ///< Offset 20 Depends on board design= the GPIO configuration may be different: 0=3DNot Supported, 1=3DPCH= Based, 2=3DI2C based=0D + UINT8 Rsvd0[3]; ///< Offset 21=0D +} CPU_PCIE_RTD3_GPIO;=0D +=0D +/**=0D + This Configuration block configures CPU PCI Express 0/1/2 RTD3 GPIOs & R= oot Port.=0D + Hybrid Gfx uses the same GPIOs & Root port as PCI Express 0/1/2 RTD3.=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Add HgSlot Policy: PEG or PCH Slot Slection for Hybrid Graphics=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D + CPU_PCIE_RTD3_GPIO CpuPcie0Rtd3Gpio; ///< Offset 28 RTD3 GPIOs use= d for PCIe=0D + UINT8 RootPortIndex; ///< Offset 52 Root Port Inde= x number used for HG=0D + UINT8 HgMode; ///< Offset 53 HgMode: 0= =3DDisabled, 1=3DHG Muxed, 2=3DHG Muxless, 3=3DPEG=0D + UINT16 HgSubSystemId; ///< Offset 54 Hybrid Graphic= s Subsystem ID: 2212=0D + UINT16 HgDelayAfterPwrEn; ///< Offset 56 Dgpu Delay aft= er Power enable using Setup option: 0=3DMinimal, 1000=3DMaximum, 300=3D3= 00 microseconds=0D + UINT16 HgDelayAfterHoldReset; ///< Offset 58 Dgpu Delay aft= er Hold Reset using Setup option: 0=3DMinimal, 1000=3DMaximum, 100=3D100= microseconds=0D + CPU_PCIE_RTD3_GPIO CpuPcie1Rtd3Gpio; ///< Offset 60 RTD3 GPIOs use= d for PCIe=0D + CPU_PCIE_RTD3_GPIO CpuPcie2Rtd3Gpio; ///< Offset 84 RTD3 GPIOs use= d for PCIe=0D + CPU_PCIE_RTD3_GPIO CpuPcie3Rtd3Gpio; ///< Offset 108 RTD3 GPIOs us= ed for PCIe=0D + UINT8 HgSlot; ///< Offset 132 Slot selectio= n between PEG and PCH=0D + UINT8 Rsvd0[3]; ///< Offset 133 Reserved Byte= s=0D +} HYBRID_GRAPHICS_CONFIG;=0D +#pragma pack(pop)=0D +#endif // _HYBRID_GRAPHICS_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridSt= orage/HybridStorageConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Con= figBlock/HybridStorage/HybridStorageConfig.h new file mode 100644 index 0000000000..705fe43751 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/HybridStorage/H= ybridStorageConfig.h @@ -0,0 +1,36 @@ +/** @file=0D + Hybrid Storage policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HYBRID_STORAGE_CONFIG_H_=0D +#define _HYBRID_STORAGE_CONFIG_H_=0D +=0D +#include =0D +=0D +#define HYBRID_STORAGE_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gHybridStorageConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The HYBRID_STORAGE_CONFIG block describes the expected configuration for= Hybrid Storage device=0D +=0D + Revision 1:=0D + - Init version=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + Hybrid Storage Mode=0D + 0: Disable, 1: Enable Dynamic Configuration=0D + **/=0D + UINT8 HybridStorageMode;=0D + UINT8 RsvdBytes[3];=0D +} HYBRID_STORAGE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _HYBRID_STORAGE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConf= ig.h new file mode 100644 index 0000000000..a9275152f5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ieh/IehConfig.h @@ -0,0 +1,34 @@ +/** @file=0D + Integrated Error Handler policy.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _IEH_CONFIG_H_=0D +#define _IEH_CONFIG_H_=0D +=0D +#define IEH_MODE_BYPASS 0=0D +#define IEH_MODE_ENABLE 1=0D +=0D +#define IEH_CONFIG_REVISION 1=0D +extern EFI_GUID gIehConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The IEH_CONFIG block describes the expected configuration of the PCH=0D + Integrated Error Handler.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + IEH mode 0: Bypass Mode; 1: Enable=0D + **/=0D + UINT32 Mode : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} IEH_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _IEH_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConf= ig.h new file mode 100644 index 0000000000..75a11e3052 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Ish/IshConfig.h @@ -0,0 +1,134 @@ +/** @file=0D + ISH policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _ISH_CONFIG_H_=0D +#define _ISH_CONFIG_H_=0D +=0D +#define ISH_PREMEM_CONFIG_REVISION 1=0D +#define ISH_CONFIG_REVISION 1=0D +extern EFI_GUID gIshPreMemConfigGuid;=0D +extern EFI_GUID gIshConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + ISH GPIO settings=0D +**/=0D +typedef struct {=0D + /**=0D + GPIO signals pin muxing settings. If signal can be enable only on a si= ngle pin=0D + then this parameter should be set to 0. Refer to GPIO_*_MUXING_ISH_*x_= * in GpioPins*.h=0D + for supported settings on a given platform=0D + **/=0D + UINT32 PinMux; ///< GPIO Pin mux configuration. R= efer to GPIO_*_MUXING_ISH_*x_MOSI_*=0D + /**=0D + GPIO Pads Internal Termination.=0D + For more information please see Platform Design Guide.=0D + Check GPIO_ELECTRICAL_CONFIG for reference=0D + **/=0D + UINT32 PadTermination;=0D +} ISH_GPIO_CONFIG;=0D +=0D +/**=0D + SPI signals settings.=0D +**/=0D +typedef struct {=0D + ISH_GPIO_CONFIG Mosi; ///< MOSI Pin configurati= on.=0D + ISH_GPIO_CONFIG Miso; ///< MISO Pin configurati= on.=0D + ISH_GPIO_CONFIG Clk; ///< CLK Pin configurati= on.=0D + ISH_GPIO_CONFIG Cs[PCH_MAX_ISH_SPI_CS_PINS]; ///< CS Pin configurati= on.=0D +} ISH_SPI_PIN_CONFIG;=0D +=0D +=0D +/**=0D + UART signals settings.=0D +**/=0D +typedef struct {=0D + ISH_GPIO_CONFIG Rx; ///< RXD Pin configuration.=0D + ISH_GPIO_CONFIG Tx; ///< TXD Pin configuration.=0D + ISH_GPIO_CONFIG Rts; ///< RTS Pin configuration.=0D + ISH_GPIO_CONFIG Cts; ///< CTS Pin configuration.=0D +} ISH_UART_PIN_CONFIG;=0D +=0D +=0D +/**=0D + I2C signals settings.=0D +**/=0D +typedef struct {=0D + ISH_GPIO_CONFIG Sda; ///< SDA Pin configuration.=0D + ISH_GPIO_CONFIG Scl; ///< SCL Pin configuration.=0D +} ISH_I2C_PIN_CONFIG;=0D +=0D +=0D +/**=0D + Struct contains GPIO pins assigned and signal settings of SPI=0D +**/=0D +typedef struct {=0D + UINT8 Enable; ///< ISH SPI GPIO= pins assigned: 0: False 1: True=0D + UINT8 CsEnable[PCH_MAX_ISH_SPI_CS_PINS]; ///< ISH SPI CS p= ins assigned: 0: False 1: True=0D + UINT16 RsvdField0; ///< Reserved fie= ld=0D + ISH_SPI_PIN_CONFIG PinConfig;=0D +} ISH_SPI;=0D +=0D +=0D +/**=0D + Struct contains GPIO pins assigned and signal settings of UART=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< ISH UART GPIO pins assigned= : 0: False 1: True=0D + UINT32 RsvdBits0 : 31; ///< Reserved Bits=0D + ISH_UART_PIN_CONFIG PinConfig;=0D +} ISH_UART;=0D +=0D +/**=0D + Struct contains GPIO pins assigned and signal settings of I2C=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< ISH I2C GPIO pins assigned:= 0: False 1: True=0D + UINT32 RsvdBits0 : 31; ///< Reserved Bits=0D + ISH_I2C_PIN_CONFIG PinConfig;=0D +} ISH_I2C;=0D +=0D +/**=0D + Struct contains GPIO pins assigned and signal settings of GP=0D +**/=0D +typedef struct {=0D + UINT32 Enable : 1; ///< ISH GP GPIO pins assigned: = 0: False 1: True=0D + UINT32 RsvdBits0 : 31; ///< Reserved Bits=0D + ISH_GPIO_CONFIG PinConfig;=0D +} ISH_GP;=0D +=0D +///=0D +/// The ISH_CONFIG block describes Integrated Sensor Hub device.=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + ISH_SPI Spi[PCH_MAX_ISH_SPI_CONTROLLERS];=0D + ISH_UART Uart[PCH_MAX_ISH_UART_CONTROLLERS];=0D + ISH_I2C I2c[PCH_MAX_ISH_I2C_CONTROLLERS];=0D + ISH_GP Gp[PCH_MAX_ISH_GP_PINS];=0D +=0D + UINT32 PdtUnlock : 1; ///< ISH PDT Unlock Msg: = 0: False 1: True=0D + UINT32 RsvdBits0 : 31; ///< Reserved Bits=0D +=0D +} ISH_CONFIG;=0D +=0D +///=0D +/// Premem Policy for Integrated Sensor Hub device.=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + ISH Controler 0: Disable; 1: Enable.=0D + For Desktop sku, the ISH POR should be disabled. 0:Disable .=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved Bits=0D +} ISH_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _ISH_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/Int= erruptConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss= /InterruptConfig.h new file mode 100644 index 0000000000..7f6fa8675b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/InterruptC= onfig.h @@ -0,0 +1,58 @@ +/** @file=0D + Interrupt policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _INTERRUPT_CONFIG_H_=0D +#define _INTERRUPT_CONFIG_H_=0D +=0D +#define INTERRUPT_CONFIG_REVISION 1=0D +extern EFI_GUID gInterruptConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +//=0D +// --------------------- Interrupts Config ------------------------------= =0D +//=0D +typedef enum {=0D + PchNoInt, ///< No Interrupt Pin=0D + PchIntA,=0D + PchIntB,=0D + PchIntC,=0D + PchIntD=0D +} PCH_INT_PIN;=0D +=0D +///=0D +/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and= interrupt mode for PCH device.=0D +///=0D +typedef struct {=0D + UINT8 Device; ///< Device number=0D + UINT8 Function; ///< Device function=0D + UINT8 IntX; ///< Interrupt pin: INTA-INTD (see= PCH_INT_PIN)=0D + UINT8 Irq; ///< IRQ to be set for device.=0D +} PCH_DEVICE_INTERRUPT_CONFIG;=0D +=0D +#define PCH_MAX_DEVICE_INTERRUPT_CONFIG 128 ///< Number of all PCH d= evices=0D +#define PCH_MAX_PXRC_CONFIG 8 ///< Number of PXRC regi= sters in ITSS=0D +#define PCH_MAX_ITSS_IPC_REGS 4 ///< Number of IPC regis= ters in ITSS=0D +#define PCH_MAX_ITSS_IRQ_NUM 120 ///< Maximum number of I= RQs=0D +=0D +=0D +///=0D +/// The PCH_INTERRUPT_CONFIG block describes interrupt settings for PCH.=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header=0D + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table=0D + UINT8 Rsvd0[3]; = ///< Reserved bytes, align to multiple 4.=0D + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings=0D + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14.=0D + UINT8 SciIrqSelect; = ///< Interrupt select for SCI. Default is 9.=0D + UINT8 TcoIrqSelect; = ///< Interrupt select for TCO. Default is 9.=0D + UINT8 TcoIrqEnable; = ///< Enable IRQ generation for TCO. 0: Disable; 1: Enable.=0D +} PCH_INTERRUPT_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _INTERRUPT_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoA= picConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/Io= ApicConfig.h new file mode 100644 index 0000000000..726a27f7a1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Itss/IoApicConf= ig.h @@ -0,0 +1,60 @@ +/** @file=0D + IoApic policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _IOAPIC_CONFIG_H_=0D +#define _IOAPIC_CONFIG_H_=0D +=0D +#define IOAPIC_CONFIG_REVISION 1=0D +extern EFI_GUID gIoApicConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PCH_IOAPIC_CONFIG block describes the expected configuration of the = PCH=0D + IO APIC, it's optional and PCH code would ignore it if the BdfValid bit = is=0D + not TRUE. Bus:device:function fields will be programmed to the register= =0D + P2SB IBDF(P2SB PCI offset R6Ch-6Dh), it's using for the following purpos= e:=0D + As the Requester ID when initiating Interrupt Messages to the processor.= =0D + As the Completer ID when responding to the reads targeting the IOxAPI's= =0D + Memory-Mapped I/O registers.=0D + This field defaults to Bus 0: Device 31: Function 0 after reset. BIOS ca= n=0D + program this field to provide a unique Bus:Device:Function number for th= e=0D + internal IOxAPIC.=0D + The address resource range of IOAPIC must be reserved in E820 and ACPI a= s=0D + system resource.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 IoApicEntry24_119 : 1; ///< 0: Disable; 1: Enable = IOAPIC Entry 24-119=0D + /**=0D + Enable 8254 Static Clock Gating during early POST time. 0: Disable, 1: Enable=0D + Setting 8254CGE is required to support SLP_S0.=0D + Enable this if 8254 timer is not used.=0D + However, set 8254CGE=3D1 in POST time might fail to boot legacy OS usi= ng 8254 timer.=0D + Make sure it is disabled to support legacy OS using 8254 timer.=0D + @note:=0D + For some OS environment that it needs to set 8254CGE in late state it = should=0D + set this policy to FALSE and use ItssSet8254ClockGateState (TRUE) in = SMM later.=0D + This is also required during S3 resume.=0D + To avoid SMI requirement in S3 reusme path, it can enable the Enable82= 54ClockGatingOnS3=0D + and RC will do 8254 CGE programming in PEI during S3 resume with BOOT_= SAI.=0D + **/=0D + UINT32 Enable8254ClockGating : 1;=0D + /**=0D + Enable 8254 Static Clock Gating on S3 resume path. 0: Disable, 1: E= nable=0D + This is only applicable when Enable8254ClockGating is disabled.=0D + If Enable8254ClockGating is enabled, RC will do the 8254 CGE programmi= ng on=0D + S3 resume path as well.=0D + **/=0D + UINT32 Enable8254ClockGatingOnS3 : 1;=0D + UINT32 RsvdBits1 : 29; ///< Reserved bits=0D + UINT8 IoApicId; ///< This member determines IOAPIC= ID. Default is 0x02.=0D + UINT8 Rsvd0[3]; ///< Reserved bytes=0D +} PCH_IOAPIC_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _IOAPIC_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePei= Config.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiCo= nfig.h new file mode 100644 index 0000000000..82786501f0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Me/MePeiConfig.h @@ -0,0 +1,117 @@ +/** @file=0D + ME config block for PEI phase=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _ME_PEI_CONFIG_H_=0D +#define _ME_PEI_CONFIG_H_=0D +=0D +#define ME_PEI_PREMEM_CONFIG_REVISION 2=0D +extern EFI_GUID gMePeiPreMemConfigGuid;=0D +=0D +#ifndef PLATFORM_POR=0D +#define PLATFORM_POR 0=0D +#endif=0D +#ifndef FORCE_ENABLE=0D +#define FORCE_ENABLE 1=0D +#endif=0D +#ifndef FORCE_DISABLE=0D +#define FORCE_DISABLE 2=0D +#endif=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + ME Pei Pre-Memory Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Add SkipCpuReplacementCheck Option.=0D + Revision 3:=0D + - Deprecate SendDidMsg.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 HeciTimeouts : 1; ///< 0: Disable; 1: Ena= ble - HECI Send/Receive Timeouts.=0D + /**=0D + (Test)=0D + 0: Disabled=0D + 1: ME DID init stat 0 - Success=0D + 2: ME DID init stat 1 - No Memory in Channels=0D + 3: ME DID init stat 2 - Memory Init Error=0D + **/=0D + UINT32 DidInitStat : 2;=0D + /**=0D + (Test)=0D + 0: Set to 0 to enable polling for CPU replacement=0D + 1: Set to 1 will disable polling for CPU replacement=0D + **/=0D + UINT32 DisableCpuReplacedPolling : 1;=0D + UINT32 SendDidMsg : 1; ///< (Deprecated) 0= : Disable; 1: Enable - Enable/Disable to send DID message.=0D + /**=0D + (Test)=0D + 0: ME BIOS will check each messages before sending=0D + 1: ME BIOS always sends messages without checking=0D + **/=0D + UINT32 DisableMessageCheck : 1;=0D + /**=0D + (Test)=0D + The SkipMbpHob policy determines whether ME BIOS Payload data will be = requested during boot=0D + in a MBP message. If set to 1, BIOS will send the MBP message with Ski= pMbp flag=0D + set causing CSME to respond with MKHI header only and no MBP data=0D + 0: ME BIOS will keep MBP and create HOB for MBP data=0D + 1: ME BIOS will skip MBP data=0D + **/=0D + UINT32 SkipMbpHob : 1;=0D + UINT32 HeciCommunication2 : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable HECI2.=0D + UINT32 KtDeviceEnable : 1; ///< (Test) 0: Disa= ble; 1: Enable - Enable/Disable Kt Device.=0D + UINT32 SkipCpuReplacementCheck : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable to skip CPU replacement check.=0D + UINT32 RsvdBits : 22; ///< Reserved for future u= se & Config block alignment=0D + UINT32 Heci1BarAddress; ///< HECI1 BAR address.=0D + UINT32 Heci2BarAddress; ///< HECI2 BAR address.=0D + UINT32 Heci3BarAddress; ///< HECI3 BAR address.=0D +} ME_PEI_PREMEM_CONFIG;=0D +#pragma pack (pop)=0D +=0D +=0D +#define ME_PEI_CONFIG_REVISION 3=0D +extern EFI_GUID gMePeiConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + ME Pei Post-Memory Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Deprecated Heci3Enabled.=0D + Revision 3=0D + - Added EnforceEDebugMode.=0D +**/=0D +=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D +=0D + UINT32 EndOfPostMessage : 2; ///< 0: Disabled; 1: Send = in PEI; 2: Send in DXE - Send EOP at specific phase.=0D + UINT32 Heci3Enabled : 1; ///< @deprecated=0D + UINT32 DisableD0I3SettingForHeci : 1; ///< (Test) 0: D= isable; 1: Enable - Enable/Disable D0i3 for HECI.=0D + /**=0D + Enable/Disable Me Unconfig On Rtc Clear. If enabled, BIOS will send Me= UnconfigOnRtcClearDisable Msg with parameter 0.=0D + It will cause ME to unconfig if RTC is cleared.=0D + - 0: Disable=0D + - 1: Enable=0D + - 2: Cmos is clear, status unkonwn=0D + - 3: Reserved=0D + **/=0D + UINT32 MeUnconfigOnRtcClear : 2;=0D + UINT32 MctpBroadcastCycle : 1; ///< (Test) 0: = Disable; 1: Enable - Program registers for MCTP Cycle.=0D + UINT32 EnforceEDebugMode : 1; ///< 0: Disable; 1= : Enable - Enforces ME to enter Enhanced Debug Mode=0D + UINT32 RsvdBits : 24; ///< Reserved for future = use & Config block alignment=0D +} ME_PEI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _ME_PEI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/V= er2/MemoryConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/= Memory/Ver2/MemoryConfig.h new file mode 100644 index 0000000000..17c0a10eee --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Memory/Ver2/Mem= oryConfig.h @@ -0,0 +1,478 @@ +/** @file=0D + Policy definition of Memory Config Block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _MEMORY_CONFIG_H_=0D +#define _MEMORY_CONFIG_H_=0D +=0D +=0D +#pragma pack(push, 1)=0D +=0D +// MEMORY_CONFIG_REVISION 3 adds DDR5 PDA Enumeration training within MEMO= RY_CONFIGURATION=0D +// MEMORY_CONFIG_REVISION 4 adds LPDDR4 Command Mirroring within MEMORY_CO= NFIGURATION=0D +// MEMORY_CONFIG_REVISION 5 adds CpuBclkSpread option within MEMORY_CONFIG= URATION=0D +// MEMORY_CONFIG_REVISION 6 adds McParity option within MEMORY_CONFIGURATI= ON=0D +// MEMORY_CONFIG_REVISION 7 adds VddqVoltageOverride option within MEMORY_= CONFIGURATION=0D +// MEMORY_CONFIG_REVISION 8 adds ExtendedBankHashing option within MEMORY_= CONFIGURATION=0D +// MEMORY_CONFIG_REVISION 9 adds IbeccErrorInj option within MEMORY_CONFIG= URATION=0D +#define MEMORY_CONFIG_REVISION 9=0D +///=0D +/// MEMORY_CONFIG interface definitions=0D +///=0D +#define MRC_MAX_RCOMP_TARGETS 5=0D +///=0D +/// Memory SubSystem Definitions=0D +///=0D +#define MEM_CFG_MAX_CONTROLLERS 2=0D +#define MEM_CFG_MAX_CHANNELS 4=0D +#define MEM_CFG_MAX_CHANNEL_SHARE_REGS 2=0D +#define MEM_CFG_MAX_DIMMS 2=0D +#define MEM_CFG_MAX_RANKS_PER_DIMM 2=0D +#define MEM_CFG_NUM_BYTES_MAPPED 2=0D +#define MEM_CFG_MAX_SPD_SIZE 1024=0D +#define MEM_CFG_MAX_SOCKETS (MEM_CFG_MAX_CONTROLLERS * MEM_CF= G_MAX_CHANNELS * MEM_CFG_MAX_DIMMS)=0D +#define MEM_CFG_MAX_ROWS (MEM_CFG_MAX_RANKS_PER_DIMM * MEM= _CFG_MAX_SOCKETS)=0D +#ifndef MEM_MAX_SAGV_POINTS=0D +#define MEM_MAX_SAGV_POINTS 4=0D +#endif=0D +#define MEM_MAX_IBECC_REGIONS 8=0D +///=0D +/// SMRAM Memory Range=0D +///=0D +#define PEI_MR_SMRAM_ABSEG_MASK 0x01=0D +#define PEI_MR_SMRAM_HSEG_MASK 0x02=0D +=0D +///=0D +/// SA SPD profile selections.=0D +///=0D +typedef enum {=0D + Default, ///< 0, Default SPD=0D + UserDefined, ///< 1, User Defined profile=0D + XMPProfile1, ///< 2, XMP Profile 1=0D + XMPProfile2, ///< 3, XMP Profile 2=0D + XMPProfileMax =3D 0xFF ///< Ensures SA_SPD is UINT8=0D +} SA_SPD;=0D +=0D +///=0D +/// Define the boot modes used by the SPD read function.=0D +///=0D +typedef enum {=0D + SpdCold, ///< Cold boot=0D + SpdWarm, ///< Warm boot=0D + SpdS3, ///< S3 resume=0D + SpdFast, ///< Fast boot=0D + SpdBootModeMax ///< Delimiter=0D +} SPD_BOOT_MODE;=0D +=0D +/**=0D + SPD Data Buffer=0D +**/=0D +typedef struct {=0D + UINT8 SpdData[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_CFG_MAX= _DIMMS][MEM_CFG_MAX_SPD_SIZE]; ///< SpdData=0D +//Next Field Offset 2048=0D +} SPD_DATA_BUFFER;=0D +=0D +/**=0D + DqDqs Mapping=0D +**/=0D +typedef struct {=0D + UINT8 DqsMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_= CFG_NUM_BYTES_MAPPED]; ///< DqsMapCpu2Dram=0D + UINT8 DqMapCpu2Dram[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS][MEM_C= FG_NUM_BYTES_MAPPED][8]; ///< DqMapCpu2Dram=0D +//Next Field Offset 16=0D +} SA_MEMORY_DQDQS_MAPPING;=0D +=0D +/**=0D + Rcomp Policies=0D +**/=0D +typedef struct {=0D + UINT16 RcompResistor; ///< Offset 0: Reference RCO= MP resistors on motherboard ~ 100 ohms=0D + UINT16 RcompTarget[MRC_MAX_RCOMP_TARGETS]; ///< Offset 1: RCOMP target = values for DqOdt, DqDrv, CmdDrv, CtlDrv, ClkDrv=0D +//Next Field Offset 16=0D +} SA_MEMORY_RCOMP;=0D +=0D +/**=0D + SPD Offset Table=0D +**/=0D +typedef struct {=0D + UINT16 Start; ///< Offset 0=0D + UINT16 End; ///< Offset 2=0D + UINT8 BootMode; ///< Offset 4=0D + UINT8 Reserved3[3]; ///< Offset 5 Reserved for future use=0D +} SPD_OFFSET_TABLE;=0D +=0D +///=0D +/// SA memory address decode.=0D +///=0D +typedef struct=0D +{=0D + UINT8 Controller; ///< Offset 0 Zero based Controller number=0D + UINT8 Channel; ///< Offset 1 Zero based Channel number=0D + UINT8 Dimm; ///< Offset 2 Zero based DIMM number=0D + UINT8 Rank; ///< Offset 3 Zero based Rank number=0D + UINT8 BankGroup; ///< Offset 4 Zero based Bank Group number=0D + UINT8 Bank; ///< Offset 5 Zero based Bank number=0D + UINT16 Cas; ///< Offset 6 Zero based CAS number=0D + UINT32 Ras; ///< Offset 8 Zero based RAS number=0D +} SA_ADDRESS_DECODE;=0D +=0D +typedef UINT8 (EFIAPI * SA_IO_READ_8) (UINTN IoAddress)= ; = = ///< CPU I/O port 8-bit read.=0D +typedef UINT16 (EFIAPI * SA_IO_READ_16) (UINTN IoAddress)= ; = = ///< CPU I/O port 16-bit read.=0D +typedef UINT32 (EFIAPI * SA_IO_READ_32) (UINTN IoAddress)= ; = = ///< CPU I/O port 32-bit read.=0D +typedef UINT8 (EFIAPI * SA_IO_WRITE_8) (UINTN IoAddress,= UINT8 Value); = = ///< CPU I/O port 8-bit write.=0D +typedef UINT16 (EFIAPI * SA_IO_WRITE_16) (UINTN IoAddress,= UINT16 Value); = = ///< CPU I/O port 16-bit write.=0D +typedef UINT32 (EFIAPI * SA_IO_WRITE_32) (UINTN IoAddress,= UINT32 Value); = = ///< CPU I/O port 32-bit write.=0D +typedef UINT8 (EFIAPI * SA_MMIO_READ_8) (UINTN Address); = = = ///< Memory Mapped I/O port 8-bit read.=0D +typedef UINT16 (EFIAPI * SA_MMIO_READ_16) (UINTN Address); = = = ///< Memory Mapped I/O port 16-bit read.=0D +typedef UINT32 (EFIAPI * SA_MMIO_READ_32) (UINTN Address); = = = ///< Memory Mapped I/O port 32-bit read.=0D +typedef UINT64 (EFIAPI * SA_MMIO_READ_64) (UINTN Address); = = = ///< Memory Mapped I/O port 64-bit read.=0D +typedef UINT8 (EFIAPI * SA_MMIO_WRITE_8) (UINTN Address, U= INT8 Value); = = ///< Memory Mapped I/O port 8-bit write.=0D +typedef UINT16 (EFIAPI * SA_MMIO_WRITE_16) (UINTN Address, U= INT16 Value); = = ///< Memory Mapped I/O port 16-bit write.=0D +typedef UINT32 (EFIAPI * SA_MMIO_WRITE_32) (UINTN Address, U= INT32 Value); = = ///< Memory Mapped I/O port 32-bit write.=0D +typedef UINT64 (EFIAPI * SA_MMIO_WRITE_64) (UINTN Address, U= INT64 Value); = = ///< Memory Mapped I/O port 64-bit write.=0D +typedef UINT8 (EFIAPI * SA_SMBUS_READ_8) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 8-bit read.=0D +typedef UINT16 (EFIAPI * SA_SMBUS_READ_16) (UINTN Address, R= ETURN_STATUS *Status); = = ///< Smbus 16-bit read.=0D +typedef UINT8 (EFIAPI * SA_SMBUS_WRITE_8) (UINTN Address, U= INT8 Value, RETURN_STATUS *Status); = = ///< Smbus 8-bit write.=0D +typedef UINT16 (EFIAPI * SA_SMBUS_WRITE_16) (UINTN Address, U= INT16 Value, RETURN_STATUS *Status); = = ///< Smbus 16-bit write.=0D +typedef UINT32 (EFIAPI * SA_GET_PCI_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI device address.=0D +typedef UINT32 (EFIAPI * SA_GET_PCIE_DEVICE_ADDRESS) (UINT8 Bus, UINT8= Device, UINT8 Function, UINT8 Offset); = = ///< Get PCI express device address.=0D +typedef VOID (EFIAPI * SA_GET_RTC_TIME) (UINT8 *Second, U= INT8 *Minute, UINT8 *Hour, UINT8 *Day, UINT8 *Month, UINT16 *Year); = = ///< Get the current time value.=0D +typedef UINT64 (EFIAPI * SA_GET_CPU_TIME) (VOID); = = = ///< The current CPU time in milliseconds.=0D +typedef VOID * (EFIAPI * SA_MEMORY_COPY) (VOID *Destinatio= n, CONST VOID *Source, UINTN NumBytes); = = ///< Perform byte copy operation.=0D +typedef VOID * (EFIAPI * SA_MEMORY_SET_BYTE) (VOID *Buffer, UI= NTN NumBytes, UINT8 Value); = = ///< Perform byte initialization operation.=0D +typedef VOID * (EFIAPI * SA_MEMORY_SET_WORD) (VOID *Buffer, UI= NTN NumWords, UINT16 Value); = = ///< Perform word initialization operation.=0D +typedef VOID * (EFIAPI * SA_MEMORY_SET_DWORD) (VOID *Buffer, UI= NTN NumDwords, UINT32 Value); = = ///< Perform dword initialization operation.=0D +typedef UINT64 (EFIAPI * SA_LEFT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Left shift the 64-bit data value by specifie= d number of bits.=0D +typedef UINT64 (EFIAPI * SA_RIGHT_SHIFT_64) (UINT64 Data, UIN= TN NumBits); = = ///< Right shift the 64-bit data value by specifi= ed number of bits.=0D +typedef UINT64 (EFIAPI * SA_MULT_U64_U32) (UINT64 Multiplic= and, UINT32 Multiplier); = = ///< Multiply a 64-bit data value by a 32-bit dat= a value.=0D +typedef UINT64 (EFIAPI * SA_DIV_U64_U64) (UINT64 Dividend,= UINT64 Divisor, UINT64 *Remainder); = = ///< Divide a 64-bit data value by a 64-bit data = value.=0D +typedef BOOLEAN (EFIAPI * SA_GET_SPD_DATA) (SPD_BOOT_MODE Bo= otMode, UINT8 SpdAddress, UINT8 *Buffer, UINT8 *Ddr3Table, UINT32 Ddr3Table= Size, UINT8 *Ddr4Table, UINT32 Ddr4TableSize, UINT8 *LpddrTable, UINT32 Lpd= drTableSize); ///< Read the SPD data over the SMBus, at the giv= en SmBus SPD address and copy the data to the data structure.=0D +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_DECODE) (UINT64 Address, = SA_ADDRESS_DECODE *DramAddress);=0D +typedef UINT8 (EFIAPI * SA_GET_MC_ADDRESS_ENCODE) (SA_ADDRESS_DECOD= E *DramAddress, UINT64 Address);=0D +typedef BOOLEAN (EFIAPI * SA_GET_RANDOM_NUMBER) (UINT32 *Rand); = = = ///< Get the next random 32-bit number.=0D +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_READ) (UINT32 Type, UIN= T32 Command, UINT32 *Value, UINT32 *Status); = = ///< Perform a CPU mailbox read.=0D +typedef EFI_STATUS (EFIAPI * SA_CPU_MAILBOX_WRITE) (UINT32 Type, UIN= T32 Command, UINT32 Value, UINT32 *Status); = = ///< Perform a CPU mailbox write.=0D +typedef UINT32 (EFIAPI * SA_GET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd); = = ///< Get the current memory voltage (VDD).=0D +typedef UINT32 (EFIAPI * SA_SET_MEMORY_VDD) (VOID *GlobalData= , UINT32 DefaultVdd, UINT32 Value); = = ///< Set the memory voltage (VDD) to the given va= lue.=0D +typedef UINT32 (EFIAPI * SA_CHECKPOINT) (VOID *GlobalData= , UINT32 CheckPoint, VOID *Scratch); = = ///< Check point that is called at various points= in the MRC.=0D +typedef VOID (EFIAPI * SA_DEBUG_HOOK) (VOID *GlobalData= , UINT16 DisplayDebugNumber); = = ///< Typically used to display to the I/O port 80= h.=0D +typedef UINT8 (EFIAPI * SA_CHANNEL_EXIST) (VOID *Outputs, U= INT8 Channel); = = ///< Returns whether Channel is or is not present= .=0D +typedef INT32 (EFIAPI * SA_PRINTF) (VOID *Debug, UIN= T32 Level, char *Format, ...); = = ///< Print to output stream/device.=0D +typedef VOID (EFIAPI * SA_DEBUG_PRINT) (VOID *String); = = = ///< Output a string to the debug stream/device.= =0D +typedef UINT32 (EFIAPI * SA_CHANGE_MARGIN) (VOID *GlobalData= , UINT8 Param, INT32 Value0, INT32 Value1, UINT8 EnMultiCast, UINT8 Channel= , UINT8 RankIn, UINT8 Byte, UINT8 BitIn, UINT8 UpdateMrcData, UINT8 SkipWai= t, UINT32 RegFileParam); ///< Change the margin.=0D +typedef UINT8 (EFIAPI * SA_SIGN_EXTEND) (UINT8 Value, UIN= T8 OldMsb, UINT8 NewMsb); = = ///< Sign extends OldMSB to NewMSB Bits (Eg: Bit = 6 to Bit 7).=0D +typedef VOID (EFIAPI * SA_SHIFT_PI_COMMAND_TRAIN) (VOID *GlobalData= , UINT8 Channel, UINT8 Iteration, UINT8 RankMask, UINT8 GroupMask, INT32 Ne= wValue, UINT8 UpdateHost); = ///< Move CMD/CTL/CLK/CKE PIs during training.=0D +typedef VOID (EFIAPI * SA_UPDATE_VREF) (VOID *GlobalData= , UINT8 Channel, UINT8 RankMask, UINT16 DeviceMask, UINT8 VrefType, INT32 O= ffset, BOOLEAN UpdateMrcData, BOOLEAN PDAmode, BOOLEAN SkipWait); = ///< Update the Vref value and wait until it is s= table.=0D +typedef UINT8 (EFIAPI * SA_GET_RTC_CMOS) (UINT8 Location);= = = ///< Get the current value of the specified RTC C= MOS location.=0D +typedef UINT64 (EFIAPI * SA_MSR_READ_64) (UINT32 Location)= ; = = ///< Get the current value of the specified MSR l= ocation.=0D +typedef UINT64 (EFIAPI * SA_MSR_WRITE_64) (UINT32 Location,= UINT64 Data); = = ///< Set the current value of the specified MSR l= ocation.=0D +typedef VOID (EFIAPI * SA_MRC_RETURN_FROM_SMC) (VOID *GlobalData= , UINT32 MrcStatus); = = ///< Hook function after returning from MrcStartM= emoryConfiguration()=0D +typedef VOID (EFIAPI * SA_MRC_DRAM_RESET) (UINT32 PciEBaseA= ddress, UINT32 ResetValue); = = ///< Assert or deassert DRAM_RESET# pin; this is = used in JEDEC Reset.=0D +typedef VOID (EFIAPI * SA_DELAY_NS) (VOID *GlobalData= , UINT32 DelayNs); = = ///< Delay (stall) for the given amount of nanose= conds.=0D +typedef VOID (EFIAPI * SA_SET_LOCK_PRMRR) (UINT64 PrmrrBase= Address, UINT32 PrmrrSize);=0D +=0D +=0D +///=0D +/// Function calls into the SA.=0D +///=0D +typedef struct {=0D + SA_IO_READ_8 IoRead8; ///< Offset 0: - CPU= I/O port 8-bit read.=0D + SA_IO_READ_16 IoRead16; ///< Offset 4: - CPU= I/O port 16-bit read.=0D + SA_IO_READ_32 IoRead32; ///< Offset 8: - CPU= I/O port 32-bit read.=0D + SA_IO_WRITE_8 IoWrite8; ///< Offset 12: - CPU= I/O port 8-bit write.=0D + SA_IO_WRITE_16 IoWrite16; ///< Offset 16: - CPU= I/O port 16-bit write.=0D + SA_IO_WRITE_32 IoWrite32; ///< Offset 20: - CPU= I/O port 32-bit write.=0D + SA_MMIO_READ_8 MmioRead8; ///< Offset 24: - Mem= ory Mapped I/O port 8-bit read.=0D + SA_MMIO_READ_16 MmioRead16; ///< Offset 28: - Mem= ory Mapped I/O port 16-bit read.=0D + SA_MMIO_READ_32 MmioRead32; ///< Offset 32: - Mem= ory Mapped I/O port 32-bit read.=0D + SA_MMIO_READ_64 MmioRead64; ///< Offset 36: - Mem= ory Mapped I/O port 64-bit read.=0D + SA_MMIO_WRITE_8 MmioWrite8; ///< Offset 40: - Mem= ory Mapped I/O port 8-bit write.=0D + SA_MMIO_WRITE_16 MmioWrite16; ///< Offset 44: - Mem= ory Mapped I/O port 16-bit write.=0D + SA_MMIO_WRITE_32 MmioWrite32; ///< Offset 48: - Mem= ory Mapped I/O port 32-bit write.=0D + SA_MMIO_WRITE_64 MmioWrite64; ///< Offset 52: - Mem= ory Mapped I/O port 64-bit write.=0D + SA_SMBUS_READ_8 SmbusRead8; ///< Offset 56: - Smb= us 8-bit read.=0D + SA_SMBUS_READ_16 SmbusRead16; ///< Offset 60: - Smb= us 16-bit read.=0D + SA_SMBUS_WRITE_8 SmbusWrite8; ///< Offset 64: - Smb= us 8-bit write.=0D + SA_SMBUS_WRITE_16 SmbusWrite16; ///< Offset 68: - Smb= us 16-bit write.=0D + SA_GET_PCI_DEVICE_ADDRESS GetPciDeviceAddress; ///< Offset 72: - Get= PCI device address.=0D + SA_GET_PCIE_DEVICE_ADDRESS GetPcieDeviceAddress; ///< Offset 76: - Get= PCI express device address.=0D + SA_GET_RTC_TIME GetRtcTime; ///< Offset 80: - Get= the current time value.=0D + SA_GET_CPU_TIME GetCpuTime; ///< Offset 84: - The= current CPU time in milliseconds.=0D + SA_MEMORY_COPY CopyMem; ///< Offset 88: - Per= form byte copy operation.=0D + SA_MEMORY_SET_BYTE SetMem; ///< Offset 92: - Per= form byte initialization operation.=0D + SA_MEMORY_SET_WORD SetMemWord; ///< Offset 96: - Per= form word initialization operation.=0D + SA_MEMORY_SET_DWORD SetMemDword; ///< Offset 100: - Per= form dword initialization operation.=0D + SA_LEFT_SHIFT_64 LeftShift64; ///< Offset 104: - Lef= t shift the 64-bit data value by specified number of bits.=0D + SA_RIGHT_SHIFT_64 RightShift64; ///< Offset 108: - Rig= ht shift the 64-bit data value by specified number of bits.=0D + SA_MULT_U64_U32 MultU64x32; ///< Offset 112: - Mul= tiply a 64-bit data value by a 32-bit data value.=0D + SA_DIV_U64_U64 DivU64x64; ///< Offset 116: - Div= ide a 64-bit data value by a 64-bit data value.=0D + SA_GET_SPD_DATA GetSpdData; ///< Offset 120: - Rea= d the SPD data over the SMBus, at the given SmBus SPD address and copy the = data to the data structure.=0D + SA_GET_RANDOM_NUMBER GetRandomNumber; ///< Offset 124: - Get= the next random 32-bit number.=0D + SA_CPU_MAILBOX_READ CpuMailboxRead; ///< Offset 128: - Per= form a CPU mailbox read.=0D + SA_CPU_MAILBOX_WRITE CpuMailboxWrite; ///< Offset 132: - Per= form a CPU mailbox write.=0D + SA_GET_MEMORY_VDD GetMemoryVdd; ///< Offset 136: - Get= the current memory voltage (VDD).=0D + SA_SET_MEMORY_VDD SetMemoryVdd; ///< Offset 140: - Set= the memory voltage (VDD) to the given value.=0D + SA_CHECKPOINT CheckPoint; ///< Offset 144: - Che= ck point that is called at various points in the MRC.=0D + SA_DEBUG_HOOK DebugHook; ///< Offset 148: - Typ= ically used to display to the I/O port 80h.=0D + SA_DEBUG_PRINT DebugPrint; ///< Offset 152: - Out= put a string to the debug stream/device.=0D + SA_GET_RTC_CMOS GetRtcCmos; ///< Offset 156: - Get= the current value of the specified RTC CMOS location.=0D + SA_MSR_READ_64 ReadMsr64; ///< Offset 160: - Get= the current value of the specified MSR location.=0D + SA_MSR_WRITE_64 WriteMsr64; ///< Offset 164 - Set= the current value of the specified MSR location.=0D + SA_MRC_RETURN_FROM_SMC MrcReturnFromSmc; ///< Offset 168 - Hoo= k function after returning from MrcStartMemoryConfiguration()=0D + SA_MRC_DRAM_RESET MrcDramReset; ///< Offset 172 - Ass= ert or deassert DRAM_RESET# pin; this is used in JEDEC Reset.=0D + SA_DELAY_NS MrcDelayNs; ///< Offset 176 - Del= ay (stall) for the given amount of nanoseconds.=0D +} SA_FUNCTION_CALLS;=0D +=0D +///=0D +/// Function calls into the MRC.=0D +///=0D +typedef struct {=0D + SA_CHANNEL_EXIST MrcChannelExist; ///< Offset 0: - Retu= rns whether Channel is or is not present.=0D + SA_PRINTF MrcPrintf; ///< Offset 4: - Prin= t to output stream/device.=0D + SA_CHANGE_MARGIN MrcChangeMargin; ///< Offset 8: - Chan= ge the margin.=0D + SA_SIGN_EXTEND MrcSignExtend; ///< Offset 12: - Sign= extends OldMSB to NewMSB Bits (Eg: Bit 6 to Bit 7).=0D + SA_SHIFT_PI_COMMAND_TRAIN ShiftPiCommandTrain; ///< Offset 16: - Move= CMD/CTL/CLK/CKE PIs during training.=0D + SA_UPDATE_VREF MrcUpdateVref; ///< Offset 20: - Upda= te the Vref value and wait until it is stable.=0D +} SA_MEMORY_FUNCTIONS;=0D +=0D +/**=0D + Memory Configuration=0D + The contents of this structure are CRC'd by the MRC for option change det= ection.=0D + This structure is copied en mass to the MrcInput structure. If you add fi= elds here, you must update the MrcInput structure.=0D + Revision 1: - Initial version.=0D + Revision 2: - Adding ChHashOverride option.=0D + Revision 3: - Adding PDA enumeration option.=0D + Revision 4: - Adding LPDDR4 Command Mirroring.=0D + Revision 5: - Adding CpuBclkSpread option.=0D + Revision 6: - Adding McParity option.=0D + Revision 7: - Adding VddqVoltageOverride option.=0D + Revision 8: - Adding ExtendedBankHashing option.=0D + Revision 9: - Adding IbeccErrorInj option=0D + **/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header=0D + UINT16 Size; ///< Offset 28 The size of this structur= e, in bytes. Must be the first entry in this structure.=0D + UINT8 HobBufferSize; ///< Offset 30 Size of HOB buffer for MR= C=0D +=0D + UINT8 SpdProfileSelected; ///< Offset 31 SPD XMP profile selection= - for XMP supported DIMM: 0=3DDefault DIMM profile, 1=3DCustomized = profile, 2=3DXMP profile 1, 3=3DXMP profile 2.=0D +=0D + // The following parameters are used only when SpdProfileSelected is Use= rDefined (CUSTOM PROFILE)=0D + UINT16 tCL; ///< Offset 32 User defined Memory Timin= g tCL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 31=3DMaximum.=0D + UINT16 tRCDtRP; ///< Offset 34 User defined Memory Timin= g tRCD value (same as tRP), valid when SpdProfileSelected is CUSTOM_PROFILE= : 0=3DAUTO, 63=3DMaximum=0D + UINT16 tRAS; ///< Offset 36 User defined Memory Timin= g tRAS value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 64=3DMaximum.=0D + UINT16 tWR; ///< Offset 38 User defined Memory Timin= g tWR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , legal values: 5, 6, 7, 8, 10, 12, 14, 16, 18, 20, 24.=0D + UINT16 tRFC; ///< Offset 40 User defined Memory Timin= g tRFC value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 1023=3DMaximum.=0D + UINT16 tRRD; ///< Offset 42 User defined Memory Timin= g tRRD value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum.=0D + UINT16 tWTR; ///< Offset 44 User defined Memory Timin= g tWTR value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 28=3DMaximum.=0D + UINT16 tRTP; ///< Offset 46 User defined Memory Timin= g tRTP value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 15=3DMaximum. DDR4 legal values: 5, 6, 7, 8, 9, 10, 12=0D + UINT16 tFAW; ///< Offset 48 User defined Memory Timin= g tFAW value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 63=3DMaximum.=0D + UINT16 tCWL; ///< Offset 50 User defined Memory Timin= g tCWL value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 20=3DMaximum.=0D + UINT16 tREFI; ///< Offset 52 User defined Memory Timin= g tREFI value, valid when SpdProfileSelected is CUSTOM_PROFILE: 0=3DAUTO= , 65535=3DMaximum.=0D + UINT16 PciIndex; ///< Offset 54 Pci index register addres= s: 0xCF8=3DDefault=0D + UINT16 PciData; ///< Offset 56 Pci data register address= : 0xCFC=3DDefault=0D + UINT16 VddVoltage; ///< Offset 58 DRAM voltage (Vdd) in mil= livolts: 0=3DPlatform Default (no override), 1200=3D1.2V, 1350=3D1.3= 5V etc.=0D + UINT16 Idd3n; ///< Offset 60 EPG Active standby curren= t (Idd3N) in milliamps from DIMM datasheet.=0D + UINT16 Idd3p; ///< Offset 62 EPG Active power-down cur= rent (Idd3P) in milliamps from DIMM datasheet.=0D +=0D + UINT32 EccSupport:1; ///< Offset 64 Bit 0 - DIMM Ecc Supp= ort option - for Desktop only: 0=3DDisable, 1=3DEnable=0D + UINT32 MrcSafeConfig:1; ///< Bit 1 - MRC Safe Mode= : 0=3DDisable, 1=3DEnable=0D + UINT32 RemapEnable:1; ///< Bit 2 - This option i= s used to control whether to enable/disable memory remap above 4GB: 0=3DDis= able, 1=3DEnable.=0D + UINT32 ScramblerSupport:1; ///< Bit 3 - Memory scramb= ler support: 0=3DDisable, 1=3DEnable=0D + UINT32 Vc1ReadMeter:1; ///< Bit 4 - VC1 Read Mete= ring Enable: 0=3DDisable, 1=3DEnable=0D + UINT32 ForceSingleSubchannel:1; ///< Bit 5 - TRUE means us= e SubChannel0 only (for LPDDR4): 0=3DDisable, 1=3DEnable=0D + UINT32 SimicsFlag:1; ///< Bit 6 - Option to Ena= ble SIMICS: 0=3DDisable, 1=3DEnable=0D + UINT32 Ddr4DdpSharedClock:1; ///< Bit 7 - Select if CLK= 0 is shared between Rank0 and Rank1 in DDR4 DDP package. 0=3DNot shared<= /b>, 1=3DShared=0D + UINT32 SharedZqPin:1; ///< Bit 8 - Select if the= ZQ resistor is shared between Ranks in DDR4/LPDDR4 DRAM Packages 0=3DNo= t Shared, 1=3DShared=0D + UINT32 LpDqsOscEn:1; ///< Bit 9 - LPDDR Write D= Q/DQS Retraining: 0=3DDisable, 1=3DEnable=0D + UINT32 RmtPerTask:1; ///< Bit 10 - Rank Margin T= ool Per Task. 0 =3D Disabled, 1 =3D Enabled=0D + UINT32 TrainTrace:1; ///< Bit 11 - Trained state= tracing debug. 0 =3D Disabled, 1 =3D Enabled=0D + UINT32 SafeMode:1; ///< Bit 12 - Define if saf= e mode is enabled for MC/IO=0D + UINT32 MsHashEnable:1; ///< Bit 13 - Controller Ha= sh Enable: 0=3DDisable, 1=3DEnable=0D + UINT32 DisPgCloseIdleTimeout:1; ///< Bit 14 - Disable Page = Close Idle Timeout: 0=3DEnable, 1=3DDisable=0D + UINT32 Ibecc:1; ///< Bit 15 - Inband ECC - = for LPDDR4, LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEnable=0D + UINT32 IbeccParity:1; ///< Bit 16 - Inband ECC Pa= rity Control - for LPDDR4, LPDDR5 and DDR4 only: 0=3DDisable, 1=3DEn= able=0D + UINT32 IbeccOperationMode:2; ///< Bits 17:18 - Inband EC= C Operation Mode: 0=3DFunctional Mode protects requests based on the addres= s range, 1=3DMakes all requests non protected and ignore range checks, 2=3DMakes all requests protected and ignore range checks=0D + UINT32 ChHashOverride:1; ///< Bit 19 - Select if Cha= nnel Hash setting values will be taken from input parameters or automatical= ly taken from POR values depending on DRAM type detected.=0D + UINT32 McParity:1; ///< Bit 20 - MC Parity Con= trol - Enable Parity for CMI/MC: 0=3DDisable, 1=3DEnable=0D + UINT32 IbeccErrorInj:1; ///< Bit 21 - In-Band ECC E= rror Injection: 1=3DEnable, 0=3DDisable=0D + UINT32 RsvdO64B22t31:10; ///< Bits 22:31 reserved=0D + /**=0D + Disables a DIMM slot in the channel even if a DIMM is present\n=0D + Array index represents the channel number (0 =3D channel 0, 1 =3D chann= el 1)\n=0D + 0x0 =3D DIMM 0 and DIMM 1 enabled\n=0D + 0x1 =3D DIMM 0 disabled, DIMM 1 enabled\n=0D + 0x2 =3D DIMM 0 enabled, DIMM 1 disabled\n=0D + 0x3 =3D DIMM 0 and DIMM 1 disabled (will disable the whole channel)\n= =0D + **/=0D + UINT8 DisableDimmChannel[MEM_CFG_MAX_CONTROLLERS][MEM_CFG_MAX_CHANNELS= ]; ///< Offset 68-75=0D + UINT8 Ratio; ///< Offset 76 DDR Frequency ratio, to m= ultiply by 133 or 100 MHz depending on RefClk. 0 =3D Auto=0D + UINT8 ProbelessTrace; ///< Offset 77 Probeless Trace: 0=3DD= isabled, 1=3DEnabled=0D + /**=0D + - Channel Hash Enable.\n=0D + NOTE: BIT7 will interleave the channels at a 2 cache-line granularity,= BIT8 at 4 and BIT9 at 8\n=0D + 0=3DBIT6, 1=3DBIT7, 2=3DBIT8, 3=3DBIT9=0D + **/=0D + UINT8 ChHashInterleaveBit; ///< Offset 78 Option to select interlea= ve Address bit. Valid values are 0 - 3 for BITS 6 - 9 (Valid values for BDW= are 0-7 for BITS 6 - 13)=0D + UINT8 SmramMask; ///< Offset 79 Reserved memory ranges fo= r SMRAM=0D + UINT32 BClkFrequency; ///< Offset 80 Base reference clock valu= e, in Hertz: 100000000 =3D 100Hz, 125000000=3D125Hz, 167000000=3D167= Hz, 250000000=3D250Hz=0D +=0D + /// Training Algorithms 1 Offset 84=0D + UINT32 ECT:1; ///< Bit 0 - Enable/Disable Early Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable.=0D + UINT32 SOT:1; ///< Bit 1 - Enable/Disable Sense Amp Of= fset Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable.=0D + UINT32 ERDMPRTC2D:1; ///< Bit 2 - Enable/Disable Early ReadMP= R Timing Centering 2D. Note it is not recommended to change this setting fr= om the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDMPRT:1; ///< Bit 3 - Enable/Disable Read MPR Tra= ining. Note it is not recommended to change this setting from the default v= alue: 0=3DDisable, 1=3DEnable.=0D + UINT32 RCVET:1; ///< Bit 4 - Enable/Disable Receive Enab= le Training. Note it is not recommended to change this setting from the def= ault value: 0=3DDisable, 1=3DEnable.=0D + UINT32 JWRL:1; ///< Bit 5 - Enable/Disable JEDEC Write = Leveling Training. Note it is not recommended to change this setting from t= he default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 EWRTC2D:1; ///< Bit 6 - Enable/Disable Early Write = Time Centering 2D Training. Note it is not recommended to change this setti= ng from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 ERDTC2D:1; ///< Bit 7 - Enable/Disable Early Read T= ime Centering 2D Training. Note it is not recommended to change this settin= g from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRTC1D:1; ///< Bit 8 - Enable/Disable 1D Write Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRVC1D:1; ///< Bit 9 - Enable/Disable 1D Write Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDTC1D:1; ///< Bit 10 - Enable/Disable 1D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 DIMMODTT:1; ///< Bit 11 - Enable/Disable DIMM ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable.=0D + UINT32 DIMMRONT:1; ///< Bit 12 - Enable/Disable DIMM RON tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRDSEQT:1; ///< Bit 13 - Enable/Disable Write Drive= Strength / Equalization Training 2D. Note it is not recommended to change = this setting from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRSRT:1; ///< Bit 14 - Enable/Disable Write Slew = Rate traning. Note it is not recommended to change this setting from the de= fault value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDODTT:1; ///< Bit 15 - Enable/Disable Read ODT Tr= aining. Note it is not recommended to change this setting from the default = value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDEQT:1; ///< Bit 16 - Enable/Disable Read Equali= zation Training. Note it is not recommended to change this setting from the= default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDAPT:1; ///< Bit 17 - Enable/Disable Read Amplif= ier Power Training. Note it is not recommended to change this setting from = the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRTC2D:1; ///< Bit 18 - Enable/Disable 2D Write Ti= ming Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDTC2D:1; ///< Bit 19 - Enable/Disable 2D Read Tim= ing Centering Training. Note it is not recommended to change this setting f= rom the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRVC2D:1; ///< Bit 20 - Enable/Disable 2D Write Vo= ltage Centering Training. Note it is not recommended to change this setting= from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDVC2D:1; ///< Bit 21 - Enable/Disable 2D Read Vol= tage Centering Training. Note it is not recommended to change this setting = from the default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 CMDVC:1; ///< Bit 22 - Enable/Disable Command Vre= f Centering Training. Note it is not recommended to change this setting fro= m the default value 0=3DDisable, 1=3DEnable.=0D + UINT32 LCT:1; ///< Bit 23 - Enable/Disable Late Comman= d Training. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RTL:1; ///< Bit 24 - Enable/Disable Round Trip = Latency function. Note it is not recommended to change this setting from th= e default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 TAT:1; ///< Bit 25 - Enable/Disable Turn Around= Time function. Note it is not recommended to change this setting from the = default value: 0=3DDisable, 1=3DEnable.=0D + UINT32 RMT:1; ///< Bit 26 - Enable/Disable Rank Margin= Tool function: 0=3DDisable, 1=3DEnable.=0D + UINT32 MEMTST:1; ///< Bit 27 - Enable/Disable Memory Test= function: 0=3DDisable, 1=3DEnable.=0D + UINT32 ALIASCHK:1; ///< Bit 28 - Enable/Disable DIMM SPD Al= ias Check: 0=3DDisable, 1=3DEnable=0D + UINT32 RCVENC1D:1; ///< Bit 29 - Enable/Disable Receive Ena= ble Centering Training (LPDDR Only). Note it is not recommended to change t= his setting from the default value: 0=3DDisable, 1=3DEnable=0D + UINT32 RMC:1; ///< Bit 30 - Enable/Disable Retrain Mar= gin Check. Note it is not recommended to change this setting from the defa= ult value: 0=3DDisable, 1=3DEnable=0D + UINT32 WRDSUDT:1; ///< Bit 31 - Enable/Disable Write Drive= Strength Up/Dn independently. Note it is not recommended to change this se= tting from the default value: 0=3DDisable, 1=3DEnable=0D + /// Training Algorithms 2 Offset 88=0D + UINT32 DCC : 1; ///< Bit 0 - Enable/Disable Duty Cycle = Correction: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDVC1D : 1; ///< Bit 1 - Enable/Disable Read Voltag= e Centering 1D: 0=3DDisable, 1=3DEnable.=0D + UINT32 TXTCO : 1; ///< Bit 2 - Enable/Disable Write TCO C= omp Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 CLKTCO : 1; ///< Bit 3 - Enable/Disable Clock TCO C= omp Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 CMDSR : 1; ///< Bit 4 - Enable/Disable CMD Slew Ra= te Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 CMDDSEQ : 1; ///< Bit 5 - Enable/Disable CMD Drive S= trength and Tx Equalization: 0=3DDisable, 1=3DEnable.=0D + UINT32 DIMMODTCA : 1; ///< Bit 6 - Enable/Disable Dimm ODT CA= Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 TXTCODQS : 1; ///< Bit 7 - Enable/Disable Write TCO D= qs Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 CMDDRUD : 1; ///< Bit 8 - Enable/Disable CMD/CTL Dri= ve Strength Up/Dn 2D: 0=3DDisable, 1=3DEnable.=0D + UINT32 VCCDLLBP : 1; ///< Bit 9 - Enable/Disable VccDLL bypa= ss to VccIOG training: 0=3DDisable, 1=3DEnable.=0D + UINT32 PVTTDNLP : 1; ///< Bit 10 - Enable/Disable PanicVttDnL= p Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 RDVREFDC : 1; ///< Bit 11 - Enable/Disable Read Vref D= ecap Training: 0=3DDisable, 1=3DEnable.=0D + UINT32 VDDQT : 1; ///< Bit 12 - Enable/Disable Vddq Traini= ng: 0=3DDisable, 1=3DEnable.=0D + UINT32 RMTBIT : 1; ///< Bit 13 - Enable/Disable Rank Margin= Tool Per Bit: 0=3DDisable, 1=3DEnable.=0D + UINT32 PDA : 1; ///< BIT 14 - Enable/Disable PDA Enumera= tion Training. Note it is not recommended to change this setting from the d= efault value: 0=3DDisable, 1=3DEnable.=0D + UINT32 WRITE0 : 1; ///< BIT 15 - Write0 feature enablement= =0D + UINT32 ReservedBits2 :16; ///< Bits 16:31 - Reserved=0D +=0D + UINT32 MrcTimeMeasure:1; ///< Offset 92 Bit 0 - Enables serial= debug level to display the MRC execution times only: 0=3DDisable, 1= =3DEnable=0D + UINT32 MrcFastBoot:1; ///< Bit 1 - Enables the MR= C fast boot path for faster cold boot execution: 0=3DDisable, 1=3DEnable= =0D + UINT32 DqPinsInterleaved:1; ///< Bit 2 - Interleaving m= ode of DQ/DQS pins which depends on board routing: 0=3DDisable, 1=3D= Enable=0D + UINT32 RankInterleave:1; ///< Bit 3 - Rank Interleav= e Mode: 0=3DDisable, 1=3DEnable=0D + UINT32 EnhancedInterleave:1; ///< Bit 4 - Enhanced Inter= leave Mode: 0=3DDisable, 1=3DEnable=0D + UINT32 WeaklockEn:1; ///< Bit 5 - Weak Lock Enab= le: 0=3DDisable, 1=3DEnable=0D + UINT32 ChHashEnable:1; ///< Bit 6 - Channel Hash E= nable: 0=3DDisable, 1=3DEnable=0D + UINT32 EnablePwrDn:1; ///< Bit 7 - Enable Power D= own control for DDR: 0=3DPCODE control, 1=3DBIOS control=0D + UINT32 EnablePwrDnLpddr:1; ///< Bit 8 - Enable Power D= own for LPDDR: 0=3DPCODE control, 1=3DBIOS control=0D + UINT32 SrefCfgEna:1; ///< Bit 9 - Enable Self Re= fresh: 0=3DDisable, 1=3DEnable=0D + UINT32 ThrtCkeMinDefeatLpddr:1; ///< Bit 10 - Throttler CKE = min defeature for LPDDR: 0=3DDisable, 1=3DEnable=0D + UINT32 ThrtCkeMinDefeat:1; ///< Bit 11 - Throttler CKE = min defeature: 0=3DDisable, 1=3DEnable=0D + UINT32 AutoSelfRefreshSupport:1; ///< Bit 12 - FALSE =3D No a= uto self refresh support, TRUE =3D auto self refresh support=0D + UINT32 ExtTemperatureSupport:1; ///< Bit 13 - FALSE =3D No e= xtended temperature support, TRUE =3D extended temperature support=0D + UINT32 MobilePlatform:1; ///< Bit 14 - Memory control= ler device id indicates: TRUE if mobile, FALSE if not. Note: This wi= ll be auto-detected and updated.=0D + UINT32 Force1Dpc:1; ///< Bit 15 - TRUE means for= ce one DIMM per channel, FALSE means no limit=0D + UINT32 ForceSingleRank:1; ///< Bit 16 - TRUE means use= Rank0 only (in each DIMM): 0=3DDisable, 1=3DEnable=0D + UINT32 VttTermination:1; ///< Bit 17 - Vtt Terminatio= n for Data ODT: 0=3DDisable, 1=3DEnable=0D + UINT32 VttCompForVsshi:1; ///< Bit 18 - Enable/Disable= Vtt Comparator For Vsshi: 0=3DDisable, 1=3DEnable=0D + UINT32 ExitOnFailure:1; ///< Bit 19 - MRC option for= exit on failure or continue on failure: 0=3DDisable, 1=3DEnable=0D + UINT32 NewFeatureEnable1:1; ///< Bit 20 - Generic enable= knob for new feature set 1 0: Disable ; 1: Enable=0D + UINT32 NewFeatureEnable2:1; ///< Bit 21 - Generic enable= knob for new feature set 2 0: Disable ; 1: Enable=0D + UINT32 RhPrevention:1; ///< Bit 22 - RH Prevention = Enable/Disable: 0=3DDisable, 1=3DEnable=0D + UINT32 RhSolution:1; ///< Bit 23 - Type of soluti= on to be used for RHP - 0/1 =3D HardwareRhp/Refresh2x=0D + UINT32 RefreshPanicWm:4; ///< Bit 24-27 - Refresh Pan= ic Watermark, Range 1-8, default 8.=0D + UINT32 RefreshHpWm:4; ///< Bit 28-31 - Refresh Hig= h Profile Watermark, Range 1-7, default 7.=0D + UINT32 VddSettleWaitTime; ///< Offset 96 Amount of time in microse= conds to wait for Vdd to settle on top of 200us required by JEDEC spec: = Default=3D0=0D + UINT16 SrefCfgIdleTmr; ///< Offset 100 Self Refresh idle timer:= 512=3DMinimal, 65535=3DMaximum=0D + UINT16 ChHashMask; ///< Offset 102 Channel Hash Mask: 0x000= 1=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT[19= :18, 13:12 ,9:7] set=0D + UINT16 DdrFreqLimit; ///< Offset 104 Memory Frequency setting= : 3=3D1067, 5=3D1333, 7=3D1600, 9=3D1867, 11=3D2133, 13=3D2400, 15=3D266= 7=0D + UINT8 MaxRttWr; ///< Offset 106 Maximum DIMM RTT_WR to u= se in power training: 0=3DODT Off, 1 =3D 120 ohms=0D + UINT8 ThrtCkeMinTmr; ///< Offset 107 Throttler CKE min timer:= 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault=0D + UINT8 ThrtCkeMinTmrLpddr; ///< Offset 108 Throttler CKE min timer = for LPDDR: 0=3DMinimal, 0xFF=3DMaximum, 0x00=3DDefault=0D + BOOLEAN PerBankRefresh; ///< Offset 109 Enables and Disables the= per bank refresh. This only impacts memory technologies that support PBR:= LPDDR3, LPDDR4. FALSE=3DDisabled, TRUE=3DEnabled=0D + UINT8 SaGv; ///< Offset 110 SA GV: 0=3DDisabled, 1=3DPoint1, 2=3DPoint2, 3=3DPoint3, 4=3DPoint4, 5=3DEnabled=0D + UINT8 NModeSupport; ///< Offset 111 Memory N Mode Support - = Enable user to select Auto, 1N or 2N: 0=3DAUTO, 1=3D1N, 2=3D2N.=0D + UINT8 RefClk; ///< Offset 112 Selects the DDR base ref= erence clock. 0x01 =3D 100MHz, 0x00 =3D 133MHz=0D + UINT8 EnCmdRate; ///< Offset 113 CMD Rate Enable: 0=3DDis= able, 5=3D2 CMDs, 7=3D3 CMDs, 9=3D4 CMDs, 11=3D5 CMDs, 13=3D6 CMDs, = 15=3D7 CMDs=0D + UINT8 Refresh2X; ///< Offset 114 Refresh 2x: 0=3DDisab= le, 1=3DEnable for WARM or HOT, 2=3DEnable for HOT only=0D + UINT8 EpgEnable; ///< Offset 115 Enable Energy Performanc= e Gain.=0D + UINT8 UserThresholdEnable; ///< Offset 116 Flag to manually select = the DIMM CLTM Thermal Threshold, 0=3DDisable, 1=3DEnable, 0=3DDefault=0D + UINT8 UserBudgetEnable; ///< Offset 117 Flag to manually select = the Budget Registers for CLTM Memory Dimms , 0=3DDisable, 1=3DEnable, 0= =3DDefault=0D + UINT8 RetrainOnFastFail; ///< Offset 118 Restart MRC in Cold mode= if SW MemTest fails during Fast flow. 0 =3D Disabled, 1 =3D Enabled= =0D + UINT8 PowerDownMode; ///< Offset 119 CKE Power Down Mode: = 0xFF=3DAUTO, 0=3DNo Power Down, 1=3D APD mode, 6=3DPPD-DLL Off mode=0D + UINT8 PwdwnIdleCounter; ///< Offset 120 CKE Power Down Mode Idle= Counter: 0=3DMinimal, 255=3DMaximum, 0x80=3D0x80 DCLK=0D + UINT8 CmdRanksTerminated; ///< Offset 121 LPDDR: Bitmask of ranks = that have CA bus terminated. 0x01=3DDefault, Rank0 is terminating and Ra= nk1 is non-terminating=0D + UINT16 MsHashMask; ///< Offset 122 Controller Hash Mask: 0x= 0001=3DBIT6 set(Minimal), 0x3FFF=3DBIT[19:6] set(Maximum), 0x30CE=3D BIT= [19:18, 13:12 ,9:7] set=0D + UINT32 Lp5CccConfig; ///< Offset 124 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 selects Ascending mapping and 1 selects Descending mapping.=0D + UINT8 RMTLoopCount; ///< Offset 128 Indicates the Loop Count= to be used for Rank Margin Tool Testing: 1=3DMinimal, 32=3DMaximum, 0=3DAU= TO, 0=3DDefault=0D + UINT8 MsHashInterleaveBit; ///< Offset 129 Option to select interle= ave Address bit. Valid values are 0 - 3 for BITS 6 - 9=0D + UINT8 GearRatio; ///< Offset 130 This input control's the= current gear expressed as an integer when SAGV is disabled: 0=3DDefault= , 1, 2.=0D + UINT8 Ddr4OneDpc; ///< Offset 131 DDR4 1DPC performance fe= ature: 0 - Disabled; 1 - Enabled on DIMM0 only, 2 - Enabled on DIMM1 only; = 3 - Enabled on both DIMMs. (bit [0] - DIMM0, bit [1] - DIMM1)=0D + UINT32 BclkRfiFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 132 Bclk RFI Frequ= ency for each SAGV point in Hz units. 98000000Hz =3D 98MHz 0 - No RFI Tu= ning. Range is 98Mhz-100Mhz.=0D + UINT16 SaGvFreq[MEM_MAX_SAGV_POINTS]; ///< Offset 148 Frequency per = SAGV point. 0 is Auto, otherwise holds the frequency value expressed as an= integer: 0=3DDefault, 1067, 1333, 1600, 1800, 1867, etc.=0D + /**=0D + Offset 156 Gear ratio per SAGV point. 0 is Auto, otherwise holds the = Gear ratio expressed as an integer: 0=3DDefault, 1, 2.=0D + Only valid combinations of Gear Ratio per point is:=0D + | point | set1 | set2 | set3=0D + | 0 | 1 | 2 | 2=0D + | 1 | 1 | 2 | 2=0D + | 2 | 1 | 2 | 2=0D + | 3 | 1 | 2 | 1=0D + **/=0D + UINT8 SaGvGear[MEM_MAX_SAGV_POINTS]; ///< Offset = 156=0D + UINT8 IbeccProtectedRegionEnable[MEM_MAX_IBECC_REGIONS]; ///< Offset = 160 Enable use of address range for ECC Protection: 0=3DDefault, 1= =0D + UINT16 IbeccProtectedRegionBase[MEM_MAX_IBECC_REGIONS]; ///< Offset = 168 Base address for address range of ECC Protection: 0=3DDefault, = 1=0D + UINT16 IbeccProtectedRegionMask[MEM_MAX_IBECC_REGIONS]; ///< Offset = 184 Mask address for address range of ECC Protection: 0=3DDefault, = 1=0D + UINT32 CmdMirror; ///< Offset 200 BitMask where bits [3:0]= are controller 0 Channel [3:0] and [7:4] are Controller 1 Channel [3:0]. = 0 =3D No Command Mirror and 1 =3D Command Mirror.=0D + UINT8 CpuBclkSpread; ///< Offset 204 CPU BCLK Spread Specturm= : 0 =3D Disabled; 1 =3D Enabled=0D + UINT8 ExtendedBankHashing; ///< Offset 205 Enable EBH Extended Bank= Hashing: 0=3DDisabled; 1 =3D Enabled.=0D + UINT16 VddqVoltageOverride; ///< Offset 206 VccddqVoltage override i= n # of 1mV=0D + UINT8 MarginLimitCheck; ///< Offset = 208 Margin limit check enable: 0=3DDisable, 1=3DL1 only, 2=3DL2 only= , 3=3DBoth L1 and L2=0D + UINT8 RsvdO209; ///< Offset = 209=0D + UINT16 MarginLimitL2; ///< Offset = 210 Margin limit check L2 threshold: 100=3DDefault=0D +} MEMORY_CONFIGURATION;=0D +=0D +/// Memory Configuration=0D +/// The contents of this structure are not CRC'd by the MRC for option cha= nge detection.=0D +/// Revision 1: - Initial version.=0D +/// Revision 2: - Added MemTestOnWarmBoot=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-23 Config Bl= ock Header=0D + SA_FUNCTION_CALLS SaCall; ///< Offset 24 Function = calls into the SA.=0D + SA_MEMORY_FUNCTIONS MrcCall; ///< Offset 204 Function = calls into the MRC.=0D + SPD_DATA_BUFFER *SpdData; ///< Offset 240 Memory SP= D data, will be used by the MRC when SPD SmBus address is zero.=0D + UINT32 Reserved0;=0D + SA_MEMORY_DQDQS_MAPPING *DqDqsMap; ///< Offset 244 LPDDR DQ = bit and DQS byte swizzling between CPU and DRAM.=0D + SA_MEMORY_RCOMP *RcompData; ///< Offset 248 DDR RCOMP= resistors and target values.=0D + UINT64 PlatformMemorySize; ///< Offset 252 The minim= um platform memory size required to pass control into DXE=0D + UINT32 CleanMemory:1; ///< Offset 256 Ask MRC t= o clear memory content: FALSE=3DDo not Clear Memory; TRUE=3DClear Me= mory=0D + UINT32 ReservedBits5:31;=0D + /**=0D + Sets the serial debug message level\n=0D + 0x00 =3D Disabled\n=0D + 0x01 =3D Errors only\n=0D + 0x02 =3D Errors and Warnings\n=0D + 0x03 =3D Errors, Warnings, and Info\n=0D + 0x04 =3D Errors, Warnings, Info, and Events\n=0D + 0x05 =3D Displays Memory Init Execution Time Summary only\n=0D + **/=0D + UINT8 SerialDebugLevel; ///< Offset 260=0D + UINT8 MemTestOnWarmBoot; ///< Offset 261 Run Base = Memory Test On WarmBoot: 0=3DDisabled, 1=3DEnabled=0D + UINT8 Reserved11[2]; ///< Offset 262 - 263 Res= erved=0D +} MEMORY_CONFIG_NO_CRC;=0D +#pragma pack(pop)=0D +=0D +#endif // _MEMORY_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overcloc= king/OverclockingConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Confi= gBlock/Overclocking/OverclockingConfig.h new file mode 100644 index 0000000000..462c02cef1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Overclocking/Ov= erclockingConfig.h @@ -0,0 +1,236 @@ +/** @file=0D + Overclocking Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _OVERCLOCKING_PREMEM_CONFIG_H_=0D +#define _OVERCLOCKING_PREMEM_CONFIG_H_=0D +=0D +#define OVERCLOCKING_CONFIG_REVISION 9=0D +=0D +extern EFI_GUID gOverclockingPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +//=0D +// Max number of VF point offset=0D +//=0D +#ifndef CPU_OC_MAX_VF_POINTS=0D +#define CPU_OC_MAX_VF_POINTS 0xF=0D +#endif=0D +=0D +#ifndef CPU_OC_MAX_CORES=0D +#define CPU_OC_MAX_CORES 8=0D +#endif=0D +/**=0D + Overclocking Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2=0D + - Add PerCoreHtDisable=0D + Revision 3=0D + - Add Avx2VoltageScaleFactor and Avx512VoltageScaleFactor=0D + Revision 4=0D + - Add CoreVfPointOffsetMode & CoreVfPointOffset & CoreVfPointRatio & Cor= eVfPointCount=0D + Revision 5=0D + - Change OcLock default to 'Enabled'=0D + Revision 6:=0D + - Add DisableCoreMask.=0D + Revision 7=0D + Add UnlimitedIccMax=0D + Revision 8=0D + - Add PerCoreRatioOverride and PerCoreRatio for Per Core PState overcloc= king.=0D + Revision 9=0D + - Add VccInVoltageOverride.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + Overclocking support. This controls whether OC mailbox transactions are = sent.=0D + If disabled, all policies in this config block besides OcSupport and OcL= ock will be ignored.=0D + 0: Disable;=0D + 1: Enable.=0D + @note If PcdOverclockEnable is disabled, this should also be disabled.=0D + **/=0D + UINT32 OcSupport : 1;=0D + UINT32 OcLock : 1; ///< If enabled, sets OC= lock bit in MSR 0x194[20], locking the OC mailbox and other OC configurati= on settings.; 0: Disable; 1: Enable (Lock).=0D + /**=0D + Core voltage mode, specifies which voltage mode the processor will be op= erating.=0D + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range;=0D + 1: Override, sets one voltage for for the entire frequency range, Pn-P0.= =0D + **/=0D + UINT32 CoreVoltageMode : 1;=0D + UINT32 CorePllVoltageOffset : 6; ///< Core PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units.=0D + UINT32 Avx2RatioOffset : 5; ///< AVX2 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX ratio to maximize= possible ratio for SSE workload.=0D + UINT32 Avx3RatioOffset : 5; ///< AVX3 Ratio Offset. = 0: No offset. Range is 0-31. Used to lower the AVX3 ratio to maximiz= e possible ratio for SSE workload.=0D + UINT32 BclkAdaptiveVoltage : 1; ///< Bclk Adaptive Volta= ge enable/disable. 0: Disabled, 1: Enabled. When enabled, the CPU V/= F curves are aware of BCLK frequency when calculated.=0D + /**=0D + Ring Downbin enable/disable.=0D + When enabled, the CPU will force the ring ratio to be lower than the cor= e ratio.=0D + Disabling will allow the ring and core ratios to run at the same frequen= cy.=0D + Uses OC Mailbox command 0x19.=0D + 0: Disables Ring Downbin feature. 1: Enables Ring downbin feature.=0D + **/=0D + UINT32 RingDownBin : 1;=0D + /**=0D + Ring voltage mode, specifies which voltage mode the processor will be op= erating.=0D + 0: Adaptive Mode allows the processor to interpolate a voltage cu= rve when beyond fused P0 range;=0D + 1: Override, sets one voltage for for the entire frequency range, Pn-P0.= =0D + **/=0D + UINT32 RingVoltageMode : 1;=0D + UINT32 GtVoltageMode : 1; ///< Specifies whether GT voltage i= s operating in Adaptive or Override mode: 0=3DAdaptive, 1=3DOverride= =0D + UINT32 RealtimeMemoryTiming : 1; ///< Enable/Disable the message sen= t to the CPU to allow realtime memory timing changes after MRC_DONE. 0= =3DDisable, 1=3DEnable=0D + UINT32 FivrFaults : 1; ///< Fivr Faults. Enable or Disable= FIVR Faults. 0: Disabled, 1: Enabled.=0D + UINT32 FivrEfficiency : 1; ///< Fivr Efficiency Management. 0:= Disabled, 1: Enabled.=0D + /**=0D + Selects Core Voltage & Frequency Point Offset between Legacy and Selecti= on modes.=0D + Need Reset System after enabling OverClocking Feature to Initialize the = default value.=0D + 0: In Legacy Mode, setting a global offset for the entire VF curve.=0D + 1: In Selection modes, setting a selected VF point.=0D + **/=0D + UINT32 CoreVfPointOffsetMode : 1;=0D + UINT32 UnlimitedIccMax : 1; ///< Support Unlimited ICCMAX more = than maximum value 255.75A. 0: Disabled, 1: Enabled.=0D + UINT32 PerCoreRatioOverride : 1; ///< Enable or disable Pe= r Core PState OC supported by writing OCMB 0x1D to program new favored core= ratio to each Core. 0: Disable, 1: enable=0D + UINT32 DynamicMemoryChange : 1; ///< Dynamic Memory Timings Changes;= 0: Disabled; 1: Enabled.=0D + UINT32 RsvdBits : 2; ///< Reserved for future use=0D +=0D + /**=0D + Maximum core turbo ratio override allows to increase CPU core frequency = beyond the fused max turbo ratio limit (P0).=0D + 0. no override/HW defaults.. Range 0-85.=0D + **/=0D + UINT8 CoreMaxOcRatio;=0D + UINT8 GtMaxOcRatio; ///< Maximum GT turbo ratio overrid= e: 0=3DMinimal, 60=3DMaximum, 0=3DAUTO=0D + /**=0D + Maximum ring ratio override allows to increase CPU ring frequency beyond= the fused max ring ratio limit.=0D + 0. no override/HW defaults.. Range 0-85.=0D + **/=0D + UINT8 RingMaxOcRatio;=0D + UINT8 RsvdByte1;=0D + /**=0D + The core voltage override which is applied to the entire range of cpu co= re frequencies.=0D + Used when CoreVoltageMode =3D Override.=0D + 0. no override. Range 0-2000 mV.=0D + **/=0D + UINT16 CoreVoltageOverride;=0D + /**=0D + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the cpu is operating in turbo mode range.=0D + Used when CoreVoltageMode =3D Adaptive.=0D + 0. no override. Range 0-2000mV.=0D + **/=0D + UINT16 CoreVoltageAdaptive;=0D + /**=0D + The core voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range.=0D + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000.=0D + **/=0D + INT16 CoreVoltageOffset;=0D + /**=0D + The ring voltage override which is applied to the entire range of cpu ri= ng frequencies.=0D + Used when RingVoltageMode =3D Override.=0D + 0. no override. Range 0-2000 mV.=0D + **/=0D + UINT16 RingVoltageOverride;=0D + /**=0D + Adaptive Turbo voltage target used to define the interpolation voltage p= oint when the ring is operating in turbo mode range.=0D + Used when RingVoltageMode =3D Adaptive.=0D + 0. no override. Range 0-2000mV.=0D + **/=0D + UINT16 RingVoltageAdaptive;=0D + /**=0D + The ring voltage offset applied on top of all other voltage modes. This = offset is applied over the entire frequency range.=0D + This is a 2's complement number in mV units. Default: 0 Range: -1= 000 to 1000.=0D + **/=0D + INT16 RingVoltageOffset;=0D +=0D + INT16 GtVoltageOffset; ///< The voltage offset = applied to GT slice. Valid range from -1000mv to 1000mv: 0=3DMinimal= , 1000=3DMaximum=0D + UINT16 GtVoltageOverride; ///< The GT voltage over= ride which is applied to the entire range of GT frequencies 0=3DDefault<= /b>=0D + UINT16 GtExtraTurboVoltage; ///< The adaptive voltag= e applied during turbo frequencies. Valid range from 0 to 2000mV: 0=3DMi= nimal, 2000=3DMaximum=0D + INT16 SaVoltageOffset; ///< The voltage offset = applied to the SA. Valid range from -1000mv to 1000mv: 0=3DDefault=0D + UINT32 GtPllVoltageOffset : 6; ///< GT PLL voltage offs= et. 0: No offset. Range 0-63 in 17.5mv units.=0D + UINT32 RingPllVoltageOffset : 6; ///< Ring PLL voltage of= fset. 0: No offset. Range 0-63 in 17.5mv units.=0D + UINT32 SaPllVoltageOffset : 6; ///< System Agent PLL vo= ltage offset. 0: No offset. Range 0-63 in 17.5mv units.=0D + UINT32 McPllVoltageOffset : 6; ///< Memory Controller P= LL voltage offset. 0: No offset. Range 0-63 in 17.5mv units.=0D + UINT32 RsvdBits1 : 8;=0D + /**=0D + TjMax Offset. Specified value here is clipped by pCode (125 - TjMax Offs= et) to support TjMax in the range of 62 to 115 deg Celsius.=0D + Default: 0 Hardware Defaults Range 10 to 63. 0 =3D No offset / = Keep HW default.=0D + **/=0D + UINT8 TjMaxOffset;=0D + UINT8 RsvdByte2[3]; //< Reserved for dword al= ignment=0D + /**=0D + This service controls Core frequency reduction caused by high package te= mperatures for processors that=0D + implement the Intel Thermal Velocity Boost (TVB) feature. It is required= to be disabled for supporting=0D + overclocking at frequencies higher than the default max turbo frequency.= =0D + 0: Disables TVB ratio clipping. 1: Enables TVB ratio clipping.=0D + **/=0D + UINT32 TvbRatioClipping : 1;=0D + /**=0D + This service controls thermal based voltage optimizations for processors= that implement the Intel=0D + Thermal Velocity Boost (TVB) feature.=0D + 0: Disables TVB voltage optimization. 1: Enables TVB voltage optimiza= tion.=0D + **/=0D + UINT32 TvbVoltageOptimization : 1;=0D + UINT32 RsvdBits2 : 30;=0D + /**=0D + Defines the per-core HT disable mask where: 1 - Disable selected logical= core HT, 0 - is ignored.=0D + Input is in HEX and each bit maps to a logical core. Ex. A value of '1F'= would disable HT for cores 4,3,2,1 and 0.=0D + Default is 0, all cores have HT enabled. Range is 0 - 0x1FF. You = can only disable up to MAX_CORE_COUNT - 1.=0D + **/=0D + UINT16 PerCoreHtDisable;=0D + /**=0D + Avx2 Voltage Guardband Scale Factor=0D + This controls the AVX2 Voltage Guardband Scale factor applied to AVX2 wo= rkloads.=0D + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a = 1.25 scale factor.=0D + A value of 0 means no scale factor applied (no change to voltage on AVX = commands)=0D + A value of 100 applies the default voltage guardband values (1.0 factor)= .=0D + A value > 100 will increase the voltage guardband on AVX2 workloads.=0D + A value < 100 will decrease the voltage guardband on AVX2 workloads.=0D +=0D + 0. No scale factor applied=0D + **/=0D + UINT8 Avx2VoltageScaleFactor;=0D + /**=0D + Avx512 Voltage Guardband Scale Factor=0D + This controls the AVX512 Voltage Guardband Scale factor applied to AVX51= 2 workloads.=0D + Valid range is 0-200 in 1/100 units, where a value of 125 would apply a = 1.25 scale factor.=0D + A value of 0 means no scale factor applied (no change to voltage on AVX = commands)=0D + A value of 100 applies the default voltage guardband values (1.0 factor)= .=0D + A value > 100 will increase the voltage guardband on AVX512 workloads.=0D + A value < 100 will decrease the voltage guardband on AVX512 workloads.=0D +=0D + 0. No scale factor applied=0D + **/=0D + UINT8 Avx512VoltageScaleFactor;=0D + /**=0D + Array used to specifies the Core Voltage Offset applied to the each sele= cted VF Point.=0D + This voltage is specified in millivolts.=0D + **/=0D + INT16 CoreVfPointOffset[CPU_OC_MAX_VF_POINTS];=0D + UINT8 RsvdByte3[2]; ///< Just to keep native alignment.=0D + /**=0D + Array for the each selected VF Point to display the Core Ration.=0D + **/=0D + UINT8 CoreVfPointRatio[CPU_OC_MAX_VF_POINTS];=0D + /**=0D + Number of supported Core Voltage & Frequency Point.=0D + **/=0D + UINT8 CoreVfPointCount;=0D + /**=0D + Core mask is a bitwise indication of which core should be disabled. Bit = 0 - core 0, bit 7 - core 7.=0D + **/=0D + UINT32 DisableCoreMask;=0D + UINT8 PerCoreRatio[CPU_OC_MAX_CORES];=0D + /**=0D + The VcccIn voltage override.=0D + This will override VccIn output voltage level to the voltage value speci= fied.=0D + The voltage level is fixed and will not change except on PKG C-states or= resets.=0D +=0D + 0. no override. Range 0-3000 mV.=0D + **/=0D + UINT32 VccInVoltageOverride;=0D +} OVERCLOCKING_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_OVERCLOCKING_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2s= bConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sb= Config.h new file mode 100644 index 0000000000..69271205b1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/P2sb/P2sbConfig= .h @@ -0,0 +1,34 @@ +/** @file=0D + P2sb policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _P2SB_CONFIG_H_=0D +#define _P2SB_CONFIG_H_=0D +=0D +#define P2SB_CONFIG_REVISION 1=0D +extern EFI_GUID gP2sbConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure contains the policies which are related to P2SB device.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + (Test)=0D + The sideband MMIO register access to specific ports will be locked=0D + before 3rd party code execution. Currently it disables PSFx access.=0D + This policy unlocks the sideband MMIO space for those IPs.=0D + 0: Lock sideband access ; 1: Unlock sideband access.=0D + NOTE: Do not set this policy "SbAccessUnlock" unless its necessary.=0D + **/=0D + UINT32 SbAccessUnlock : 1;=0D + UINT32 Rsvdbits : 31; ///< Reserved bits=0D +} PCH_P2SB_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _P2SB_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/P= chDmiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDm= i/PchDmiConfig.h new file mode 100644 index 0000000000..b73108bcfd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PchDmi/PchDmiCo= nfig.h @@ -0,0 +1,44 @@ +/** @file=0D + DMI policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_DMI_CONFIG_H_=0D +#define _PCH_DMI_CONFIG_H_=0D +=0D +#define PCH_DMI_CONFIG_REVISION 2=0D +extern EFI_GUID gPchDmiConfigGuid;=0D +=0D +=0D +#pragma pack (push,1)=0D +=0D +=0D +/**=0D + The PCH_DMI_CONFIG block describes the expected configuration of the PCH = for DMI.=0D + Revision 1: - Initial version.=0D + Revision 2: - Add OpioRecenter=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D +=0D + UINT32 PwrOptEnable : 1; ///< 0: Disable; 1: Enable = DMI Power Optimizer on PCH side.=0D + UINT32 DmiAspmCtrl : 8; ///< ASPM configuration on the PCH= side of the DMI/OPI Link. Default is PchPcieAspmAutoConfig=0D + UINT32 CwbEnable : 1; ///< 0: Disable; 1: Enable = Central Write Buffer feature configurable and enabled by default=0D + UINT32 L1RpCtl : 1; ///< 0: Disable; 1: Enable = Allow DMI enter L1 when all root ports are in L1, L0s or link down. Disable= d by default.=0D + /**=0D + When set to TRUE turns on:=0D + - L1 State Controller Power Gating=0D + - L1 State PHY Data Lane Power Gating=0D + - PHY Common Lane Power Gating=0D + - Hardware Autonomous Enable=0D + - PMC Request Enable and Sleep Enable=0D + **/=0D + UINT32 DmiPowerReduction : 1;=0D + UINT32 OpioRecenter : 1; ///< 0: Disable; 1: Enable = Opio Recentering Disable for Pcie latency=0D + UINT32 Rsvdbits : 19; ///< Reserved bits=0D +} PCH_DMI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PCH_DMI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= chPcieRp/PchPcieRpConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/Conf= igBlock/PcieRp/PchPcieRp/PchPcieRpConfig.h new file mode 100644 index 0000000000..de086473a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PchPcieR= p/PchPcieRpConfig.h @@ -0,0 +1,368 @@ +/** @file=0D + PCH Pcie root port policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCIERP_CONFIG_H_=0D +#define _PCH_PCIERP_CONFIG_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#define PCIE_RP_CONFIG_REVISION 1=0D +#define PCIE_RP_PREMEM_CONFIG_REVISION 1=0D +#define PCIE_RP_DXE_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gPchPcieConfigGuid;=0D +extern EFI_GUID gPcieRpPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +#define PCIE_LINK_EQ_COEFFICIENTS_MAX 10=0D +#define PCIE_LINK_EQ_PRESETS_MAX 11=0D +=0D +typedef enum {=0D + PchPcieOverrideDisabled =3D 0,=0D + PchPcieL1L2Override =3D 0x01,=0D + PchPcieL1SubstatesOverride =3D 0x02,=0D + PchPcieL1L2AndL1SubstatesOverride =3D 0x03,=0D + PchPcieLtrOverride =3D 0x04=0D +} PCH_PCIE_OVERRIDE_CONFIG;=0D +=0D +/**=0D + PCIe device table entry entry=0D +=0D + The PCIe device table is being used to override PCIe device ASPM setting= s.=0D + To take effect table consisting of such entries must be instelled as PPI= =0D + on gPchPcieDeviceTablePpiGuid.=0D + Last entry VendorId must be 0.=0D +**/=0D +typedef struct {=0D + UINT16 VendorId; ///< The vendor Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Vendor ID=0D + UINT16 DeviceId; ///< The Device Id of Pci Express c= ard ASPM setting override, 0xFFFF means any Device ID=0D + UINT8 RevId; ///< The Rev Id of Pci Express card= ASPM setting override, 0xFF means all steppings=0D + UINT8 BaseClassCode; ///< The Base Class Code of Pci Exp= ress card ASPM setting override, 0xFF means all base class=0D + UINT8 SubClassCode; ///< The Sub Class Code of Pci Expr= ess card ASPM setting override, 0xFF means all sub class=0D + UINT8 EndPointAspm; ///< Override device ASPM (see: PCH= _PCIE_ASPM_CONTROL)=0D + ///< Bit 1 must be set in OverrideC= onfig for this field to take effect=0D + UINT16 OverrideConfig; ///< The override config bitmap (se= e: PCH_PCIE_OVERRIDE_CONFIG).=0D + /**=0D + The L1Substates Capability Offset Override. (applicable if bit 2 is se= t in OverrideConfig)=0D + This field can be zero if only the L1 Substate value is going to be ov= erride.=0D + **/=0D + UINT16 L1SubstatesCapOffset;=0D + /**=0D + L1 Substate Capability Mask. (applicable if bit 2 is set in OverrideCo= nfig)=0D + Set to zero then the L1 Substate Capability [3:0] is ignored, and only= L1s values are override.=0D + Only bit [3:0] are applicable. Other bits are ignored.=0D + **/=0D + UINT8 L1SubstatesCapMask;=0D + /**=0D + L1 Substate Port Common Mode Restore Time Override. (applicable if bit= 2 is set in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sCommonModeRestoreTime;=0D + /**=0D + L1 Substate Port Tpower_on Scale Override. (applicable if bit 2 is set= in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sTpowerOnScale;=0D + /**=0D + L1 Substate Port Tpower_on Value Override. (applicable if bit 2 is set= in OverrideConfig)=0D + L1sCommonModeRestoreTime and L1sTpowerOnScale can have a valid value o= f 0, but not the L1sTpowerOnValue.=0D + If L1sTpowerOnValue is zero, all L1sCommonModeRestoreTime, L1sTpowerOn= Scale, and L1sTpowerOnValue are ignored,=0D + and only L1SubstatesCapOffset is override.=0D + **/=0D + UINT8 L1sTpowerOnValue;=0D +=0D + /**=0D + SnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid=0D + When clear values in bits 9:0 will be ignored=0D + BITS[14:13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Snoop Latency Value. The value in these bits will be mul= tiplied with=0D + the scale in bits 12:10=0D +=0D + This field takes effect only if bit 3 is set in OverrideConfig.=0D + **/=0D + UINT16 SnoopLatency;=0D + /**=0D + NonSnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 ar= e valid=0D + When clear values in bits 9:0 will be ignored=0D + BITS[14:13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in t= hese bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be= multiplied with=0D + the scale in bits 12:10=0D +=0D + This field takes effect only if bit 3 is set in OverrideConfig.=0D + **/=0D + UINT16 NonSnoopLatency;=0D +=0D + /**=0D + Forces LTR override to be permanent=0D + The default way LTR override works is:=0D + rootport uses LTR override values provided by BIOS until connected d= evice sends an LTR message, then it will use values from the message=0D + This settings allows force override of LTR mechanism. If it's enabled,= then:=0D + rootport will use LTR override values provided by BIOS forever; LTR = messages sent from connected device will be ignored=0D + **/=0D + UINT8 ForceLtrOverride;=0D + UINT8 Reserved[3];=0D +} PCH_PCIE_DEVICE_OVERRIDE;=0D +=0D +///=0D +/// The values before AutoConfig match the setting of PCI Express Base Spe= cification 1.1, please be careful for adding new feature=0D +///=0D +typedef enum {=0D + PchPcieAspmDisabled,=0D + PchPcieAspmL0s,=0D + PchPcieAspmL1,=0D + PchPcieAspmL0sL1,=0D + PchPcieAspmAutoConfig,=0D + PchPcieAspmMax=0D +} PCH_PCIE_ASPM_CONTROL;=0D +=0D +/**=0D + Refer to PCH EDS for the PCH implementation values corresponding=0D + to below PCI-E spec defined ranges=0D +**/=0D +typedef enum {=0D + PchPcieL1SubstatesDisabled,=0D + PchPcieL1SubstatesL1_1,=0D + PchPcieL1SubstatesL1_1_2,=0D + PchPcieL1SubstatesMax=0D +} PCH_PCIE_L1SUBSTATES_CONTROL;=0D +=0D +enum PCH_PCIE_MAX_PAYLOAD {=0D + PchPcieMaxPayload128 =3D 0,=0D + PchPcieMaxPayload256,=0D + PchPcieMaxPayloadMax=0D +};=0D +=0D +typedef enum {=0D + PcieLinkHardwareEq =3D 0, ///< Hardware is responsible for performing c= oefficient/preset search.=0D + PcieLinkFixedEq ///< No coefficient/preset search is performed.= Fixed values are used.=0D +} PCIE_LINK_EQ_METHOD;=0D +=0D +typedef enum {=0D + PcieLinkEqPresetMode =3D 0, ///< Use presets during PCIe link equaliza= tion=0D + PcieLinkEqCoefficientMode ///< Use coefficients during PCIe link equal= ization=0D +} PCIE_LINK_EQ_MODE;=0D +=0D +typedef struct {=0D + UINT32 PreCursor; ///< Pre-cursor coefficient=0D + UINT32 PostCursor; ///< Post-cursor coefficient=0D +} PCIE_LINK_EQ_COEFFICIENTS;=0D +=0D +/**=0D + PCIe Link EQ Platform Settings=0D +**/=0D +typedef struct {=0D + UINT8 PcieLinkEqMethod; ///< Tells BI= OS which link EQ method should be used for this port. Please refer to PCIE_= LINK_EQ_METHOD for details of supported methods. Default: PcieLinkHardwareE= q=0D + UINT8 PcieLinkEqMode; ///< Tells BI= OS which mode should be used for PCIe link EQ. Please refer to PCIE_LINK_EQ= _MODE for details of supported modes. Default: depends on SoC=0D + /**=0D + Specifies if BIOS should perform local transmitter override during pha= se 2 of EQ process.=0D + If enabled value in Ph2LocalTransmitterOverridePreset must be valid.=0D + 0: Disabled; 1: Enabled=0D + **/=0D + UINT8 LocalTransmitterOverrideEnable;=0D + /**=0D + Tells BIOS how many presets/coefficients should be used during link EQ= .=0D + Entries in the Ph3CoefficientsList or Ph3PresetList(depending on chose= n mode) need to be valid up to the number specified in this field.=0D + **/=0D + UINT8 Ph3NumberOfPresetsOrCoefficients;=0D +=0D + PCIE_LINK_EQ_COEFFICIENTS Ph3CoefficientsList[PCIE_LINK_EQ_COEFFICIENTS= _MAX]; ///< List of the PCIe coefficients to be used during equalization p= rocess. Only valid if PcieLinkEqMode is PcieLinkEqCoefficientMode=0D + UINT32 Ph3PresetList[PCIE_LINK_EQ_PRESETS_MAX]; = ///< List of the PCIe preset values to be used during equalization = process. Only valid if PcieLinkEqMode is PcieLinkEqPresetMode=0D + UINT32 Ph1DownstreamPortTransmitterPreset; ///< Spe= cifies the value of the downstream port transmitter preset to be used durin= g phase 1 of the equalization process. Will be applied to all lanes=0D + UINT32 Ph1UpstreamPortTransmitterPreset; ///< Spe= cifies the value of the upstream port transmitter preset to be used during = phase 1 of the equalization process. Will be applied to all lanes=0D + /**=0D + Specifies the preset that should be used during local transmitter over= ride during phase 2 of EQ process.=0D + Used only if LocalTransmitterOverrideEnable is TRUE. Will be applied t= o all PCIe lanes of the root port.=0D + Valid up to the PCIE_LINK_EQ_PRESET_MAX value. Default: 0<\b>=0D + **/=0D + UINT32 Ph2LocalTransmitterOverridePreset;=0D +} PCIE_LINK_EQ_PLATFORM_SETTINGS;=0D +=0D +#define PCH_PCIE_NO_SUCH_CLOCK 0xFF=0D +=0D +typedef enum {=0D + PchClockUsagePchPcie0 =3D 0,=0D + PchClockUsagePchPcie1 =3D 1,=0D + PchClockUsagePchPcie2 =3D 2,=0D + PchClockUsagePchPcie3 =3D 3,=0D + PchClockUsagePchPcie4 =3D 4,=0D + PchClockUsagePchPcie5 =3D 5,=0D + PchClockUsagePchPcie6 =3D 6,=0D + PchClockUsagePchPcie7 =3D 7,=0D + PchClockUsagePchPcie8 =3D 8,=0D + PchClockUsagePchPcie9 =3D 9,=0D + PchClockUsagePchPcie10 =3D 10,=0D + PchClockUsagePchPcie11 =3D 11,=0D + PchClockUsagePchPcie12 =3D 12,=0D + PchClockUsagePchPcie13 =3D 13,=0D + PchClockUsagePchPcie14 =3D 14,=0D + PchClockUsagePchPcie15 =3D 15,=0D + PchClockUsagePchPcie16 =3D 16,=0D + PchClockUsagePchPcie17 =3D 17,=0D + PchClockUsagePchPcie18 =3D 18,=0D + PchClockUsagePchPcie19 =3D 19,=0D + PchClockUsagePchPcie20 =3D 20,=0D + PchClockUsagePchPcie21 =3D 21,=0D + PchClockUsagePchPcie22 =3D 22,=0D + PchClockUsagePchPcie23 =3D 23,=0D + /**=0D + Quantity of PCH and CPU PCIe ports, as well as their encoding in this = enum, may change between=0D + silicon generations and series. Do not assume that PCH port 0 will be = always encoded by 0.=0D + Instead, it is recommended to use (PchClockUsagePchPcie0 + PchPortInde= x) style to be forward-compatible=0D + **/=0D + PchClockUsageCpuPcie0 =3D 0x40,=0D + PchClockUsageCpuPcie1 =3D 0x41,=0D + PchClockUsageCpuPcie2 =3D 0x42,=0D + PchClockUsageCpuPcie3 =3D 0x43,=0D +=0D + PchClockUsageLan =3D 0x70,=0D + PchClockUsageUnspecified =3D 0x80, ///< In use for a purpose not liste= d above=0D + PchClockUsageNotUsed =3D 0xFF=0D +} PCH_PCIE_CLOCK_USAGE;=0D +=0D +/**=0D + PCH_PCIE_CLOCK describes PCIe source clock generated by PCH.=0D +**/=0D +typedef struct {=0D + UINT8 Usage; ///< Purpose of given clock (see PCH_PCIE_CLOCK_US= AGE). Default: Unused, 0xFF=0D + UINT8 ClkReq; ///< ClkSrc - ClkReq mapping. Default: 1:1 mapping= with Clock numbers=0D + UINT8 RsvdBytes[2]; ///< Reserved byte=0D +} PCH_PCIE_CLOCK;=0D +=0D +/**=0D + The PCH_PCI_EXPRESS_ROOT_PORT_CONFIG describe the feature and capability= of each PCH PCIe root port.=0D +**/=0D +typedef struct {=0D + PCIE_ROOT_PORT_COMMON_CONFIG PcieRpCommonConfig; ///an instance of Pcie= Common Config=0D + UINT8 ExtSync; ///< Indicate whether the extended synch is= enabled. 0: Disable; 1: Enable.=0D + //=0D + // Error handlings=0D + //=0D + UINT8 SystemErrorEnable; ///< Indicate whether the System Error is e= nabled. 0: Disable; 1: Enable.=0D + /**=0D + The Multiple VC (MVC) supports hardware to avoid HoQ block for latency= sensitive TC.=0D + Currently it is only applicable to Root Ports with 2pX4 port configura= tion with 2 VCs,or=0D + DMI port configuration with 3 VCs. For Root Ports 2pX4 configuration, = two RPs (RP0,=0D + RP2) shall support two PCIe VCs (VC0 & VC1) and the other RPs (RP1, RP= 3) shall be=0D + disabled.=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT8 MvcEnabled;=0D + /**=0D + Virtual Pin Port is industry standard introduced to PCIe Hot Plug supp= ort in systems=0D + when GPIO pins expansion is needed. It is server specific feature.=0D + 0x00: Default; 0xFF: Disabled=0D + **/=0D + UINT8 VppPort;=0D + UINT8 VppAddress; ///< PCIe Hot Plug VPP= SMBus Address. Default is zero.=0D + UINT8 RsvdBytes0[3]; ///< Reserved bytes=0D +} PCH_PCIE_ROOT_PORT_CONFIG;=0D +=0D +/**=0D + The PCH_PCIE_CONFIG block describes the expected configuration of the PC= H PCI Express controllers=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + ///=0D + /// These members describe the configuration of each PCH PCIe root port.= =0D + ///=0D + PCIE_COMMON_CONFIG PcieCommonConfig;=0D + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];=0D + PCIE_LINK_EQ_PLATFORM_SETTINGS PcieLinkEqPlatformSettings; ///< Glob= al PCIe link EQ settings that BIOS will use during PCIe link EQ for every p= ort.=0D + ///=0D + /// 0: Use project default equalization settings; 1: Use equaliza= tion settings from PcieLinkEqPlatformSettings=0D + ///=0D + UINT8 OverrideEqualizationDefaults;=0D + ///=0D + /// (Test) This member describes whether PCIE root port Port 8xh = Decode is enabled. 0: Disable; 1: Enable.=0D + ///=0D + UINT8 EnablePort8xhDecode;=0D + ///=0D + /// (Test) The Index of PCIe Port that is selected for Port8xh De= code (0 Based)=0D + ///=0D + UINT8 PchPciePort8xhDecodePortIndex;=0D + UINT8 RsvdBytes0[1];=0D +} PCH_PCIE_CONFIG;=0D +=0D +/**=0D + The PCH_PCIE_RP_PREMEM_CONFIG block describes early configuration of the= PCH PCI Express controllers=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config= Block Header=0D + /**=0D + Root Port enabling mask.=0D + Bit0 presents RP1, Bit1 presents RP2, and so on.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 RpEnabledMask;=0D + /// Configuration of PCIe source clocks=0D + ///=0D + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];=0D +=0D + /**=0D + Per Controller Bifurcation Configuration=0D + 0: Disabled; 1: 4x1; 2: 1x2_2x1; 3: 2x2; 4: 1x4; 5: 4x2; 6: 1x4= _2x2; 7: 2x2_1x4; 8: 2x4; 9: 1x8 (see: PCIE_BIFURCATION_CONFIG)=0D + **/=0D + UINT8 Bifurcation[PCH_MAX_PCIE_CONTROLLERS];=0D + UINT8 Rsvd4[(4 - PCH_MAX_PCIE_CONTROLLERS % 4) % 4];=0D +} PCH_PCIE_RP_PREMEM_CONFIG;=0D +=0D +/**=0D + The PCIE_RP_DXE_CONFIG block describes the expected configuration of the= PCH PCI Express controllers in DXE phase=0D +=0D + Revision 1:=0D + - Init version=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block H= eader=0D +=0D + /**=0D + PCIe device override table=0D + The PCIe device table is being used to override PCIe device ASPM setti= ngs.=0D + And it's only used in DXE phase.=0D + Please refer to PCH_PCIE_DEVICE_OVERRIDE structure for the table.=0D + Last entry VendorId must be 0.=0D + **/=0D + PCH_PCIE_DEVICE_OVERRIDE *PcieDeviceOverrideTablePtr;=0D +} PCIE_RP_DXE_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PCH_PCIERP_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/P= cieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/= PcieConfig.h new file mode 100644 index 0000000000..4c5b075334 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/PcieRp/PcieConf= ig.h @@ -0,0 +1,217 @@ +/** @file=0D + PCIe Config Block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCIE_CONFIG_H_=0D +#define _PCIE_CONFIG_H_=0D +#include =0D +=0D +#define PCIE_CONFIG_REVISION 3=0D +/*=0D +Revision 2< / b>:=0D +FomsCp - Deprecated=0D +Revision 3< / b>:=0D +Added PCIE_EQ_PARAM HwEqGen3CoeffList for all CPU_PCIE_MAX_ROOT_PORTS=0D +Added PCIE_EQ_PARAM HwEqGen4CoeffList for all CPU_PCIE_MAX_ROOT_PORTS=0D +Added PCIE_EQ_PARAM HwEqGen5CoeffList for all CPU_PCIE_MAX_ROOT_PORTS=0D +*/=0D +=0D +extern EFI_GUID gPcieConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +enum PCIE_COMPLETION_TIMEOUT {=0D + PcieCompletionTO_Default,=0D + PcieCompletionTO_50_100us,=0D + PcieCompletionTO_1_10ms,=0D + PcieCompletionTO_16_55ms,=0D + PcieCompletionTO_65_210ms,=0D + PcieCompletionTO_260_900ms,=0D + PcieCompletionTO_1_3P5s,=0D + PcieCompletionTO_4_13s,=0D + PcieCompletionTO_17_64s,=0D + PcieCompletionTO_Disabled=0D +};=0D +=0D +enum PCIE_SPEED {=0D + PcieAuto,=0D + PcieGen1,=0D + PcieGen2,=0D + PcieGen3,=0D + PcieGen4=0D +};=0D +=0D +/**=0D + Represent lane specific PCIe Gen3 equalization parameters.=0D +**/=0D +typedef struct {=0D + UINT8 Cm; ///< Coefficient C-1=0D + UINT8 Cp; ///< Coefficient C+1=0D + UINT8 Rsvd0[2]; ///< Reserved bytes=0D +} PCIE_EQ_PARAM;=0D +=0D +typedef struct {=0D + UINT16 LtrMaxSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Snoop Latency.=0D + UINT16 LtrMaxNoSnoopLatency; ///< (Test) Laten= cy Tolerance Reporting, Max Non-Snoop Latency.=0D + UINT8 SnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Mode.=0D + UINT8 SnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Multiplier.=0D + UINT16 SnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Snoop Latency Override Value.=0D + UINT8 NonSnoopLatencyOverrideMode; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Mode.=0D + UINT8 NonSnoopLatencyOverrideMultiplier; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Multiplier.=0D + UINT16 NonSnoopLatencyOverrideValue; ///< (Test) Laten= cy Tolerance Reporting, Non-Snoop Latency Override Value.=0D + UINT8 LtrConfigLock; ///< 0: Disable; = 1: Enable.=0D + UINT8 ForceLtrOverride;=0D + UINT16 RsvdByte1;=0D +} PCIE_LTR_CONFIG;=0D +=0D +=0D +/**=0D + Specifies the form factor that the slot=0D + implements. For custom form factors that=0D + do not require any special handling please=0D + set PcieFormFactorOther.=0D +**/=0D +typedef enum {=0D + PcieFormFactorOther =3D 0,=0D + PcieFormFactorCem,=0D + PcieFormFactorMiniPci,=0D + PcieFormFactorM2,=0D + PcieFormFactorOcuLink,=0D + PcieFormFactorExpressModule, // Also known as Server IO module(SIOM)=0D + PcieFormFactorExpressCard,=0D + PcieFormFactorU2 // Also known as SF-8639=0D +} PCIE_FORM_FACTOR;=0D +=0D +//Note: This structure will be expanded to hold all common PCIe policies b= etween SA and PCH RootPort=0D +typedef struct {=0D + UINT32 HotPlug : 1; ///< Indicate whether th= e root port is hot plug available. 0: Disable; 1: Enable.=0D + UINT32 PmSci : 1; ///< Indicate whether th= e root port power manager SCI is enabled. 0: Disable; 1: Enable.=0D + UINT32 TransmitterHalfSwing : 1; ///< Indicate whether th= e Transmitter Half Swing is enabled. 0: Disable; 1: Enable.=0D + UINT32 AcsEnabled : 1; ///< Indicate whether th= e ACS is enabled. 0: Disable; 1: Enable.=0D + //=0D + // Error handlings=0D + //=0D + UINT32 AdvancedErrorReporting : 1; ///< Indicate whether th= e Advanced Error Reporting is enabled. 0: Disable; 1: Enable.=0D + UINT32 UnsupportedRequestReport : 1; ///< Indicate whether th= e Unsupported Request Report is enabled. 0: Disable; 1: Enable.=0D + UINT32 FatalErrorReport : 1; ///< Indicate whether th= e Fatal Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT32 NoFatalErrorReport : 1; ///< Indicate whether th= e No Fatal Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT32 CorrectableErrorReport : 1; ///< Indicate whether th= e Correctable Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT32 SystemErrorOnFatalError : 1; ///< Indicate whether th= e System Error on Fatal Error is enabled. 0: Disable; 1: Enable.=0D + UINT32 SystemErrorOnNonFatalError : 1; ///< Indicate whether th= e System Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.= =0D + UINT32 SystemErrorOnCorrectableError : 1; ///< Indicate whether th= e System Error on Correctable Error is enabled. 0: Disable; 1: Enabl= e.=0D + /**=0D + Max Payload Size supported, Default 128B, see enum CPU_PCIE_MAX= _PAYLOAD=0D + Changes Max Payload Size Supported field in Device Capabilities of the= root port.=0D + **/=0D + UINT32 MaxPayload : 2;=0D + UINT32 DpcEnabled : 1; ///< Downstream Port Con= tainment. 0: Disable; 1: Enable=0D + UINT32 RpDpcExtensionsEnabled : 1; ///< RP Extensions for D= ownstream Port Containment. 0: Disable; 1: Enable=0D + /**=0D + Indicates how this root port is connected to endpoint. 0: built-in dev= ice; 1: slot=0D + Built-in is incompatible with hotplug-capable ports.=0D + **/=0D + UINT32 SlotImplemented : 1;=0D + UINT32 PtmEnabled : 1; ///< Enables PTM capabil= ity=0D + UINT32 SlotPowerLimitScale : 2; ///< (Test) Speci= fies scale used for slot power limit value. Leave as 0 to set to default. D= efault is zero.=0D + UINT32 SlotPowerLimitValue : 12; //< (Test) Specif= ies upper limit on power supplies by slot. Leave as 0 to set to default. De= fault is zero.=0D + /**=0D + Probe CLKREQ# signal before enabling CLKREQ# based power management.=0D + Conforming device shall hold CLKREQ# low until CPM is enabled. This fe= ature attempts=0D + to verify CLKREQ# signal is connected by testing pad state before enab= ling CPM.=0D + In particular this helps to avoid issues with open-ended PCIe slots.=0D + This is only applicable to non hot-plug ports.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 ClkReqDetect : 1;=0D + /**=0D + Set if the slot supports manually operated retention latch.=0D + **/=0D + UINT32 MrlSensorPresent : 1;=0D + UINT32 RelaxedOrder : 1;=0D + UINT32 NoSnoop : 1;=0D + UINT32 RsvdBits0 : 28; ///< Reserved bits.=0D + /**=0D + PCIe Gen3 Equalization Phase 3 Method (see CPU_PCIE_EQ_METHOD).=0D + 0: DEPRECATED, hardware equalization; 1: hardware equalization;= 4: Fixed Coefficients=0D + **/=0D + UINT8 Gen3EqPh3Method;=0D + UINT8 PhysicalSlotNumber; ///< Indicates the slot = number for the root port. Default is the value as root port index.=0D + UINT8 CompletionTimeout; ///< The completion time= out configuration of the root port (see: CPU_PCIE_COMPLETION_TIMEOUT). Defa= ult is PchPcieCompletionTO_Default.=0D + //=0D + // Power Management=0D + //=0D + UINT8 Aspm; ///< The ASPM configurat= ion of the root port (see: CPU_PCIE_ASPM_CONTROL). Default is PchPcieAsp= mAutoConfig.=0D + UINT8 L1Substates; ///< The L1 Substates co= nfiguration of the root port (see: CPU_PCIE_L1SUBSTATES_CONTROL). Default i= s PchPcieL1SubstatesL1_1_2.=0D + UINT8 LtrEnable; ///< Latency Tolerance R= eporting Mechanism. 0: Disable; 1: Enable.=0D + UINT8 EnableCpm; ///< Enables Clock Power= Management; even if disabled, CLKREQ# signal can still be controlled by L1= PM substates mechanism=0D + UINT8 PcieSpeed; ///< Contains speed of P= CIe bus (see: PCIE_SPEED)=0D + /**=0D + (Test)=0D + Forces LTR override to be permanent=0D + The default way LTR override works is:=0D + rootport uses LTR override values provided by BIOS until connected devic= e sends an LTR message, then it will use values from the message=0D + This settings allows force override of LTR mechanism. If it's enabled, t= hen:=0D + rootport will use LTR override values provided by BIOS forever; LTR mess= ages sent from connected device will be ignored=0D + **/=0D + PCIE_LTR_CONFIG PcieRpLtrConfig; ///< (Test)= Latency Tolerance Reporting Policies including LTR limit and Override= =0D + /**=0D + The number of milliseconds reference code will wait for link to exit D= etect state for enabled ports=0D + before assuming there is no device and potentially disabling the port.= =0D + It's assumed that the link will exit detect state before root port ini= tialization (sufficient time=0D + elapsed since PLTRST de-assertion) therefore default timeout is zero. = However this might be useful=0D + if device power-up seqence is controlled by BIOS or a specific device = requires more time to detect.=0D + In case of non-common clock enabled the default timout is 15ms.=0D + Default: 0=0D + **/=0D + UINT16 DetectTimeoutMs;=0D + UINT8 FormFactor; // Please check PCIE_FORM_FACTOR for supported value= s=0D + UINT8 Reserved;=0D +} PCIE_ROOT_PORT_COMMON_CONFIG;=0D +=0D +/**=0D + PCIe Common Config=0D + @note This structure will be expanded to hold all common PCIe policies b= etween SA and PCH=0D +**/=0D +typedef struct {=0D + ///=0D + /// This member describes whether Peer Memory Writes are enabled on the = platform. 0: Disable; 1: Enable.=0D + ///=0D + UINT32 EnablePeerMemoryWrite : 1;=0D + /**=0D + RpFunctionSwap allows BIOS to use root port function number swapping w= hen root port of function 0 is disabled.=0D + A PCIE device can have higher functions only when Function0 exists. To= satisfy this requirement,=0D + BIOS will always enable Function0 of a device that contains more than = 0 enabled root ports.=0D + - Enabled: One of enabled root ports get assigned to Function0.= =0D + This offers no guarantee that any particular root port will be avail= able at a specific DevNr:FuncNr location=0D + - Disabled: Root port that corresponds to Function0 will be kept visib= le even though it might be not used.=0D + That way rootport - to - DevNr:FuncNr assignment is constant. This o= ption will impact ports 1, 9, 17.=0D + NOTE: This option will not work if ports 1, 9, 17 are fused or confi= gured for RST PCIe storage or disabled through policy=0D + In other words, it only affects ports that would become hidden= because they have no device connected.=0D + NOTE: Disabling function swap may have adverse impact on power manag= ement. This option should ONLY=0D + be used when each one of root ports 1, 9, 17:=0D + - is configured as PCIe and has correctly configured ClkReq signal= , or=0D + - does not own any mPhy lanes (they are configured as SATA or USB)= =0D + **/=0D + UINT32 RpFunctionSwap : 1;=0D + /**=0D + Compliance Test Mode shall be enabled when using Compliance Load Board= .=0D + 0: Disable, 1: Enable=0D + **/=0D + UINT32 ComplianceTestMode : 1;=0D + UINT32 RsvdBits0 : 29; ///< Reserved bits=0D + ///=0D + /// List of coefficients used during equalization (applicable to both so= ftware and hardware EQ)=0D + /// Deprecated Policy=0D + ///=0D + PCIE_EQ_PARAM HwEqGen3CoeffList[PCIE_HWEQ_COEFFS_MAX]= ;=0D +} PCIE_COMMON_CONFIG;=0D +=0D +typedef struct {=0D + PCIE_EQ_PARAM HwEqGen3CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];=0D + PCIE_EQ_PARAM HwEqGen4CoeffList[CPU_PCIE_MAX_= ROOT_PORTS][PCIE_HWEQ_COEFFS_MAX];=0D +} PCIE_COMMON_CONFIG2;=0D +=0D +#pragma pack (pop)=0D +#endif // _PCIE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConf= ig.h new file mode 100644 index 0000000000..5c7811823d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/AdrConfig.h @@ -0,0 +1,86 @@ +/** @file=0D + ADR policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _ADR_CONFIG_H_=0D +#define _ADR_CONFIG_H_=0D +=0D +#include =0D +=0D +#define ADR_CONFIG_REVISION 1=0D +extern EFI_GUID gAdrConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef enum {=0D + AdrScale1us,=0D + AdrScale10us,=0D + AdrScale100us,=0D + AdrScale1ms,=0D + AdrScale10ms,=0D + AdrScale100ms,=0D + AdrScale1s,=0D + AdrScale10s=0D +} ADR_TIMER_SCALE;=0D +=0D +/**=0D + ADR Source Enable=0D +**/=0D +typedef union {=0D + struct {=0D + UINT32 Reserved1 : 1;=0D + UINT32 AdrSrcPbo : 1;=0D + UINT32 AdrSrcPmcUncErr : 1;=0D + UINT32 AdrSrcPchThrm : 1;=0D + UINT32 AdrSrcMePbo : 1;=0D + UINT32 AdrSrcCpuThrm : 1;=0D + UINT32 AdrSrcMegbl : 1;=0D + UINT32 AdrSrcLtReset : 1;=0D + UINT32 AdrSrcPmcWdt : 1;=0D + UINT32 AdrSrcMeWdt : 1;=0D + UINT32 AdrSrcPmcFw : 1;=0D + UINT32 AdrSrcPchpwrFlr : 1;=0D + UINT32 AdrSrcSyspwrFlr : 1;=0D + UINT32 Reserved2 : 1;=0D + UINT32 AdrSrcMiaUxsErr : 1;=0D + UINT32 AdrSrcMiaUxErr : 1;=0D + UINT32 AdrSrcCpuThrmWdt : 1;=0D + UINT32 AdrSrcMeUncErr : 1;=0D + UINT32 AdrSrcAdrGpio : 1;=0D + UINT32 AdrSrcOcwdtNoicc : 1;=0D + UINT32 AdrSrcOcwdtIcc : 1;=0D + UINT32 AdrSrcCseHecUncErr : 1;=0D + UINT32 AdrSrcPmcSramUncErr : 1;=0D + UINT32 AdrSrcPmcIromParity : 1;=0D + UINT32 AdrSrcPmcRfFusaErr : 1;=0D + UINT32 Reserved3 : 4;=0D + UINT32 AdrSrcPpbrParityErr : 1;=0D + UINT32 Reserved4 : 2;=0D + } Field;=0D + UINT32 Value;=0D +} ADR_SOURCE_ENABLE;=0D +=0D +/**=0D + ADR Configuration=0D + Revision 1: - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 AdrEn : 2; ///< Determine if Adr is enabl= ed - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE=0D + UINT32 AdrTimerEn : 2; ///< Determine if Adr timer op= tions are enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE=0D + UINT32 AdrTimer1Val : 2; ///< Determines the Timeout va= lue used for the ADR timer 1. A value of zero bypasses the timer=0D + UINT32 AdrMultiplier1Val : 8; ///< Specifies the tick freque= ncy upon which the timer 1 will increment. ADR_TIMER_SCALE should be used t= o encode values=0D + UINT32 AdrTimer2Val : 8; ///< Determines the Timeout va= lue used for the ADR timer 2. A value of zero bypasses the timer=0D + UINT32 AdrMultiplier2Val : 8; ///< Specifies the tick freque= ncy upon which the timer 2 will increment. ADR_TIMER_SCALE should be used t= o encode values=0D + UINT32 AdrHostPartitionReset : 2; ///< Determine if Host Partiti= on Reset is enabled - 0: PLATFORM_POR, 1: FORCE_ENABLE, 2: FORCE_DISABLE=0D + UINT32 AdrSrcOverride : 1; ///< Check if default ADR sour= ces will be overriten with custom 0: Not overwritten, 1: Overwritten=0D + UINT32 ReservedBits : 31;=0D + ADR_SOURCE_ENABLE AdrSrcSel; ///< Determine which ADR sourc= es are enabled - 0: Enabled, 1: Disabled=0D +} ADR_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _ADR_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmCo= nfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig= .h new file mode 100644 index 0000000000..2f8e19b50b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Pmc/PmConfig.h @@ -0,0 +1,391 @@ +/** @file=0D + Power Management policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PM_CONFIG_H_=0D +#define _PM_CONFIG_H_=0D +=0D +#include =0D +=0D +#define PM_CONFIG_REVISION 2=0D +extern EFI_GUID gPmConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure allows to customize PCH wake up capability from S5 or Dee= pSx by WOL, LAN, PCIE wake events.=0D +**/=0D +typedef struct {=0D + /**=0D + Corresponds to the PME_B0_S5_DIS bit in the General PM Configuration B= (GEN_PMCON_B) register.=0D + When set to 1, this bit blocks wake events from PME_B0_STS in S5, rega= rdless of the state of PME_B0_EN.=0D + When cleared (default), wake events from PME_B0_STS are allowed in S5 = if PME_B0_EN =3D 1. 0: Disable; 1: Enable.=0D + **/=0D + UINT32 PmeB0S5Dis : 1;=0D + UINT32 WolEnableOverride : 1; ///< Corresponds to the "WOL Enabl= e Override" bit in the General PM Configuration B (GEN_PMCON_B) register. 0= : Disable; 1: Enable.=0D + UINT32 PcieWakeFromDeepSx : 1; ///< Determine if enable PCIe to w= ake from deep Sx. 0: Disable; 1: Enable.=0D + UINT32 WoWlanEnable : 1; ///< Determine if WLAN wake from S= x, corresponds to the "HOST_WLAN_PP_EN" bit in the PWRM_CFG3 register. 0= : Disable; 1: Enable.=0D + UINT32 WoWlanDeepSxEnable : 1; ///< Determine if WLAN wake from D= eepSx, corresponds to the "DSX_WLAN_PP_EN" bit in the PWRM_CFG3 register. <= b>0: Disable; 1: Enable.=0D + UINT32 LanWakeFromDeepSx : 1; ///< Determine if enable LAN to wa= ke from deep Sx. 0: Disable; 1: Enable.=0D + UINT32 RsvdBits0 : 26;=0D +} PCH_WAKE_CONFIG;=0D +=0D +typedef enum {=0D + PchDeepSxPolDisable,=0D + PchDpS5BatteryEn,=0D + PchDpS5AlwaysEn,=0D + PchDpS4S5BatteryEn,=0D + PchDpS4S5AlwaysEn,=0D + PchDpS3S4S5BatteryEn,=0D + PchDpS3S4S5AlwaysEn=0D +} PCH_DEEP_SX_CONFIG;=0D +=0D +typedef enum {=0D + PchSlpS360us =3D 1,=0D + PchSlpS31ms,=0D + PchSlpS350ms,=0D + PchSlpS32s=0D +} PCH_SLP_S3_MIN_ASSERT;=0D +=0D +typedef enum {=0D + PchSlpS4PchTime, ///< The time defined in PCH EDS Power Sequencing a= nd Reset Signal Timings table=0D + PchSlpS41s,=0D + PchSlpS42s,=0D + PchSlpS43s,=0D + PchSlpS44s=0D +} PCH_SLP_S4_MIN_ASSERT;=0D +=0D +typedef enum {=0D + PchSlpSus0ms =3D 1,=0D + PchSlpSus500ms,=0D + PchSlpSus1s,=0D + PchSlpSus4s,=0D +} PCH_SLP_SUS_MIN_ASSERT;=0D +=0D +typedef enum {=0D + PchSlpA0ms =3D 1,=0D + PchSlpA4s,=0D + PchSlpA98ms,=0D + PchSlpA2s,=0D +} PCH_SLP_A_MIN_ASSERT;=0D +=0D +typedef enum {=0D + S0ixDisQNoChange,=0D + S0ixDisQDciOob,=0D + S0ixDisQUsb2Dbc,=0D + S0ixDisQMax,=0D +} S0IX_DISQ_PROBE_TYPE;=0D +=0D +/**=0D + Low Power Mode Enable config.=0D + Used to configure if respective S0i2/3 sub-states are to be supported=0D + by the platform. Each bit corresponds to one LPM state - LPMx->BITx.=0D + Some sub-states will require external FETs controlled by EXT_PWR_GATE#/E= XT_PWR_GATE2# pins=0D + to gate v1p05-PHY or v1p05-IS supplies=0D +**/=0D +typedef union {=0D + struct {=0D + UINT32 S0i2p0En : 1; ///< LPM0 - S0i2.0 Enable=0D + UINT32 S0i2p1En : 1; ///< LPM1 - S0i2.1 Enable=0D + /**=0D + LPM2 - S0i2.2 Enable.=0D + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.=0D + Refer to V1p05PhyExtFetControlEn.=0D + **/=0D + UINT32 S0i2p2En : 1;=0D + UINT32 S0i3p0En : 1; ///< LPM3 - S0i3.0 Enable=0D + UINT32 S0i3p1En : 1; ///< LPM4 - S0i3.1 Enable=0D + UINT32 S0i3p2En : 1; ///< LPM5 - S0i3.2 Enable=0D + /**=0D + LPM5 - S0i3.3 Enable.=0D + Requires EXT_PWR_GATE# controlled FET to gate v1p05 PHY.=0D + Refer to V1p05PhyExtFetControlEn.=0D + **/=0D + UINT32 S0i3p3En : 1;=0D + /**=0D + LPM7 - S0i3.4 Enable.=0D + Requires EXT_PWR_GATE2# controlled FET to gate v1p05-SRAM/ISCLK.=0D + Refer to V1p05IsExtFetControlEn.=0D + **/=0D + UINT32 S0i3p4En : 1;=0D + UINT32 Reserved : 24; ///< Reserved=0D + } Field;=0D + UINT32 Val;=0D +} PMC_LPM_S0IX_SUB_STATE_EN;=0D +=0D +/**=0D + Description of Global Reset Trigger/Event Mask register=0D +**/=0D +typedef union {=0D + struct {=0D + UINT32 Reserved1 : 1;=0D + UINT32 Pbo : 1;=0D + UINT32 PmcUncErr : 1;=0D + UINT32 PchThrm : 1;=0D + UINT32 MePbo : 1;=0D + UINT32 CpuThrm : 1;=0D + UINT32 Megbl : 1;=0D + UINT32 LtReset : 1;=0D + UINT32 PmcWdt : 1;=0D + UINT32 MeWdt : 1;=0D + UINT32 PmcFw : 1;=0D + UINT32 PchpwrFlr : 1;=0D + UINT32 SyspwrFlr : 1;=0D + UINT32 Reserved2 : 1;=0D + UINT32 MiaUxsErr : 1;=0D + UINT32 MiaUxErr : 1;=0D + UINT32 CpuThrmWdt : 1;=0D + UINT32 MeUncErr : 1;=0D + UINT32 AdrGpio : 1;=0D + UINT32 OcwdtNoicc : 1;=0D + UINT32 OcwdtIcc : 1;=0D + UINT32 CseHecUncErr : 1;=0D + UINT32 PmcSramUncErr : 1;=0D + UINT32 PmcIromParity : 1;=0D + UINT32 PmcRfFusaErr : 1;=0D + UINT32 Reserved3 : 4;=0D + UINT32 PpbrParityErr : 1;=0D + UINT32 Reserved4 : 2;=0D + } Field;=0D + UINT32 Value;=0D +} PMC_GLOBAL_RESET_MASK;=0D +=0D +/**=0D + The PCH_PM_CONFIG block describes expected miscellaneous power managemen= t settings.=0D + The PowerResetStatusClear field would clear the Power/Reset status bits,= please=0D + set the bits if you want PCH Init driver to clear it, if you want to che= ck the=0D + status later then clear the bits.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2=0D + - Added C10DynamicThresholdAdjustment=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header=0D +=0D + PCH_WAKE_CONFIG WakeConfig; ///< Specify W= ake Policy=0D + UINT32 PchDeepSxPol : 4; ///< Deep Sx P= olicy. Refer to PCH_DEEP_SX_CONFIG for each value. Default is PchDeepSxP= olDisable.=0D + UINT32 PchSlpS3MinAssert : 4; ///< SLP_S3 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S3_MIN_ASSERT for each value= . Default is PchSlpS350ms.=0D + UINT32 PchSlpS4MinAssert : 4; ///< SLP_S4 Mi= nimum Assertion Width Policy. Refer to PCH_SLP_S4_MIN_ASSERT for each value= . Default is PchSlpS44s.=0D + UINT32 PchSlpSusMinAssert : 4; ///< SLP_SUS M= inimum Assertion Width Policy. Refer to PCH_SLP_SUS_MIN_ASSERT for each val= ue. Default is PchSlpSus4s.=0D + UINT32 PchSlpAMinAssert : 4; ///< SLP_A Min= imum Assertion Width Policy. Refer to PCH_SLP_A_MIN_ASSERT for each value. = Default is PchSlpA2s.=0D + UINT32 RsvdBits0 : 12;=0D + /**=0D + This member describes whether or not the LPC ClockRun feature of PCH s= hould=0D + be enabled. 0: Disable; 1: Enable=0D + **/=0D + UINT32 SlpStrchSusUp : 1; ///< 0: Dis= able; 1: Enable SLP_X Stretching After SUS Well Power Up=0D + /**=0D + Enable/Disable SLP_LAN# Low on DC Power. 0: Disable; 1: Enable.= =0D + Configure On DC PHY Power Diable according to policy SlpLanLowDc.=0D + When this is enabled, SLP_LAN# will be driven low when ACPRESENT is lo= w.=0D + This indicates that LAN PHY should be powered off on battery mode.=0D + This will override the DC_PP_DIS setting by WolEnableOverride.=0D + **/=0D + UINT32 SlpLanLowDc : 1;=0D + /**=0D + PCH power button override period.=0D + 000b-4s, 001b-6s, 010b-8s, 011b-10s, 100b-12s, 101b-14s=0D + Default is 0: 4s=0D + **/=0D + UINT32 PwrBtnOverridePeriod : 3;=0D + /**=0D + (Test)=0D + Disable/Enable PCH to CPU enery report feature. 0: Disable; 1: = Enable.=0D + Enery Report is must have feature. Wihtout Energy Report, the performa= nce report=0D + by workloads/benchmarks will be unrealistic because PCH's energy is no= t being accounted=0D + in power/performance management algorithm.=0D + If for some reason PCH energy report is too high, which forces CPU to = try to reduce=0D + its power by throttling, then it could try to disable Energy Report to= do first debug.=0D + This might be due to energy scaling factors are not correct or the LPM= settings are not=0D + kicking in.=0D + **/=0D + UINT32 DisableEnergyReport : 1;=0D + /**=0D + When set to Disable, PCH will internal pull down AC_PRESENT in deep SX= and during G3 exit.=0D + When set to Enable, PCH will not pull down AC_PRESENT.=0D + This setting is ignored when DeepSx is not supported.=0D + Default is 0:Disable=0D + **/=0D + UINT32 DisableDsxAcPresentPulldown : 1;=0D + /**=0D + Power button native mode disable.=0D + While FALSE, the PMC's power button logic will act upon the input valu= e from the GPIO unit, as normal.=0D + While TRUE, this will result in the PMC logic constantly seeing the po= wer button as de-asserted.=0D + Default is FALSE.=0D + **/=0D + UINT32 DisableNativePowerButton : 1;=0D + UINT32 MeWakeSts : 1; ///< Clea= r the ME_WAKE_STS bit in the Power and Reset Status (PRSTS) register. 0: Di= sable; 1: Enable.=0D + UINT32 WolOvrWkSts : 1; ///< Clea= r the WOL_OVR_WK_STS bit in the Power and Reset Status (PRSTS) register. 0:= Disable; 1: Enable.=0D + /*=0D + Set true to enable TCO timer.=0D + When FALSE, it disables PCH ACPI timer, and stops TCO timer.=0D + @note: This will have significant power impact when it's enabled.=0D + If TCO timer is disabled, uCode ACPI timer emulation must be enabled,= =0D + and WDAT table must not be exposed to the OS.=0D + 0: Disable, 1: Enable=0D + */=0D + UINT32 EnableTcoTimer : 1;=0D + /*=0D + When VRAlert# feature pin is enabled and its state is '0',=0D + the PMC requests throttling to a T3 Tstate to the PCH throttling unit.= =0D + 0: Disable; 1: Enable.=0D + */=0D + UINT32 VrAlert : 1;=0D + /**=0D + Decide if PS_ON is to be enabled. This is available on desktop only.=0D + PS_ON is a new C10 state from the CPU on desktop SKUs that enables a=0D + lower power target that will be required by the California Energy=0D + Commission (CEC). When FALSE, PS_ON is to be disabled.}=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 PsOnEnable : 1;=0D + /**=0D + Enable/Disable platform support for CPU_C10_GATE# pin to control gatin= g=0D + of CPU VccIO and VccSTG rails instead of SLP_S0# pin. This policy need= s=0D + to be set if board design includes support for CPU_C10_GATE# pin.=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT32 CpuC10GatePinEnable : 1;=0D + /**=0D + Control whether to enable PMC debug messages to Trace Hub.=0D + When Enabled, PMC HW will send debug messages to trace hub;=0D + When Disabled, PMC HW will never send debug meesages to trace hub.=0D + @note: When enabled, system may not enter S0ix=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 PmcDbgMsgEn : 1;=0D + /**=0D + Enable/Disable ModPHY SUS Power Domain Dynamic Gating.=0D + EXT_PWR_GATE# signal (if supported on platform) can be used to=0D + control external FET for power gating ModPHY=0D + @note: This setting is not supported and ignored on PCH-H=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 ModPhySusPgEnable : 1;=0D + /**=0D + (Test)=0D + This policy option enables USB2 PHY SUS Well Power Gating functionalit= y.=0D + @note: This setting is not supported and ignored on PCH-H=0D + 0: disable USB2 PHY SUS Well Power Gating=0D + 1: enable USB2 PHY SUS Well Power Gating=0D + **/=0D + UINT32 Usb2PhySusPgEnable : 1;=0D + /**=0D + Enable Os Idle Mode.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 OsIdleEnable : 1;=0D + /**=0D + Enable control using EXT_PWR_GATE# pin of external FET=0D + to power gate v1p05-PHY=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 V1p05PhyExtFetControlEn : 1;=0D + /**=0D + Enable control using EXT_PWR_GATE2# pin of external FET=0D + to power gate v1p05-IS supply=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 V1p05IsExtFetControlEn : 1;=0D + /**=0D + Enable/Disable the Low Power Mode Host S0ix Auto-Demotion=0D + feature. This feature enables the PMC to autonomously manage=0D + the deepest allowed S0ix substate to combat thrashing between=0D + power management states.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 S0ixAutoDemotion : 1;=0D + /**=0D + Enable/Disable Latch Events C10 Exit. When this bit is set to 1,=0D + SLP_S0# entry events in SLP_S0_DEBUG_REGx registers are captured=0D + on C10 exit (instead of C10 entry which is default)=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 LatchEventsC10Exit : 1;=0D + UINT32 RsvdBits1 : 10;=0D + /*=0D + Power button debounce configuration=0D + Debounce time can be specified in microseconds. Only certain values ac= cording=0D + to below formula are supported:=0D + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(glitch filter clock perio= d).=0D + RTC clock with f =3D 32 KHz is used for glitch filter.=0D + DebounceTime =3D (2 ^ PADCFG_DW2.DEBOUNCE)*(31.25 us).=0D + Supported DebounceTime values are following:=0D + DebounceTime =3D 0 -> Debounce feature disabled=0D + DebounceTime > 0 && < 250us -> Not supported=0D + DebounceTime =3D 250us - 1024000us -> Supported range (DebounceTime = =3D 250us * 2^n)=0D + For values not supported by HW, they will be rounded down to closest s= upported one=0D + Default is 0=0D + */=0D + UINT32 PowerButtonDebounce;=0D + /**=0D + Reset Power Cycle Duration could be customized in the unit of second. = Please refer to EDS=0D + for all support settings. PCH HW default is 4 seconds, and range is 1~= 4 seconds, where=0D + 0 is default, 1 is 1 second, 2 is 2 seconds, ... 4 is 4 seconds= .=0D + And make sure the setting correct, which never less than the following= register.=0D + - GEN_PMCON_B.SLP_S3_MIN_ASST_WDTH=0D + - GEN_PMCON_B.SLP_S4_MIN_ASST_WDTH=0D + - PWRM_CFG.SLP_A_MIN_ASST_WDTH=0D + - PWRM_CFG.SLP_LAN_MIN_ASST_WDTH=0D + **/=0D + UINT8 PchPwrCycDur;=0D + /**=0D + Specifies the Pcie Pll Spread Spectrum Percentage=0D + The value of this policy is in 1/10th percent units.=0D + Valid spread range is 0-20. A value of 0xFF is reserved for AUTO.=0D + A value of 0 is SSC of 0.0%. A value of 20 is SSC of 2.0%=0D + The default is 0xFF: AUTO - No BIOS override.=0D + **/=0D + UINT8 PciePllSsc;=0D + /**=0D + Tells BIOS to enable C10 dynamic threshold adjustment mode.=0D + BIOS will only attemt to enable it on PCH SKUs which support it.=0D + **/=0D + UINT8 C10DynamicThresholdAdjustment;=0D + UINT8 Rsvd0[1]; ///< Reser= ved bytes=0D + /**=0D + (Test)=0D + Low Power Mode Enable/Disable config.=0D + Configure if respective S0i2/3 sub-states are to be supported=0D + by the platform. By default all sub-states are enabled but=0D + for test purpose respective states can be disabled.=0D + Default is 0xFF=0D + **/=0D + PMC_LPM_S0IX_SUB_STATE_EN LpmS0ixSubStateEnable;=0D + /*=0D + Set true to enable Timed GPIO 0 timer.=0D + 0: Disable, 1: Enable=0D + */=0D + UINT32 EnableTimedGpio0 : 1;=0D + /*=0D + Set true to enable Timed GPIO 1 timer.=0D + 0: Disable, 1: Enable=0D + */=0D + UINT32 EnableTimedGpio1 : 1;=0D + UINT32 Rsvdbits : 30;=0D +=0D + /**=0D + Set true to enable override of Global Reset Event/Trigger masks.=0D + Values from GlobalResetTriggerMask and GlobalResetEventMask will=0D + be used as override value.=0D + 0: Disable, 1: Enable=0D + **/=0D + UINT8 GlobalResetMasksOverride;=0D + UINT8 Rsvd1[3]; ///< Reserved bytes=0D + /*=0D + Mask for enabling Global Reset Trigger prevention=0D + */=0D + PMC_GLOBAL_RESET_MASK GlobalResetTriggerMask;=0D + /*=0D + Mask for enabling Global Reset Event prevention=0D + */=0D + PMC_GLOBAL_RESET_MASK GlobalResetEventMask;=0D +} PCH_PM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConf= ig.h new file mode 100644 index 0000000000..033e416b83 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Psf/PsfConfig.h @@ -0,0 +1,32 @@ +/** @file=0D + Primary Sideband Fabric policy.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PSF_CONFIG_H_=0D +#define _PSF_CONFIG_H_=0D +=0D +#define PSF_CONFIG_REVISION 1=0D +extern EFI_GUID gPsfConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PSF_CONFIG block describes the expected configuration of the Primary= =0D + Sideband Fabric.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + Psf Tcc (Time Coordinated Computing) Enable will decrease psf transact= ion latency by disable=0D + some psf power management features. 0: Disable; 1: Enable.=0D + **/=0D + UINT32 TccEnable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} PSF_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PSF_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConf= ig.h new file mode 100644 index 0000000000..469d46a205 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rst/RstConfig.h @@ -0,0 +1,82 @@ +/** @file=0D + Rst policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _RST_CONFIG_H_=0D +#define _RST_CONFIG_H_=0D +#include =0D +#include =0D +=0D +#define RST_CONFIG_REVISION 1=0D +extern EFI_GUID gRstConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef enum {=0D + SataOromDelay2sec,=0D + SataOromDelay4sec,=0D + SataOromDelay6sec,=0D + SataOromDelay8sec=0D +} SATA_OROM_DELAY;=0D +=0D +/**=0D + This structure describes the details of Intel RST for PCIe Storage remap= ping=0D + Note: In order to use this feature, Intel RST Driver is required=0D +**/=0D +typedef struct {=0D + /**=0D + This member describes whether or not the Intel RST for PCIe Storage re= mapping should be enabled. 0: Disable; 1: Enable.=0D + Note 1: If Sata Controller is disabled, PCIe Storage Remapping should = be disabled as well=0D + Note 2: If PCIe Storage remapping is enabled, the PCH integrated AHCI = controllers Class Code is configured as RAID=0D + **/=0D + UINT32 Enable : 1;=0D + /**=0D + Intel RST for PCIe Storage remapping - PCIe Port Selection (1-based, <= b>0 =3D autodetect)=0D + The supported ports for PCIe Storage remapping is different depend on = the platform and cycle router=0D + **/=0D + UINT32 RstPcieStoragePort : 5;=0D + /**=0D + PCIe Storage Device Reset Delay in milliseconds (ms), which it guarant= ees such delay gap is fulfilled=0D + before PCIe Storage Device configuration space is accessed after an re= set caused by the link disable and enable step.=0D + Default value is 100ms.=0D + **/=0D + UINT32 DeviceResetDelay : 8;=0D + UINT32 RsvdBits0 : 18; ///< Reserved bits=0D +=0D +} RST_HARDWARE_REMAPPED_STORAGE_CONFIG;=0D +=0D +/**=0D + Rapid Storage Technology settings.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header=0D +=0D + UINT32 Raid0 : 1; ///< 0 : Disable; 1 : Enab= le RAID0=0D + UINT32 Raid1 : 1; ///< 0 : Disable; 1 : Enab= le RAID1=0D + UINT32 Raid10 : 1; ///< 0 : Disable; 1 : Enab= le RAID10=0D + UINT32 Raid5 : 1; ///< 0 : Disable; 1 : Enab= le RAID5=0D + UINT32 Irrt : 1; ///< 0 : Disable; 1 : Enab= le Intel Rapid Recovery Technology=0D + UINT32 OromUiBanner : 1; ///< 0 : Disable; 1 : Enab= le OROM UI and BANNER=0D + UINT32 OromUiDelay : 2; ///< 00b : 2 secs; 01b = : 4 secs; 10b : 6 secs; 11 : 8 secs (see : SATA_OROM_DELAY)=0D + UINT32 HddUnlock : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the HDD password unlock in the OS is enabled=0D + UINT32 LedLocate : 1; ///< 0 : Disable; 1 : Enab= le. Indicates that the LED/SGPIO hardware is attached and ping to locat= e feature is enabled on the OS=0D + UINT32 IrrtOnly : 1; ///< 0 : Disable; 1 : Enab= le. Allow only IRRT drives to span internal and external ports=0D + UINT32 SmartStorage : 1; ///< 0 : Disable; 1 : Enab= le RST Smart Storage caching Bit=0D + UINT32 LegacyOrom : 1; ///< 0 : Disable; 1 : = Enable RST Legacy OROM=0D + UINT32 OptaneMemory : 1; ///< 0: Disable; 1: Enable RST Optane(TM) Memory=0D + UINT32 CpuAttachedStorage : 1; ///< 0: Disable; 1: Enable CPU Attached Storage=0D + UINT32 RsvdBits0 : 17; ///< Reserved Bits=0D + /**=0D + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required)=0D + Note: RST for PCIe Sorage remapping is supported only for first SATA c= ontroller if more controllers are available=0D + **/=0D + RST_HARDWARE_REMAPPED_STORAGE_CONFIG HardwareRemappedStorageConfig[PCH= _MAX_RST_PCIE_STORAGE_CR];=0D +} RST_CONFIG;=0D +=0D +#pragma pack (pop)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConf= ig.h new file mode 100644 index 0000000000..1f354c10ae --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Rtc/RtcConfig.h @@ -0,0 +1,38 @@ +/** @file=0D + RTC policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _RTC_CONFIG_H_=0D +#define _RTC_CONFIG_H_=0D +=0D +#define RTC_CONFIG_REVISION 1=0D +extern EFI_GUID gRtcConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The RTC_CONFIG block describes the expected configuration of RTC configu= ration.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + When set, prevents RTC TS (BUC.TS) from being changed.=0D + This BILD bit has different function compared to LPC/eSPI, SPI.=0D + 0: Disabled; 1: Enabled=0D + **/=0D + UINT32 BiosInterfaceLock : 1;=0D + /**=0D + When set, bytes 38h-3Fh in the upper 128bytes bank of RTC RAM are lock= ed=0D + and cannot be accessed.=0D + Writes will be droipped and reads will not return any guaranteed data.= =0D + 0: Disabled; 1: Enabled=0D + **/=0D + UINT32 MemoryLock : 1;=0D + UINT32 RsvdBits0 : 30;=0D +} RTC_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _RTC_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/Sat= aConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/Sata= Config.h new file mode 100644 index 0000000000..c560fdd3ab --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Sata/SataConfig= .h @@ -0,0 +1,168 @@ +/** @file=0D + Sata policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SATA_CONFIG_H_=0D +#define _SATA_CONFIG_H_=0D +=0D +#include =0D +=0D +#define SATA_CONFIG_REVISION 1=0D +extern EFI_GUID gSataConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef enum {=0D + SataModeAhci,=0D + SataModeRaid,=0D + SataModeMax=0D +} SATA_MODE;=0D +=0D +typedef enum {=0D + SataSpeedDefault,=0D + SataSpeedGen1,=0D + SataSpeedGen2,=0D + SataSpeedGen3=0D +} SATA_SPEED;=0D +=0D +typedef enum {=0D + SataRstMsix,=0D + SataRstMsi,=0D + SataRstLegacy=0D +} SATA_RST_INTERRUPT;=0D +=0D +typedef enum {=0D + SataRaidClient,=0D + SataRaidAlternate,=0D + SataRaidServer=0D +} SATA_RAID_DEV_ID;=0D +=0D +/**=0D + This structure configures the features, property, and capability for eac= h SATA port.=0D +**/=0D +typedef struct {=0D + /**=0D + Enable SATA port.=0D + It is highly recommended to disable unused ports for power savings=0D + **/=0D + UINT32 Enable : 1; ///< 0: Disable; 1: E= nable=0D + UINT32 HotPlug : 1; ///< 0: Disable; = 1: Enable=0D + UINT32 InterlockSw : 1; ///< 0: Disable; = 1: Enable=0D + UINT32 External : 1; ///< 0: Disable; = 1: Enable=0D + UINT32 SpinUp : 1; ///< 0: Disable; = 1: Enable the COMRESET initialization Sequence to the device=0D + UINT32 SolidStateDrive : 1; ///< 0: HDD; 1: S= SD=0D + UINT32 DevSlp : 1; ///< 0: Disable; = 1: Enable DEVSLP on the port=0D + UINT32 EnableDitoConfig : 1; ///< 0: Disable; = 1: Enable DEVSLP Idle Timeout settings (DmVal, DitoVal)=0D + UINT32 DmVal : 4; ///< DITO multiplier. De= fault is 15.=0D + UINT32 DitoVal : 10; ///< DEVSLP Idle Timeout= (DITO), Default is 625.=0D + /**=0D + Support zero power ODD 0: Disable, 1: Enable.=0D + This is also used to disable ModPHY dynamic power gate.=0D + **/=0D + UINT32 ZpOdd : 1;=0D + UINT32 DevSlpResetConfig : 4; ///< 0: Hardware default= ; 0x01: GpioResumeReset; 0x03: GpioHostDeepReset; 0x05: GpioPlatform= Reset; 0x07: GpioDswReset=0D + UINT32 SataPmPtm : 1; ///< Deprecated=0D + UINT32 RxPolarity : 1; ///< 0: Disable; = 1: Enable; Rx Polarity=0D + UINT32 RsvdBits0 : 3; ///< Reserved fields for= future expansion w/o protocol change=0D +} PCH_SATA_PORT_CONFIG;=0D +=0D +/**=0D + This structure lists PCH supported SATA thermal throttling register sett= ing for customization.=0D + The settings is programmed through SATA Index/Data registers.=0D + When the SuggestedSetting is enabled, the customized values are ignored.= =0D +**/=0D +typedef struct {=0D + UINT32 P0T1M : 2; ///< Port 0 T1 Multipler=0D + UINT32 P0T2M : 2; ///< Port 0 T2 Multipler=0D + UINT32 P0T3M : 2; ///< Port 0 T3 Multipler=0D + UINT32 P0TDisp : 2; ///< Port 0 Tdispatch=0D +=0D + UINT32 P1T1M : 2; ///< Port 1 T1 Multipler=0D + UINT32 P1T2M : 2; ///< Port 1 T2 Multipler=0D + UINT32 P1T3M : 2; ///< Port 1 T3 Multipler=0D + UINT32 P1TDisp : 2; ///< Port 1 Tdispatch=0D +=0D + UINT32 P0Tinact : 2; ///< Port 0 Tinactive=0D + UINT32 P0TDispFinit : 1; ///< Port 0 Alternate Fast Init Td= ispatch=0D + UINT32 P1Tinact : 2; ///< Port 1 Tinactive=0D + UINT32 P1TDispFinit : 1; ///< Port 1 Alternate Fast Init Td= ispatch=0D + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values=0D + UINT32 RsvdBits0 : 9; ///< Reserved bits=0D +} SATA_THERMAL_THROTTLING;=0D +=0D +/**=0D + The SATA_CONFIG block describes the expected configuration of the SATA = controllers.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Bl= ock Header=0D + ///=0D + /// This member describes whether or not the SATA controllers should be = enabled. 0: Disable; 1: Enable.=0D + ///=0D + UINT8 Enable;=0D + UINT8 TestMode; ///< (Test) 0: D= isable; 1: Allow entrance to the PCH SATA test modes=0D + UINT8 SalpSupport; ///< 0: Disable; 1: Ena= ble Aggressive Link Power Management=0D + UINT8 PwrOptEnable; ///< 0: Disable; 1: Ena= ble SATA Power Optimizer on PCH side.=0D + /**=0D + EsataSpeedLimit=0D + When enabled, BIOS will configure the PxSCTL.SPD to 2 to limit the eSA= TA port speed.=0D + Please be noted, this setting could be cleared by HBA reset, which mig= ht be issued=0D + by EFI AHCI driver when POST time, or by SATA inbox driver/RST driver = after POST.=0D + To support the Speed Limitation when POST, the EFI AHCI driver should = preserve the=0D + setting before and after initialization. For support it after POST, it= 's dependent on=0D + driver's behavior.=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT8 EsataSpeedLimit;=0D + UINT8 LedEnable; ///< SATA LED indicates S= ATA controller activity. 0: Disable; 1: Enable SATA LED.=0D + /**=0D + This option allows to configure SATA controller device ID while in RAI= D mode.=0D + Refer to SATA_RAID_DEV_ID enumeration for supported options.=0D + Choosing Client will allow RST driver loading, RSTe driver will not be= able to load=0D + Choosing Alternate will not allow RST inbox driver loading in Windows= =0D + Choosing Server will allow RSTe driver loading, RST driver will not lo= ad=0D + 0: Client; 1: Alternate; 2: Server=0D + **/=0D + UINT8 RaidDeviceId;=0D + /**=0D + Controlls which interrupts will be linked to SATA controller CAP list= =0D + This option will take effect only if SATA controller is in RAID mode=0D + Default: PchSataMsix=0D + **/=0D + UINT8 SataRstInterrupt;=0D +=0D + /**=0D + Determines the system will be configured to which SATA mode.=0D + Refer to SATA_MODE enumeration for supported options. Default is Sa= taModeAhci.=0D + **/=0D + UINT8 SataMode;=0D + /**=0D + Indicates the maximum speed the SATA controller can support.=0D + Refer to SATA_SPEED enumeration for supported options.=0D + 0h: SataSpeedDefault; 1h: 1.5 Gb/s (Gen 1); 2h: 3 Gb/s(Gen 2); = 3h: 6 Gb/s (Gen 1)=0D + **/=0D + UINT8 SpeedLimit;=0D + UINT8 EnclosureSupport; ///< Enclosure Managem= ent Support. 0: Disable; 1: Enable=0D + /**=0D + Controlls whenever Serial GPIO support is enabled for controller=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT8 SgpioSupport;=0D + /**=0D + This member configures the features, property, and capability for each= SATA port.=0D + **/=0D + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];=0D + /**=0D + This field decides the settings of Sata thermal throttling. When the S= uggested Setting=0D + is enabled, PCH RC will use the suggested representative values.=0D + **/=0D + SATA_THERMAL_THROTTLING ThermalThrottling;=0D +} SATA_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SATA_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConf= ig.h new file mode 100644 index 0000000000..2ebc901896 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Scs/ScsConfig.h @@ -0,0 +1,139 @@ +/** @file=0D + Scs policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SCS_CONFIG_H_=0D +#define _SCS_CONFIG_H_=0D +=0D +#include =0D +#include =0D +=0D +#define SCS_SDCARD_CONFIG_REVISION 1=0D +#define SCS_EMMC_CONFIG_REVISION 1=0D +#define SCS_EMMC_DXE_CONFIG_REVISION 1=0D +#define SCS_SDCARD_MAX_DATA_GPIOS 4=0D +#define SCS_EMMC_MAX_DATA_GPIOS 8=0D +extern EFI_GUID gSdCardConfigGuid;=0D +extern EFI_GUID gEmmcConfigGuid;=0D +extern EFI_GUID gUfsConfigGuid;=0D +extern EFI_GUID gEmmcDxeConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structre holds the DLL configuration=0D + register values that will be programmed by RC=0D + if EnableCustomDlls field is set to TRUE. Those=0D + policies should be used by platform if default values=0D + provided by RC are not sufficient to provide stable operation=0D + at all supported spped modes. RC will blindly set the DLL values=0D + as provided in this structre.=0D +=0D + For help with obtaining valid DLL values for your platform please=0D + contact enabling support.=0D +**/=0D +typedef struct {=0D + UINT32 TxCmdDelayControl; // Offset 820h: Tx CMD Delay Control=0D + UINT32 TxDataDelayControl1; // Offset 824h: Tx Data Delay Control 1= =0D + UINT32 TxDataDelayControl2; // Offset 828h: Tx Data Delay Control 2= =0D + UINT32 RxCmdDataDelayControl1; // Offset 82Ch: Rx CMD + Data Delay Cont= rol 1=0D + UINT32 RxCmdDataDelayControl2; // Offset 834h: Rx CMD + Data Delay Cont= rol 2=0D + UINT32 RxStrobeDelayControl; // Offset 830h: Rx Strobe Delay Control,= valid only for eMMC=0D +} SCS_SD_DLL;=0D +=0D +/**=0D + SD GPIO settings=0D +**/=0D +typedef struct {=0D + /**=0D + GPIO signals pin muxing settings. If signal can be enable only on a si= ngle pin=0D + then this parameter should be set to 0. Refer to GPIO_*_MUXING_SDCARD_= *x_* in GpioPins*.h=0D + for supported settings on a given platform=0D + **/=0D + UINT32 PinMux;=0D + /**=0D + GPIO Pads Internal Termination.=0D + For more information please see Platform Design Guide.=0D + Check GPIO_ELECTRICAL_CONFIG for reference=0D + **/=0D + UINT32 PadTermination;=0D +} MUX_GPIO_PARAM;=0D +=0D +typedef struct {=0D + MUX_GPIO_PARAM PowerEnable;=0D + MUX_GPIO_PARAM Cmd;=0D + MUX_GPIO_PARAM Data[SCS_SDCARD_MAX_DATA_GPIOS];=0D + MUX_GPIO_PARAM Cdb;=0D + MUX_GPIO_PARAM Clk;=0D + MUX_GPIO_PARAM Wp;=0D +} SCS_SDCARD_GPIO_CONFIG;=0D +=0D +typedef struct {=0D + MUX_GPIO_PARAM Cmd;=0D + MUX_GPIO_PARAM Data[SCS_EMMC_MAX_DATA_GPIOS];=0D + MUX_GPIO_PARAM Rclk;=0D + MUX_GPIO_PARAM Clk;=0D + MUX_GPIO_PARAM Resetb;=0D +} SCS_EMMC_GPIO_CONFIG;=0D +=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header;=0D +=0D + UINT32 Enable : 1; ///< Enable/Disable SdCard 0: D= isabled, 1: Enabled=0D + UINT32 PowerEnableActiveHigh : 1; ///< Determine SD_PWREN# polari= ty 0: Active low, 1: Active high=0D + UINT32 UseCustomDlls : 1; ///< Use tuned DLL values from = policy 0: Use default DLL, 1: Use values from TunedDllValues field=0D + UINT32 Reserved : 29;=0D + SCS_SD_DLL CustomDllValues; ///< Structure containing custo= m DLL values for SD card=0D + SCS_SDCARD_GPIO_CONFIG GpioConfig;=0D +} SCS_SDCARD_CONFIG;=0D +=0D +typedef struct {=0D + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value=0D + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value=0D + UINT32 Reserved : 18;=0D +} SCS_EMMC_TUNED_DLL;=0D +=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header;=0D +=0D + UINT32 Enable : 1; ///< Enable/Disable eMMC 0: Disabled, = 1: Enabled=0D + UINT32 Hs400Supported : 1; ///< Enable/Disable eMMC HS400 support= 0: Disabled, 1: Enabled=0D + UINT32 UseCustomDlls : 1; ///< Use custom DLL values from policy= 0: Use default DLL, 1: Use values from TunedDllValues field=0D + UINT32 Reserved : 29;=0D + SCS_SD_DLL CustomDllValues; ///< Structure containing custom DLL v= alues for eMMC ///< Structure containing tuned DLL setti= ngs for eMMC=0D + SCS_EMMC_GPIO_CONFIG GpioConfig;=0D +} SCS_EMMC_CONFIG;=0D +=0D +typedef enum {=0D + DriverStrength33Ohm =3D 0,=0D + DriverStrength40Ohm,=0D + DriverStrength50Ohm=0D +} SCS_EMMC_DRIVER_STRENGTH;=0D +=0D +typedef struct {=0D + UINT32 TuningSuccessful : 1; ///< Informs software tuning module abou= t previous software tuning status.=0D + UINT32 Hs400RxValue : 7; ///< Value of the tuned HS400 Rx value r= eturned from software tuning module=0D + UINT32 Hs400TxValue : 7; ///< Value of the tuned HS400 Tx value r= eturned from software tuning module=0D + UINT32 Reserved : 17;=0D +} SCS_EMMC_SOFTWARE_TUNING_RESULTS;=0D +=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header;=0D +=0D + UINT32 EnableSoftwareHs400Tuning : 1; ///< Enable/Di= sable software eMMC HS400 tuning: 0 - Disable, 1 - Enable=0D + UINT32 DriverStrength : 2; ///< I/O drive= r strength: 0 - 33 Ohm, 1 - 40 Ohm, 2 - 50 Ohm=0D + UINT32 Reserved : 29;=0D + EFI_LBA TuningLba; ///< Specifies= LBA which will be used during software tuning process.=0D + SCS_EMMC_SOFTWARE_TUNING_RESULTS PreviousTuningResults; ///< Informes = software tuning module about previous software tuning results.} SCS_EMMC_DX= E_CONFIG;=0D +} SCS_EMMC_DXE_CONFIG;=0D +=0D +typedef struct {=0D + UINT32 Enable : 1; ///< Enable/Disable UFS controller 0: Disabled, <= b>1: Enabled=0D + UINT32 Reserved : 31;=0D +} SCS_UFS_CONTROLLER_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SCS_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo= /SerialIoConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/S= erialIo/SerialIoConfig.h new file mode 100644 index 0000000000..d76937cf59 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SerialIo/Serial= IoConfig.h @@ -0,0 +1,32 @@ +/** @file=0D + Serial IO policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SERIAL_IO_CONFIG_H_=0D +#define _SERIAL_IO_CONFIG_H_=0D +=0D +#define SERIAL_IO_CONFIG_REVISION 1=0D +extern EFI_GUID gSerialIoConfigGuid;=0D +=0D +#include =0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The SERIAL_IO_CONFIG block provides the configurations to set the Serial= IO controllers=0D +=0D + Revision 1:=0D + - Inital version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header=0D + SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS];= ///< SPI Configuration=0D + SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS];= ///< I2C Configuration=0D + SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS= ]; ///< UART Configuration=0D +} SERIAL_IO_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SERIAL_IO_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig= .h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h new file mode 100644 index 0000000000..7ee4554b1d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiConfig.h @@ -0,0 +1,152 @@ +/** @file=0D + Si Config Block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_CONFIG_H_=0D +#define _SI_CONFIG_H_=0D +=0D +#define SI_CONFIG_REVISION 2=0D +=0D +extern EFI_GUID gSiConfigGuid;=0D +=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The Silicon Policy allows the platform code to publish a set of configur= ation=0D + information that the RC drivers will use to configure the silicon hardwa= re.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Added TraceHubMemBase=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header=0D + //=0D + // Platform specific common policies that used by several silicon compon= ents.=0D + //=0D + UINT8 CsmFlag; ///< CSM status flag.=0D + /**=0D + This is used to skip the SSID programming in silicon code.=0D + When set to TRUE, silicon code will not do any SSID programming and pl= atform code=0D + needs to handle that by itself properly.=0D + 0: FALSE, 1: TRUE=0D + **/=0D + UINT8 SkipSsidProgramming;=0D + UINT8 RsvdBytes0[2];=0D + /**=0D + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value=0D + to program the SVID for all internal devices.=0D + 0: use silicon default SVID 0x8086 , Non-zero: use customized S= VID.=0D + **/=0D + UINT16 CustomizedSvid;=0D + /**=0D + When SkipSsidProgramming is FALSE, silicon code will use this as defau= lt value=0D + to program the Sid for all internal devices.=0D + 0: use silicon default SSID 0x7270 , Non-zero: use customized S= SID.=0D + **/=0D + UINT16 CustomizedSsid;=0D + /**=0D + SsidTablePtr contains the SVID_SID_INIT_ENTRY table.=0D + This is valid when SkipSsidProgramming is FALSE;=0D + It doesn't need to contain entries for all Intel internal devices.=0D + It can only contains the SVID_SID_INIT_ENTRY entries for those Dev# Fu= nc# which needs=0D + to be overridden.=0D + In the enties, only Dev, Function, SubSystemVendorId, and SubSystemId = are required.=0D + Default is NULL.=0D +=0D + E.g. Platform only needs to override BDF 0:31:5 to AAAA:BBBB and BDF 0= :31:3 to CCCC:DDDD,=0D + it can be done in platform like this:=0D + STATIC SVID_SID_INIT_ENTRY mSsidTablePtr[SI_MAX_DEVICE_COUNT] =3D {0};= =0D +=0D + VOID SiPolicyUpdate () {=0D + UINT32 EntryCount =3D 0;=0D + SiPolicy->SkipSsidProgramming =3D FALSE;=0D + SiPolicy->SsidTablePtr =3D mSsidTablePtr;=0D +=0D + mSsidTablePtr[EntryCount].Address.Bits.Device =3D SpiDeviceNumber = ();=0D + mSsidTablePtr[EntryCount].Address.Bits.Function =3D SpiFunctionNumbe= r ();=0D + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D 0xAAAA;= =0D + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xBBBB;= =0D + EntryCount ++;=0D + mSsidTablePtr[EntryCount].Address.Bits.Device =3D HdaDevNumber ();= =0D + mSsidTablePtr[EntryCount].Address.Bits.Function =3D HdaFuncNumber ()= ;=0D + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemVendorId =3D 0xCCCC;= =0D + mSsidTablePtr[EntryCount].SvidSidValue.SubSystemId =3D 0xDDDD;= =0D + EntryCount ++;=0D + ASSERT (EntryCount < SI_MAX_DEVICE_COUNT);=0D + SiPolicy->NumberOfSsidTableEntry =3D EntryCount;=0D + }=0D + **/=0D + UINT32 *SsidTablePtr;=0D + /**=0D + Number of valid enties in SsidTablePtr.=0D + This is valid when SkipSsidProgramming is FALSE;=0D + Default is 0.=0D + **/=0D + UINT16 NumberOfSsidTableEntry;=0D + UINT8 RsvdBytes1[2];=0D + /**=0D + If Trace Hub is enabled and trace to memory is desired, Platform code = or BootLoader needs to allocate trace hub memory=0D + as reserved, and save allocated memory base to TraceHubMemBase to ensu= re Trace Hub memory is configured properly.=0D + To get total trace hub memory size please refer to TraceHubCalculateTo= talBufferSize ()=0D +=0D + Noted: If EDKII memory service is used to allocate memory, it will req= uire double memory size to support size-aligned memory allocation,=0D + so Platform code or FSP Wrapper code should ensure enough memory avail= able for size-aligned TraceHub memory allocation.=0D + **/=0D + UINT32 TraceHubMemBase; // Offset 58=0D + /**=0D + This is used to skip setting BIOS_DONE MSR during firmware update boot= mode.=0D + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,=0D + skip setting BIOS_DONE MSR at EndofPei.=0D + 0: FALSE, 1: TRUE=0D + **/=0D + UINT8 SkipBiosDoneWhenFwUpdate;=0D + UINT8 RsvdBytes2[3];=0D +} SI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#define DEFAULT_SSVID 0x8086=0D +#define DEFAULT_SSDID 0x7270=0D +#define SI_MAX_DEVICE_COUNT 70=0D +=0D +///=0D +/// Subsystem Vendor ID / Subsystem ID=0D +///=0D +typedef struct {=0D + UINT16 SubSystemVendorId;=0D + UINT16 SubSystemId;=0D +} SVID_SID_VALUE;=0D +=0D +//=0D +// Below is to match PCI_SEGMENT_LIB_ADDRESS () which can directly send to= PciSegmentRead/Write functions.=0D +//=0D +typedef struct {=0D + union {=0D + struct {=0D + UINT32 Register:12;=0D + UINT32 Function:3;=0D + UINT32 Device:5;=0D + UINT32 Bus:8;=0D + UINT32 Reserved1:4;=0D + UINT32 Segment:16;=0D + UINT32 Reserved2:16;=0D + } Bits;=0D + UINT64 SegBusDevFuncRegister;=0D + } Address;=0D + SVID_SID_VALUE SvidSidValue;=0D + UINT32 Reserved;=0D +} SVID_SID_INIT_ENTRY;=0D +=0D +=0D +typedef struct {=0D + UINT32 SkipBus;=0D + UINT32 SkipDevice;=0D + UINT32 SkipFunction;=0D +} SVID_SID_SKIP_TABLE;=0D +=0D +#endif // _SI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMem= Config.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemCo= nfig.h new file mode 100644 index 0000000000..4bf014e9ba --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/SiPreMemConfig.h @@ -0,0 +1,67 @@ +/** @file=0D + Si Config Block PreMem=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_PREMEM_CONFIG_H_=0D +#define _SI_PREMEM_CONFIG_H_=0D +=0D +#define SI_PREMEM_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gSiPreMemConfigGuid;=0D +=0D +typedef enum {=0D + ProbeTypeDisabled =3D 0x00,=0D + ProbeTypeDciOob =3D 0x02,=0D + ProbeTypeUsb3Dbc =3D 0x03,=0D + ProbeTypeXdp3 =3D 0x04,=0D + ProbeTypeUsb2Dbc =3D 0x05,=0D + ProbeType2WireDciOob =3D 0x06,=0D + ProbeTypeManual =3D 0x07,=0D + ProbeTypeMax=0D +} PLATFORM_DEBUG_CONSENT_PROBE_TYPE;=0D +=0D +#pragma pack (push,1)=0D +/**=0D + The Silicon PreMem Policy allows the platform code to publish a set of c= onfiguration=0D + information that the RC drivers will use to configure the silicon hardwa= re.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0 - 27 Config Block Header=0D + /**=0D + Platform Debug Consent=0D + As a master switch to enable platform debug capability and relevant se= ttings with specified probe type.=0D + Manual: Do not use Platform Debug Consent to override other debug-rele= vant policies, but the user must set each debug option manually, aimed at a= dvanced users.=0D +=0D + PDC-dependent policies are listed:=0D + DciPreMemConfig->DciEn=0D + DciPreMemConfig->DciDbcMode=0D + CpuTraceHubConfig->EnableMode=0D + CpuTraceHubConfig->CpuTraceHubMemReg0Size=0D + CpuTraceHubConfig->CpuTraceHubMemReg1Size=0D + PchTraceHubPreMemConfig->EnableMode=0D + PchTraceHubPreMemConfig->MemReg0Size=0D + PchTraceHubPreMemConfig->MemReg1Size=0D +=0D + Note: DCI OOB (aka BSSB) uses CCA probe.=0D + Refer to definition of PLATFORM_DEBUG_CONSENT_PROBE_TYPE=0D + 0:Disabled; 2:DCI OOB; 3:USB3 DbC; 4:XDP3/MIPI60 5:USB2 DbC; 6:= 2-wire DCI OOB; 7:Manual=0D + **/=0D + UINT32 PlatformDebugConsent : 4;=0D + UINT32 RsvdBits : 28;=0D + /**=0D + This is used to skip override boot mode during firmware update boot mo= de.=0D + When set to TRUE and boot mode is BOOT_ON_FLASH_UPDATE,=0D + skip setting boot mode to BOOT_WITH_FULL_CONFIGURATION in PEI memory i= nit.=0D + 0: FALSE, 1: TRUE=0D + **/=0D + UINT8 SkipOverrideBootModeWhenFwUpdate;=0D + UINT8 RsvdBytes[3];=0D +} SI_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +#endif // _SI_PREMEM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/Sm= busConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/S= mbusConfig.h new file mode 100644 index 0000000000..36f96a4f32 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Smbus/SmbusConf= ig.h @@ -0,0 +1,50 @@ +/** @file=0D + Smbus policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SMBUS_CONFIG_H_=0D +#define _SMBUS_CONFIG_H_=0D +=0D +#define SMBUS_PREMEM_CONFIG_REVISION 1=0D +extern EFI_GUID gSmbusPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +#define PCH_MAX_SMBUS_RESERVED_ADDRESS 128=0D +=0D +///=0D +/// The SMBUS_CONFIG block lists the reserved addresses for non-ARP capabl= e devices in the platform.=0D +///=0D +typedef struct {=0D + /**=0D + Revision 1: Init version=0D + **/=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + This member describes whether or not the SMBus controller of PCH shoul= d be enabled.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 ArpEnable : 1; ///< Enable SMBus ARP support, = 0: Disable; 1: Enable.=0D + UINT32 DynamicPowerGating : 1; ///< (Test) Disable = or Enable Smbus dynamic power gating.=0D + ///=0D + /// (Test) SPD Write Disable, 0: leave SPD Write Disable bit; = 1: set SPD Write Disable bit.=0D + /// For security recommendations, SPD write disable bit must be set.=0D + ///=0D + UINT32 SpdWriteDisable : 1;=0D + UINT32 SmbAlertEnable : 1; ///< Enable SMBus Alert pin (SMBAL= ERT#). 0: Disabled, 1: Enabled.=0D + UINT32 RsvdBits0 : 27; ///< Reserved bits=0D + UINT16 SmbusIoBase; ///< SMBUS Base Address (IO space)= . Default is 0xEFA0.=0D + UINT8 Rsvd0; ///< Reserved bytes=0D + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the= RsvdSmbusAddressTable.=0D + /**=0D + Array of addresses reserved for non-ARP-capable SMBus devices.=0D + **/=0D + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];=0D +} PCH_SMBUS_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SMBUS_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConf= ig.h new file mode 100644 index 0000000000..f3e52ff453 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Spi/SpiConfig.h @@ -0,0 +1,43 @@ +/** @file=0D + PCH SPI Flash Controller config block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SPI_CONFIG_H_=0D +#define _SPI_CONFIG_H_=0D +=0D +#define SPI_CONFIG_REVISION 1=0D +extern EFI_GUID gSpiConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + Basic configuration for option features of PCH SPI Flash controller=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + Enable extended BIOS Direct Read Region feature=0D + Enabling this will make all memory accesses in a decode range to be tr= anslated=0D + to BIOS region reads from SPI flash=0D + 0: Disabled, 1: Enabled=0D + **/=0D + UINT32 ExtendedBiosDecodeRangeEnable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits= =0D + /**=0D + Base address that will be used for Extended Decode Range.=0D + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.=0D + **/=0D + UINT32 ExtendedBiosDecodeRangeBase;=0D + /**=0D + Limit address that will be used for Extended Decode Range.=0D + This will be ignored when ExtendedBiosDecodeRangeEnable is set to 0.=0D + **/=0D + UINT32 ExtendedBiosDecodeRangeLimit;=0D +} SPI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _SPI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/Tcs= sPeiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/T= cssPeiConfig.h new file mode 100644 index 0000000000..53af4ccd45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Tcss/TcssPeiCon= fig.h @@ -0,0 +1,145 @@ +/** @file=0D + TCSS PEI policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _TCSS_PEI_CONFIG_H_=0D +#define _TCSS_PEI_CONFIG_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#define TCSS_PEI_CONFIG_REVISION 2=0D +extern EFI_GUID gTcssPeiConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +=0D +#define MAX_IOM_AUX_BIAS_COUNT 4=0D +=0D +///=0D +/// The IOM_AUX_ORI_PAD_CONFIG describes IOM TypeC port map GPIO pin.=0D +/// Those GPIO setting for DP Aux Orientation Bias Control when the TypeC = port didn't have re-timer.=0D +/// IOM needs know Pull-Up and Pull-Down pin for Bias control=0D +///=0D +typedef struct {=0D + UINT32 GpioPullN; ///< GPIO Pull Up Ping number that is for IOM inde= cate the pull up pin from TypeC port.=0D + UINT32 GpioPullP; ///< GPIO Pull Down Ping number that is for IOM in= decate the pull down pin from TypeC port.=0D +} IOM_AUX_ORI_PAD_CONFIG;=0D +=0D +///=0D +/// The IOM_EC_INTERFACE_CONFIG block describes interaction between BIOS a= nd IOM-EC.=0D +///=0D +=0D +typedef struct {=0D + UINT32 VccSt; ///< IOM VCCST request. (Not equal to actual V= CCST value)=0D + UINT32 UsbOverride; ///< IOM to override USB connection.=0D + UINT32 D3ColdEnable; ///< Enable/disable D3 Cold support in TCSS=0D + UINT32 D3HotEnable; ///< Enable/disable D3 Hot support in TCSS=0D +} IOM_INTERFACE_CONFIG;=0D +=0D +///=0D +/// The PMC_INTERFACE_CONFIG block describes interaction between BIOS and = PMC=0D +///=0D +typedef struct {=0D + UINT8 PmcPdEnable; ///< PMC PD Solution Enable=0D + UINT8 Rsvd[3];=0D +} PMC_INTERFACE_CONFIG;=0D +=0D +///=0D +/// The SA XDCI INT Pin and IRQ number=0D +///=0D +typedef struct {=0D + UINT8 IntPing; ///< Int Pin Number=0D + UINT8 Irq; ///< Irq Number=0D + UINT16 Rsvd;=0D +} SA_XDCI_IRQ_INT_CONFIG;=0D +=0D +///=0D +/// The TCSS_PCIE_PORT_POLICY block describes PCIe settings for TCSS.=0D +///=0D +typedef struct {=0D + UINT8 AcsEnabled; ///< Indicate whether the AC= S is enabled. 0: Disable; 1: Enable.=0D + UINT8 DpcEnabled; ///< Downstream Port Contain= ment. 0: Disable; 1: Enable=0D + UINT8 RpDpcExtensionsEnabled; ///< RP Extensions for Downs= tream Port Containment. 0: Disable; 1: Enable=0D + UINT8 LtrEnable; ///< Latency Tolerance Repor= ting Mechanism. 0: Disable; 1: Enable.=0D + UINT8 PtmEnabled; ///< Enables PTM capability= =0D +=0D + UINT8 Aspm; ///< The ASPM configuration = of the root port (see: PCH_PCIE_ASPM_CONTROL). Default is =0D + UINT8 SlotNumber; ///< Indicates the slot numb= er for the root port. Default is the value as root port index.=0D + UINT8 SlotPowerLimitScale; ///< (Test) Specifies= scale used for slot power limit value. Leave as 0 to set to default. Defau= lt is zero.=0D + UINT16 SlotPowerLimitValue; ///< (Test) Specifies= upper limit on power supplies by slot. Leave as 0 to set to default. Defau= lt is zero.=0D +=0D + UINT8 AdvancedErrorReporting; ///< Indicate whether the Ad= vanced Error Reporting is enabled. 0: Disable; 1: Enable.=0D + UINT8 UnsupportedRequestReport; ///< Indicate whether the Un= supported Request Report is enabled. 0: Disable; 1: Enable.=0D + UINT8 FatalErrorReport; ///< Indicate whether the Fa= tal Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT8 NoFatalErrorReport; ///< Indicate whether the No= Fatal Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT8 CorrectableErrorReport; ///< Indicate whether the Co= rrectable Error Report is enabled. 0: Disable; 1: Enable.=0D + UINT8 SystemErrorOnFatalError; ///< Indicate whether the Sy= stem Error on Fatal Error is enabled. 0: Disable; 1: Enable.=0D + UINT8 SystemErrorOnNonFatalError; ///< Indicate whether the Sy= stem Error on Non Fatal Error is enabled. 0: Disable; 1: Enable.=0D + UINT8 SystemErrorOnCorrectableError; ///< Indicate whether the Sy= stem Error on Correctable Error is enabled. 0: Disable; 1: Enable.=0D +=0D + UINT16 LtrMaxSnoopLatency; ///< Latency Tolerance Repor= ting, Max Snoop Latency.=0D + UINT16 LtrMaxNoSnoopLatency; ///< Latency Tolerance Repor= ting, Max Non-Snoop Latency.=0D + UINT8 SnoopLatencyOverrideMode; ///< Latency Tolerance Repor= ting, Snoop Latency Override Mode.=0D + UINT8 SnoopLatencyOverrideMultiplier; ///< Latency Tolerance Repor= ting, Snoop Latency Override Multiplier.=0D + UINT16 SnoopLatencyOverrideValue; ///< Latency Tolerance Repor= ting, Snoop Latency Override Value.=0D + UINT8 NonSnoopLatencyOverrideMode; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Mode.=0D + UINT8 NonSnoopLatencyOverrideMultiplier; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Multiplier.=0D + UINT16 NonSnoopLatencyOverrideValue; ///< Latency Tolerance Repor= ting, Non-Snoop Latency Override Value.=0D + UINT8 ForceLtrOverride; ///< 0: Disable; 1: E= nable.=0D + UINT8 LtrConfigLock; ///< 0: Disable; 1: E= nable.=0D +} TCSS_PCIE_PORT_POLICY;=0D +=0D +///=0D +/// TCSS_PCIE_PEI_POLICY describes PCIe port settings for TCSS.=0D +///=0D +typedef struct {=0D + TCSS_PCIE_PORT_POLICY PciePortPolicy[MAX_ITBT_PCIE_PORT];=0D +} TCSS_PCIE_PEI_POLICY;=0D +=0D +///=0D +/// The TCSS_IOM_PEI_CONFIG block describes IOM Aux/HSL override settings = for TCSS.=0D +///=0D +typedef struct {=0D + UINT16 AuxOri; ///< Bits defining value for IOM Aux Orientation R= egister=0D + UINT16 HslOri; ///< Bits defining value for IOM HSL Orientation R= egister=0D +} TCSS_IOM_ORI_OVERRIDE;=0D +=0D +///=0D +/// The TCSS_IOM_PEI_CONFIG block describes IOM settings for TCSS.=0D +///=0D +typedef struct {=0D + IOM_AUX_ORI_PAD_CONFIG IomAuxPortPad[MAX_IOM_AUX_BIAS_COUNT]; ///< Th= e IOM_AUX_ORI_BIAS_CTRL port config setting.=0D + TCSS_IOM_ORI_OVERRIDE IomOverrides;=0D + IOM_INTERFACE_CONFIG IomInterface; ///< Co= nfig settings are BIOS <-> IOM interface.=0D + PMC_INTERFACE_CONFIG PmcInterface; ///< Co= nfig settings for BIOS <-> PMC interface=0D + UINT8 TcStateLimit; ///< Tc= ss C-State deep stage=0D + UINT8 Usb3ComplModeEnable;=0D + UINT8 Reserved[2]; ///< Re= served bytes for future use=0D +} TCSS_IOM_PEI_CONFIG;=0D +=0D +///=0D +/// The TCSS_MISC_PEI_CONFIG block describes MISC settings for TCSS.=0D +///=0D +typedef struct {=0D + SA_XDCI_IRQ_INT_CONFIG SaXdci; ///< System Agent Xdci Int Pin and I= rq setting=0D + UINT32 Rsvd; ///< Reserved bytes for future use, = align to multiple 4=0D +} TCSS_MISC_PEI_CONFIG;=0D +=0D +///=0D +/// The TCSS_PEI_CONFIG block describes TCSS settings for SA.=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header= =0D + TCSS_PCIE_PEI_POLICY PciePolicy; ///< The PCIe Config=0D + USB_CONFIG UsbConfig; ///< USB config is shared between PC= H and SA.=0D + TCSS_IOM_PEI_CONFIG IomConfig; ///< The Iom Config=0D + TCSS_MISC_PEI_CONFIG MiscConfig; ///< The MISC Config=0D +} TCSS_PEI_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif /* _TCSS_PEI_CONFIG_H_ */=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConf= ig.h new file mode 100644 index 0000000000..23c3750216 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thc/ThcConfig.h @@ -0,0 +1,73 @@ +/** @file=0D + Touch Host Controller policy.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _THC_CONFIG_H_=0D +#define _THC_CONFIG_H_=0D +=0D +#define THC_CONFIG_REVISION 1=0D +extern EFI_GUID gThcConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + Available Port Assignments=0D +=0D +**/=0D +typedef enum {=0D + ThcAssignmentNone, ///< None of the avaialbe controllers assigned=0D + ThcAssignmentThc0, ///< Port assigned to THC0=0D + ThcAssignmentThc1 ///< Port assigned to THC1=0D +} THC_PORT_ASSIGNMENT;=0D +=0D +=0D +/**=0D + Port Configuration structure required for each Port that THC might use.= =0D +=0D +**/=0D +typedef struct {=0D + UINT32 Assignment; ///< Sets THCx assignment see THC_PORT_ASSIGN= MENT=0D + UINT32 InterruptPinMuxing; ///< Each GPIO PORTx/SPIx INTB Pin has differ= ent muxing options refer to GPIO_*_MUXING_THC_SPIx_*=0D +} THC_PORT;=0D +=0D +/**=0D + THC_CONFIG block provides the configurations forTouch Host Controllers=0D +=0D + Assignment field in each THC port controlls the THC behavior.=0D +=0D + Available scenarios:=0D + 1: Single Port 0 used by THC0=0D + - THC0 Enabled=0D + - Port0 assigned to THC0=0D + - Port1 unassigned=0D + - THC1 will be automatically Disabled.=0D + 2: Both ports used by THC0=0D + - THC0 Enabled=0D + - Port0 assigned to THC0=0D + - Port1 assigned to THC0=0D + - THC1 will be automatically Disabled.=0D + 3: Port 0 used by THC0 and Port 1 used by THC1=0D + - THC0 Enabled=0D + - Port0 assigned to THC0=0D + - THC1 Enabled=0D + - Port1 assigned to THC1.=0D +4: Both Ports unassigned.=0D + Both THC Controllers will be disabled in that case.=0D +=0D + @note=0D + Invalid scenario that will cause ASSERT.=0D + 1. Same port Number assigned to THC0 or THC1.=0D + 2. Two Ports assigned to THC1.=0D +=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + THC_PORT ThcPort[2]; ///< Port Configuration=0D +} THC_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _THC_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/= ThermalConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/The= rmal/ThermalConfig.h new file mode 100644 index 0000000000..a952f74238 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Thermal/Thermal= Config.h @@ -0,0 +1,153 @@ +/** @file=0D + Thermal policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _THERMAL_CONFIG_H_=0D +#define _THERMAL_CONFIG_H_=0D +=0D +#define THERMAL_CONFIG_REVISION 1=0D +extern EFI_GUID gThermalConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure lists PCH supported throttling register setting for custi= mization.=0D + When the SuggestedSetting is enabled, the customized values are ignored.= =0D +**/=0D +typedef struct {=0D + UINT32 T0Level : 9; ///< Custimized T0Level value. If = SuggestedSetting is used, this setting is ignored.=0D + UINT32 T1Level : 9; ///< Custimized T1Level value. If = SuggestedSetting is used, this setting is ignored.=0D + UINT32 T2Level : 9; ///< Custimized T2Level value. If = SuggestedSetting is used, this setting is ignored.=0D + UINT32 TTEnable : 1; ///< Enable the thermal throttle f= unction. If SuggestedSetting is used, this settings is ignored.=0D + /**=0D + When set to 1 and the programmed GPIO pin is a 1, then PMSync state 13= will force at least T2 state.=0D + If SuggestedSetting is used, this setting is ignored.=0D + **/=0D + UINT32 TTState13Enable : 1;=0D + /**=0D + When set to 1, this entire register (TL) is locked and remains locked = until the next platform reset.=0D + If SuggestedSetting is used, this setting is ignored.=0D + **/=0D + UINT32 TTLock : 1;=0D + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values.=0D + /**=0D + ULT processors support thermal management and cross thermal throttling= between the processor package=0D + and LP PCH. The PMSYNC message from PCH to CPU includes specific bit f= ields to update the PCH=0D + thermal status to the processor which is factored into the processor t= hrottling.=0D + Enable/Disable PCH Cross Throttling; 0: Disabled, 1: Enabled.=0D + **/=0D + UINT32 PchCrossThrottling : 1;=0D + UINT32 Rsvd0; ///< Reserved bytes=0D +} THERMAL_THROTTLE_LEVELS;=0D +=0D +//=0D +// Supported Thermal Sensor Target Width=0D +//=0D +typedef enum {=0D + DmiThermSensWidthX1 =3D 0,=0D + DmiThermSensWidthX2 =3D 1,=0D + DmiThermSensWidthX4 =3D 2,=0D + DmiThermSensWidthX8 =3D 3,=0D + DmiThermSensWidthX16 =3D 4=0D +} DMI_THERMAL_SENSOR_TARGET_WIDTH;=0D +=0D +/**=0D + This structure allows to customize DMI HW Autonomous Width Control for T= hermal and Mechanical spec design.=0D + When the SuggestedSetting is enabled, the customized values are ignored.= =0D + Look at DMI_THERMAL_SENSOR_TARGET_WIDTH for possible values=0D +**/=0D +typedef struct {=0D + UINT32 DmiTsawEn : 1; ///< DMI Thermal Sensor Autonomous= Width Enable=0D + UINT32 SuggestedSetting : 1; ///< 0: Disable; 1: Enable = suggested representative values=0D + UINT32 RsvdBits0 : 6; ///< Reserved bits=0D + UINT32 TS0TW : 3; ///< Thermal Sensor 0 Target Width= (DmiThermSensWidthx8)=0D + UINT32 TS1TW : 3; ///< Thermal Sensor 1 Target Width= (DmiThermSensWidthx4)=0D + UINT32 TS2TW : 3; ///< Thermal Sensor 2 Target Width= (DmiThermSensWidthx2)=0D + UINT32 TS3TW : 3; ///< Thermal Sensor 3 Target Width= (DmiThermSensWidthx1)=0D + UINT32 RsvdBits1 : 12; ///< Reserved bits=0D +} DMI_HW_WIDTH_CONTROL;=0D +=0D +/**=0D + This structure configures PCH memory throttling thermal sensor GPIO PIN = settings=0D +**/=0D +typedef struct {=0D + /**=0D + GPIO PM_SYNC enable, 0:Diabled, 1:Enabled=0D + When enabled, RC will overrides the selected GPIO native mode.=0D + For GPIO_C, PinSelection 0: CPU_GP_0 (default) or 1: CPU_GP_1=0D + For GPIO_D, PinSelection 0: CPU_GP_3 (default) or 1: CPU_GP_2=0D + For CNL: CPU_GP_0 is GPP_E3, CPU_GP_1 is GPP_E7, CPU_GP_2 is GPP_B3, C= PU_GP_3 is GPP_B4.=0D + **/=0D + UINT32 PmsyncEnable : 1;=0D + UINT32 C0TransmitEnable : 1; ///< GPIO Transmit enable in C0 st= ate, 0:Disabled, 1:Enabled=0D + UINT32 PinSelection : 1; ///< GPIO Pin assignment selection= , 0: default, 1: secondary=0D + UINT32 RsvdBits0 : 29;=0D +} TS_GPIO_PIN_SETTING;=0D +=0D +enum PCH_PMSYNC_GPIO_X_SELECTION {=0D + TsGpioC,=0D + TsGpioD,=0D + MaxTsGpioPin=0D +};=0D +=0D +/**=0D + This structure supports an external memory thermal sensor (TS-on-DIMM or= TS-on-Board).=0D +**/=0D +typedef struct {=0D + /**=0D + This will enable PCH memory throttling.=0D + While this policy is enabled, must also enable EnableExtts in SA policy= .=0D + 0: Disable; 1: Enable=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 RsvdBits0 : 31;=0D + /**=0D + GPIO_C and GPIO_D selection for memory throttling.=0D + It's strongly recommended to choose GPIO_C and GPIO_D for memory throt= tling feature,=0D + and route EXTTS# accordingly.=0D + **/=0D + TS_GPIO_PIN_SETTING TsGpioPinSetting[2];=0D +} PCH_MEMORY_THROTTLING;=0D +=0D +/**=0D + The THERMAL_CONFIG block describes the expected configuration of the The= rmal IP block.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 PchHotEnable : 1; ///< Enable PCHHOT# pin assertion = when temperature is higher than PchHotLevel. 0: Disabled, 1: Enabled.= =0D + UINT32 RsvdBits0 : 31;=0D + /**=0D + This field decides the settings of Thermal throttling. When the Sugges= ted Setting=0D + is enabled, PCH RC will use the suggested representative values.=0D + **/=0D + THERMAL_THROTTLE_LEVELS TTLevels;=0D + /**=0D + This field decides the settings of DMI throttling. When the Suggested = Setting=0D + is enabled, PCH RC will use the suggested representative values.=0D + **/=0D + DMI_HW_WIDTH_CONTROL DmiHaAWC;=0D + /**=0D + Memory Thermal Management settings=0D + **/=0D + PCH_MEMORY_THROTTLING MemoryThrottling;=0D + /**=0D + The recommendation is the same as Cat Trip point.=0D + This field decides the temperature, default is 120.=0D + Temperature value used for PCHHOT# pin assertion based on 2s complemen= t format=0D + - 0x001 positive 1'C=0D + - 0x000 0'C=0D + - 0x1FF negative 1'C=0D + - 0x1D8 negative 40'C=0D + - and so on=0D + **/=0D + UINT16 PchHotLevel;=0D + UINT8 Rsvd0[6];=0D +=0D +=0D +} THERMAL_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _THERMAL_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub= /TraceHubConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/T= raceHub/TraceHubConfig.h new file mode 100644 index 0000000000..9c315fb4a4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/TraceHub/TraceH= ubConfig.h @@ -0,0 +1,101 @@ +/** @file=0D + Configurations for CPU and PCH trace hub=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _TRACE_HUB_CONFIG_H_=0D +#define _TRACE_HUB_CONFIG_H_=0D +=0D +#include =0D +=0D +#define CPU_TRACEHUB_PREMEM_CONFIG_REVISION 1=0D +#define PCH_TRACEHUB_PREMEM_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gPchTraceHubPreMemConfigGuid;=0D +extern EFI_GUID gCpuTraceHubPreMemConfigGuid;=0D +=0D +typedef enum {=0D + CpuTraceHub,=0D + PchTraceHub=0D +} TRACE_HUB_DEVICE;=0D +///=0D +/// The TRACE_HUB_ENABLE_MODE describes TraceHub mode of operation=0D +///=0D +typedef enum {=0D + TraceHubModeDisabled =3D 0,=0D + TraceHubModeTargetDebugger =3D 1,=0D + TraceHubModeHostDebugger =3D 2,=0D + TraceHubModeMax=0D +} TRACE_HUB_ENABLE_MODE;=0D +=0D +///=0D +/// The TRACE_BUFFER_SIZE describes the desired TraceHub buffer size=0D +///=0D +typedef enum {=0D + TraceBufferNone,=0D + TraceBuffer1M,=0D + TraceBuffer8M,=0D + TraceBuffer64M,=0D + TraceBuffer128M,=0D + TraceBuffer256M,=0D + TraceBuffer512M,=0D + TraceBufferMax=0D +} TRACE_BUFFER_SIZE;=0D +=0D +#pragma pack (push,1)=0D +///=0D +/// TRACE_HUB_CONFIG block describes TraceHub settings=0D +///=0D +typedef struct {=0D + /**=0D + Trace hub mode. Default is disabled.=0D + Target Debugger mode refers to debug tool running on target device itsel= f and it works as a conventional PCI device;=0D + Host Debugger mode refers to SUT debugged via probe on host, configured = as ACPI device with PCI configuration sapce hidden.=0D + 0 =3D Disable; 1 =3D Target Debugger mode; 2 =3D Host Debugger mo= de=0D + Refer to TRACE_HUB_ENABLE_MODE=0D + **/=0D + UINT8 EnableMode;=0D + /**=0D + Trace hub memory buffer region size policy.=0D + The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB= , 3:64MB, 4:128MB, 5:256MB, 6:512MB.=0D + Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is = enabled, the total size limits to 256 MB.=0D + Refer to TRACE_BUFFER_SIZE=0D + **/=0D + UINT8 MemReg0Size;=0D + UINT8 MemReg1Size;=0D + /**=0D + AET Trace. AET base address can be set to FW Base either from CPU trace = hub or PCH one.=0D + AetEnabled must be exclusive, if AetEnabled =3D 1 for CPU trace hub, mus= t AetEnabled =3D 0 for PCH one.=0D + The default is set to PCH.=0D + CPU Trace Hub=0D + 0 =3D Disabled; 1 =3D Enabled=0D + PCH Trace Hub=0D + 0 =3D Disabled; 1 =3D Enabled=0D + **/=0D + UINT8 AetEnabled;=0D +} TRACE_HUB_CONFIG;=0D +=0D +/**=0D + CPU Trace Hub PreMem Configuration=0D + Contains Trace Hub settings for CPU side tracing=0D + Revision 1: - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config=0D +} CPU_TRACE_HUB_PREMEM_CONFIG;=0D +=0D +/**=0D + PCH Trace Hub PreMem Configuration=0D + Contains Trace Hub settings for PCH side tracing=0D + Revision 1: - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + TRACE_HUB_CONFIG TraceHub; ///< Trace Hub Config=0D +} PCH_TRACE_HUB_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2= PhyConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb= 2PhyConfig.h new file mode 100644 index 0000000000..99063103c3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb2PhyConf= ig.h @@ -0,0 +1,81 @@ +/** @file=0D + USB2 PHY configuration policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _USB2_PHY_CONFIG_H_=0D +#define _USB2_PHY_CONFIG_H_=0D +=0D +#include =0D +=0D +#define USB2_PHY_CONFIG_REVISION 1=0D +extern EFI_GUID gUsb2PhyConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure configures per USB2 AFE settings.=0D + It allows to setup the port electrical parameters.=0D +**/=0D +typedef struct {=0D +/** Per Port HS Preemphasis Bias (PERPORTPETXISET)=0D + 000b - 0mV=0D + 001b - 11.25mV=0D + 010b - 16.9mV=0D + 011b - 28.15mV=0D + 100b - 28.15mV=0D + 101b - 39.35mV=0D + 110b - 45mV=0D + 111b - 56.3mV=0D +**/=0D + UINT8 Petxiset;=0D +/** Per Port HS Transmitter Bias (PERPORTTXISET)=0D + 000b - 0mV=0D + 001b - 11.25mV=0D + 010b - 16.9mV=0D + 011b - 28.15mV=0D + 100b - 28.15mV=0D + 101b - 39.35mV=0D + 110b - 45mV=0D + 111b - 56.3mV=0D +**/=0D + UINT8 Txiset;=0D +/**=0D + Per Port HS Transmitter Emphasis (IUSBTXEMPHASISEN)=0D + 00b - Emphasis OFF=0D + 01b - De-emphasis ON=0D + 10b - Pre-emphasis ON=0D + 11b - Pre-emphasis & De-emphasis ON=0D +**/=0D + UINT8 Predeemp;=0D +/**=0D + Per Port Half Bit Pre-emphasis (PERPORTTXPEHALF)=0D + 1b - half-bit pre-emphasis=0D + 0b - full-bit pre-emphasis=0D +**/=0D + UINT8 Pehalfbit;=0D +} USB2_PHY_PARAMETERS;=0D +=0D +/**=0D + This structure holds info on how to tune electrical parameters of USB2 p= orts based on board layout=0D +=0D + Revision 1:=0D + - Initial version.=0D +=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er=0D + /**=0D + This structure configures per USB2 port physical settings.=0D + It allows to setup the port location and port length, and configures t= he port strength accordingly.=0D + Changing this policy values from default ones may require disabling US= B2 PHY Sus Well Power Gating=0D + through Usb2PhySusPgEnable on PCH-LP=0D + **/=0D + USB2_PHY_PARAMETERS Port[MAX_USB2_PORTS];=0D +} USB2_PHY_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _USB2_PHY_CONFIG_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3= HsioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Us= b3HsioConfig.h new file mode 100644 index 0000000000..da816b1378 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/Usb3HsioCon= fig.h @@ -0,0 +1,138 @@ +/** @file=0D + USB3 Mod PHY configuration policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _USB3_HSIO_CONFIG_H_=0D +#define _USB3_HSIO_CONFIG_H_=0D +=0D +#include =0D +=0D +#define USB3_HSIO_CONFIG_REVISION 2=0D +extern EFI_GUID gUsb3HsioConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure describes USB3 Port N configuration parameters=0D +**/=0D +typedef struct {=0D + /**=0D + USB 3.0 TX Output Downscale Amplitude Adjustment (orate01margin)=0D + HSIO_TX_DWORD8[21:16]=0D + Default =3D 00h=0D + **/=0D + UINT8 HsioTxDownscaleAmp;=0D + /**=0D + USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting (ow2tapgen2dee= mph3p5)=0D + HSIO_TX_DWORD5[21:16]=0D + Default =3D 29h (approximately -3.5dB De-Emphasis)=0D + **/=0D + UINT8 HsioTxDeEmph;=0D + /**=0D + Signed Magnatude number added to the CTLE code.(ctle_adapt_offset_cfg_= 4_0)=0D + HSIO_RX_DWORD25 [20:16]=0D + Ex: -1 -- 1_0001. +1: 0_0001=0D + Default =3D 0h=0D + **/=0D + UINT8 HsioCtrlAdaptOffsetCfg;=0D + /**=0D + LFPS filter select for n (filter_sel_n_2_0)=0D + HSIO_RX_DWORD51 [29:27]=0D + 0h:1.6ns=0D + 1h:2.4ns=0D + 2h:3.2ns=0D + 3h:4.0ns=0D + 4h:4.8ns=0D + 5h:5.6ns=0D + 6h:6.4ns=0D + Default =3D 0h=0D + **/=0D + UINT8 HsioFilterSelN;=0D + /**=0D + LFPS filter select for p (filter_sel_p_2_0)=0D + HSIO_RX_DWORD51 [26:24]=0D + 0h:1.6ns=0D + 1h:2.4ns=0D + 2h:3.2ns=0D + 3h:4.0ns=0D + 4h:4.8ns=0D + 5h:5.6ns=0D + 6h:6.4ns=0D + Default =3D 0h=0D + **/=0D + UINT8 HsioFilterSelP;=0D + /**=0D + Controls the input offset (olfpscfgpullupdwnres_sus_usb_2_0)=0D + HSIO_RX_DWORD51 [2:0]=0D + 000 Prohibited=0D + 001 45K=0D + 010 Prohibited=0D + 011 31K=0D + 100 36K=0D + 101 36K=0D + 110 36K=0D + 111 36K=0D + Default =3D 3h=0D + **/=0D + UINT8 HsioOlfpsCfgPullUpDwnRes;=0D +=0D + UINT8 HsioTxDeEmphEnable; ///< Enable the write to USB 3.0 = TX Output -3.5dB De-Emphasis Adjustment, 0: Disable; 1: Enable.=0D + UINT8 HsioTxDownscaleAmpEnable; ///< Enable the write to USB 3.0 = TX Output Downscale Amplitude Adjustment, 0: Disable; 1: Enable.=0D + UINT8 HsioCtrlAdaptOffsetCfgEnable; ///< Enable the write to Signed M= agnatude number added to the CTLE code, 0: Disable; 1: Enable.=0D + UINT8 HsioFilterSelNEnable; ///< Enable the write to LFPS fil= ter select for n, 0: Disable; 1: Enable.=0D + UINT8 HsioFilterSelPEnable; ///< Enable the write to LFPS fil= ter select for p, 0: Disable; 1: Enable.=0D + UINT8 HsioOlfpsCfgPullUpDwnResEnable; ///< Enable the write to olfpscfg= pullupdwnres, 0: Disable; 1: Enable.=0D + /**=0D + USB 3.0 TX Output - Unique Transition Bit Scale for rate 3 (rate3UniqT= ranScale)=0D + HSIO_TX_DWORD9[6:0]=0D + Default =3D 4Ch=0D + **/=0D + UINT8 HsioTxRate3UniqTran;=0D + /**=0D + USB 3.0 TX Output -Unique Transition Bit Scale for rate 2 (rate2UniqTr= anScale)=0D + HSIO_TX_DWORD9[14:8]=0D + Default =3D 4Ch=0D + **/=0D + UINT8 HsioTxRate2UniqTran;=0D + /**=0D + USB 3.0 TX Output - Unique Transition Bit Scale for rate 1 (rate1UniqT= ranScale)=0D + HSIO_TX_DWORD9[22:16]=0D + Default =3D 4Ch=0D + **/=0D + UINT8 HsioTxRate1UniqTran;=0D + /**=0D + USB 3.0 TX Output - Unique Transition Bit Scale for rate 0 (rate0UniqT= ranScale)=0D + HSIO_TX_DWORD9[30:24]=0D + Default =3D 4Ch=0D + **/=0D + UINT8 HsioTxRate0UniqTran;=0D +=0D + UINT8 HsioTxRate3UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 3, 0: Disable; 1: Enable.=0D + UINT8 HsioTxRate2UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 2, 0: Disable; 1: Enable.=0D + UINT8 HsioTxRate1UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 1, 0: Disable; 1: Enable.=0D + UINT8 HsioTxRate0UniqTranEnable; ///< Enable the write to USB 3.0 TX Un= ique Transition Bit Mode for rate 0, 0: Disable; 1: Enable.=0D +} HSIO_PARAMETERS;=0D +=0D +/**=0D + Structure for holding USB3 tuning parameters=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - USB 3.0 TX Output Unique Transition Bit Scale policies added=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er=0D + /**=0D + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules.=0D + **/=0D + HSIO_PARAMETERS Port[MAX_USB3_PORTS];=0D +} USB3_HSIO_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _USB3_HSIO_CONFIG_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConf= ig.h new file mode 100644 index 0000000000..a1c7f0bb04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Usb/UsbConfig.h @@ -0,0 +1,149 @@ +/** @file=0D + Common USB policy shared between PCH and CPU=0D + Contains general features settings for xHCI and xDCI=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _USB_CONFIG_H_=0D +#define _USB_CONFIG_H_=0D +=0D +#define USB_CONFIG_REVISION 2=0D +extern EFI_GUID gUsbConfigGuid;=0D +=0D +#define MAX_USB2_PORTS 16=0D +#define MAX_USB3_PORTS 10=0D +=0D +#pragma pack (push,1)=0D +=0D +typedef UINT8 USB_OVERCURRENT_PIN;=0D +#define USB_OC_SKIP 0xFF=0D +#define USB_OC_MAX_PINS 16 ///< Total OC pins number (both p= hysical and virtual)=0D +=0D +/**=0D + This structure configures per USB2.0 port settings like enabling and ove= rcurrent protection=0D +**/=0D +typedef struct {=0D + /**=0D + These members describe the specific over current pin number of USB 2.0= Port N.=0D + It is SW's responsibility to ensure that a given port's bit map is set= only for=0D + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin.=0D + **/=0D + UINT32 OverCurrentPin : 8;=0D + UINT32 Enable : 1; ///< 0: Disable; 1: Enab= le.=0D + UINT32 PortResetMessageEnable : 1; ///< 0: Disable USB2 Port R= eset Message; 1: Enable USB2 Port Reset Message=0D + UINT32 RsvdBits0 : 22; ///< Reserved bits=0D +} USB2_PORT_CONFIG;=0D +=0D +/**=0D + This structure configures per USB3.x port settings like enabling and ove= rcurrent protection=0D +**/=0D +typedef struct {=0D + /**=0D + These members describe the specific over current pin number of USB 3.x= Port N.=0D + It is SW's responsibility to ensure that a given port's bit map is set= only for=0D + one OC pin Description. USB2 and USB3 on the same combo Port must use = the same OC pin.=0D + **/=0D + UINT32 OverCurrentPin : 8;=0D + UINT32 Enable : 1; ///< 0: Disable; 1: Enable= .=0D + UINT32 RsvdBits0 : 23; ///< Reserved bits=0D +} USB3_PORT_CONFIG;=0D +=0D +/**=0D + The XDCI_CONFIG block describes the configurations=0D + of the xDCI Usb Device controller.=0D +**/=0D +typedef struct {=0D + /**=0D + This member describes whether or not the xDCI controller should be ena= bled.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} XDCI_CONFIG;=0D +=0D +=0D +/**=0D + This member describes the expected configuration of the USB controller,= =0D + Platform modules may need to refer Setup options, schematic, BIOS specif= ication to update this field.=0D + The Usb20OverCurrentPins and Usb30OverCurrentPins field must be updated = by referring the schematic.=0D +=0D + Revision 1: - Initial version.=0D + Revision 2: - Add USB3LinkSpeed=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Head= er=0D + /**=0D + This policy option when set will make BIOS program Port Disable Overri= de register during PEI phase.=0D + When disabled BIOS will not program the PDO during PEI phase and leave= PDO register unlocked for later programming.=0D + If this is disabled, platform code MUST set it before booting into OS.= =0D + 1: Enable=0D + 0: Disable=0D + **/=0D + UINT32 PdoProgramming : 1;=0D + /**=0D + This option allows for control whether USB should program the Overcurr= ent Pins mapping into xHCI.=0D + Disabling this feature will disable overcurrent detection functionalit= y.=0D + Overcurrent Pin mapping data is contained in respective port structure= s (i.e. USB30_PORT_CONFIG) in OverCurrentPin field.=0D + By default this Overcurrent functionality should be enabled and disabl= ed only for OBS debug usage.=0D + 1: Will program USB OC pin mapping in respective xHCI controller re= gisters=0D + 0: Will clear OC pin mapping allow for OBS usage of OC pins=0D + **/=0D + UINT32 OverCurrentEnable : 1;=0D + /**=0D + (Test)=0D + If this policy option is enabled then BIOS will program OCCFDONE bit i= n xHCI meaning that OC mapping data will be=0D + consumed by xHCI and OC mapping registers will be locked. OverCurrent = mapping data is taken from respective port data=0D + structure from OverCurrentPin field.=0D + If EnableOverCurrent policy is enabled this also should be enabled, ot= herwise xHCI won't consume OC mapping data.=0D + 1: Program OCCFDONE bit and make xHCI consume OverCurrent mapping d= ata=0D + 0: Do not program OCCFDONE bit making it possible to use OBS debug on = OC pins.=0D + **/=0D + UINT32 XhciOcLock : 1;=0D + /**=0D + Enabling this feature will allow for overriding LTR values for xHCI co= ntroller.=0D + Values used for programming will be taken from this config block and B= IOS will disregard recommended ones.=0D + 0: disable - do not override recommended LTR values=0D + 1: enable - override recommended LTR values=0D + **/=0D + UINT32 LtrOverrideEnable : 1;=0D + /**=0D + This setting enable LBPM GEN1 speed=0D + 0: GEN2;=0D + 1: GEN1;=0D + **/=0D + UINT32 USB3LinkSpeed : 1;=0D + UINT32 RsvdBits0 : 27; ///< Rese= rved bits=0D + /**=0D + High Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrHighIdleTimeOverride;=0D + /**=0D + Medium Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrMediumIdleTimeOverride;=0D + /**=0D + Low Idle Time Control override value=0D + This setting is used only if LtrOverrideEnable is enabled=0D + **/=0D + UINT32 LtrLowIdleTimeOverride;=0D + /**=0D + These members describe whether the USB2 Port N of PCH is enabled by pl= atform modules.=0D + **/=0D + USB2_PORT_CONFIG PortUsb20[MAX_USB2_PORTS];=0D + /**=0D + These members describe whether the USB3 Port N of PCH is enabled by pl= atform modules.=0D + **/=0D + USB3_PORT_CONFIG PortUsb30[MAX_USB3_PORTS];=0D + /**=0D + This member describes whether or not the xDCI controller should be ena= bled.=0D + **/=0D + XDCI_CONFIG XdciConfig;=0D +=0D +} USB_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _USB_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageR= egulator/CpuPowerMgmtVrConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include= /ConfigBlock/VoltageRegulator/CpuPowerMgmtVrConfig.h new file mode 100644 index 0000000000..8b01ecd262 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/VoltageRegulato= r/CpuPowerMgmtVrConfig.h @@ -0,0 +1,114 @@ +/** @file=0D + CPU Power Management VR Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POWER_MGMT_VR_CONFIG_H_=0D +#define _CPU_POWER_MGMT_VR_CONFIG_H_=0D +=0D +#define CPU_POWER_MGMT_VR_CONFIG_REVISION 7=0D +=0D +extern EFI_GUID gCpuPowerMgmtVrConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +///=0D +/// Defines the maximum number of VR domains supported.=0D +/// @warning: Changing this define would cause DWORD alignment issues in p= olicy structures.=0D +///=0D +#define MAX_NUM_VRS 5=0D +=0D +/**=0D + CPU Power Management VR Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Updated Acoustic Noise Mitigation.=0D + Revision 3:=0D + - Deprecate PsysOffset and added PsysOffset1 for Psys Offset Correction= =0D + Revision 4:=0D + - Deprecate TdcTimeWindow and added TdcTimeWindow1 for TDC Time=0D + Added Irms support.=0D + Revision 5:=0D + - Add RfiMitigation.=0D + Revision 6:=0D + - Added an option to Enable/Disable FIVR Spread Spectrum=0D + Revision 7:=0D + - Add Dynamic Periodicity Alteration (DPA) tuning feature=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + UINT32 AcousticNoiseMitigation : 1; ///< Enable or Disable A= coustic Noise Mitigation feature. 0: Disabled; 1: Enabled=0D + /**=0D + VR specific mailbox commands.=0D + 00b - no VR specific command sent.=0D + 01b - A VR mailbox command specifically for the MPS IMPV8 VR will be se= nt.=0D + 10b - VR specific command sent for PS4 exit issue.=0D + 11b - Reserved.=0D + **/=0D + UINT32 SendVrMbxCmd : 2;=0D + UINT32 EnableMinVoltageOverride : 1; ///< Enable or disable M= inimum Voltage override for minimum voltage runtime and minimum voltage C8.= 0: Disabled 1: Enabled.=0D + UINT32 RfiMitigation : 1; ///< Enable or Disable R= FI Mitigation. 0: Disable - DCM is the IO_N default; 1: Enable - Ena= ble IO_N DCM/CCM switching as RFI mitigation.=0D + UINT32 RsvdBits : 27; ///< Reserved for future= use.=0D + UINT8 PsysSlope; ///< PCODE MMIO Mailbox:= Platform Psys slope correction. 0: Auto Specified in 1/100 incremen= t values. Range is 0-200. 125 =3D 1.25.=0D + UINT8 PsysOffset; ///< PCODE MMIO Mailbox:= Platform Psys offset correction. 0: Auto Units 1/4, Range 0-255. Va= lue of 100 =3D 100/4 =3D 25 offset. Deprecated=0D + UINT8 FivrSpreadSpectrum; ///< Set the Spread Spec= trum Range. 1.5%, Range: 0.5%, 1%, 1.5%, 2%, 3%, 4%, 5%, 6%. Each Ra= nge is translated to internally encoded values. 0.5% =3D 0, 1% =3D 3, 1.5% = =3D 8, 2% =3D 18, 3% =3D 28, 4% =3D 34, 5% =3D 39, 6% =3D 44.=0D + UINT8 RsvdBytes0;=0D + /**=0D + PCODE MMIO Mailbox: Set the desired RFI frequency, in increments of 100= KHz.=0D + 0: Auto=0D + Range varies based on XTAL clock:=0D + - 0-1918 (Up to 191.8HMz) for 24MHz clock.=0D + - 0-1535 (Up to 153.5MHz) for 19MHz clock.=0D + **/=0D + UINT16 FivrRfiFrequency;=0D + UINT8 RsvdBytes1[2];=0D + /** @name VR Settings=0D + The VR related settings are sorted in an array where each index maps to = the VR domain as defined below:=0D + - 0 =3D System Agent VR=0D + - 1 =3D IA Core VR=0D + - 2 =3D Ring Vr=0D + - 3 =3D GT VR=0D + - 4 =3D FIVR VR=0D +=0D + The VR settings for a given domain must be populated in the appropriate = index.=0D + **/=0D + ///@{=0D + UINT16 TdcCurrentLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current current limit. Specified in 1/8A units. Range is 0-= 4095. 1000 =3D 125A. 0: 0 Amps=0D + UINT16 AcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= AcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0-6249. I= ntel Recommended Defaults vary by domain and SKU.=0D + UINT16 DcLoadline[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= DcLoadline in 1/100 mOhms (ie. 1250 =3D 12.50 mOhm); Range is 0-6249.In= tel Recommended Defaults vary by domain and SKU.=0D + UINT16 Psi1Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 1 current cuttof in 1/4 Amp increments. Range is 0-128A.=0D + UINT16 Psi2Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 2 current cuttof in 1/4 Amp increments. Range is 0-128A.=0D + UINT16 Psi3Threshold[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 3 current cuttof in 1/4 Amp increments. Range is 0-128A.=0D + INT16 ImonOffset[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Imon offset correction. Value is a 2's complement signed integer. Units 1/= 1000, Range 0-63999. For an offset =3D 12.580, use 12580. 0: Auto=0D + UINT16 IccMax[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= VR Icc Max limit. 0-255A in 1/4 A units. 400 =3D 100A. Default: 0 - Aut= o, no override=0D + UINT16 VrVoltageLimit[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= VR Voltage Limit. Range is 0-7999mV.=0D + UINT16 ImonSlope[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Imon slope correction. Specified in 1/100 increment values. Range is 0-200= . 125 =3D 1.25. 0: Auto=0D + UINT8 Psi3Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 3 enable/disable; 0: Disable; 1: Enable.=0D + UINT8 Psi4Enable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Power State 4 enable/disable; 0: Disable; 1: Enable.=0D + UINT8 VrConfigEnable[MAX_NUM_VRS]; ///< Enable/Disable BIOS= configuration of VR; 0: Disable; 1: Enable.=0D + UINT8 TdcEnable[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current enable/disable; 0: Disable; 1: Enable=0D + UINT8 TdcTimeWindow[MAX_NUM_VRS]; ///< @deprecated. PCODE = MMIO Mailbox: Thermal Design Current time window. Defined in milli seconds.= 1ms default=0D + UINT8 TdcLock[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current Lock; 0: Disable; 1: Enable.=0D + UINT8 FastPkgCRampDisable[MAX_NUM_VRS]; ///< Disable Fast Slew R= ate for Deep Package C States for VR IA,GT,SA,VLCC,FIVR domain based on Aco= ustic Noise Mitigation feature enabled. 0: False; 1: True=0D + UINT8 SlowSlewRate[MAX_NUM_VRS]; ///< Slew Rate configura= tion for Deep Package C States for VR VR IA,GT,SA,VLCC,FIVR domain based on= Acoustic Noise Mitigation feature enabled. 0: Fast/2; 1: Fast/4; 2:= Fast/8; 3: Fast/16=0D + ///@}=0D + UINT16 MinVoltageRuntime; ///< PCODE MMIO Mailbox:= Minimum voltage for runtime. Valid if EnableMinVoltageOverride =3D 1 .Rang= e 0 to 1999mV. 0: 0mV =0D + UINT16 MinVoltageC8; ///< PCODE MMIO Mailbox:= Minimum voltage for C8. Valid if EnableMinVoltageOverride =3D 1. Range 0 t= o 1999mV. 0: 0mV =0D + UINT16 PsysOffset1; ///< PCODE MMIO Mailbox:= Platform Psys offset correction. 0: Auto Units 1/1000, Range 0-6399= 9. For an offset of 25.348, enter 25348.=0D + UINT8 RsvdBytes2[2];=0D + UINT32 TdcTimeWindow1[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Thermal Design Current time window. Defined in milli seconds. 1ms defau= lt=0D + UINT8 Irms[MAX_NUM_VRS]; ///< PCODE MMIO Mailbox:= Current root mean square. 0: Disable; 1: Enable.=0D + UINT8 FivrSpectrumEnable; ///< Enable or Disable F= IVR Spread Spectrum 0: Disable; 1: Enable.=0D + UINT8 Rsvd1[2];=0D + UINT8 PreWake; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max pre-wake randomization time in micro ticks. Range is 0-255.=0D + UINT8 RampUp; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max ramp up randomization time in micro ticks. Range is 0-255.=0D + UINT8 RampDown; ///< PCODE MMIO Mailbox:= Acoustic Noise Mitigation Range. This can be programmed only if AcousticNo= iseMitigation is enabled.Default Value =3D 0 micro ticks Defines the= max ramp down randomization time in micro ticks. Range is 0-255.=0D + UINT8 Rsvd2[1];=0D +} CPU_POWER_MGMT_VR_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_POWER_MGMT_VR_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConf= ig.h new file mode 100644 index 0000000000..74ca983a5d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Vtd/VtdConfig.h @@ -0,0 +1,64 @@ +/** @file=0D + VT-d policy definitions.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _VTD_CONFIG_H_=0D +#define _VTD_CONFIG_H_=0D +=0D +#include =0D +#pragma pack(push, 1)=0D +=0D +#define VTD_CONFIG_REVISION 1=0D +#define VTD_DXE_CONFIG_REVISION 2=0D +=0D +/**=0D + The data elements should be initialized by a Platform Module.=0D + The data structure is for VT-d driver initialization\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header=0D + /**=0D + Offset 28:=0D + VT-D Support can be verified by reading CAP ID register as expalined i= n BIOS Spec.=0D + This policy is for debug purpose only.=0D + If VT-D is not supported, all other policies in this config block will= be ignored.=0D + 0 =3D To use Vt-d;=0D + 1 =3D Avoids programming Vtd bars, Vtd overrides and DMAR table.=0D + **/=0D + UINT8 VtdDisable;=0D + UINT8 X2ApicOptOut; ///< Offset 29 :This field is used to = enable the X2APIC_OPT_OUT bit in the DMAR table. 1=3DEnable/Set and 0=3D= Disable/Clear=0D + UINT8 DmaControlGuarantee; ///< Offset 30 :This field is used to = enable the DMA_CONTROL_GUARANTEE bit in the DMAR table. 1=3DEnable/Set and = 0=3DDisable/Clear=0D + UINT8 VtdIgdEnable; ///< Offset 31 :This field is used to = enable the VtdIgdEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear= =0D + UINT8 VtdIpuEnable; ///< Offset 32 :This field is used to = enable the VtdIpuEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear= =0D + UINT8 VtdIopEnable; ///< Offset 33 :This field is used to = enable the VtdIopEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear= =0D + UINT8 VtdItbtEnable; ///< Offset 34 :This field is used to = enable the VtdItbtEnable Policy. 1=3DEnable/Set and 0=3DDisable/Clear=0D + UINT8 PreBootDmaMask; ///< Offset 35 :Convey PcdVTdPolicyPro= pertyMask value from EDK2 IntelSiliconPkg=0D + /**=0D + Offset 36:=0D + This field is used to describe the base addresses for VT-d function:\n= =0D + VTD BAR for Gfx if IGfx is supported : BaseAddress[0]=3D0xFED90000,= \n=0D + VTD BAR for IPU if IPU is supporrted : BaseAddress[1]=3D0xFED92000,\n= =0D + VTD BAR for other DMA Agents (except Igfx and IPU) : BaseAddress[2]=3D= 0xFED91000,\n=0D + VTD BAR for iTBT if iTBT is supported : BaseAddress[3]=3D0xFED84000, B= aseAddress[4]=3D0xFED85000, BaseAddress[5]=3D0xFED86000,BaseAddress[6]=3D0x= FED87000=0D + **/=0D + UINT32 BaseAddress[VTD_ENGINE_NUMBER];=0D + UINT32 DmaBufferSize; ///< Offset 64 :Protect Memory Region (= PMR) DMA buffer size=0D +=0D +=0D +} VTD_CONFIG;=0D +=0D +/**=0D + The data structure is for VT-d driver initialization in DXE\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config= Block Header=0D +} VTD_DXE_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _VTD_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/Watc= hDogConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/Wa= tchDogConfig.h new file mode 100644 index 0000000000..8766762580 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Include/ConfigBlock/Wdt/WatchDogCon= fig.h @@ -0,0 +1,31 @@ +/** @file=0D + WatchDog policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _WATCH_DOG_CONFIG_H_=0D +#define _WATCH_DOG_CONFIG_H_=0D +=0D +#define WATCH_DOG_PREMEM_CONFIG_REVISION 1=0D +extern EFI_GUID gWatchDogPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This policy clears status bits and disable watchdog, then lock the=0D + WDT registers.=0D + while WDT is designed to be disabled and locked by Policy,=0D + bios should not enable WDT by WDT PPI. In such case, bios shows the=0D + warning message but not disable and lock WDT register to make sure=0D + WDT event trigger correctly.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 DisableAndLock : 1; ///< (Test) Set 1 to clear = WDT status, then disable and lock WDT registers. 0: Disable; 1: Enab= le.=0D + UINT32 RsvdBits : 31;=0D +} PCH_WDT_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _WATCH_DOG_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec b/Silicon/Intel/Ti= gerlakeSiliconPkg/SiPkg.dec new file mode 100644 index 0000000000..0c0f2db104 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SiPkg.dec @@ -0,0 +1,1207 @@ +## @file=0D +# Component description file for the Silicon Reference Code.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +DEC_SPECIFICATION =3D 0x00010017=0D +PACKAGE_NAME =3D SiPkg=0D +PACKAGE_VERSION =3D 0.1=0D +PACKAGE_GUID =3D F245E276-44A0-46b3-AEB5-9898BBCF008D=0D +=0D +[Includes.Common.Private]=0D +=0D +#=0D +# TigerLake Fru=0D +#=0D +Fru/TglCpu/IncludePrivate=0D +Fru/TglPch/IncludePrivate=0D +=0D +##=0D +# IpBlock IncludePrivate=0D +#=0D +IpBlock/Psf/IncludePrivate=0D +IpBlock/Pmc/IncludePrivate=0D +IpBlock/Smbus/IncludePrivate=0D +IpBlock/Graphics/IncludePrivate=0D +IpBlock/CpuPcieRp/IncludePrivate=0D +IpBlock/Hda/IncludePrivate=0D +IpBlock/PchDmi/IncludePrivate=0D +IpBlock/P2sb/IncludePrivate=0D +IpBlock/Spi/IncludePrivate=0D +IpBlock/Gpio/IncludePrivate=0D +IpBlock/Cnvi/IncludePrivate=0D +IpBlock/Gbe/IncludePrivate=0D +IpBlock/PcieRp/IncludePrivate=0D +IpBlock/Vtd/IncludePrivate=0D +IpBlock/HostBridge/IncludePrivate=0D +IpBlock/SerialIo/IncludePrivate=0D +=0D +SystemAgent/IncludePrivate=0D +=0D +Pch/IncludePrivate=0D +=0D +[Includes]=0D +#=0D +# TigerLake=0D +#=0D +Fru/TglCpu/Include=0D +Fru/TglPch/Include=0D +=0D +# CPU PCIe=0D +IpBlock/CpuPcieRp/Include=0D +=0D +IpBlock/Gpio/Include=0D +=0D +=0D +##=0D +#=0D +# This section is for IP ConfigBlock versions control=0D +#=0D +# - Memory=0D +Include/ConfigBlock/Memory/Ver2=0D +#=0D +# - Graphics=0D +Include/ConfigBlock/Graphics/Gen12=0D +#=0D +# - CPU PCIe=0D +Include/ConfigBlock/CpuPcieRp/Gen4=0D +Include/ConfigBlock/CpuDmi=0D +=0D +# - Hybrid Graphics=0D +Include/ConfigBlock/HybridGraphics=0D +=0D +Include=0D +#=0D +# SystemAgent=0D +#=0D +SystemAgent/Include=0D +SystemAgent/AcpiTables=0D +SystemAgent/AcpiTables/SaSsdt=0D +Include/ConfigBlock/Vtd=0D +Include/ConfigBlock/PcieRp=0D +Include/ConfigBlock/Gna=0D +Include/ConfigBlock/CpuPcieRp/Gen4=0D +Include/ConfigBlock/CpuDmi=0D +Include/ConfigBlock/HybridGraphics=0D +Include/ConfigBlock/HostBridge=0D +#=0D +# Cpu=0D +#=0D +Cpu/Include=0D +Include/ConfigBlock/Overclocking=0D +Include/ConfigBlock/VoltageRegulator=0D +=0D +#=0D +# Pch=0D +#=0D +Pch/Include=0D +Include/ConfigBlock/Thermal=0D +Include/ConfigBlock/P2sb=0D +Include/ConfigBlock/Ish=0D +Include/ConfigBlock/Usb=0D +Include/ConfigBlock/Espi=0D +Include/ConfigBlock/Fivr=0D +Include/ConfigBlock/Rtc=0D +Include/ConfigBlock/Smbus=0D +Include/ConfigBlock/Pmc=0D +Include/ConfigBlock/Itss=0D +Include/ConfigBlock/Scs=0D +Include/ConfigBlock/Hda=0D +Include/ConfigBlock/Sata=0D +Include/ConfigBlock/Rst=0D +Include/ConfigBlock/Ieh=0D +Include/ConfigBlock/Me=0D +Include/ConfigBlock/PchDmi=0D +Include/ConfigBlock/Gpio=0D +Include/ConfigBlock/Dci=0D +Include/ConfigBlock/Cnvi=0D +Include/ConfigBlock/Gbe=0D +Include/ConfigBlock/TraceHub=0D +Include/ConfigBlock/Thc=0D +Include/ConfigBlock/Wdt=0D +Include/ConfigBlock/PcieRp/PchPcieRp=0D +Include/ConfigBlock/PcieRp=0D +Include/ConfigBlock/Psf=0D +Include/ConfigBlock/SerialIo=0D +Include/ConfigBlock/HybridStorage=0D +Include/ConfigBlock/Spi=0D +=0D +=0D +#=0D +# - Tcss=0D +Include/ConfigBlock/Tcss=0D +[Guids.common.Private]=0D +#=0D +# PCH=0D +#=0D +gPchDeviceTableHobGuid =3D { 0xb3e123d0, 0x7a1e, 0x4db4, { 0xaf, 0x6= 6, 0xbe, 0xd4, 0x1e, 0x9c, 0x66, 0x38 }}=0D +gWdtHobGuid =3D { 0x65675786, 0xacca, 0x4b11, { 0x8a, 0xb= 7, 0xf8, 0x43, 0xaa, 0x2a, 0x8b, 0xea }}=0D +gPchConfigHobGuid =3D { 0x524ed3ca, 0xb250, 0x49f5, { 0x94, 0xd= 9, 0xa2, 0xba, 0xff, 0xc7, 0x0e, 0x14 }}=0D +gGpioLibUnlockHobGuid =3D { 0xA7892E49, 0x0F9F, 0x4166, { 0xB8, 0xD= 6, 0x8A, 0x9B, 0xD9, 0x8B, 0x17, 0x38 }}=0D +gSiScheduleResetHobGuid =3D { 0xEA0597FF, 0x8858, 0x41CA, { 0xBB, 0xC= 1, 0xFE, 0x18, 0xFC, 0xD2, 0x8E, 0x22 }}=0D +gCnviConfigHobGuid =3D { 0xa8d6e4d9, 0x94b7, 0x4fc9, { 0x94, 0x3= f, 0x7a, 0x9c, 0xb2, 0x31, 0x57, 0xce }}=0D +=0D +#=0D +# CPU=0D +#=0D +gPeiAcpiCpuDataGuid =3D { 0x7682bbef, 0xb0b6, 0x4939, { 0xae, 0x6= 6, 0x1b, 0x3d, 0xf2, 0xf6, 0xaa, 0xf3 }}=0D +gCpuStatusCodeDataTypeExceptionHandlerGuid =3D { 0x3BC2BD12, 0xAD2E, 0x11D= 5, { 0x87, 0xDD, 0x00, 0x06, 0x29, 0x45, 0xC3, 0xB9 }}=0D +=0D +#=0D +# SA=0D +#=0D +gSchemaListGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xC= B, 0xEA, 0xAD, 0x0A, 0x88, 0x86, 0x1B }}=0D +gEqPhase3SchemaGuid =3D { 0x145AC084, 0x340E, 0x4777, { 0xBC, 0x7= 5, 0xF8, 0x50, 0x5F, 0xFD, 0x50, 0x9D }}=0D +gScoreSchemaGuid =3D { 0x8233A1BB, 0x58D5, 0x4F66, { 0xA1, 0x3= F, 0x8A, 0xA3, 0xED, 0x6A, 0xF5, 0xA0 }}=0D +gPortMarginGuid =3D { 0xD7154D12, 0x03B2, 0x4054, { 0x8C, 0xD= 2, 0x9F, 0x4B, 0x20, 0x90, 0xBE, 0xF7 }}=0D +gJitterTolerenceGuid =3D { 0xB52A2E04, 0x45FF, 0x484E, { 0xB5, 0xF= E, 0xEE, 0x47, 0x8F, 0x5F, 0x6C, 0x9B }}=0D +gLaneMarginGuid =3D { 0x7AC0996D, 0xA601, 0x4210, { 0x94, 0x4= E, 0x93, 0x4E, 0x51, 0x7B, 0x6C, 0x57 }}=0D +gVocMarginGuid =3D { 0x3578349A, 0x9E98, 0x4F70, { 0x91, 0xC= B, 0xE2, 0x5B, 0x98, 0x99, 0xBC, 0x16 }}=0D +=0D +[Guids]=0D +gSmbiosProcessorInfoHobGuid =3D {0xe6d73d92, 0xff56, 0x4146, {0xaf= , 0xac, 0x1c, 0x18, 0x81, 0x7d, 0x68, 0x71}}=0D +gSmbiosCacheInfoHobGuid =3D {0xd805b74e, 0x1460, 0x4755, {0xbb= , 0x36, 0x1e, 0x8c, 0x8a, 0xd6, 0x78, 0xd7}}=0D +=0D +##=0D +## IntelFrameworkPkg=0D +##=0D +# MsegSmramPei.inf=0D +gEfiSmmPeiSmramMemoryReserveGuid =3D {0x6dadf1d1, 0xd4cc, 0x4910, {0xbb= , 0x6e, 0x82, 0xb1, 0xfd, 0x80, 0xff, 0x3d}}=0D +##=0D +## MdeModulePkg=0D +##=0D +gEfiMemoryTypeInformationGuid =3D {0x4c19049f, 0x4137, 0x4dd3, {0x9c, 0x= 10, 0x8b, 0x97, 0xa8, 0x3f, 0xfd, 0xfa}}=0D +gEfiCapsuleVendorGuid =3D {0x711c703f, 0xc285, 0x4b10, {0xa3, 0xb0, 0x36= , 0xec, 0xbd, 0x3c, 0x8b, 0xe2}}=0D +gEfiConsoleOutDeviceGuid =3D { 0xd3b36f2c, 0xd551, 0x11d4, { 0x9a, 0x46, 0= x0, 0x90, 0x27, 0x3f, 0xc1, 0x4d}}=0D +##=0D +## Common=0D +##=0D +## Include/ConfigBlock/SiConfig.h=0D +gSiConfigGuid =3D {0x4ed6d282, 0x22f3, 0x4fe1, {0xa6, 0x61, 0x6, 0x1a, 0x9= 7, 0x38, 0x59, 0xd8}}=0D +##=0D +gSiPreMemConfigGuid =3D {0xb94c004c, 0xa0ab, 0x40f0, {0x9b, 0x61, 0x0b, 0x= 25, 0x88, 0xbe, 0xfd, 0xc6}}=0D +##=0D +##=0D +gPciePreMemConfigGuid =3D {0xd0f9c2a9, 0x7332, 0x4733, {0x8d, 0xb1, 0x98, = 0x79, 0x27, 0x60, 0xda, 0xe6}}=0D +##=0D +gSiPkgTokenSpaceGuid =3D {0x977c97c1, 0x47e1, 0x4b6b, {0x96, 0x69, 0x43,= 0x66, 0x99, 0xcb, 0xe4, 0x5b}}=0D +## Include/SiConfigHob.h=0D +gSiConfigHobGuid =3D {0xb3903068, 0x7482, 0x4424, {0xba, 0x4b, 0x40, 0x5f,= 0x8f, 0xd7, 0x65, 0x4e}}=0D +gBootMediaHobGuid =3D {0x8c7340ea, 0xde8b, 0x4e06, {0xa4, 0x78, 0xec, 0x8b= , 0x62, 0xd7, 0xa, 0x8b}}=0D +gEfiPramConfGuid =3D { 0xecb54cd9, 0xe5ae, 0x4fdc, { 0xa9, 0x71, 0xe8, 0x7= 7, 0x75, 0x60, 0x68, 0xf7}}=0D +##=0D +##=0D +## IPU's GUIDs=0D +##=0D +gIpuDataHobGuid =3D {0x61dd66, 0x212b, 0x4dae, {0x9b, 0xc0, 0x30, 0xe0, 0= x2e, 0x3f, 0x40, 0xfd}}=0D +gIpuConfigHobGuid =3D {0x446268e5, 0x8c30, 0x4e0a, {0x9b, 0x28, 0xa3, 0xe= 7, 0xf0, 0x4, 0x31, 0xd0}}=0D +=0D +## Include/FspErrorInfo.h=0D +gFspErrorInfoHobGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, 0xff, 0xe4, 0= x73, 0x04, 0xb4, 0x3d, 0xa6}}=0D +gStatusCodeDataTypeFspErrorGuid =3D {0x611e6a88, 0xadb7, 0x4301, {0x93, 0x= ff, 0xe4, 0x73, 0x04, 0xb4, 0x3d, 0xa6}}=0D +=0D +##=0D +##=0D +## SystemAgent=0D +##=0D +gSaOverclockingPreMemConfigGuid =3D { 0x09ecc29d, 0xdbbe, 0x49fb, { 0xa6= , 0x49, 0x4b, 0xf6, 0x40, 0xe2, 0xeb, 0xd6}}=0D +gSaAcpiTableStorageGuid =3D {0x3c0ed5e2, 0x91ea, 0x4b94, { 0x82, 0xd, 0x= 9d, 0xaf, 0x9a, 0x3b, 0xb4, 0xa2}}=0D +gSaDataHobGuid =3D {0xe07d0bda, 0xbf90, 0x46a9, { 0xb0, 0x0e, 0xb2, 0xc4= , 0x4a, 0x0e, 0xd6, 0xd0}}=0D +gPsmiDataHobGuid =3D {0xa9652bd, 0x6acd, 0x47e5, { 0x80, 0x3a, 0x9, 0x53= , 0x7b, 0xd2, 0xa8, 0x48 }}=0D +gSaConfigHobGuid =3D {0x762fa2e6, 0xea3b, 0x41c8, { 0x8c, 0x52, 0x63, 0x7= 6, 0x6d, 0x70, 0x39, 0xe0}}=0D +gCpuPcieHobGuid =3D {0x440ab2e5, 0xa3ea, 0x466f, { 0x84, 0x96, 0xdf, 0xb1= , 0x3b, 0x75, 0x29, 0x95}}=0D +gSaPegHobGuid =3D {0x5807c388, 0xfa06, 0x4683, { 0xab, 0xd3, 0x1b, 0x31= , 0xbb, 0x81, 0x2d, 0x23}}=0D +gHgAcpiTableStorageGuid =3D {0x8de8964f, 0x2939, 0x4b49, { 0xa3, 0x48, 0= xf6, 0xb2, 0xb2, 0xde, 0x4a, 0x42}}=0D +gSaSsdtAcpiTableStorageGuid =3D {0xca89914d, 0x2317, 0x452e, { 0xb2, 0x4= 5, 0x36, 0xc6, 0xfb, 0x77, 0xa9, 0xc6}}=0D +gSegSsdtAcpiTableStorageGuid =3D {0x10c3800d, 0xe225, 0x480e, { 0x85, 0x= da, 0xbe, 0xed, 0xdb, 0x88, 0xe1, 0xc6}}=0D +gHgAcpiTablePchStorageGuid =3D {0xe3164526, 0x690a, 0x4e0d, { 0xb0, 0x28= , 0xae, 0xa1, 0x6f, 0xe2, 0xbc, 0xf3}}=0D +gSaMiscPeiPreMemConfigGuid =3D {0x4a525577, 0x3469, 0x4f11, { 0x99, 0xcf= , 0xfb, 0xcd, 0x5e, 0xf1, 0x84, 0xe4}}=0D +gSaMiscPeiConfigGuid =3D {0x1def8e6, 0xe998, 0x4e27, { 0x89, 0x98, 0x9c,= 0xfa, 0xb2, 0x92, 0xbc, 0x50}}=0D +gCpuPciePeiPreMemConfigGuid =3D { 0x81baf3c9, 0xf295, 0x4572, { 0x8b, 0x= 21, 0x79, 0x3f, 0xa3, 0x1b, 0xa5, 0xdb}}=0D +gCpuDmiPreMemConfigGuid =3D { 0x30d12ad5, 0xa3c6, 0x49c7, { 0xa2, 0xfd, = 0x35, 0x5c, 0xcb, 0x61, 0xcb, 0xcf}}=0D +gVmdPeiConfigGuid =3D { 0x79b52c74, 0xb9ba, 0x4f36, {0xa2, 0x40, 0xf2, 0x4= 1, 0x0d, 0x20, 0x84, 0x8a}}=0D +gVmdInfoHobGuid =3D { 0xccd0306e, 0x7fa1, 0x4df5, {0x99, 0x99, = 0xc1, 0xf8, 0x9a, 0x1d, 0x1b, 0xa9}}=0D +gEfiVmdFeatureVariableGuid =3D { 0x61a14fe8, 0x4dab, 0x4a19, {0xb1, 0xe3, = 0x97, 0xfb, 0x23, 0xd0, 0x92, 0x12}}=0D +gPramPreMemConfigGuid =3D { 0xcf0b9b31, 0xa1a6, 0x46d9, { 0x8d, 0x14, 0x= e3, 0xac, 0x69, 0x0f, 0x52, 0x3a}}=0D +gHybridGraphicsConfigGuid =3D { 0xc7956998, 0xc065, 0x46c4, { 0x8e, 0x2f= , 0x58, 0x2b, 0x67, 0xeb, 0xbe, 0x2f}}=0D +gHybridGraphicsInfoHobGuid =3D { 0x46cbed07, 0x717a, 0x4a75, { 0x85, 0xb3= , 0xf4, 0xb6, 0xc4, 0xe2, 0x3a, 0x75}}=0D +gMemoryConfigGuid =3D { 0x26cf084c, 0xc9db, 0x41bb, { 0x92, 0xc6, 0xd1, = 0x97, 0xb8, 0xa1, 0xe4, 0xbf}}=0D +gMemoryConfigNoCrcGuid =3D { 0xc56c73d0, 0x1cdb, 0x4c0c, { 0xa9, 0x57, 0= xea, 0x62, 0xa9, 0xe6, 0xf5, 0x0c}}=0D +gGnaConfigGuid =3D { 0x53e0ef18, 0xb8a8, 0x4795, { 0xa6, 0x6d, 0xe4, 0x7= 7, 0x2c, 0xc3, 0xae, 0x82}}=0D +gVtdDxeConfigGuid =3D {0xcbbf1996, 0x4a4c, 0x4dd9, {0xab, 0xbe, 0x83, 0x= 89, 0x73, 0xd, 0x48, 0xb0}}=0D +gPcieDxeConfigGuid =3D {0x1ed2d6f1, 0xa9d2, 0x476e, {0x8e, 0x74, 0xad, 0= xd9, 0x5b, 0x5, 0x10, 0x82}}=0D +gMemoryDxeConfigGuid =3D {0xa5c7dda8, 0x686b, 0x404f, {0x86, 0x40, 0xf8,= 0x2, 0xd, 0x84, 0x4c, 0x94}}=0D +gFspReservedMemoryResourceHobTsegGuid =3D { 0xd038747c, 0xd00c, 0x4980, = { 0xb3, 0x19, 0x49, 0x01, 0x99, 0xa4, 0x7d, 0x55}}=0D +gCpuPcieRpPrememConfigGuid =3D { 0x41aef892, 0xc800, 0x4ac0, {0xa9, 0x30, = 0x84, 0xac, 0x47, 0xca, 0xca, 0x7e}}=0D +gCpuPcieRpConfigGuid =3D { 0x9749a5fb, 0x9130, 0x44f0, {0x8f, 0x61, 0xdb, = 0xff, 0x8e, 0xf2, 0xca, 0xc7}}=0D +## Include/Guid/AcpiS3Context.h=0D +gEfiAcpiVariableGuid =3D {0xaf9ffd67, 0xec10, 0x488a, {0x9d, 0xfc, 0x6c,= 0xbf, 0x5e, 0xe2, 0x2c, 0x2e}}=0D +## IntelFsp2Pkg/IntelFsp2Pkg.dec gSiMemoryS3DataGuid is the same as gFspNo= nVolatileStorageHobGuid=0D +gSiMemoryS3DataGuid =3D { 0x721acf02, 0x4d77, 0x4c2a, { 0xb3, 0xdc, = 0x27, 0x0b, 0x7b, 0xa9, 0xe4, 0xb0 } }=0D +gSiMemoryInfoDataGuid =3D { 0x9b2071d4, 0xb054, 0x4e0c, { 0x8d, 0x09, = 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 } }=0D +gSiMemoryPlatformDataGuid =3D { 0x6210d62f, 0x418d, 0x4999, { 0xa2, 0x45, = 0x22, 0x10, 0x0a, 0x5d, 0xea, 0x44 } }=0D +## Include/MrcRmtData.h=0D +gEfiMemorySchemaGuid =3D { 0xCE3F6794, 0x4883, 0x492C, { 0x8D, 0xBA, 0x2F= , 0xC0, 0x98, 0x44, 0x77, 0x10}}=0D +gMrcSchemaListHobGuid =3D { 0x3047C2AC, 0x5E8E, 0x4C55, { 0xA1, 0xCB, 0xEA= , 0xAD, 0x0A, 0x88, 0x86, 0x1B}}=0D +gRmtResultMetadataGuid =3D { 0x02CB1552, 0xD659, 0x4232, { 0xB5, 0x1F, 0xC= A, 0xB1, 0xE1, 0x1F, 0xCA, 0x87}}=0D +gRmtResultColumnsGuid =3D { 0x0E60A1EB, 0x331F, 0x42A1, { 0x9D, 0xE7, 0x4= 5, 0x3E, 0x84, 0x76, 0x11, 0x54}}=0D +gMargin2DResultMetadataGuid =3D { 0x48265582, 0x8E49, 0x4AC7, { 0xAA, 0x06= , 0xE1, 0xB9, 0xA7, 0x4C, 0x97, 0x16}}=0D +gMargin2DResultColumnsGuid =3D { 0x91A449EC, 0x8A4A, 0x4736, { 0xAD, 0x71= , 0xA3, 0xF6, 0xF6, 0xD7, 0x52, 0xD9}}=0D +gSaFspErrorTypePeiGopInit =3D { 0x8106a5cc, 0x30ba, 0x41cf, { 0xa1, 0x78, = 0x63, 0x38, 0x91, 0x11, 0xae, 0xb2}}=0D +gSaFspErrorTypePeiGopGetMode =3D { 0x348cc7fe, 0x1e9a, 0x4c7a, { 0x86, 0x2= 8, 0xae, 0x48, 0x5b, 0x42, 0x10, 0xf0}}=0D +gSaFspErrorTypeCallerId =3D { 0x98230916, 0xe632, 0x49ff, { 0x81, 0x81, 0x= 55, 0xce, 0xe5, 0x10, 0x36, 0x89}}=0D +gMrcFspErrorTypeCallerId =3D { 0x5a47c211, 0x642f, 0x4f92, { 0x9c, 0xb3, 0= x7f, 0xeb, 0x93, 0xda, 0xdd, 0xba}}=0D +gMrcFspErrorTypeMemoryInit =3D { 0x5de1c071, 0x2c9c, 0x4a53, { 0x80, 0x21,= 0x4e, 0x80, 0xd2, 0x5d, 0x44, 0xa8}}=0D +gSaPciePeiConfigGuid =3D { 0xdaa929a9, 0x5ec9, 0x486a, { 0xb0, 0xf7, 0x82,= 0x3a, 0x55, 0xc7, 0xb5, 0xb3}}=0D +gSaPciePeiPreMemConfigGuid =3D { 0xfc5e01a3, 0x69f6, 0x4e35, { 0x9f, 0xcf,= 0x6, 0x68, 0x7b, 0xab, 0x31, 0xd7}}=0D +=0D +=0D +#=0D +# Host Bridge=0D +#=0D +gHostBridgePeiPreMemConfigGuid =3D {0xbdef6805, 0x2080, 0x44ad, { 0x93, = 0x2e, 0x00, 0x04, 0xf5, 0x2c, 0xb7, 0xa1}}=0D +gHostBridgePeiConfigGuid =3D {0x3b6d998e, 0x8b6e, 0x4f53, { 0xbe, 0x41, = 0x7, 0x41, 0x95, 0x53, 0x8a, 0xaf}}=0D +gHostBridgeDataHobGuid =3D {0x3b682d57, 0xd402, 0x40a6, { 0xb1, 0x34, 0x= a0, 0xc4, 0xf6, 0x31, 0x1d, 0x9}}=0D +=0D +#=0D +# Graphics=0D +#=0D +gGraphicsPeiPreMemConfigGuid =3D {0x0319c56b, 0xc43a, 0x42f1, { 0x80, 0x= be, 0xca, 0x5b, 0xd1, 0xd5, 0xc9, 0x28}}=0D +gGraphicsPeiConfigGuid =3D {0x04249ac0, 0x0088, 0x439f, { 0xa7, 0x4e, 0x= a7, 0x04, 0x2a, 0x06, 0x2f, 0x5d}}=0D +gGraphicsDxeConfigGuid =3D {0x34d93161, 0xf78e, 0x4915, {0xad, 0xc4, 0xd= b, 0x67, 0x16, 0x42, 0x39, 0x24}}=0D +gGraphicsAcpiTableStorageGuid =3D {0xce9caa0e, 0x8248, 0x442c, { 0x9e, 0= x57, 0x50, 0xf2, 0x12, 0xe2, 0xba, 0xed}}=0D +## IpBlock/Graphics/IncludePrivate/GraphicsDataHob.h=0D +gGraphicsDataHobGuid =3D { 0x48e6e20a, 0x9110, 0x4332, { 0x8c, 0x9f, 0x5f,= 0x7c, 0xae, 0x76, 0xfc, 0xf3}}=0D +=0D +#=0D +# IPU=0D +#=0D +gIpuPreMemConfigGuid =3D { 0x830a222b, 0x3ff5, 0x432e, { 0x9d, 0xd5, 0x4= e, 0xe3, 0xfc, 0xa2, 0xaa, 0xa2}}=0D +gIpuAcpiTableStorageGuid =3D {0x9b25dba6, 0x45b3, 0x4190, { 0x99, 0x8d, = 0xaf, 0x31, 0xdc, 0x21, 0x78, 0x21}}=0D +=0D +## Include/SsaCommonConfig.h=0D +gSsaPostcodeHookGuid =3D {0xADF0A27B, 0x61A6, 0x4F18, {0x9E, 0xAC, 0x46, 0= x87, 0xE7, 0x9E, 0x6F, 0xBB}}=0D +gSsaBiosVariablesGuid =3D {0x43eeffe8, 0xa978, 0x41dc, {0x9d, 0xb6, 0x54, = 0xc4, 0x27, 0xf2, 0x7e, 0x2a}}=0D +gSsaBiosResultsGuid =3D {0x8f4e928, 0xf5f, 0x46d4, {0x84, 0x10, 0x47, 0x9f= , 0xda, 0x27, 0x9d, 0xb6}}=0D +gHobUsageDataGuid =3D {0xc764a821, 0xec41, 0x450d, { 0x9c, 0x99, 0x27, 0x2= 0, 0xfc, 0x7c, 0xe1, 0xf6 }}=0D +##=0D +## TBT=0D +##=0D +gPeiITbtConfigGuid =3D {0xd7e7e1e6, 0xcbec, 0x4f5f, {0xae, 0xd= 3, 0xfd, 0xc0, 0xa8, 0xb0, 0x7e, 0x25}}=0D +gDxeITbtConfigGuid =3D {0x196bf9e3, 0x20d7, 0x4b7b, {0x89, 0xf= 9, 0x31, 0xc2, 0x72, 0x08, 0xc9, 0xb9}}=0D +gITbtInfoHobGuid =3D {0x74a81eaa, 0x033c, 0x4783, {0xbe, 0x2= b, 0x84, 0x85, 0x74, 0xa6, 0x97, 0xb7}}=0D +=0D +##=0D +## TCSS=0D +##=0D +gTcssHobGuid =3D { 0x455702ce, 0x4adb, 0x45d9, { 0x8b, 0x27, 0xf7, 0xb0, = 0xd9, 0x79, 0x8a, 0xe0}}=0D +gTcssSsdtAcpiTableStorageGuid =3D { 0xbd53572c, 0x6486, 0x45e2, { 0x90, = 0xe, 0xb9, 0x8a, 0xc1, 0xa8, 0x25, 0x45}}=0D +gTcssPeiConfigGuid =3D { 0xfb631590, 0x79c9, 0x4f0d, { 0xa9, 0x96, 0xee, = 0xe2, 0x98, 0x66, 0xfa, 0xfd}}=0D +gTcssPeiPreMemConfigGuid =3D { 0x514ed829, 0xb2bb, 0x46be, { 0xa9, 0x78, 0= x6d, 0xc, 0x91, 0xc1, 0xeb, 0xe4}}=0D +gTcssSsidHobGuid =3D { 0x8903d47a, 0x8f82, 0x4063, { 0xa8, 0x40, 0x31, 0x= 68, 0x9c, 0x9e, 0x78, 0x20}}=0D +##=0D +## Telemetry=0D +##=0D +gTelemetryPeiConfigGuid =3D { 0x8ebf9fee, 0x7496, 0x42b4, { 0xa6, 0= xf6, 0xcf, 0x2b, 0x33, 0x99, 0x30, 0xd6}}=0D +gTelemetryPeiPreMemConfigGuid =3D { 0x422de269, 0xb2ef, 0x4829, { 0x93, 0= x36, 0x0b, 0xe4, 0x98, 0xb5, 0x53, 0xb2}}=0D +=0D +##=0D +## VTD=0D +##=0D +gVtdDataHobGuid =3D {0x1d60dce8, 0x503a, 0x44a8, { 0xb3, 0x2d, 0x56, 0xb3= , 0x88, 0xf3, 0x4c, 0x55}}=0D +gVtdConfigGuid =3D {0x03e5cf63, 0xbebb, 0x4041, { 0xb7, 0xe7, 0xbf, 0x54= , 0x61, 0x20, 0xf1, 0xc5}}=0D +=0D +#=0D +# TRACEHUB=0D +#=0D +gCpuTraceHubPreMemConfigGuid =3D { 0xf2e17477, 0x93f3, 0x430d, { 0x9e, 0x= 08, 0x3c, 0xcc, 0x6e, 0x2f, 0x6c, 0x4b}}=0D +gTraceHubDataHobGuid =3D { 0xf1187e54, 0x995f, 0x49d9, { 0xac, 0x= ee, 0xc5, 0x34, 0xf4, 0x5a, 0x18, 0xc7}}=0D +=0D +##=0D +## Cpu=0D +##=0D +gSmramCpuDataHeaderGuid =3D {0x5848fd2d, 0xd6af, 0x474b, {0x82, 0x75, 0x= 95, 0xdd, 0xe7, 0x0a, 0xe8, 0x23}}=0D +gCpuAcpiTableStorageGuid =3D {0xc38fb0e2, 0x0c43, 0x49c9, {0xb5, 0x44, 0= x9b, 0x17, 0xaa, 0x4d, 0xcb, 0xa3}}=0D +gTxtInfoHobGuid =3D {0x2986883f, 0x88e0, 0x48d0, {0x4b, 0x82, 0x20, 0xc2= , 0x69, 0x48, 0xdd, 0xac}}=0D +gHtBistHobGuid =3D {0xbe644001, 0xe7d4, 0x48b1, {0xb0, 0x96, 0x8b, 0xa0,= 0x47, 0xbc, 0x7a, 0xe7}}=0D +gProcessorProducerGuid =3D {0x1bf06aea, 0x5bec, 0x4a8d, {0x95, 0x76, 0x7= 4, 0x9b, 0x09, 0x56, 0x2d, 0x30}}=0D +gCpuInitDataHobGuid =3D {0x266e31cc, 0x13c5, 0x4807, {0xb9, 0xdc, 0x39, = 0xa6, 0xba, 0x88, 0xff, 0x1a}}=0D +gBiosGuardHobGuid =3D {0x66f0c42d, 0x0d0e, 0x4c23, {0x93, 0xc0, 0x2d, 0x= 52, 0x95, 0xdc, 0x5e, 0x21}}=0D +gCpuSecurityPreMemConfigGuid =3D {0xfd5c346, 0x8260, 0x4067, {0x94, 0x69, = 0xcf, 0x91, 0x68, 0xa3, 0x42, 0x90}}=0D +gCpuConfigLibPreMemConfigGuid =3D {0xfc1c0ec2, 0xc6b4, 0x4f05, {0xbb, 0x85= , 0xc8, 0x0, 0x8d, 0x5b, 0x4a, 0xb7}}=0D +gCpuTxtPreMemConfigGuid =3D {0x20b4db03, 0xd160, 0x4f83, {0xa4, 0x1, 0x9a,= 0x8a, 0xa8, 0x88, 0x68, 0x14}}=0D +gCpuTestConfigGuid =3D {0xd4dba957, 0xd9c, 0x4af2, {0x9d, 0x40, 0x35, 0xa8= , 0x44, 0xe4, 0x93, 0xad}}=0D +gBiosGuardConfigGuid =3D {0x762f9ddb, 0x1c89, 0x4612, {0x84, 0x6b, 0xee, 0= xdc, 0x8f, 0x62, 0x25, 0x45}}=0D +gCpuConfigGuid =3D {0x48c3aac9, 0xd66c, 0x42e4, {0x9b, 0x1d, 0x39, 0x4, 0x= 5f, 0x46, 0x53, 0x41}}=0D +gCpuPidTestConfigGuid =3D {0x2511095f, 0xd49e, 0x4537, {0xa6, 0x60, 0x88, = 0x71, 0x31, 0xd1, 0x53, 0xda}}=0D +gCpuPowerMgmtBasicConfigGuid =3D {0xa021e31d, 0x7c14, 0x47da, {0xb5, 0xec,= 0xca, 0xbb, 0x4d, 0x76, 0xed, 0xc8}}=0D +gCpuPowerMgmtCustomConfigGuid =3D {0x562fa1c8, 0x55ee, 0x4e2f, {0x91, 0xca= , 0x8d, 0x84, 0x50, 0x3, 0x2f, 0xe}}=0D +gCpuPowerMgmtPsysConfigGuid =3D {0x4e7f850, 0x19b5, 0x47ba, {0x9d, 0x28, 0= xb1, 0xe7, 0x5e, 0x1f, 0x48, 0x53}}=0D +gCpuPowerMgmtTestConfigGuid =3D {0x5161ed3d, 0x90bf, 0x436f, {0xb8, 0x33, = 0xd7, 0x17, 0x89, 0xb3, 0x48, 0xc1}}=0D +gCpuPowerMgmtVrConfigGuid =3D {0x254766c9, 0x929d, 0x4eac, {0x9e, 0xec, 0x= df, 0xa2, 0x2, 0x44, 0xb5, 0xea}}=0D +gTxtPrivateBaseHobGuid =3D {0x651EBDB4, 0x4E1D, 0x422A, {0x82, 0xFB, 0x1E,= 0xDA, 0x66, 0x71, 0x6C, 0x0B}}=0D +gTxtAcmInfoTableGuid =3D {0x7FC03AAA, 0x46A7, 0x18DB, {0x2E, 0xAC, 0x69, 0= x8F, 0x8D, 0x41, 0x7F, 0x5A}}=0D +gOverclockingPreMemConfigGuid =3D {0xad151bbc, 0xd5a0, 0x481e, {0x9d, 0x19= , 0xf6, 0x7b, 0x79, 0xe9, 0x8f, 0x68}}=0D +gCpuDataHobGuid =3D {0x1eec629f, 0xf3cf, 0x4b02, { 0xa9, 0xa5, 0x27, 0xa2,= 0x33, 0x20, 0xbe, 0x5d}}=0D +=0D +##=0D +## Me=0D +##=0D +gMePlatformReadyToBootGuid =3D {0x03fdf171, 0x1d67, 0x4ace, {0xa9, 0x04,= 0x3e, 0x36, 0xd3, 0x38, 0xfa, 0x74}}=0D +gMeSsdtAcpiTableStorageGuid =3D {0x9a8f82d5, 0x39b1, 0x48da, {0x92, 0xdc= , 0xa2, 0x2d, 0xa8, 0x83, 0x4d, 0xf6}}=0D +gMeDataHobGuid =3D {0x1e94f097, 0x5acd, 0x4089, {0xb2, 0xe3, 0xb9, 0xa5,= 0xc8, 0x79, 0xa7, 0x0c}}=0D +gMeEDebugHobGuid =3D {0x5f672ec1, 0xa8f6, 0x47d3, {0x9c, 0xd0, 0x92, 0xe9,= 0xe9, 0xe0, 0xb3, 0x84}}=0D +gPciImrHobGuid =3D {0x49b1eac3, 0x0cd6, 0x451e, {0x96, 0x30, 0x92, 0x4b,= 0xc2, 0x69, 0x35, 0x86}}=0D +gTpm2AcpiTableStorageGuid =3D {0x7d279373, 0xeecc, 0x4d4f, {0xae, 0x2f, = 0xce, 0xc4, 0xb7, 0x06, 0xb0, 0x6a}}=0D +gMeBiosPayloadHobGuid =3D {0x992c52c8, 0xbc01, 0x4ecd, {0x20, 0xbf, 0xf9= , 0x57, 0x16, 0x0e, 0x9e, 0xf7}}=0D +gEfiTouchPanelGuid =3D {0x91b1d27b, 0xe126, 0x48d1, {0x82, 0x34, 0xd2, 0= x8b, 0x81, 0xc8, 0x83, 0x62}}=0D +gMeFwHobGuid =3D {0x52885e62, 0x4c4d, 0x9546, {0x2d, 0xba, 0x2a, 0x84, 0x= 89, 0xee, 0xa8, 0xa3 }}=0D +gMePeiPreMemConfigGuid =3D {0x67ed113b, 0xd4ab, 0x43f5, {0x9c, 0x3c, 0x3= 5, 0x44, 0x15, 0xaa, 0x47, 0x5c}}=0D +gMePeiConfigGuid =3D {0x9bad5628, 0x657b, 0x48e3, {0xb1, 0x11, 0xc3, 0xb= 9, 0xeb, 0xea, 0xee, 0x17}}=0D +gMeDxeConfigGuid =3D {0xad08bacc, 0x4906, 0x4d9b, {0xbe, 0xd1, 0x81, 0xa= 5, 0x2c, 0x13, 0xdb, 0xf8}}=0D +gIvmProtocolGuid =3D {0x3C4852D6, 0xD47B, 0x4F46, {0xB0, 0x5E, 0xB5, 0xED= , 0xC1, 0xAA, 0x44, 0x0E}}=0D +gSdmProtocolGuid =3D {0xDBA4D603, 0xD7ED, 0x4931, {0x88, 0x23, 0x17, 0xAD= , 0x58, 0x57, 0x05, 0xD5}}=0D +gRtmProtocolGuid =3D {0x5565A099, 0x7FE2, 0x45C1, {0xA2, 0x2B, 0xD7, 0xE9= , 0xDF, 0xEA, 0x9A, 0x2E}}=0D +gSvmProtocolGuid =3D {0xF47ACC04, 0xD94B, 0x49CA, {0x87, 0xA6, 0x7F, 0x7D= , 0xC0, 0x3F, 0xBA, 0xF3}}=0D +gMeEopDoneHobGuid =3D {0x247323af, 0xc8f1, 0x4b8c, {0x90, 0x87, 0xaa, 0x4b= , 0xa7, 0xb7, 0x6d, 0x6a}}=0D +gMePreMemPolicyHobGuid =3D {0xe6de74a5, 0x21b, 0x4f78, {0xa3, 0xcd, 0x34, = 0xd6, 0x7e, 0xe4, 0x82, 0xbf}}=0D +gMePolicyHobGuid =3D {0x0341cf17, 0xbc8f, 0x4a20, {0xac, 0x28, 0x6c, 0x3c= , 0x32, 0x4c, 0xd4, 0x17}}=0D +gMeFspErrorTypeEop =3D {0x948585c4, 0x76a4, 0x45bb, {0xbe, 0x6c, 0x39, 0x6= 1, 0xc3, 0xab, 0xde, 0x15}}=0D +gMeFspErrorTypeCallerId =3D {0x1f4dc7e9, 0x26ca, 0x4336, { 0x8c, 0xe3, 0x3= 9, 0x31, 0x3, 0xb5, 0xf3, 0xd7}}=0D +gMeConfigSpaceGuid =3D {0xcb405fd3, 0x4404, 0x4ccd, {0x85, 0x18, 0x0d, 0x0= 3, 0x07, 0x48, 0xd0, 0xa6}}=0D +gMeDidSentHobGuid =3D {0x4c3d3af1, 0x1720, 0x4c3f, {0xab, 0x7c, 0x36, 0x50= , 0xbb, 0x5b, 0x85, 0x7e}}=0D +gMeDisabledEventHobGuid =3D {0x1500b6a7, 0xb82f, 0x456b, {0xba, 0x2b, 0x4,= 0x72, 0x41, 0x6, 0xf, 0x7}}=0D +gMeSavedPmconHobGuid =3D {0xb8baee93, 0xea15, 0x4ddc, {0x90, 0xb8, 0x44, 0= x12, 0xd2, 0xea, 0xcf, 0x4f}}=0D +=0D +##=0D +## Amt=0D +##=0D +gAmtForcePushPetPolicyGuid =3D {0xacc8e1e4, 0x9f9f, 0x4e40, {0xa5, 0x7e,= 0xf9, 0x9e, 0x52, 0xf3, 0x4c, 0xa5}}=0D +gAmtForcePushPetVariableGuid =3D {0xd7ac94af, 0xa498, 0x45ec, {0xbf, 0xa= 2, 0xa5, 0x6e, 0x95, 0x34, 0x61, 0x8b}}=0D +gMeBiosExtensionSetupGuid =3D {0xaf013532, 0xc828, 0x4fbd, {0x20, 0xae, = 0xfe, 0xe6, 0xaf, 0xbe, 0xdd, 0x4e}}=0D +gAmtPetQueueHobGuid =3D {0xca0801d3, 0xafb1, 0x4dec, {0x9b, 0x65, 0x93, = 0x65, 0xec, 0xc7, 0x93, 0x6b}}=0D +gAmtForcePushPetHobGuid =3D {0x4efa0db6, 0x26dc, 0x4bb1, {0xa7, 0x6f, 0x= 14, 0xbc, 0x63, 0x0c, 0x7b, 0x3c}}=0D +gAmtPeiConfigGuid =3D {0x7254546a, 0xace3, 0x4a32, {0x9a, 0xc2, 0xf0, 0x= cc, 0x28, 0x4e, 0x1e, 0x4d}}=0D +gAmtDxeConfigGuid =3D {0x3f12ab6b, 0xb04d, 0x4824, {0xbf, 0xb6, 0x3e, 0x= e7, 0x5d, 0x02, 0x0b, 0x84}}=0D +gAmtPolicyHobGuid =3D {0x703eb2cd, 0x5ca8, 0x4233, {0x9d, 0xa3, 0x0d, 0x2d= , 0x57, 0xe6, 0x73, 0x34}}=0D +gAmtMebxDataGuid =3D { 0x912e1538, 0x371d, 0x4ea6, { 0xa8, 0x41, 0xd7, 0x= 6a, 0x8, 0x93, 0x3a, 0x70}}=0D +=0D +##=0D +## PCH=0D +##=0D +gEfiSmbusArpMapGuid =3D {0x707be83e, 0x0bf6, 0x40a5, {0xbe, 0x64, 0x34, = 0xc0, 0x3a, 0xa0, 0xb8, 0xe2}}=0D +gIrmtAcpiTableStorageGuid =3D {0x6684d675, 0xee06, 0x49b2, {0x87, 0x6f, = 0x79, 0xc5, 0x8f, 0xdd, 0xa5, 0xb7}}=0D +gPchGlobalResetGuid =3D { 0x9db31b4c, 0xf5ef, 0x48bb, { 0x94, 0x2b, 0x18= , 0x1f, 0x7e, 0x3a, 0x3e, 0x40 }}=0D +gI2c0MasterGuid =3D {0xa121a5db, 0xb0cb, 0x46ec, {0xa0, 0xcb, 0x27, 0xf8= , 0xda, 0x72, 0xd4, 0x0e}}=0D +gI2c1MasterGuid =3D {0x55e3d0f9, 0xc954, 0x422d, {0x9c, 0x4c, 0xcc, 0x46= , 0x12, 0x7c, 0x5b, 0xa8}}=0D +gI2c2MasterGuid =3D {0x9289aa40, 0xdf32, 0x474e, {0xb0, 0x3a, 0xc7, 0x7f= , 0x76, 0xd3, 0x45, 0x21}}=0D +gI2c3MasterGuid =3D {0xd8b2c17f, 0x4117, 0x4166, {0x90, 0x17, 0x01, 0x68= , 0xb4, 0x81, 0xac, 0x18}}=0D +gI2c4MasterGuid =3D {0x513d943d, 0x15d9, 0x4bd0, {0xb1, 0x41, 0x14, 0x50= , 0x2b, 0xbf, 0xa9, 0xf2}}=0D +gI2c5MasterGuid =3D {0x50df382a, 0xb6bf, 0x4435, {0xae, 0xe6, 0x21, 0xf4= , 0x85, 0x7c, 0xa8, 0xb4}}=0D +gChipsetInitHobGuid =3D {0xc1392859, 0x1f75, 0x446e, {0xb3, 0xf5, 0x83, = 0x35, 0xfc, 0xc8, 0xd1, 0xc4}}=0D +=0D +gPchGeneralPreMemConfigGuid =3D {0xC65F62FA, 0x52B9, 0x4837, {0x86, 0xEB,= 0x1A, 0xFB, 0xD4, 0xAD, 0xBB, 0x3E}}=0D +gDciPreMemConfigGuid =3D {0xAB4AF366, 0x2250, 0x40C3, {0x92, 0xDB, 0x36= , 0x61, 0xC6, 0x71, 0x3C, 0x5A}}=0D +gWatchDogPreMemConfigGuid =3D {0xFBCE08CC, 0x60F2, 0x4BDF, {0xB7, 0x88, = 0x09, 0xBB, 0x81, 0x65, 0x52, 0x2B}}=0D +gPchTraceHubPreMemConfigGuid =3D {0x8456c11, 0xdb85, 0x4914, {0x8d, 0x1a,= 0xe5, 0xac, 0x64, 0x37, 0xe8, 0x96}}=0D +gPcieRpPreMemConfigGuid =3D {0x8377AB38, 0xF8B0, 0x476A, { 0x9C, 0xA1, 0= x68, 0xEA, 0x78, 0x57, 0xD8, 0x2A}}=0D +gSmbusPreMemConfigGuid =3D {0x77A6E62C, 0x716B, 0x4386, {0x9E, 0x9C, 0x2= 3, 0xA0, 0x2E, 0x13, 0x7B, 0x3A}}=0D +gLpcPreMemConfigGuid =3D {0xA6E6032F, 0x1E58, 0x407E, {0x9A, 0xB8, 0xC6,= 0x30, 0xC6, 0xC4, 0x11, 0x8E}}=0D +gHsioPciePreMemConfigGuid =3D {0xE8FB0C12, 0x0DA1, 0x4A20, {0xB3, 0x36, = 0xFB, 0x75, 0x93, 0x8C, 0xE0, 0x14}}=0D +gHsioSataPreMemConfigGuid =3D {0x732260D0, 0xA5C1, 0x4119, {0xAA, 0x0C, = 0x93, 0xDC, 0xAC, 0x67, 0x0A, 0x31}}=0D +=0D +gPchGeneralConfigGuid =3D {0x6ED94C8C, 0x25F7, 0x4686, {0xB2, 0x46, 0xCA= , 0x4D, 0xE2, 0x95, 0x4B, 0x5D}}=0D +gPchPcieConfigGuid =3D {0x0A53B507, 0x988B, 0x475C, {0xBF, 0x76, 0x33, 0= xDE, 0x10, 0x6D, 0x94, 0x84}}=0D +gPchPcieRpDxeConfigGuid =3D {0x475530EA, 0xBD72, 0x416F, {0x98, 0x9F,0x4= 8, 0x70, 0x5F, 0x14, 0x4E, 0xD9}}=0D +gSataConfigGuid =3D {0xF5F87B4F, 0xCC3C, 0x408D, {0x89, 0xE3, 0x61, 0xC5= , 0x9C, 0x54, 0x07, 0xC4}}=0D +gRstConfigGuid =3D {0x43B6F112, 0x3851, 0x4DDC, {0x81, 0xB9, 0xE4, 0x5A, 0= x2B, 0xE, 0xB3, 0x25}}=0D +gIoApicConfigGuid =3D {0x2873D0F1, 0x00F6, 0x40AB, {0xAC, 0x36, 0x9A, 0x= 68, 0xBA, 0x87, 0x3E, 0x6C}}=0D +gPchDmiConfigGuid =3D {0xB3A61210, 0x1CD3, 0x4797, {0x8E, 0xE6, 0xD3, 0x= 42, 0x9C, 0x4F, 0x17, 0xBD}}=0D +gFlashProtectionConfigGuid =3D {0xD0F71512, 0x9E32, 0x4CC9, {0xA5, 0xA3,= 0xAD, 0x67, 0x9A, 0x06, 0x67, 0xB8}}=0D +gHdAudioPreMemConfigGuid =3D {0xD38F1E2B, 0x21B3, 0x43D1, {0x9F, 0xA8, 0= xA5, 0xE1, 0x78, 0x73, 0x1E, 0x88}}=0D +gHdAudioConfigGuid =3D {0x7EB3CE7E, 0x82E0, 0x4CD7, {0xBD, 0xE5, 0xB2, 0= xBF, 0x4E, 0x91, 0xC3, 0x4C}}=0D +gHdAudioDxeConfigGuid =3D {0x22EFC2DE, 0x66EB, 0x412D, {0x97, 0x17, 0xE7= , 0x7A, 0xA1, 0x4E, 0x87, 0x76}}=0D +gInterruptConfigGuid =3D {0x09A2B815, 0xBE29, 0x45EF, {0xBF, 0xBF, 0x58,= 0xEA, 0xAC, 0x5E, 0x29, 0x78}}=0D +gIshPreMemConfigGuid =3D {0x7C24E649, 0xC1F0, 0x4CF9, {0x87, 0x96, 0xE7,= 0xA0, 0xEE, 0x34, 0x43, 0xF8}}=0D +gIshConfigGuid =3D {0x433AE2AA, 0xC5A6, 0x46ED, {0x94, 0x19, 0x1E, 0x5D,= 0xB8, 0x1C, 0x57, 0x40}}=0D +gGbeConfigGuid =3D {0x4B2DE99E, 0x7517, 0x4D04, {0x8C, 0x02, 0xF1, 0x1A,= 0x59, 0x2B, 0x14, 0x2F}}=0D +gTsnConfigGuid =3D {0x9E9A93CB, 0x0F4E, 0x4E56, {0x90, 0x2D, 0x6C, 0x76,= 0xDE, 0x90, 0xF7, 0x71}}=0D +gLockDownConfigGuid =3D {0x8A838E0A, 0xA639, 0x46F0, {0xA9, 0xCE, 0x70, = 0xC4, 0x85, 0xFB, 0xA8, 0x0D}}=0D +gP2sbConfigGuid =3D {0x2474DCB8, 0x4BB4, 0x49DA, {0x87, 0x83, 0x7C, 0xD3= , 0xD3, 0x85, 0xFF, 0x07}}=0D +gPmConfigGuid =3D {0x93826157, 0xDC85, 0x4E34, {0xAE, 0xD9, 0x6E, 0xA1, = 0x0D, 0xF9, 0xE3, 0xA7}}=0D +gScsConfigGuid =3D {0xF4DE6D52, 0xB5C9, 0x48C0, {0xA0, 0x4A, 0x68, 0x54,= 0x20, 0x94, 0x05, 0xD0}}=0D +gScsInfoHobGuid =3D {0x94C5E85B, 0xAA6D, 0x481D, {0x8B, 0xBD, 0x54, 0xAA, = 0xE2, 0x99, 0x78, 0xB2}}=0D +gSdCardConfigGuid =3D {0xD6A3038E, 0x50AE, 0x44B0, {0x93, 0xE2, 0xF7, 0x93= , 0xF5, 0x90, 0x50, 0x27}}=0D +gEmmcConfigGuid =3D {0xE0C6FB5D, 0x5696, 0x47F3, {0x84, 0xE8, 0xCC, 0x6C, = 0x68, 0xA4, 0xB2, 0x1D}}=0D +gUfsConfigGuid =3D {0x3AF25C55, 0x76B4, 0x4367, {0x85, 0xEF, 0x9D, 0x51, 0= x2F, 0x2F, 0x8F, 0xA7}}=0D +gEmmcDxeConfigGuid =3D {0x59440AA6, 0xEB45, 0x4E36, {0xBC, 0x90, 0xBE, 0xF= 9, 0x0C, 0xB0, 0xC8, 0x18}}=0D +gSerialIoConfigGuid =3D {0x6CC06EBF, 0x0D34, 0x4340, {0xBC, 0x16, 0xDA, = 0x09, 0xE5, 0x78, 0x3A, 0xDB}}=0D +gSerialIrqConfigGuid =3D {0x251701E7, 0xE266, 0x4623, {0x99, 0x68, 0x73,= 0x8C, 0xD2, 0x23, 0x10, 0x96}}=0D +gSpiConfigGuid =3D {0x150360EF, 0x99BE, 0x4E43, {0x94, 0xBB, 0xBD, 0x40,= 0x26, 0xCA, 0x34, 0x57}}=0D +gEspiConfigGuid =3D {0x60FBF3B8, 0x96D4, 0x4187, {0x84, 0x9E, 0xAA, 0xF7= , 0x5C, 0x4B, 0xE1, 0xE3}}=0D +gThermalConfigGuid =3D {0x4416506D, 0x1197, 0x4722, {0xA5, 0xB4, 0x46, 0= x11, 0xF9, 0x23, 0x9E, 0xAE}}=0D +gUsbConfigGuid =3D {0xB2DA9CCD, 0x6A8C, 0x4BB6, {0xB3, 0xE6, 0xCD, 0xFB,= 0xB7, 0x66, 0x8B, 0xDE}}=0D +gUsb2PhyConfigGuid =3D {0x576C1134, 0x2E0C, 0xCB7D, {0xCD, 0x3F, 0xAC, 0= x68, 0x2D, 0xAE, 0xD3, 0xF2}}=0D +gUsb3HsioConfigGuid =3D {0xF8AFC238, 0xF176, 0x12CE, {0xBE, 0xF4, 0x69, = 0xF9, 0xB1, 0xAC, 0x40, 0xD5}}=0D +gPchPcieStorageDetectHobGuid =3D {0xC682F3F4, 0x2F46, 0x495E, {0x98, 0xAA,= 0x43, 0x14, 0x4B, 0xA5, 0xA4, 0x85}}=0D +gCnviConfigGuid =3D {0xE53EBEF7, 0x103D, 0x4A70, {0x9B, 0x6A, 0x73, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}}=0D +gHsioConfigGuid =3D {0xE53EBEE7, 0x103D, 0x4A71, {0x9B, 0x6A, 0x74, 0xEE, = 0x5F, 0x4C, 0x8D, 0xF5}}=0D +gPchRstHobGuid =3D {0x4ECA680C, 0x660D, 0x48F8, {0xAA, 0xD8, 0x94, 0xD6, = 0x56, 0x10, 0xF9, 0x86}}=0D +gPchInfoHobGuid =3D {0x99FD5E18, 0xE262, 0x4E6A, {0x82, 0x66, 0x77, 0xD0= , 0x36, 0x5F, 0xD6, 0x3E}}=0D +gGpioDxeConfigGuid =3D {0x06985984, 0xAFA3, 0x429C, {0x80, 0xCD, 0x69, 0= x43, 0xF3, 0x38, 0x31, 0x4D}}=0D +gFivrConfigGuid =3D {0x68EE8BD4, 0x05F2, 0x4656, {0xAE, 0xE4, 0xAD, 0x10= , 0xC7, 0x22, 0xC3, 0x4F}}=0D +gThcConfigGuid =3D {0x1B318AD1, 0xAA0D, 0x4764, {0x99, 0xFD, 0xBB, 0x2B,= 0xF4, 0x7F, 0x7E, 0xD6}}=0D +gIehConfigGuid =3D {0x42C4D7F3, 0x981D, 0x4475, {0xA2, 0xAE, 0xAD, 0xCD,= 0xD5, 0xCE, 0x87, 0x1E}}=0D +gRtcConfigGuid =3D {0x0E9259B8, 0x3DDE, 0x40C7, {0xAA, 0x5F, 0x94, 0x82,= 0x9A, 0x86, 0x8F, 0xAF}}=0D +gCnviConfigGuid =3D {0xa660970e, 0x511b, 0x46bb, {0xa7, 0xb8, 0xec, 0xdd,= 0xf5, 0xe2, 0x2d, 0x73}}=0D +gGpioCheckConflictHobGuid =3D {0x5603f872, 0xefac, 0x40ae, {0xb9, 0x7e, 0x= 13, 0xb2, 0xf8, 0x07, 0x80, 0x21}}=0D +gPsfConfigGuid =3D {0x49B12CF6, 0x0A56, 0x4B9F, {0xA8, 0x4C, 0xF5, 0x7D,= 0x21, 0x23, 0x8C, 0x77}}=0D +gHybridStorageConfigGuid =3D {0x265CE069, 0xD8CF, 0x48BE, {0xAE, 0x12, 0x0= 2, 0x4C, 0x25, 0x12, 0xFA, 0xF8}}=0D +gHybridStorageHobGuid =3D {0xFF91F620, 0x069E, 0x4191, {0x83, 0x73, 0x11, = 0x60, 0x9F, 0x24, 0x90, 0xEB}}=0D +gAdrConfigGuid =3D {0x5B36A07C, 0x3BBF, 0x4D53, {0x8A, 0x2D, 0xE1, 0xCF, 0= x97, 0x39, 0x0C, 0x65}}=0D +gSpiConfigGuid =3D {0xD61A6A07, 0xAD25, 0xBFC2, {0x8C, 0x60, 0xD0, 0xD1, 0= xF4, 0x13, 0x14, 0xBC}}=0D +=0D +##=0D +## Fusa=0D +##=0D +gFusaConfigGuid =3D {0xF9225896, 0xA9C8, 0x4543, {0xBA, 0x9E, 0x53, 0x32,= 0xD7, 0xBF, 0x8C, 0x2B}}=0D +gSiFusaInfoGuid =3D {0xcc7876ba, 0xee7b, 0x4bd4, {0x99, 0x4b, 0x7e, 0xc9, = 0x74, 0xc9, 0xd8, 0x43}}=0D +=0D +##=0D +## SecurityPkg=0D +##=0D +## GUID used to "Tcg2PhysicalPresence" variable and "Tcg2PhysicalPresenceF= lags" variable for TPM2 request and response.=0D +# Include/Guid/Tcg2PhysicalPresenceData.h=0D +gEfiTcg2PhysicalPresenceGuid =3D { 0xaeb9c5c1, 0x94f1, 0x4d02, { = 0xbf, 0xd9, 0x46, 0x2, 0xdb, 0x2d, 0x3c, 0x54 }}=0D +gEfiTrEEPhysicalPresenceGuid =3D {0xf24643c2, 0xc622, 0x494e, {0= x8a, 0x0d, 0x46, 0x32, 0x57, 0x9c, 0x2d, 0x5b}}=0D +gTcoWdtHobGuid =3D { 0x3e405418, 0x0d8c, 0x4f1a, { = 0xb0, 0x55, 0xbe, 0xf9, 0x08, 0x41, 0x46, 0x8d }}=0D +=0D +##=0D +## UEFI Variable Support (Direct SPI and UFS)=0D +##=0D +gCseVariableStoragePpiInstanceGuid =3D { 0x9513730d, 0x06ce, 0x4cf= 6, { 0x9d, 0x95, 0xb0, 0x76, 0x31, 0xbc, 0xd5, 0xa9}}=0D +gFvbVariableStoragePpiInstanceGuid =3D { 0x5067b88a, 0xaa37, 0x414= d, { 0xa3, 0xca, 0xc8, 0x37, 0xfc, 0xec, 0xd6, 0xf3}}=0D +gCseVariableStorageProtocolInstanceGuid =3D { 0x5d5ede0b, 0x5d93, 0x4aa= e, { 0xa8, 0xec, 0x08, 0x41, 0xd0, 0x53, 0x85, 0xc4}}=0D +gFvbVariableStorageProtocolInstanceGuid =3D { 0xe98252e8, 0xf209, 0x4ef= 5, { 0xab, 0x7e, 0x12, 0x69, 0x45, 0x14, 0x47, 0xbe}}=0D +gPeiVariableCacheHobGuid =3D { 0x35212b29, 0x128a, 0x475= 4, { 0xb9, 0x96, 0x62, 0x45, 0xcc, 0xa8, 0xa0, 0x66}}=0D +gCseVariableStorageSecurePreMemoryDataGuid =3D { 0xa1749e1e, 0x8ce1, 0x431= 0, { 0xbd, 0x3f, 0x64, 0xc9, 0x01, 0xc6, 0x13, 0xc2}}=0D +gCseVariableStorageGeneralDataAreaGuid =3D { 0x6d7a6128, 0x685b, 0x4f7= 5, { 0x87, 0x87, 0xba, 0x93, 0x08, 0x60, 0x75, 0x0c}}=0D +gCseVariableStorageFileSystemGuid =3D { 0xdb798aca, 0x3533, 0x41c= 7, { 0x9a, 0x98, 0x00, 0x31, 0x1b, 0x66, 0x0a, 0x15}}=0D +gBugCheckVariableGuid =3D { 0xba57e015, 0x65b3, 0x4c3= c, { 0xb2, 0x74, 0x65, 0x91, 0x92, 0xf6, 0x99, 0xe3}}=0D +=0D +##=0D +## PreMem Performance=0D +##=0D +gPerfPchPrePolicyGuid =3D {0x3112356F, 0xCC77, 0x4E82, {0x86, 0xD5, 0x= 3E, 0x25, 0xEE, 0x81, 0x92, 0xA4}}=0D +gPerfSiValidateGuid =3D {0x681F96E6, 0xF9CF, 0x464D, {0x97, 0x9A, 0x= B1, 0x11, 0x33, 0xDE, 0x37, 0xA9}}=0D +gPerfPchValidateGuid =3D {0xD0FF37D6, 0xA569, 0x4058, {0xB3, 0xDA, 0x= 29, 0x0B, 0x38, 0xC5, 0x32, 0x25}}=0D +gPerfAmtValidateGuid =3D {0x9E949422, 0x4A7A, 0x4E41, {0xB0, 0xAB, 0x= 3C, 0x0D, 0x88, 0x0A, 0x00, 0xFF}}=0D +gPerfCpuValidateGuid =3D {0xB760CFCC, 0xDEEF, 0x4C7E, {0x99, 0x5B, 0x= ED, 0xFE, 0xF2, 0x23, 0xB2, 0x09}}=0D +gPerfMeValidateGuid =3D {0x8CF7A498, 0x588D, 0x4D39, {0xBD, 0xAC, 0x= 51, 0x0C, 0x31, 0xAF, 0x45, 0xD0}}=0D +gPerfSaValidateGuid =3D {0xA73B382B, 0x62D4, 0x4A19, {0xBB, 0xF9, 0x= 09, 0x3E, 0xC5, 0xA5, 0x93, 0x11}}=0D +gPerfHeciPreMemGuid =3D {0xD815D922, 0x4994, 0x40B3, {0x97, 0xCC, 0x= 07, 0xF3, 0x7D, 0x42, 0xE7, 0x97}}=0D +gPerfPchPreMemGuid =3D {0xBB73E2B1, 0xB9FD, 0x4A80, {0xB8, 0x1A, 0x= 52, 0x39, 0xE9, 0x4D, 0x06, 0x2E}}=0D +gPerfCpuPreMemGuid =3D {0xAC5FCBC6, 0x084D, 0x445D, {0xB3, 0xF3, 0x= CA, 0x16, 0xDE, 0xE9, 0xBB, 0x47}}=0D +gPerfMePreMemGuid =3D {0x6051338E, 0x0FFA, 0x40F7, {0xAF, 0xEF, 0x= AB, 0x86, 0x7A, 0x38, 0xCC, 0xF3}}=0D +gPerfAmtPreMemGuid =3D {0xDB732D50, 0x9BB8, 0x489A, {0xA1, 0xD1, 0x= DD, 0xD2, 0x16, 0x1D, 0x72, 0xB8}}=0D +gPerfAmtPostMemGuid =3D {0x0329D610, 0x4269, 0xD28F, {0x61, 0xBF, 0x= B9, 0xA2, 0xD9, 0xFA, 0x96, 0x93}}=0D +gPerfSaPreMemGuid =3D {0x76F18BDA, 0x2195, 0x4FB6, {0x9A, 0x94, 0x= 0E, 0x0B, 0xAC, 0xDE, 0xEC, 0xAB}}=0D +gPerfEvlGuid =3D {0x8221518B, 0xAC19, 0x4E32, {0xAB, 0x5F, 0x= 00, 0x47, 0x0A, 0x50, 0x69, 0x40}}=0D +gPerfMemGuid =3D {0x2B57B316, 0x5CF7, 0x4847, {0xB0, 0x76, 0x= 6B, 0x5D, 0x23, 0xC3, 0xAA, 0x3E}}=0D +=0D +##=0D +## PostMem Performance=0D +##=0D +gPerfPchPostMemGuid =3D {0x70B67A99, 0x5556, 0x4315, {0xB3, 0x05, 0x= D5, 0xDC, 0x4A, 0x35, 0x63, 0x70}}=0D +gPerfSaPostMemGuid =3D {0x9FF0CE92, 0x883F, 0x43DC, {0x8A, 0x07, 0x= E0, 0xCB, 0x6D, 0x56, 0x7D, 0xE0}}=0D +gPerfS3CpuInitPostMemGuid =3D {0x976262C2, 0xD202, 0x4D12, {0x82, 0xAD, 0x= F4, 0xA9, 0x8F, 0x9B, 0x96, 0x01}}=0D +gPerfSaSecLockPostMemGuid =3D {0x272AC110, 0x0B60, 0x4D07, {0xA5, 0x58, 0x= 6D, 0x73, 0xE2, 0x43, 0x85, 0x95}}=0D +gPerfCpuStrapPostMemGuid =3D {0x8EF4372B, 0x68F0, 0x4957, {0xBC, 0x4D, 0x= 7E, 0x5C, 0xFE, 0xDA, 0xB6, 0x3E}}=0D +gPerfMpPostMemGuid =3D {0xA59BAC5B, 0xC6A4, 0x4AEB, {0x84, 0x32, 0x= 7A, 0x8B, 0x6B, 0x68, 0x5F, 0x37}}=0D +gPerfCpuPostMemGuid =3D {0xE2FE5ED3, 0x1417, 0x451A, {0x95, 0xC9, 0x= D0, 0xB2, 0xB9, 0x7B, 0xE0, 0x54}}=0D +gPerfSaResetPostMemGuid =3D {0xBE152BEE, 0xFD19, 0x4274, {0xA8, 0xBA, 0x= FB, 0x31, 0x42, 0xB5, 0xB5, 0xC3}}=0D +gPerfCpuPowerMgmtGuid =3D {0x9ED307D6, 0x4AEB, 0x44A9, {0x9B, 0x11, 0x= D8, 0x21, 0x84, 0x9A, 0xCB, 0xF7}}=0D +gPerfMePostMemGuid =3D {0x2CC8626D, 0x3387, 0x4817, {0xAB, 0xF6, 0x= 86, 0x9A, 0xF5, 0xF0, 0x51, 0xAA}}=0D +gPerfHdaPostMemGuid =3D {0xB31883B7, 0x5A05, 0x4040, {0x40, 0x80, 0x= 66, 0x8D, 0x29, 0x13, 0xD7, 0x84}}=0D +=0D +##=0D +## Dp-In Guid=0D +##=0D +## Include/DpInDataHob.h=0D +gDpInHobGuid =3D {0x3e110a83, 0xb94b, 0x4648, {0xa2, 0x26, 0x50, 0x9b, 0xd= 5, 0x55, 0xe3, 0x6b}}=0D +## Include/ConfigBlock/Tcss/DpInPreMemConfig.h=0D +gDpInPreMemConfigGuid =3D {0x80c14ba, 0xcc84, 0x4746, {0xbf, 0x6b, 0xd1, 0= xf1, 0x8e, 0xaa, 0xe8, 0x35}}=0D +=0D +[Protocols.common.Private]=0D +##=0D +## SA=0D +##=0D +gSaIotrapSmiProtocolGuid =3D { 0x1861e089, 0xcaa3, 0x473e, { 0x84, 0x32= , 0xdc, 0x1f, 0x94, 0xc6, 0xc1, 0xa6 }}=0D +gCpuPcieIoTrapProtocolGuid =3D { 0xda904080, 0x33ab, 0x48ca, { 0x97, 0x5b= , 0x5f, 0x2f, 0x23, 0x8a, 0x41, 0xb4 }}=0D +=0D +gPchPcieIoTrapProtocolGuid =3D { 0xd66a1cf, 0x79ad, 0x494b, { 0x97, = 0x8b, 0xb2, 0x59, 0x81, 0x68, 0x93, 0x34 }}=0D +=0D +[Protocols]=0D +##=0D +## MdeModulePkg=0D +##=0D +gEfiSmmVariableProtocolGuid =3D {0xed32d533, 0x99e6, 0x4209, {0x9c, 0xc0= , 0x2d, 0x72, 0xcd, 0xd9, 0x98, 0xa7}}=0D +gEdkiiPlatformSpecificResetFilterProtocolGuid =3D { 0x695d7835, 0x8d47, 0= x4c11, { 0xab, 0x22, 0xfa, 0x8a, 0xcc, 0xe7, 0xae, 0x7a } }=0D +gEdkiiPlatformSpecificResetHandlerProtocolGuid =3D { 0x2df6ba0b, 0x7092, 0= x440d, { 0xbd, 0x4, 0xfb, 0x9, 0x1e, 0xc3, 0xf3, 0xc1 } }=0D +=0D +##=0D +## SystemAgent=0D +##=0D +gBdatAccessGuid =3D {0x9477482c, 0x8717, 0x4725, {0x98, 0= x28, 0x7b, 0xd8, 0xc9, 0xa3, 0x75, 0x6a}}=0D +gIgdOpRegionProtocolGuid =3D {0x9e67aecf, 0x4fbb, 0x4c84, {0x99, 0= xa5, 0x10, 0x73, 0x40, 0x7, 0x6d, 0xb4}}=0D +gMemInfoProtocolGuid =3D {0xd4d2f201, 0x50e8, 0x4d45, {0x8e, 0= x5, 0xfd, 0x49, 0xa8, 0x2a, 0x15, 0x69}}=0D +gSaPolicyProtocolGuid =3D {0xc6aa1f27, 0x5597, 0x4802, {0x9f, 0= x63, 0xd6, 0x28, 0x36, 0x59, 0x86, 0x35}}=0D +gSaNvsAreaProtocolGuid =3D {0x149a10a5, 0x9d06, 0x4c6b, {0xbe, 0= x44, 0x08, 0x92, 0xce, 0x20, 0x61, 0xac}}=0D +gGopPolicyProtocolGuid =3D {0xec2e931b, 0x3281, 0x48a5, {0x81, 0= x07, 0xdf, 0x8a, 0x8b, 0xed, 0x3c, 0x5d}}=0D +gGen12PolicyProtocolGuid =3D {0x40f60ea0, 0x6c96, 0x4ed3, {0x96, 0= xe5, 0xba, 0x6f, 0x6d, 0x66, 0x28, 0x9f}}=0D +gGen9PolicyProtocolGuid =3D {0xeaaed1ba, 0xf15c, 0x4112, {0xb5, 0= x82, 0x90, 0x63, 0xac, 0xa0, 0x7f, 0x06}}=0D +gGopComponentName2ProtocolGuid =3D {0x651b7ebd, 0xce13, 0x41d0, {0x82, 0= xe5, 0xa0, 0x63, 0xab, 0xbe, 0x9b, 0xb6}}=0D +gGopOverrideProtocolGuid =3D {0x4a89a16e, 0x67b8, 0x4429, {0x8c, 0= x47, 0x43, 0x67, 0x90, 0xf2, 0xf2, 0x69}}=0D +gMemoryAddressEncodeDecodeProtocolGuid =3D {0x603df7ca, 0x1ba8, 0x4c12, {0= xa9, 0x8a, 0x49, 0x6d, 0xfe, 0x77, 0xeb, 0xdf}}=0D +=0D +##=0D +## TBT=0D +##=0D +gITbtPolicyProtocolGuid =3D {0xb0563c42, 0x28ea, 0x40e6, {0x99, 0x8= 4, 0xd5, 0xbf, 0xf8, 0xb0, 0x40, 0x56}}=0D +gITbtNvsAreaProtocolGuid =3D {0xdabf85bd, 0xfbdc, 0x4ed2, {0xb1, 0x0= d, 0xc9, 0x08, 0xd0, 0x8c, 0xee, 0xe8}}=0D +gDisableITbtBmeProtocolGuid =3D {0x89a9adc3, 0x9b7c, 0x4b53, {0x82, = 0xbf, 0x78, 0x72, 0x6b, 0x91, 0x4f, 0x9f}}=0D +=0D +##=0D +## Cpu=0D +##=0D +gCpuInfoProtocolGuid =3D {0xe223cf65, 0xf6ce, 0x4122, {0xb3, 0xaf, 0x4b,= 0xd1, 0x8a, 0xff, 0x40, 0xa1}}=0D +gSmmBiosGuardProtocolGuid =3D {0x17565311, 0x4b71, 0x4340, {0x88, 0xaa, = 0xdc, 0x9f, 0x44, 0x22, 0xe5, 0x3a}}=0D +gCpuNvsAreaProtocolGuid =3D {0xb9cf3f43, 0xbe3e, 0x4e45, {0xa0, 0xbe, 0x= 1a, 0x4, 0x89, 0xdf, 0x1a, 0xc9}}=0D +gDxeCpuPolicyProtocolGuid =3D {0x8282b977, 0x22f9, 0x4134, {0x99, 0x43, = 0x7b, 0xcc, 0x5f, 0x40, 0x33, 0x52}}=0D +gBiosGuardNvsAreaProtocolGuid =3D {0x5df588da, 0x991e, 0x4a7f, {0x80, 0x= 51, 0x70, 0xc7, 0x12, 0xb7, 0xba, 0xb0}}=0D +gSmmResourceConfigProtocolGuid =3D {0xA37FC2D2, 0x822D, 0x4A63, {0x9C, 0x4= 2, 0xBE, 0xB1, 0xD6, 0xEE, 0x85, 0x39}}=0D +=0D +##=0D +## Me=0D +##=0D +gActiveManagementProtocolGuid =3D {0xd25dc167, 0xeb6a, 0x432d, {0x65, = 0x91, 0xbf, 0x80, 0x29, 0xb0, 0x05, 0xbb}}=0D +gAlertStandardFormatProtocolGuid =3D {0x45de9920, 0xcd54, 0x446a, {0xa0, = 0x3c, 0x22, 0xe6, 0xfb, 0xb4, 0x51, 0xe4}}=0D +gHeciProtocolGuid =3D {0x3c7bc880, 0x41f8, 0x4869, {0xae, = 0xfc, 0x87, 0x0a, 0x3e, 0xd2, 0x82, 0x99}}=0D +gHeciFlowProtocolGuid =3D {0x1498d127, 0x123c, 0x4e52, {0x84, = 0x00, 0xcc, 0x3c, 0x9f, 0x79, 0xc4, 0x0e}}=0D +gMebxProtocolGuid =3D {0x01ab1829, 0xcecd, 0x4cfa, {0xa1, = 0x8c, 0xea, 0x75, 0xd6, 0x6f, 0x3e, 0x74}}=0D +gDxeMePolicyGuid =3D {0xa0b5dc52, 0x4f34, 0x3990, {0xd4, = 0x91, 0x10, 0x8b, 0xe8, 0xba, 0x75, 0x42}}=0D +gMeInfoProtocolGuid =3D {0x7523c8e4, 0x4fbe, 0x9661, {0x29, = 0x96, 0x14, 0x97, 0xff, 0x36, 0x2f, 0x3b}}=0D +gPlatformMeHookProtocolGuid =3D {0xbc52476e, 0xf67e, 0x4301, {0xb2, = 0x62, 0x36, 0x9c, 0x48, 0x78, 0xaa, 0xc2}}=0D +gMeNvsAreaProtocolGuid =3D {0x3bffecfd, 0xd75f, 0x4975, {0xb8, = 0x88, 0x39, 0x02, 0xbd, 0x69, 0x00, 0x2b}}=0D +gJhiProtocolGuid =3D {0xccba3051, 0xa574, 0x4f9d, {0x96, = 0xf4, 0xec, 0x0d, 0x4a, 0x87, 0xbc, 0x5a}}=0D +gIntegratedTouchHidProtocolGuid =3D {0x3d0479c1, 0x6b19, 0x4191, {0xb8, = 0x09, 0x60, 0x08, 0xdd, 0x07, 0x97, 0x55}}=0D +gIntegratedTouchProtocolGuid =3D {0x2b12e46f, 0x3c24, 0x47ff, {0x8b, = 0x89, 0xc0, 0x60, 0x2c, 0x1c, 0x61, 0x42}}=0D +gMeEopDoneProtocolGuid =3D {0x8d9b3387, 0x73db, 0x456f, {0x88, = 0x9d, 0x6f, 0xfe, 0x90, 0x82, 0x64, 0x09}}=0D +gMeSendEopInFspProtocolGuid =3D {0xcecdba92, 0x76c6, 0x4063, {0xaa, = 0x6b, 0x19, 0xfc, 0x60, 0x5c, 0x70, 0xff}}=0D +=0D +gHeciAccessProtocolGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0= xe2, 0xed, 0x8f, 0x7b, 0x43, 0x23, 0x9d}}=0D +gHeciTransportProtocolGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0= x58, 0xa8, 0xd9, 0x04, 0x01, 0xcd, 0x78}}=0D +gHeciControlProtocolGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0= x55, 0x02, 0x0a, 0x64, 0x1b, 0xe3, 0x4f}}=0D +gHeciAccessSmmProtocolGuid =3D {0x5da6182c, 0xf679, 0x49eb, {0x96, 0= xf5, 0xe6, 0x24, 0x9b, 0x54, 0x0b, 0x96}}=0D +gHeciTransportSmmProtocolGuid =3D {0xf5f7b292, 0xbb38, 0x4e59, {0xa1, 0= x6e, 0x0f, 0x27, 0x15, 0xd4, 0xb7, 0xf4}}=0D +gHeciControlSmmProtocolGuid =3D {0x7e1e508d, 0x7def, 0x4d69, {0xa9, 0= xb3, 0xa5, 0x23, 0xe8, 0x48, 0xc6, 0x98}}=0D +=0D +##=0D +## Amt=0D +##=0D +gAmtSaveMebxProtocolGuid =3D {0x86682c04, 0xea42, 0x49e5, {0x96, = 0x81, 0xe3, 0x32, 0xaa, 0xb0, 0x9e, 0xd7}}=0D +gDxeAmtPolicyGuid =3D {0x6725e645, 0x4a7f, 0x9969, {0x82, = 0xec, 0xd1, 0x87, 0x21, 0xde, 0x5a, 0x57}}=0D +gAmtReadyToBootProtocolGuid =3D {0xcc9d5c0b, 0x9010, 0x45f1, {0x99, = 0x3c, 0x83, 0x27, 0x67, 0xf1, 0x67, 0x77}}=0D +gMeSmbiosTablesUpdateProtocolGuid =3D {0x5054ee06, 0x4ce0, 0x4acc, {0x9a, = 0x80, 0xdf, 0x73, 0xbf, 0xa5, 0x38, 0xdd}}=0D +gOneClickRecoveryProtocolGuid =3D {0x93598eac, 0xc62b, 0x4dbb, {0x96, = 0x76, 0xe0, 0x5e, 0x8c, 0xc3, 0x84, 0x44}}=0D +=0D +##=0D +## PCH=0D +##=0D +gThcProtocolGuid =3D {0x00860921, 0x7B9B, 0x4EA8, {0xAD, 0x23, 0x3C, 0xCA= , 0x33, 0x9E, 0x7D, 0xFE}}=0D +gPchSpiProtocolGuid =3D {0xc7d289, 0x1347, 0x4de0, {0xbf, 0x42, 0xe, 0x2= 6, 0x9d, 0xe, 0xf3, 0x4a}}=0D +gWdtProtocolGuid =3D {0xb42b8d12, 0x2acb, 0x499a, {0xa9, 0x20, 0xdd, 0x5= b, 0xe6, 0xcf, 0x09, 0xb1}}=0D +gPchSerialIoUartDebugInfoProtocolGuid =3D {0x2fd2b1bd, 0x0387, 0x4ec6, {= 0x94, 0x1f, 0xf1, 0x4b, 0x7f, 0x1c, 0x94, 0xb6}}=0D +gEfiSmmSmbusProtocolGuid =3D {0x72e40094, 0x2ee1, 0x497a, {0x8f, 0x33, 0= x4c, 0x93, 0x4a, 0x9e, 0x9c, 0x0c}}=0D +gPchSmmSpiProtocolGuid =3D {0x56521f06, 0xa62, 0x4822, {0x99, 0x63, 0xdf= , 0x1, 0x9d, 0x72, 0xc7, 0xe1}}=0D +gPchSmmIoTrapControlGuid =3D {0x514d2afd, 0x2096, 0x4283, {0x9d, 0xa6, 0= x70, 0x0c, 0xd2, 0x7d, 0xc7, 0xa5}}=0D +gPchTcoSmiDispatchProtocolGuid =3D {0x9e71d609, 0x6d24, 0x47fd, {0xb5, 0= x72, 0x61, 0x40, 0xf8, 0xd9, 0xc2, 0xa4}}=0D +gPchPcieSmiDispatchProtocolGuid =3D {0x3e7d2b56, 0x3f47, 0x42aa, {0x8f, = 0x6b, 0x22, 0xf5, 0x19, 0x81, 0x8d, 0xab}}=0D +gPchAcpiSmiDispatchProtocolGuid =3D {0xd52bb262, 0xf022, 0x49ec, {0x86, = 0xd2, 0x7a, 0x29, 0x3a, 0x7a, 0x05, 0x4b}}=0D +gPchSmiDispatchProtocolGuid =3D {0xE6A81BBF, 0x873D, 0x47FD, {0xB6, 0xBE= , 0x61, 0xB3, 0xE5, 0x72, 0x09, 0x93}}=0D +gPchNvsAreaProtocolGuid =3D {0x2e058b2b, 0xedc1, 0x4431, {0x87, 0xd9, 0x= c6, 0xc4, 0xea, 0x10, 0x2b, 0xe3}}=0D +gPchEspiSmiDispatchProtocolGuid =3D {0xB3C14FF3, 0xBAE8, 0x456C, {0x86, = 0x31, 0x27, 0xFE, 0x0C, 0xEB, 0x34, 0x0C}}=0D +gPchSmmPeriodicTimerControlGuid =3D {0x6906E93B, 0x603B, 0x4A0F, {0x86, = 0x92, 0x83, 0x20, 0x04, 0xAA, 0xF2, 0xDB}}=0D +gIoTrapExDispatchProtocolGuid =3D {0x5B48E913, 0x707B, 0x4F9D, {0xAF, 0x= 2E, 0xEE, 0x03, 0x5B, 0xCE, 0x39, 0x5D}}=0D +gPchPolicyProtocolGuid =3D {0x543d5c93, 0x6a28, 0x4513, {0x85, = 0x9a, 0x82, 0xa7, 0xb9, 0x12, 0xcb, 0xbe}}=0D +gScsEmmcSoftwareTuningProtocolGuid =3D {0x972215b2, 0x9616, 0x4de4, {0xa9,= 0x75, 0xb0, 0x74, 0x3e, 0xe1, 0x78, 0x54}}=0D +=0D +##=0D +## Hsti=0D +##=0D +## HstiSiliconDxe Driver Entry Point=0D +gHstiProtocolGuid =3D { 0x1b05de41, 0xc93b, 0x4bb4, { 0xad, 0x47, 0x2a, 0x= 78, 0xac, 0xf, 0xc9, 0xe4 }}=0D +## Handler to gather and publish HSTI results on ReadyToBootEvent=0D +gHstiPublishCompleteProtocolGuid =3D {0x0f500be6, 0xece4, 0x4ed8, { 0x90,= 0x81, 0x9a, 0xa9, 0xa5, 0x23, 0xfb, 0x7b}}=0D +gEfiAdapterInformationProtocolGuid =3D { 0xE5DD1403, 0xD622, 0xC24E, {0x84= , 0x88, 0xC7, 0x1B, 0x17, 0xF5, 0xE8, 0x02 }}=0D +=0D +##=0D +## Silicon Policy=0D +##=0D +## Include/Protocol/SiPolicyProtocol.h=0D +gDxeSiPolicyProtocolGuid =3D { 0xeca27516, 0x306c, 0x4e28, { 0x8c, 0x94, 0= x4e, 0x52, 0x10, 0x96, 0x69, 0x5e }}=0D +=0D +##=0D +## DGR=0D +##=0D +gEfiSpaLogOutputProtocolGuid =3D { 0x1d10d46b, 0x0306, 0x454a, { 0x90, 0x8= c, 0x93, 0x65, 0xb3, 0x8a, 0x90, 0x26 }}=0D +=0D +[Ppis.common.Private]=0D +gPchHsioChipsetInitSusTblDataPpiGuid =3D { 0x97ed4e5d, 0x01a5, 0x4a3c, { 0= xb7, 0xe9, 0x1a, 0x4e, 0xa3, 0xdd, 0x23, 0xce }}=0D +gHybridStorageCfgPpiGuid =3D {0x8557e481, 0xc00e, 0x4929, {0xb4, 0x53, 0xf= 6, 0xc2, 0x53, 0x79, 0xb0, 0x13}}=0D +=0D +[Ppis]=0D +##=0D +## MdeModulePkg=0D +##=0D +gPeiCapsulePpiGuid =3D {0x3acf33ee, 0xd892, 0x40f4, {0xa2, 0xfc, 0x38, 0= x54, 0xd2, 0xe1, 0x32, 0x3d}}=0D +gPeiSmmControlPpiGuid =3D {0x61c68702, 0x4d7e, 0x4f43, {0x8d, 0xef, 0xa7= , 0x43, 0x05, 0xce, 0x74, 0xc5}}=0D +gEdkiiPlatformSpecificResetFilterPpiGuid =3D { 0x8c9f4de3, 0x7b90, 0x47ef,= { 0x93, 0x8, 0x28, 0x7c, 0xec, 0xd6, 0x6d, 0xe8 } }=0D +gEdkiiPlatformSpecificResetNotificationPpiGuid =3D { 0xe09f355d, 0xdae8, 0= x4910, { 0xb1, 0x4a, 0x92, 0x78, 0xf, 0xdc, 0xf7, 0xcb } }=0D +gEdkiiPlatformSpecificResetHandlerPpiGuid =3D { 0x75cf14ae, 0x3441, 0x49dc= , { 0xaa, 0x10, 0xbb, 0x35, 0xa7, 0xba, 0x8b, 0xab } }=0D +=0D +##=0D +## SecurityPkg=0D +##=0D +gPeiTpmInitializedPpiGuid =3D {0xe9db0d58, 0xd48d, 0x47f6, {0x9c, 0x6e, = 0x6f, 0x40, 0xe8, 0x6c, 0x7b, 0x41}}=0D +gPeiTpmInitializationDonePpiGuid =3D {0xa030d115, 0x54dd, 0x447b, { 0x90, = 0x64, 0xf2, 0x6, 0x88, 0x3d, 0x7c, 0xcc}}=0D +##=0D +## Common=0D +##=0D +## Include/Ppi/SiPolicy.h=0D +gSiPolicyPpiGuid =3D {0xaebffa01, 0x7edc, 0x49ff, {0x8d, 0x88, 0xcb, 0x8= 4, 0x8c, 0x5e, 0x86, 0x70}}=0D +## Include/Ppi/SiPolicy.h=0D +gSiPreMemPolicyPpiGuid =3D {0xc133fe57, 0x17c7, 0x4b09, {0x8b, 0x3c, 0x97,= 0xc1, 0x89, 0xd0, 0xab, 0x8d}}=0D +gFspApiModePpiGuid =3D {0xa1eeab87, 0xc859, 0x479d, {0x89, 0xb5, = 0x14, 0x61, 0xf4, 0x06, 0x1a, 0x3e}}=0D +## Silicon Initialization PPI is used to export End of Silicon init.=0D +gEndOfSiInitPpiGuid =3D {0xE2E3D5D1, 0x8356, 0x4F96, {0x9C, 0x9E, = 0x2E, 0xC3, 0x48, 0x1D, 0xEA, 0x88}}=0D +gEfiEndOfPeiSignal2PpiGuid =3D {0x22918381, 0xd018, 0x4d7c, {0x9d, 0x62, = 0xf5, 0xa5, 0x70, 0x1c, 0x66, 0x80}}=0D +gFspTempRamExitPpiGuid =3D {0xbc1cfbdb, 0x7e50, 0x42be, {0xb4, 0x87, = 0x22, 0xe0, 0xa9, 0x0c, 0xb0, 0x52}}=0D +gFspmArchConfigPpiGuid =3D {0x824d5a3a, 0xaf92, 0x4c0c, {0x9f, 0x19, = 0x19, 0x52, 0x6d, 0xca, 0x4a, 0xbb}}=0D +gSiPreMemDefaultPolicyInitPpiGuid =3D {0xfec36242, 0xf8d8, 0x4b43, {0x87,= 0x94, 0x4f, 0x1f, 0x9f, 0x63, 0x8d, 0xdc}}=0D +gSiPreMemPolicyReadyPpiGuid =3D {0x85270bef, 0x6984, 0x4375, {0xa6, 0xea, = 0xb5, 0xaa, 0x90, 0x6e, 0xdd, 0x4a}}=0D +gSiDefaultPolicyInitPpiGuid =3D {0xf69abf86, 0x4048, 0x44ef, { 0xa8, 0xef,= 0x6c, 0x7f, 0x20, 0x4a, 0xc8, 0xda}}=0D +gSiPolicyReadyPpiGuid =3D {0xd570de8c, 0xb9c4, 0x4ffa, {0xad, 0xee, = 0xa5, 0x82, 0x7c, 0xe3, 0x17, 0x79}}=0D +=0D +##=0D +## UEFI Variable Support (Override Until BP1.5)=0D +##=0D +gEdkiiVariableStoragePpiGuid =3D { 0x90d915c5, 0xe4c1, 0x4da8, {0xa7, 0x= 6f, 0x9, 0xe5, 0x78, 0x91, 0x65, 0x48}}=0D +gEdkiiVariableStorageSelectorPpiGuid =3D { 0x782546d1, 0x03ab, 0x41e4, {= 0xa0, 0x1d, 0x7a, 0x9b, 0x22, 0xba, 0x2e, 0x1e}}=0D +gReadOnlyVariablePreMemoryDescriptorPpiGuid =3D { 0xbe136fc9, 0xc277, 0x= 4dd1, {0xbe, 0x42, 0xce, 0xf0, 0x9f, 0xf4, 0x3f, 0x55}}=0D +gEfiReadyToInstallEndOfPei2PpiGuid =3D {0xeef72924, 0x2db2, 0x4569, { 0x86= , 0x3f, 0xd4, 0x86, 0xae, 0x7a, 0xe4, 0x12}}=0D +=0D +##=0D +## SystemAgent=0D +##=0D +gSsaBiosCallBacksPpiGuid =3D {0x99b56126, 0xe16c, 0x4d9b, {0xbb, 0x71, 0= xaa, 0x35, 0x46, 0x1a, 0x70, 0x2f}}=0D +gSsaBiosServicesPpiGuid =3D {0x55750d10, 0x6d3d, 0x4bf5, {0x89, 0xd8, 0= xe3, 0x5e, 0xf0, 0xb0, 0x90, 0xf4}}=0D +gEnablePeiGraphicsPpiGuid =3D {0x8e3bb474, 0x545, 0x4902, {0x86, 0xb0, 0= x6c, 0xb5, 0xe2, 0x64, 0xb4, 0xa5}}=0D +gPeiGraphicsFramebufferReadyPpiGuid =3D {0x590ad868, 0xb0b1, 0x4d20, {0x91= , 0xff, 0xc2, 0xa9, 0xd6, 0x88, 0x81, 0x94}}=0D +gMrcMemoryInitDonePpiGuid =3D {0x0ff07255, 0x67c2, 0x456d, {0x9a, 0x95, 0= xc9, 0x16, 0x2c, 0x23, 0x86, 0x8d}}=0D +## X Compatibility support PPI=0D +gCompatibleMemoryInitPpiGuid =3D {0xca311f82, 0xf490, 0x4b12, {0x9e, 0xe1,= 0x2b, 0x66, 0xa3, 0x6c, 0x3e, 0xa}}=0D +gVmdInitDonePpiGuid =3D {0x42a187c8, 0xca0a, 0x4750, {0x82, 0xfd,= 0xc9, 0xa0, 0xd5, 0x9, 0xfe, 0xd1}}=0D +=0D +##=0D +## TwoLm=0D +##=0D +gMrcMemoryInitDonePpiGuid =3D { 0x598907f5, 0xd5fc, 0x435c, { 0x8a, 0x7f,= 0x53, 0xc5, 0xa4, 0xb5, 0x31, 0xc4}}=0D +=0D +##=0D +## Nvdimm Cache Info=0D +##=0D +gNvdimmCachePpiGuid =3D { 0x1bbc5601, 0xe571, 0x4ae0, { 0xbc, 0x38, 0xb8,= 0x65, 0x0d, 0x50, 0x6f, 0x5b}}=0D +=0D +##=0D +## Cpu=0D +##=0D +gPeiCachePpiGuid =3D {0x09be4bc2, 0x790e, 0x4dea, {0x8b, 0xdc, 0x38, 0x0= 5, 0x16, 0x98, 0x39, 0x44}}=0D +gPeiTxtMemoryUnlockedPpiGuid =3D {0x38cdd10b, 0x767d, 0x4f6e, {0xa7, 0x4= 4, 0x67, 0xee, 0x1d, 0xfe, 0x2f, 0xa5}}=0D +gPeiTxtReadyToRunMemoryInitPpiGuid =3D {0x9ecafd30, 0x29e2, 0x42f6, {0xba,= 0xf3, 0x8b, 0x7d, 0xb8, 0xfe, 0x1f, 0x22}}=0D +gPeiReadyToInstallMpPpiGuid =3D { 0x1a266768, 0xfd43, 0x4e18, { 0xa8, 0x8a= , 0x35, 0xc7, 0x94, 0xc3, 0x91, 0x0e }}=0D +##=0D +## Me=0D +##=0D +gHeciPpiGuid =3D {0xd14319e2, 0x407a, 0x9580, {0x8d, 0xe5, 0x51, 0xa8, 0= xff, 0xc6, 0xd7, 0xd7}}=0D +gMbpSensitivePpiGuid =3D {0xed7c9ce9, 0x5912, 0x4807, {0xec, 0x90, 0x22,= 0x18, 0xbc, 0x7b, 0xfc, 0x6c}}=0D +gHeci3IntegratedTouchControllerGuid =3D {0x3e8d0870, 0x271a, 0x4208, {0x= 8e, 0xb5, 0x9a, 0xcb, 0x94, 0x02, 0xae, 0x04}}=0D +gSiNvmOwnershipAcquiredPpiGuid =3D {0xe5db3d8c, 0xefa4, 0x4308, {0x9a, 0xa= b, 0x6b, 0x97, 0x81, 0x09, 0x98, 0xa0}}=0D +gHeciAccessPpiGuid =3D {0x3a5aab32, 0xd5a7, 0x4ce8, {0x88, 0xe2, 0xed, 0x8= f, 0x7b, 0x43, 0x23, 0x9d}}=0D +gHeciTransportPpiGuid =3D {0x9fc932b9, 0x8851, 0x43f7, {0x8a, 0x58, 0xa8, = 0xd9, 0x04, 0x01, 0xcd, 0x78}}=0D +gHeciControlPpiGuid =3D {0xd86381d8, 0xff7e, 0x462e, {0x9b, 0x55, 0x02, 0= x0a, 0x64, 0x1b, 0xe3, 0x4f}}=0D +gMeBeforeDidSentPpiGuid =3D {0xd497b143, 0xf3ef, 0x4192, {0xa8, 0xc5, 0x5e= , 0xf6, 0xcd, 0x6e, 0x4c, 0x87}}=0D +=0D +##=0D +## PCH=0D +##=0D +gWdtPpiGuid =3D {0xf38d1338, 0xaf7a, 0x4fb6, {0x91, 0xdb, 0x1a, 0x9c, 0x= 21, 0x83, 0x57, 0x0d}}=0D +gPchSpiPpiGuid =3D {0xdade7ce3, 0x6971, 0x4b75, {0x82, 0x5e, 0xe, 0xe0, = 0xeb, 0x17, 0x72, 0x2d}}=0D +gPeiSmbusPolicyPpiGuid =3D {0x63b6e435, 0x32bc, 0x49c6, {0x81, 0xbd, 0xb= 7, 0xa1, 0xa0, 0xfe, 0x1a, 0x6c}}=0D +=0D +##=0D +## TCSS=0D +##=0D +gTcssPeiInitDonePpiGuid =3D {0x5ad291b8, 0xace4, 0x416a, {0xb7, 0x50, 0x7,= 0x63, 0x59, 0xfc, 0xc1, 0x5b}}=0D +=0D +[LibraryClasses]=0D +## @libraryclass=0D +## Common=0D +##=0D +MmPciLib|Include/Library/MmPciLib.h=0D +=0D +## @libraryclass=0D +## SampleCode=0D +##=0D +## CPU=0D +##=0D +CpuPolicyLib|Cpu/Include/Library/CpuPolicyLib.h=0D +=0D +## @libraryclass=0D +## Me=0D +##=0D +=0D +MeChipsetLib|Me/Include/Library/MeChipsetLib.h=0D +=0D +PeiMePolicyLib|Me/Include/Library/PeiMePolicyLib.h=0D +PttHciLib|Me/Include/Library/PttHciLib.h=0D +PttHeciLib|Me/Include/Library/PttHeciLib.h=0D +## @libraryclass=0D +## Pch=0D +##=0D +GpioLib|Include/Library/GpioLib.h=0D +GpioLib|Include/Library/GpioNativeLib.h=0D +PchCycleDecodingLib|Pch/Include/Library/PchCycleDecodingLib.h=0D +EspiLib|Include/Library/PchEspiLib.h=0D +GbeLib|Include/Library/GbeLib.h=0D +GbeMdiLib|IpBlock/Gbe/IncludePrivate/Library/GbeMdiLib.h=0D +PchHsioLib|Pch/IncludePrivate/PchHsio.h=0D +PchInfoLib|Pch/Include/Library/PchInfoLib.h=0D +PchP2sbLib|Pch/Include/Library/PchP2sbLib.h=0D +PchPcieRpLib|Pch/Include/Library/PchPcieRpLib.h=0D +PchPcrLib|Pch/Include/Library/PchPcrLib.h=0D +PchPolicyLib|Pch/Include/Library/PchPolicyLib.h=0D +PchSbiAccessLib|Pch/IncludePrivate/Library/PchSbiAccessLib.h=0D +SerialIoAccessLib|Include/Library/SerialIoAccessLib.h=0D +DxePchPolicyLib|Pch/Include/Library/DxePchPolicyLib.h=0D +=0D +## @libraryclass=0D +## Sa=0D +##=0D +DxeSaPolicyLib|SystemAgent/Include/Library/DxeSaPolicyLib.h=0D +SaPlatformLib|SystemAgent/Include/Library/SaPlatformLib.h=0D +Include/Library/VoltageRegulatorCommands.h=0D +=0D +[PcdsFixedAtBuild]=0D +## From MdeModulePkg.dec=0D +## Progress Code for S3 Suspend start.=0D +## PROGRESS_CODE_S3_SUSPEND_START =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OE= M_SPECIFIC | 0x00000000)) =3D 0x03078000=0D +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendStart|0x03078000|UINT32|0x300= 01032=0D +## Progress Code for S3 Suspend end.=0D +## PROGRESS_CODE_S3_SUSPEND_END =3D (EFI_SOFTWARE_SMM_DRIVER | (EFI_OEM_= SPECIFIC | 0x00000001)) =3D 0x03078001=0D +gSiPkgTokenSpaceGuid.PcdProgressCodeS3SuspendEnd|0x03078001|UINT32|0x30001= 033=0D +##=0D +## PcdNemCodeCacheBase is usally the same as PEI FV Base address,=0D +## FLASH_BASE+FLASH_REGION_FV_RECOVERY_OFFSET from PlatformPkg.fdf.=0D +##=0D +## Restriction:=0D +## 1) PcdNemCodeCacheBase - (PcdTemporaryRamBase + PcdTemporaryRamSize) >= =3D 4K=0D +## 2) PcdTemporaryRamBase >=3D 4G - 64M=0D +##=0D +gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase|0xFFF80000|UINT32|0x20000009=0D +##=0D +## NemCodeCacheSize is usally the same as PEI FV Size,=0D +## FLASH_REGION_FV_RECOVERY_SIZE from PlatformPkg.fdf.=0D +##=0D +## Restriction:=0D +## 1) PcdNemTotalCacheSize =3D NemCodeCacheSize + PcdTemporaryRamSize=0D +## <=3D Maximun CPU NEM total size (Code + Data)=0D +## =3D LLC size - 0.5M=0D +## 2) PcdTemporaryRamSize <=3D Maximum CPU NEM data size=0D +## =3D MLC size=0D +## NOTE: The size restriction may be changed in next generation processor.= =0D +## Please refer to Processor BWG for detail.=0D +##=0D +gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress|0xFF800000|UINT32|0x10000001=0D +gSiPkgTokenSpaceGuid.PcdBiosSize|0x00800000|UINT32|0x10000002=0D +gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xfef00000|UINT32|0x00010028=0D +gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x2000|UINT32|0x00010029=0D +gSiPkgTokenSpaceGuid.PcdTopMemoryCacheSize|0x0|UINT32|0x0001002A=0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|0xFFE60000|UINT32|0x30000004= =0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize|0x000A0000|UINT32|0x30000005= =0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset|0x00000060|UINT32|0x30000013= =0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|0x00660000|UINT32|0x3000000= 6=0D +##=0D +## The CPU Trace Hub's BARs base and size=0D +##=0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarBase|0xfad00000|UINT32|0x30000007= =0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubMtbBarSize|0x100000|UINT32|0x30000008=0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarBase|0xfc000000|UINT32|0x30000009= =0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubSwBarSize|0x800000|UINT32|0x3000000A=0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarBase|0xfacfc000|UINT32|0x3000000= B=0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubRtitBarSize|0x4000|UINT32|0x3000000C=0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarBase|0xfae00000|UINT32|0x3000000D= =0D +gSiPkgTokenSpaceGuid.PcdCpuTraceHubFwBarSize|0x200000|UINT32|0x3000000E=0D +=0D +gSiPkgTokenSpaceGuid.PcdFspWrapperEnable |FALSE|BOOLEAN|0x3000000F=0D +gSiPkgTokenSpaceGuid.PcdFspBinaryEnable|FALSE|BOOLEAN|0x30000010=0D +gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0|UINT8|0x30000012=0D +=0D +##=0D +## PcdEfiGcdAllocateType is using for EFI_GCD_ALLOCATE_TYPE selection=0D +## value of the struct=0D +## 0x00 EfiGcdAllocateAnySearchBottomUp=0D +## 0x01 EfiGcdAllocateMaxAddressSearchBottomUp=0D +## 0x03 EfiGcdAllocateAnySearchTopDown=0D +## 0x04 EfiGcdAllocateMaxAddressSearchTopDown=0D +##=0D +## below value should not using in this situation=0D +## 0x05 EfiGcdMaxAllocateType : design for max value of struct=0D +## 0x02 EfiGcdAllocateAddress : design for speccification address allocat= e=0D +##=0D +gSiPkgTokenSpaceGuid.PcdEfiGcdAllocateType|0x01|UINT8|0x40000000=0D +=0D +##=0D +## Handshake register value driven to DMA controller PCIE venodr specific= configuration register from FW=0D +## (LC/CM to host)=0D +##=0D +gSiPkgTokenSpaceGuid.PcdITbtToPcieRegister|0xEC|UINT8|0x40000003=0D +##=0D +## Handshake register value driven from DMA controller PCIE venodr specif= ic configuration register to FW=0D +## (HOST to LC/CM)=0D +##=0D +gSiPkgTokenSpaceGuid.PcdPcieToITbtRegister|0xF0|UINT8|0x40000004=0D +=0D +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioBase|0x0000004000000000|UINT64|0x40000= 005=0D +gSiPkgTokenSpaceGuid.PcdAbove4GBMmioSize|0x0000004000000000|UINT64|0x40000= 006=0D +=0D +gSiPkgTokenSpaceGuid.PcdSmmEntryPointBinFile|{ 0x52, 0xce, 0xc8, 0xe0, 0x5= 1, 0x2b, 0xc2, 0x4c, 0xb3, 0xc7, 0xd2, 0x11, 0xa6, 0x25, 0xc1, 0xba }|VOID*= |0x40000007=0D +gSiPkgTokenSpaceGuid.PcdSpsBinFile|{ 0xEE, 0xE3, 0x34, 0x71, 0xA6, 0x7F, 0= x89, 0x44, 0x87, 0xA7, 0xAE, 0x38, 0x98, 0x4E, 0xAE, 0xD8 }|VOID*|0x4000000= 8=0D +gSiPkgTokenSpaceGuid.PcdSpsSmmEntryPointBinFile|{ 0x5B, 0x63, 0x7D, 0x7C, = 0x9C, 0x8B, 0x3C, 0x46, 0x9F, 0x7F, 0x91, 0xF6, 0x09, 0x06, 0x84, 0x8F }|VO= ID*|0x40000009=0D +gSiPkgTokenSpaceGuid.PcdSpaBinFile|{ 0xE1, 0x19, 0xB7, 0x7B, 0x2A, 0x53, 0= x40, 0x7B, 0xA3, 0x4C, 0xC4, 0xF9, 0xE2, 0x6C, 0x27, 0x74 }|VOID*|0x4000000= A=0D +gSiPkgTokenSpaceGuid.PcdSpaSmmEntryPointBinFile|{ 0xD7, 0xAD, 0xB2, 0x9F, = 0x4D, 0x53, 0x4B, 0xA6, 0x8D, 0x55, 0x5D, 0x28, 0x91, 0x60, 0x10, 0x19 }|VO= ID*|0x4000000B=0D +=0D +##=0D +## - DpIn Silicon Feature=0D +##=0D +# Note: PcdDpInEnable is Default Disable. Override it based on Platform/ = CPU=0D +gSiPkgTokenSpaceGuid.PcdDpInEnable|FALSE|BOOLEAN|0x4000000C=0D +# Note: For PcdMaxDpInExtPortSupported, we can have Maximum value of 0x08= .=0D +# Please Don't exceed beyond that. As it will cause boundary overflow.= =0D +# Currently hadrware wise maximum Dp-In External Port supported is 4.=0D +# And it will never exceed the value of 0x08. That's why we don't suppo= rt=0D +# PcdMaxDpInExtPortSupported value more than 0x08=0D +gSiPkgTokenSpaceGuid.PcdMaxDpInExtPortSupported|0x4|UINT8|0x4000000D=0D +=0D +gSiPkgTokenSpaceGuid.VtdEngine1BaseAddeess|0xFED90000|UINT32|0x50000001=0D +gSiPkgTokenSpaceGuid.VtdEngine2BaseAddeess|0xFED92000|UINT32|0x50000002=0D +gSiPkgTokenSpaceGuid.VtdEngine3BaseAddeess|0xFED91000|UINT32|0x50000003=0D +gSiPkgTokenSpaceGuid.VtdEngine4BaseAddeess|0xFED84000|UINT32|0x50000004=0D +gSiPkgTokenSpaceGuid.VtdEngine5BaseAddeess|0xFED85000|UINT32|0x50000005=0D +gSiPkgTokenSpaceGuid.VtdEngine6BaseAddeess|0xFED86000|UINT32|0x50000006=0D +gSiPkgTokenSpaceGuid.VtdEngine7BaseAddeess|0xFED87000|UINT32|0x50000007=0D +##=0D +## Those PCDs are used to control build process.=0D +##=0D +gSiPkgTokenSpaceGuid.PcdTraceHubEnable |FALSE|BOOLEAN|0xF000= 0001=0D +gSiPkgTokenSpaceGuid.PcdSmmVariableEnable |FALSE|BOOLEAN|0xF000= 0002=0D +gSiPkgTokenSpaceGuid.PcdAtaEnable |FALSE|BOOLEAN|0xF000= 0004=0D +gSiPkgTokenSpaceGuid.PcdAcpiEnable |TRUE |BOOLEAN|0xF000= 0009=0D +gSiPkgTokenSpaceGuid.PcdSourceDebugEnable |FALSE|BOOLEAN|0xF000= 000B=0D +gSiPkgTokenSpaceGuid.PcdPpmEnable |TRUE |BOOLEAN|0xF000= 000C=0D +gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable |FALSE|BOOLEAN|0xF000= 000F=0D +gSiPkgTokenSpaceGuid.PcdPttEnable |FALSE|BOOLEAN|0xF000= 0011=0D +gSiPkgTokenSpaceGuid.PcdJhiEnable |FALSE|BOOLEAN|0xF000= 0012=0D +gSiPkgTokenSpaceGuid.PcdSoftwareGuardEnable |FALSE|BOOLEAN|0xF000= 0013=0D +gSiPkgTokenSpaceGuid.PcdSmbiosEnable |TRUE |BOOLEAN|0xF000= 0014=0D +gSiPkgTokenSpaceGuid.PcdS3Enable |TRUE |BOOLEAN|0xF000= 0015=0D +gSiPkgTokenSpaceGuid.PcdOverclockEnable |FALSE|BOOLEAN|0xF000= 0016=0D +gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable |FALSE|BOOLEAN|0xF000= 0017=0D +gSiPkgTokenSpaceGuid.PcdSsaFlagEnable |FALSE|BOOLEAN|0xF000= 0018=0D +gSiPkgTokenSpaceGuid.PcdEvLoaderEnable |FALSE|BOOLEAN|0xF000= 0019=0D +gSiPkgTokenSpaceGuid.PcdIgdEnable |TRUE |BOOLEAN|0xF000= 001A=0D +gSiPkgTokenSpaceGuid.PcdPegEnable |TRUE |BOOLEAN|0xF000= 001B=0D +gSiPkgTokenSpaceGuid.PcdSaDmiEnable |TRUE |BOOLEAN|0xF000= 001C=0D +gSiPkgTokenSpaceGuid.PcdGnaEnable |FALSE |BOOLEAN|0xF00= 0001E=0D +gSiPkgTokenSpaceGuid.PcdVtdEnable |TRUE |BOOLEAN|0xF000= 0020=0D +gSiPkgTokenSpaceGuid.PcdBiosGuardEnable |FALSE|BOOLEAN|0xF000= 0021=0D +gSiPkgTokenSpaceGuid.PcdSimicsEnable |FALSE|BOOLEAN|0xF000= 0022=0D +gSiPkgTokenSpaceGuid.PcdBdatEnable |FALSE|BOOLEAN|0xF000= 0023=0D +gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable |TRUE |BOOLEAN|0xF000= 0024=0D +gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable |TRUE |BOOLEAN|0xF000= 0025=0D +gSiPkgTokenSpaceGuid.PcdOcWdtEnable |FALSE|BOOLEAN|0xF000= 0029=0D +gSiPkgTokenSpaceGuid.PcdMinTreeEnable |FALSE|BOOLEAN|0xF000= 002A # To separate modules used in mininal source tree and advanced featur= es=0D +gSiPkgTokenSpaceGuid.PcdBootGuardEnable |FALSE|BOOLEAN|0xF000= 0030=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable |FALSE|BOOLEAN|0xF000= 0033=0D +gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable |FALSE|BOOLEAN|0xF000= 0037=0D +gSiPkgTokenSpaceGuid.PcdBfxEnable |FALSE|BOOLEAN|0xF000= 003A=0D +gSiPkgTokenSpaceGuid.PcdThcEnable |FALSE|BOOLEAN|0xF000= 003B=0D +=0D +gSiPkgTokenSpaceGuid.PcdPpamEnable |FALSE|BOOLEAN|0xF000= 003F=0D +gSiPkgTokenSpaceGuid.PcdPsmiEnable |FALSE|BOOLEAN|0xF000= 0042=0D +gSiPkgTokenSpaceGuid.PcdCpuPcieEnable |TRUE |BOOLEAN|0xF000= 0043=0D +gSiPkgTokenSpaceGuid.PcdHybridStorageSupport |FALSE|BOOLEAN|0xF000= 0044=0D +gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported |TRUE |BOOLEAN|0xF000= 0045=0D +gSiPkgTokenSpaceGuid.PcdTmeLibSupported |FALSE|BOOLEAN|0xF000= 0046=0D +gSiPkgTokenSpaceGuid.PcdAdlLpSupport |FALSE|BOOLEAN|0xF000= 0047=0D +gSiPkgTokenSpaceGuid.PcdSpsStateSaveEnable |FALSE|BOOLEAN|0xF000= 0048=0D +gSiPkgTokenSpaceGuid.PcdSpaEnable |FALSE|BOOLEAN|0xF000= 0049=0D +=0D +## PCD for TraceHub=0D +[PcdsDynamic, PcdsPatchableInModule]=0D +## From MdeModulePkg.dec=0D +## Default OEM ID for ACPI table creation, its length must be 0x6 bytes to= follow ACPI specification.=0D +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemId|"INTEL "|VOID*|0x30001034=0D +## Default OEM Table ID for ACPI table creation, it is "EDK2 ".=0D +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemTableId|0x20202020324B4445|UINT64|0x= 30001035=0D +## Default OEM Revision for ACPI table creation.=0D +gSiPkgTokenSpaceGuid.PcdAcpiDefaultOemRevision|0x00000002|UINT32|0x3000103= 6=0D +## Default Creator ID for ACPI table creation.=0D +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorId|0x20202020|UINT32|0x30001037= =0D +## Default Creator Revision for ACPI table creation.=0D +gSiPkgTokenSpaceGuid.PcdAcpiDefaultCreatorRevision|0x01000013|UINT32|0x300= 01038=0D +## ME HECI interface configuration=0D +gMeConfigSpaceGuid.PcdHeciDumpsEnabled|TRUE|BOOLEAN|0x50000001=0D +gMeConfigSpaceGuid.PcdHeciTimeoutsEnabled|TRUE|BOOLEAN|0x50000002=0D +=0D +=0D +[PcdsFixedAtBuild, PcdsPatchableInModule]=0D +## This value is used to set the base address of PCH devices=0D +gSiPkgTokenSpaceGuid.PcdSmbusBaseAddress|0x0000EFA0|UINT16|0x00010031=0D +gSiPkgTokenSpaceGuid.PcdTcoBaseAddress|0x0400|UINT16|0x00010033=0D +gSiPkgTokenSpaceGuid.PcdAcpiBaseAddress|0x1800|UINT16|0x00010035=0D +=0D +=0D +## Stack size in the temporary RAM.=0D +## 0 means half of TemporaryRamSize.=0D +gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0|UINT32|0x00010036=0D +##=0D +## PcdFviSmbiosType determines the SMBIOS OEM type (0x80 to 0xFF) defined = in SMBIOS,=0D +## values 0-0x7F will be treated as disable FVI reporting.=0D +## FVI structure uses it as SMBIOS OEM type to provide version information= .=0D +##=0D +gSiPkgTokenSpaceGuid.PcdFviSmbiosType|0xDD|UINT8|0x00010037=0D +gSiPkgTokenSpaceGuid.PcdSaPciPrint|FALSE|BOOLEAN|0x00010039=0D +##=0D +## SMBIOS defaults=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSocketDesignation|"U3E1"|VOID*|0x0001= 003a=0D +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultSerialNumber|"To Be Filled By O.E.M."= |VOID*|0x0001003b=0D +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultAssetTag|"To Be Filled By O.E.M."|VOI= D*|0x0001003c=0D +gSiPkgTokenSpaceGuid.PcdSmbiosDefaultPartNumber|"To Be Filled By O.E.M."|V= OID*|0x0001003d=0D +=0D +##=0D +## Allocate 56 KB [0x2000..0xFFFF] of I/O space for Pci Devices=0D +## If PcdPciReservedMemLimit =3D0 Pci Reserved default MMIO Limit is 0xE= 0000000 else use PcdPciReservedMemLimit .=0D +##=0D +gSiPkgTokenSpaceGuid.PcdPciReservedIobase |0x2000 |UINT16|0x00010041= =0D +gSiPkgTokenSpaceGuid.PcdPciReservedIoLimit |0xFFFF |UINT16|0x00010042= =0D +gSiPkgTokenSpaceGuid.PcdPciReservedMemLimit |0x0000 |UINT32|0x00010043= =0D +gSiPkgTokenSpaceGuid.PcdPciDmaAbove4G |FALSE |BOOLEAN|0x00010044= =0D +gSiPkgTokenSpaceGuid.PcdPciNoExtendedConfigSpace|FALSE |BOOLEAN|0x00010045= =0D +=0D +##=0D +## Default 8MB TSEG for Release build BIOS when IED disabled (Also a defau= lt)=0D +##=0D +gSiPkgTokenSpaceGuid.PcdTsegSize|0x00800000|UINT32|0x00010046=0D +##=0D +## gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType determines the SMBIOS OEM type = (0x80 to 0xFF) defined=0D +## in SMBIOS, values 0-0x7F will be treated as disable FWSTS SMBIOS report= ing.=0D +## FWSTS structure uses it as SMBIOS OEM type to provide FWSTS information= .=0D +##=0D +gSiPkgTokenSpaceGuid.PcdFwStsSmbiosType|0xDB|UINT8|0x00010047=0D +=0D +##=0D +## Maximum Address the AP Wakeup Buffer can start.=0D +##=0D +gSiPkgTokenSpaceGuid.PcdCpuApWakeupBufferMaxAddr|0x58000|UINT32|0x00010048= =0D +=0D +##=0D +## Silicon Reference Code versions=0D +##=0D +##Revision:Weekly build number=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionRevision|0x33|UINT8|0x00010051=0D +=0D +##Build[7:4]:Daily build number.=0D +##Build[3:0]:Patch build number.=0D +=0D +##=0D +## Temp MEM IO resource=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMin |2 |UINT8 |0x0= 0010053=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitTempPciBusMax |10 |UINT8 |0x0= 0010054=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemBaseAddr |0xFE600000|UINT32|0x0= 0010055=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitTempMemSize |0x00200000|UINT32|0x0= 0010056=0D +=0D +##=0D +## This PCD specifies the base address of the HPET timer.=0D +## The acceptable values are 0xFED00000, 0xFED01000, 0xFED02000, and 0xFED= 03000=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSiHpetBaseAddress |0xFED00000|UINT32|0x00010057= =0D +##=0D +## This PCD specifies the base address of the IO APIC.=0D +## The acceptable values are 0xFECxx000.=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSiIoApicBaseAddress |0xFEC00000|UINT32|0x00010058= =0D +=0D +=0D +##=0D +## VTD Base Addresses=0D +##=0D +=0D +## Null-terminated string of the Version of Physical Presence interface su= pported by platform.=0D +# @Prompt Version of Physical Presence interface supported by platform.=0D +gSiPkgTokenSpaceGuid.PcdTcgPhysicalPresenceInterfaceVer|"1.3"|VOID*|0x0000= 0008=0D +=0D +## This PCD specifies Master of TraceHub device=0D +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibMaster|0x0|UINT32|0x00011000=0D +## This PCD specifies Channel of TraceHub device=0D +gSiPkgTokenSpaceGuid.PcdTraceHubDebugLibChannel|0x0|UINT32|0x00011001=0D +=0D +=0D +[PcdsPatchableInModule, PcdsFixedAtBuild]=0D +## This value is used to set the base address of MCH=0D +gSiPkgTokenSpaceGuid.PcdMchBaseAddress|0xFEDC0000|UINT64|0x00010030=0D +## 128KB window=0D +gSiPkgTokenSpaceGuid.PcdMchMmioSize|0x20000|UINT32|0x50000000=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMajor |0x0A|UINT8|0x00010049=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionValue |0x0000000800260020|UINT= 64|0x00010077=0D +=0D +##Minor:the program that supported by same core generation.=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionMinor |0x00|UINT8|0x00010050=0D +=0D +gSiPkgTokenSpaceGuid.PcdSiliconInitVersionBuild |0x10|UINT8|0x00010052=0D +gSiPkgTokenSpaceGuid.PcdRegBarBaseAddress|0xFB000000|UINT32|0x00010059=0D +[PcdsFixedAtBuild, PcdsPatchableInModule, PcdsDynamic, PcdsDynamicEx]=0D +##=0D +## SerialIo Uart Configuration=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable |0 |UINT8 |0x00= 210001 # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing= =0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartNumber |2 |UINT8 |0x00= 210002=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartMode |2 |UINT8 |0x00= 210003 # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartBaudRate |115200 |UINT32|0x00= 210004 # 0:Default, Max:6000000=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartParity |1 |UINT8 |0x00= 210008 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartDataBits |8 |UINT8 |0x00= 210009 # 0:Default, 5,6,7,8=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartStopBits |1 |UINT8 |0x00= 21000A # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits= =0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartAutoFlow |0 |UINT8 |0x00= 21000B # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rt= s/Cts lines enabled;=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartRxPinMux |0x0 |UINT32|0x00= 21000C # Pin muxing config for UART Rx pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartTxPinMux |0x0 |UINT32|0x00= 210010 # Pin muxing config for UART Tx pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartRtsPinMux |0x0 |UINT32|0x00= 210014 # Pin muxing config for UART Rts pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartCtsPinMux |0x0 |UINT32|0x00= 210018 # Pin muxing config for UART Cts pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugMmioBase |0xFE036000 |UINT32|0x00= 21001C # PcdSerialIoUartMode =3D Enabled, need to assign MMIO Resource in S= EC/PEI Phase=0D +=0D +gSiPkgTokenSpaceGuid.PcdLpcUartDebugEnable |0x1 |UINT8 |0x00= 210026 # 0:Disable, 1:Enable=0D +gSiPkgTokenSpaceGuid.PcdDebugInterfaceFlags |0x12 |UINT8 |0x00= 210027 # BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub, BIT= 2 - Not used.=0D +gSiPkgTokenSpaceGuid.PcdSerialDebugLevel |0x3 |UINT8 |0x00= 210028 # {0:Disable, 1:Error Only, 2:Error and Warnings, 3:Load Error Warni= ngs and Info, 4:Load Error Warnings and Info, 5:Load Error Warnings Info an= d Verbose=0D +gSiPkgTokenSpaceGuid.PcdIsaSerialUartBase |0x0 |UINT8 |0x00= 210029 # 0:0x3F8, 1:0x2F8=0D +=0D +## UART Lib TimeOut=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartTimeOut |1000000 |UINT32 |= 0x00210020 # Write TimeOut in Micro Seconds - 0 =3D disabbled, default 1 se= cond,=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartLibSkipMmioCheck |FALSE |BOOLEAN|= 0x00210024 # If TRUE MMIO sanity checks are skipped=0D +=0D +## UART Dxe Driver IgnoreBaudRateSet=0D +## TRUE - Blocks changing BaudRate, so that driver will not override UART'= s initial configuration.=0D +## Required to support redirection on higher BaudRates.=0D +## FALSE - Allows for UART settings to be changed through the Serial Io Pr= otocol=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSerialIoUartDriverIgnoreBaudRateSet|FALSE|BOOLEAN|= 0x00210025=0D +=0D +##=0D +## SerialIo 2nd Uart Configuration=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartEnable |0 |UINT8 |0x002= 1002A # 0:Disable, 1:Enable and Initialize, 2:Enable without Initializing=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartNumber |2 |UINT8 |0x002= 1002B=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMode |2 |UINT8 |0x002= 1002C # 0:Disabled, 1:Enabled, 2:Hidden, 3:COM, 4:SkipInit=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartBaudRate |115200 |UINT32|0x002= 1002D # 0:Default, Max:6000000=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartParity |1 |UINT8 |0x002= 10031 # 0:DefaultParity, 1:NoParity, 2:EvenParity, 3:OddParity=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartDataBits |8 |UINT8 |0x002= 10032 # 0:Default, 5,6,7,8=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartStopBits |1 |UINT8 |0x002= 10033 # 0:DefaultStopBits, 1:OneStopBit, 2:OneFiveStopBits, 3:TwoStopBits=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartAutoFlow |0 |UINT8 |0x002= 10034 # 0:No HW flow control, Only RX/TX Enabled; 1:HW Flow Control On, Rts= /Cts lines enabled;=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRxPinMux |0x0 |UINT32|0x002= 10035 # Pin muxing config for UART Rx pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartTxPinMux |0x0 |UINT32|0x002= 10039 # Pin muxing config for UART Tx pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartRtsPinMux |0x0 |UINT32|0x002= 1003D # Pin muxing config for UART Rts pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartCtsPinMux |0x0 |UINT32|0x002= 10041 # Pin muxing config for UART Cts pin=0D +gSiPkgTokenSpaceGuid.PcdSerialIo2ndUartMmioBase |0xFE034000 |UINT32|0x002= 10045 # PcdSerialIoUartMode =3D Enabled, need to assign MMIO Resource in SE= C/PEI Phase=0D +=0D +##=0D +## PCI Express MMIO region length=0D +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x= 4000000/64MB=0D +##=0D +gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000|UINT32|0x0020000= 1=0D +##=0D +## Typically this should be the same with gEfiMdePkgTokenSpaceGuid.PcdPciE= xpressBaseAddress.=0D +## This PCD is added for supporting different PCD type in different phases= .=0D +##=0D +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress |0xC0000000|UINT64|0x00200= 002=0D +##=0D +## PCI Express MMIO temporary region length in SEC phase.=0D +## Valid settings: 0x20000000/512MB, 0x10000000/256MB, 0x8000000/128MB, 0x= 4000000/64MB=0D +##=0D +gSiPkgTokenSpaceGuid.PcdTemporaryPciExpressRegionLength|0x10000000|UINT32|= 0x00200005=0D +=0D +## Specifies the SMRR2 base address.

=0D +# @Prompt SMRR2 base address.=0D +# @Expression 0x80000001 | (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base & 0xf= ff) =3D=3D 0=0D +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Base|0|UINT32|0x20000002=0D +=0D +## Specifies the SMRR2 range size.

=0D +# @Prompt SMRR2 range size.=0D +# @Expression 0x80000001 | (gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size & 0xf= ff) =3D=3D 0=0D +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2Size|0|UINT32|0x20000003=0D +=0D +## Specifies the SMRR2 range cache type.=0D +# If SMRR2 is used to map a flash/ROM based handler, it would be configur= ed as WP.

=0D +# 5: WP(Write Protect).
=0D +# 6: WB(Write Back).
=0D +# @Prompt SMRR2 range cache type.=0D +gSiPkgTokenSpaceGuid.PcdCpuSmmSmrr2CacheType|5|UINT8|0x20000004=0D +=0D +## Indidates if SMM PROT MODE feature is supported.

=0D +# TRUE - SMM PROT MODE feature is supported.
=0D +# FALSE - SMM PROT MODE feature is not supported.
=0D +# @Prompt SMM PROT MODE feature.=0D +gSiPkgTokenSpaceGuid.PcdCpuSmmProtectedModeEnable|FALSE|BOOLEAN|0x20000008= =0D +=0D +## Specifies the a size of memory region to reserve in SMM for testing onl= y.=0D +# One can look in BIOS serial log for PCD to get region base address.=0D +# Note: A different region may be allocated in release build than debug b= uild.=0D +# @Prompt SMM test region size.\r=0D +gSiPkgTokenSpaceGuid.PcdSmmTestRsvMemorySize|0x0|UINT32|0x2000000E=0D +=0D +[PcdsDynamic]=0D +=0D +## Indidates if SMM Code Access Check feature is supported.

=0D +# TRUE - SMM Code Access Check feature is supported.
=0D +# FALSE - SMM Code Access Check feature is not supported.
=0D +# @Prompt SMM Code Access Check feature.=0D +gSiPkgTokenSpaceGuid.PcdCpuSmmCodeAccessCheckEnable|TRUE|BOOLEAN|0x001000D= =0D +=0D +## Causes all UEFI variables to be treated as volatile and hence never wri= tten to non-volatile=0D +## storage.=0D +## This is useful in cases such as a simulation environment that does not = emulate a non-volatile=0D +## storage device or in recovery scenarios where system errors prevent non= -volatile storage from being accessed=0D +gSiPkgTokenSpaceGuid.PcdNvVariableEmulationMode|FALSE|BOOLEAN|0x0010000E=0D +=0D +## Enables or disables storage of UEFI variables using the CSE Variable St= orage drivers=0D +## If disabled at runtime, it must be set before the CSE Variable Storag= e driver loads.=0D +gSiPkgTokenSpaceGuid.PcdEnableCseVariableStorage|FALSE|BOOLEAN|0x0010000F= =0D +=0D +## Enables or disables storage of UEFI variables using the FVB Variable St= orage drivers=0D +## If disabled at runtime, it must be set before the FVB Variable Storage= driver loads.=0D +gSiPkgTokenSpaceGuid.PcdEnableFvbVariableStorage|TRUE|BOOLEAN|0x00100010=0D +=0D --=20 2.24.0.windows.2