From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web11.5275.1612510889619185483 for ; Thu, 04 Feb 2021 23:41:33 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: Zl3CVEIMFvjEhy3Imlp53stFMQ3OrTshMMT5kMxIea/1h3ZJXKauJIkJGjVE5YIriqJeiF2ptv ZBLHVOgRFjCw== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543656" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543656" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:31 -0800 IronPort-SDR: RJnbVbMUv7bcwFWjJTDSIlZoh0gsEVwjBOy+Aj+Hb3AQZeWR4HWefYSQY5Xf5O+kPXlYp2ZfcX U2QDuZDF7VhQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260273" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:29 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Date: Fri, 5 Feb 2021 15:40:16 +0800 Message-Id: <20210205074045.3916-11-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Fru/TglPch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment.h = | 326 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h = | 16 ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResources.= h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 397 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAss= ignment.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssi= gnment.h new file mode 100644 index 0000000000..0d00f25d5e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchBdfAssignment= .h @@ -0,0 +1,326 @@ +/** @file=0D + Header file for TigerLake PCH devices PCI Bus Device Function map.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_BDF_ASSIGNMENT_H_=0D +#define _PCH_BDF_ASSIGNMENT_H_=0D +=0D +#define NOT_PRESENT 0xFF=0D +=0D +#define MAX_SATA_CONTROLLER 1=0D +=0D +//=0D +// PCH PCIe Controllers=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_1 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_2 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_3 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_4 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_5 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_6 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_7 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_8 28=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_9 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_10 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_11 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_12 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_13 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_14 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_15 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_16 29=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_17 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_18 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_19 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_20 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_21 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_22 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_23 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_24 27=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_25 NOT_PRESENT=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_26 NOT_PRESENT=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_27 NOT_PRESENT=0D +#define PCI_DEVICE_NUMBER_PCH_PCIE_ROOT_PORT_28 NOT_PRESENT=0D +=0D +//=0D +// USB3 (XHCI) Controller PCI config=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_XHCI 20=0D +#define PCI_FUNCTION_NUMBER_PCH_XHCI 0=0D +=0D +//=0D +// xDCI (OTG) USB Device Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_XDCI 20=0D +#define PCI_FUNCTION_NUMBER_PCH_XDCI 1=0D +=0D +//=0D +// Thermal Device=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_THERMAL NOT_PRESENT=0D +#define PCI_FUNCTION_NUMBER_PCH_THERMAL NOT_PRESENT=0D +=0D +//=0D +// CSME HECI #1=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_HECI1 22=0D +#define PCI_FUNCTION_NUMBER_PCH_HECI1 0=0D +=0D +//=0D +// CSME HECI #2=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_HECI2 22=0D +#define PCI_FUNCTION_NUMBER_PCH_HECI2 1=0D +=0D +//=0D +// CSME IDE-Redirection (IDE-R)=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_IDER 22=0D +#define PCI_FUNCTION_NUMBER_PCH_IDER 2=0D +=0D +//=0D +// CSME Keyboard and Text (KT) Redirection=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_KTR 22=0D +#define PCI_FUNCTION_NUMBER_PCH_KTR 3=0D +=0D +//=0D +// CSME HECI #3=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_HECI3 22=0D +#define PCI_FUNCTION_NUMBER_PCH_HECI3 4=0D +=0D +//=0D +// CSME HECI #4=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_HECI4 22=0D +#define PCI_FUNCTION_NUMBER_PCH_HECI4 5=0D +=0D +//=0D +// CSME MROM=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_MROM NOT_PRESENT=0D +#define PCI_FUNCTION_NUMBER_PCH_MROM NOT_PRESENT=0D +=0D +//=0D +// CSME WLAN=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_WLAN 22=0D +#define PCI_FUNCTION_NUMBER_PCH_WLAN 7=0D +=0D +//=0D +// SATA Controllers=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SATA_1 23=0D +#define PCI_FUNCTION_NUMBER_PCH_SATA_1 0=0D +#define PCI_DEVICE_NUMBER_PCH_SATA_2 NOT_PRESENT=0D +#define PCI_FUNCTION_NUMBER_PCH_SATA_2 NOT_PRESENT=0D +#define PCI_DEVICE_NUMBER_PCH_SATA_3 NOT_PRESENT=0D +#define PCI_FUNCTION_NUMBER_PCH_SATA_3 NOT_PRESENT=0D +=0D +//=0D +// PCH LP Serial IO I2C #0 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C0 21=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C0 0=0D +=0D +//=0D +// PCH LP Serial IO I2C #1 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C1 21=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C1 1=0D +=0D +//=0D +// PCH LP Serial IO I2C #2 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C2 21=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C2 2=0D +=0D +//=0D +// PCH LP Serial IO I2C #3 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C3 21=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C3 3=0D +=0D +//=0D +// PCH LP Serial IO I2C #4 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C4 25=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C4 0=0D +=0D +//=0D +// PCH LP Serial IO I2C #5 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C5 25=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C5 1=0D +=0D +//=0D +// PCH LP Serial IO I2C #6 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C6 16=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C6 0=0D +=0D +//=0D +// PCH LP Serial IO I2C #7 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_I2C7 16=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_I2C7 1=0D +=0D +//=0D +// PCH LP Serial IO SPI #0 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI0 30=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI0 2=0D +=0D +//=0D +// PCH LP Serial IO SPI #1 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI1 30=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI1 3=0D +=0D +//=0D +// PCH LP Serial IO SPI #2 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI2 18=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI2 6=0D +=0D +//=0D +// PCH LP Serial IO SPI #3 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI3 19=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI3 0=0D +=0D +//=0D +// PCH LP Serial IO SPI #4 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI4 19=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI4 1=0D +=0D +//=0D +// PCH LP Serial IO SPI #5 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI5 19=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI5 2=0D +=0D +//=0D +// PCH LP Serial IO SPI #6 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_SPI6 19=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_SPI6 3=0D +=0D +//=0D +// PCH LP Serial IO UART #0 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART0 30=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART0 0=0D +=0D +//=0D +// PCH LP Serial IO UART #1 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART1 30=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART1 1=0D +=0D +//=0D +// PCH LP Serial IO UART #2 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART2 25=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART2 2=0D +=0D +//=0D +// PCH LP Serial IO UART #3 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART3 17=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART3 0=0D +=0D +//=0D +// PCH LP Serial IO UART #4 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART4 17=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART4 1=0D +=0D +//=0D +// PCH LP Serial IO UART #5 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART5 17=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART5 2=0D +=0D +//=0D +// PCH LP Serial IO UART #6 Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SERIAL_IO_UART6 17=0D +#define PCI_FUNCTION_NUMBER_PCH_SERIAL_IO_UART6 3=0D +=0D +//=0D +// DMA-SMBus Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_DMA_SMBUS 30=0D +#define PCI_FUNCTION_NUMBER_PCH_DMA_SMBUS 4=0D +=0D +//=0D +// TSN GbE Controller #1=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_TSN0 30=0D +#define PCI_FUNCTION_NUMBER_PCH_TSN0 4=0D +=0D +//=0D +// TSN GbE Controller #2=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_TSN1 30=0D +#define PCI_FUNCTION_NUMBER_PCH_TSN1 5=0D +=0D +//=0D +// LPC Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_LPC 31=0D +#define PCI_FUNCTION_NUMBER_PCH_LPC 0=0D +=0D +//=0D +// eSPI Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_ESPI 31=0D +#define PCI_FUNCTION_NUMBER_PCH_ESPI 0=0D +=0D +//=0D +// Primary to Sideband (P2SB) Bridge=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_P2SB 31=0D +#define PCI_FUNCTION_NUMBER_PCH_P2SB 1=0D +=0D +//=0D +// PMC (D31:F2)=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_PMC 31=0D +#define PCI_FUNCTION_NUMBER_PCH_PMC 2=0D +=0D +//=0D +// PMC SSRAM Registers=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_PMC_SSRAM 20=0D +#define PCI_FUNCTION_NUMBER_PCH_PMC_SSRAM 2=0D +=0D +//=0D +// HD-A Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_HDA 31=0D +#define PCI_FUNCTION_NUMBER_PCH_HDA 3=0D +=0D +//=0D +// SMBus Controller=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SMBUS 31=0D +#define PCI_FUNCTION_NUMBER_PCH_SMBUS 4=0D +=0D +//=0D +// SPI Controller (D31:F5)=0D +//=0D +#define PCI_DEVICE_NUMBER_PCH_SPI 31=0D +#define PCI_FUNCTION_NUMBER_PCH_SPI 5=0D +=0D +//=0D +// Gigabit Ethernet LAN Controller (D31:F6)=0D +//=0D +#define PCI_DEVICE_NUMBER_GBE 31=0D +#define PCI_FUNCTION_NUMBER_GBE 6=0D +=0D +#endif // _PCH_BDF_ASSIGNMENT_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRp= Info.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo= .h new file mode 100644 index 0000000000..d3548796a3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchPcieRpInfo.h @@ -0,0 +1,16 @@ +/** @file=0D + Pcie Root Port info header=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PCH_PCIERP_INFO_H_=0D +#define _PCH_PCIERP_INFO_H_=0D +=0D +//=0D +// Number of PCIe ports per PCIe controller=0D +//=0D +#define PCH_PCIE_CONTROLLER_PORTS 4u=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReserv= edResources.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchRes= ervedResources.h new file mode 100644 index 0000000000..283246692f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/Include/PchReservedResou= rces.h @@ -0,0 +1,55 @@ +/** @file=0D + PCH preserved MMIO resource definitions.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PRESERVED_RESOURCES_H_=0D +#define _PCH_PRESERVED_RESOURCES_H_=0D +=0D +/**=0D + Detailed recommended static allocation=0D + +-----------------------------------------------------------------------= --+=0D + | PCH preserved MMIO range, 32 MB, from 0xFC800000 to 0xFE7FFFFF = |=0D + +-----------------------------------------------------------------------= --+=0D + | Size | Start | End | Usage = |=0D + | 8 MB | 0xFC800000 | 0xFCFFFFFF | TraceHub SW BAR = |=0D + | 16 MB | 0xFD000000 | 0xFDFFFFFF | SBREG = |=0D + | 64 KB | 0xFE000000 | 0xFE00FFFF | PMC MBAR = |=0D + | 4 KB | 0xFE010000 | 0xFE010FFF | SPI BAR0 = |=0D + | 176 KB | 0xFE020000 | 0xFE04BFFF | SerialIo BAR in ACPI mode = |=0D + | 400 KB | 0xFE04C000 | 0xFE0AFFFF | Unused = |=0D + | 64 KB | 0xFE0B0000 | 0xFE0BFFFF | eSPI LGMR BAR = |=0D + | 64 KB | 0xFE0C0000 | 0xFE0CFFFF | eSPI2 SEGMR BAR = |=0D + | 192 KB | 0xFE0D0000 | 0xFE0FFFFF | Unused = |=0D + | 1 MB | 0xFE100000 | 0xFE1FFFFF | TraceHub MTB BAR = |=0D + | 2 MB | 0xFE200000 | 0xFE3FFFFF | TraceHub FW BAR = |=0D + | 2 MB | 0xFE400000 | 0xFE5FFFFF | Unused = |=0D + | 2 MB | 0xFE600000 | 0xFE7FFFFF | Temp address = |=0D + +-----------------------------------------------------------------------= --+=0D +**/=0D +#define PCH_PRESERVED_BASE_ADDRESS 0xFC800000 ///< Pch preserved = MMIO base address=0D +#define PCH_PRESERVED_MMIO_SIZE 0x02000000 ///< 32MB=0D +#define PCH_TRACE_HUB_SW_BASE_ADDRESS 0xFC800000 ///< TraceHub SW MM= IO base address=0D +#define PCH_TRACE_HUB_SW_MMIO_SIZE 0x00800000 ///< 8MB=0D +#define PCH_PCR_BASE_ADDRESS 0xFD000000 ///< SBREG MMIO bas= e address=0D +#define PCH_PCR_MMIO_SIZE 0x01000000 ///< 16MB=0D +#define PCH_PWRM_BASE_ADDRESS 0xFE000000 ///< PMC MBAR MMIO = base address=0D +#define PCH_PWRM_MMIO_SIZE 0x00010000 ///< 64KB=0D +#define PCH_SPI_BASE_ADDRESS 0xFE010000 ///< SPI BAR0 MMIO = base address=0D +#define PCH_SPI_MMIO_SIZE 0x00001000 ///< 4KB=0D +#define PCH_SERIAL_IO_BASE_ADDRESS 0xFE020000 ///< SerialIo MMIO = base address=0D +#define PCH_SERIAL_IO_MMIO_SIZE 0x0002C000 ///< 176KB=0D +#define PCH_ESPI_LGMR_BASE_ADDRESS 0xFE0B0000 ///< eSPI LGMR MMIO= base address=0D +#define PCH_ESPI_LGMR_MMIO_SIZE 0x00010000 ///< 64KB=0D +#define PCH_ESPI_SEGMR_BASE_ADDRESS 0xFE0C0000 ///< Second eSPI GM= R MMIO base address=0D +#define PCH_ESPI_SEGMR_MMIO_SIZE 0x00010000 ///< 64KB=0D +#define PCH_TRACE_HUB_MTB_BASE_ADDRESS 0xFE100000 ///< TraceHub MTB M= MIO base address=0D +#define PCH_TRACE_HUB_MTB_MMIO_SIZE 0x00100000 ///< 1MB=0D +#define PCH_TRACE_HUB_FW_BASE_ADDRESS 0xFE200000 ///< TraceHub FW MM= IO base address=0D +#define PCH_TRACE_HUB_FW_MMIO_SIZE 0x00200000 ///< 2MB=0D +#define PCH_TEMP_BASE_ADDRESS 0xFE600000 ///< preserved temp= address for misc usage,=0D +#define PCH_TEMP_MMIO_SIZE 0x00200000 ///< 2MB=0D +=0D +#endif // _PCH_PRESERVED_RESOURCES_H_=0D +=0D --=20 2.24.0.windows.2