[Patch V3 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers

["Heng Luo" <heng.luo@intel.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171

Adds the following header files:
  * Fru/TglPch/IncludePrivate

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 66 insertions(+)

diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h
new file mode 100644
index 0000000000..4987d21f09
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Fru/TglPch/IncludePrivate/Register/PchPcrRegs.h
@@ -0,0 +1,66 @@
+/** @file
+  Register names for PCH private chipset register
+
+Conventions:
+
+  - Register definition format:
+    Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+  - Prefix:
+    Definitions beginning with "R_" are registers
+    Definitions beginning with "B_" are bits within registers
+    Definitions beginning with "V_" are meaningful values within the bits
+    Definitions beginning with "S_" are register size
+    Definitions beginning with "N_" are the bit position
+  - [GenerationName]:
+    Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+    Register name without GenerationName applies to all generations.
+  - [ComponentName]:
+    This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+    Register name without ComponentName applies to all components.
+    Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+  - SubsystemName:
+    This field indicates the subsystem name of the component that the register belongs to
+    (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+  - RegisterSpace:
+    MEM - MMIO space register of subsystem.
+    IO  - IO space register of subsystem.
+    PCR - Private configuration register of subsystem.
+    CFG - PCI configuration space register of subsystem.
+  - RegisterName:
+    Full register name.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PCR_H_
+#define _PCH_REGS_PCR_H_
+
+/**
+  Definition for SBI PID
+  The PCH_SBI_PID defines the PID for PCR MMIO programming and PCH SBI programming as well.
+**/
+#define PID_CNVI       0x73
+#define PID_ICLK       0xAD
+#define PID_DMI        0x88
+#define PID_PSTH       0x89
+#define PID_ESPISPI    0x72
+#define PID_SPF        0x85
+#define PID_SPE        0x84
+#define PID_SPD        0x83
+#define PID_SPC        0x82
+#define PID_SPB        0x81
+#define PID_SPA        0x80
+#define PID_PSF6       0x7F
+#define PID_PSF4       0xBD
+#define PID_PSF3       0xBC
+#define PID_PSF2       0xBB
+#define PID_PSF1       0xBA
+#define PID_GPIOCOM0   0x6E
+#define PID_GPIOCOM1   0x6D
+#define PID_GPIOCOM2   0x6C
+#define PID_GPIOCOM3   0x6B
+#define PID_GPIOCOM4   0x6A
+#define PID_GPIOCOM5   0x69
+#define PID_CSME_PSF   0x8F
+
+#endif
-- 
2.24.0.windows.2