From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web10.5199.1612510905365067950 for ; Thu, 04 Feb 2021 23:41:50 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: BFW79lYOuMpF/smBm1j4F+07Zh1xAM72BN8IzU4farmYQPadoLjQARNai1qRtilMbkdTbPTeCu DJXnNA5FuU/Q== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200397205" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="200397205" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:42 -0800 IronPort-SDR: Q6H6Nvi4hWq3U5vNkysd0cfcGkE2nvvq6aBgIM9aylnhzOtkMHDHdS8L8hHuieW9rKsQq/Cqxc 0xaq03Dvr+jw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260365" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:40 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Date: Fri, 5 Feb 2021 15:40:23 +0800 Message-Id: <20210205074045.3916-18-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/Graphics/AcpiTables * IpBlock/Graphics/IncludePrivate * IpBlock/Graphics/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.asl = | 1955 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCommon.a= sl | 480 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm.asl = | 398 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpGbda.a= sl | 127 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpRn.asl= | 314 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpSbcb.a= sl | 261 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.asl= | 73 ++++++++++++++++++++++++++++= +++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsdt.inf= | 23 +++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/= DxeGraphicsInitLib.h | 53 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/= DxeGraphicsPolicyLib.h | 71 ++++++++++++++++++++++++++++= ++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Library/= DxeIgdOpRegionInitLib.h | 177 ++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraph= icsInitLib/DxeGraphicsInitLib.c | 135 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraph= icsInitLib/DxeGraphicsInitLib.inf | 45 +++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraph= icsPolicyLib/DxeGraphicsPolicyLib.c | 118 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraph= icsPolicyLib/DxeGraphicsPolicyLib.inf | 37 +++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOp= RegionInitLib/DxeIgdOpRegionInit.c | 541 ++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOp= RegionInitLib/DxeIgdOpRegionInitLib.inf | 49 ++++++++++++++++++++++ 17 files changed, 4857 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= Igfx.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Ig= fx.asl new file mode 100644 index 0000000000..d00a1d8f58 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/Igfx.asl @@ -0,0 +1,1955 @@ +/** @file=0D + This file contains the IGD OpRegion/Software ACPI Reference=0D + Code.=0D + It defines the methods to enable/disable output switching,=0D + store display switching and LCD brightness BIOS control=0D + and return valid addresses for all display device encoders=0D + present in the system, etc.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +External(\PLD1, MethodObj)=0D +External(\PLD2, MethodObj)=0D +External(\ECST, MethodObj)=0D +External(\PBCL, MethodObj)=0D +External(HDOS, MethodObj)=0D +External(\ECON, IntObj)=0D +External(\PNHM, IntObj)=0D +External(OSYS, IntObj)=0D +External(CPSC)=0D +External(\GUAM, MethodObj)=0D +External(DSEN)=0D +External(S0ID)=0D +=0D +//=0D +// Default Physical Location of Device=0D +//=0D +Name (DPLD, Package (0x1) {=0D + ToPLD (=0D + PLD_Revision =3D 0x2,=0D + PLD_IgnoreColor =3D 0x1,=0D + PLD_Red =3D 0x0,=0D + PLD_Green =3D 0x0,=0D + PLD_Blue =3D 0x0,=0D + PLD_Width =3D 0x320, //800 mm=0D + PLD_Height =3D 0x7D0, //2000 mm=0D + PLD_UserVisible =3D 0x1, //Set if the device connectio= n point can be seen by the user without disassembly.=0D + PLD_Dock =3D 0x0, // Set if the device connecti= on point resides in a docking station or port replicator.=0D + PLD_Lid =3D 0x0, // Set if this device connect= ion point resides on the lid of laptop system.=0D + PLD_Panel =3D "TOP", // Describes which pan= el surface of the systems housing the device connection point resides on.=0D + PLD_VerticalPosition =3D "CENTER", // Vertical Position o= n the panel where the device connection point resides.=0D + PLD_HorizontalPosition =3D "RIGHT", // Horizontal Position= on the panel where the device connection point resides.=0D + PLD_Shape =3D "VERTICALRECTANGLE",=0D + PLD_GroupOrientation =3D 0x0, // if Set, indicates vertical= grouping, otherwise horizontal is assumed.=0D + PLD_GroupToken =3D 0x0, // Unique numerical value ide= ntifying a group.=0D + PLD_GroupPosition =3D 0x0, // Identifies this device con= nection points position in the group (i.e. 1st, 2nd)=0D + PLD_Bay =3D 0x0, // Set if describing a device= in a bay or if device connection point is a bay.=0D + PLD_Ejectable =3D 0x0, // Set if the device is eject= able. Indicates ejectability in the absence of _EJx objects=0D + PLD_EjectRequired =3D 0x0, // OSPM Ejection required: Se= t if OSPM needs to be involved with ejection process. User-operated physica= l hardware ejection is not possible.=0D + PLD_CabinetNumber =3D 0x0, // For single cabinet system,= this field is always 0.=0D + PLD_CardCageNumber =3D 0x0, // For single card cage syste= m, this field is always 0.=0D + PLD_Reference =3D 0x0, // if Set, this _PLD defines = a reference shape that is used to help orient the user with respect to the = other shapes when rendering _PLDs.=0D + PLD_Rotation =3D 0x0, // 0 - 0deg, 1 - 45deg, 2 - 9= 0deg, 3 - 135deg, 4 - 180deg, 5 - 225deg, 6 - 270deg, 7 - 315deg=0D + PLD_Order =3D 0x3, // Identifies the drawing ord= er of the connection point described by a _PLD=0D + PLD_VerticalOffset =3D 0x0,=0D + PLD_HorizontalOffset =3D 0x0=0D + )=0D + } // Package=0D +) //DPLD=0D +=0D +// Enable/Disable Output Switching. In WIN2K/WINXP, _DOS =3D 0 will=0D +// get called during initialization to prepare for an ACPI Display=0D +// Switch Event. During an ACPI Display Switch, the OS will call=0D +// _DOS =3D 2 immediately after a Notify=3D0x80 to temporarily disable=0D +// all Display Switching. After ACPI Display Switching is complete,=0D +// the OS will call _DOS =3D 0 to re-enable ACPI Display Switching.=0D +Method(_DOS,1)=0D +{=0D + //=0D + // Store Display Switching and LCD brightness BIOS control bit=0D + //=0D + Store(And(Arg0,7),DSEN)=0D +=0D + If(LEqual(And(Arg0, 0x3), 0)) // If _DOS[1:0]=3D0=0D + {=0D + If(CondRefOf(HDOS))=0D + {=0D + HDOS()=0D + }=0D + }=0D +}=0D +=0D +//=0D +// Enumerate the Display Environment. This method will return=0D +// valid addresses for all display device encoders present in the=0D +// system. The Miniport Driver will reject the addresses for every=0D +// encoder that does not have an attached display device. After=0D +// enumeration is complete, the OS will call the _DGS methods=0D +// during a display switch only for the addresses accepted by the=0D +// Miniport Driver. For hot-insertion and removal of display=0D +// devices, a re-enumeration notification will be required so the=0D +// address of the newly present display device will be accepted by=0D +// the Miniport Driver.=0D +//=0D +Method(_DOD,0)=0D +{=0D + //=0D + // Two LFP devices are supporte by default=0D + //=0D + Store(2, NDID)=0D + If(LNotEqual(DIDL, Zero))=0D + {=0D + Store(SDDL(DIDL),DID1)=0D + }=0D + If(LNotEqual(DDL2, Zero))=0D + {=0D + Store(SDDL(DDL2),DID2)=0D + }=0D + If(LNotEqual(DDL3, Zero))=0D + {=0D + Store(SDDL(DDL3),DID3)=0D + }=0D + If(LNotEqual(DDL4, Zero))=0D + {=0D + Store(SDDL(DDL4),DID4)=0D + }=0D + If(LNotEqual(DDL5, Zero))=0D + {=0D + Store(SDDL(DDL5),DID5)=0D + }=0D + If(LNotEqual(DDL6, Zero))=0D + {=0D + Store(SDDL(DDL6),DID6)=0D + }=0D + If(LNotEqual(DDL7, Zero))=0D + {=0D + Store(SDDL(DDL7),DID7)=0D + }=0D + If(LNotEqual(DDL8, Zero))=0D + {=0D + Store(SDDL(DDL8),DID8)=0D + }=0D + If(LNotEqual(DDL9, Zero))=0D + {=0D + Store(SDDL(DDL9),DID9)=0D + }=0D + If(LNotEqual(DD10, Zero))=0D + {=0D + Store(SDDL(DD10),DIDA)=0D + }=0D + If(LNotEqual(DD11, Zero))=0D + {=0D + Store(SDDL(DD11),DIDB)=0D + }=0D + If(LNotEqual(DD12, Zero))=0D + {=0D + Store(SDDL(DD12),DIDC)=0D + }=0D + If(LNotEqual(DD13, Zero))=0D + {=0D + Store(SDDL(DD13),DIDD)=0D + }=0D + If(LNotEqual(DD14, Zero))=0D + {=0D + Store(SDDL(DD14),DIDE)=0D + }=0D + If(LNotEqual(DD15, Zero))=0D + {=0D + Store(SDDL(DD15),DIDF)=0D + }=0D +=0D + //=0D + // Enumerate the encoders. Note that for=0D + // current silicon, the maximum number of encoders=0D + // possible is 15.=0D + //=0D + If(LEqual(NDID,1))=0D + {=0D + Name(TMP1,Package() {=0D + 0xFFFFFFFF})=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP1,0))=0D + } Else {=0D + Store(Or(0x10000,DID1),Index(TMP1,0))=0D + }=0D + Return(TMP1)=0D + }=0D +=0D + If(LEqual(NDID,2))=0D + {=0D + Name(TMP2,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP2,0))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP2,1))=0D + } Else {=0D + Store(Or(0x10000,DID2),Index(TMP2,1))=0D + }=0D + Return(TMP2)=0D + }=0D +=0D + If(LEqual(NDID,3))=0D + {=0D + Name(TMP3,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP3,0))=0D + Store(Or(0x10000,DID2),Index(TMP3,1))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP3,2))=0D + } Else {=0D + Store(Or(0x10000,DID3),Index(TMP3,2))=0D + }=0D + Return(TMP3)=0D + }=0D +=0D + If(LEqual(NDID,4))=0D + {=0D + Name(TMP4,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP4,0))=0D + Store(Or(0x10000,DID2),Index(TMP4,1))=0D + Store(Or(0x10000,DID3),Index(TMP4,2))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP4,3))=0D + } Else {=0D + Store(Or(0x10000,DID4),Index(TMP4,3))=0D + }=0D + Return(TMP4)=0D + }=0D +=0D + If(LEqual(NDID,5))=0D + {=0D + Name(TMP5,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP5,0))=0D + Store(Or(0x10000,DID2),Index(TMP5,1))=0D + Store(Or(0x10000,DID3),Index(TMP5,2))=0D + Store(Or(0x10000,DID4),Index(TMP5,3))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP5,4))=0D + } Else {=0D + Store(Or(0x10000,DID5),Index(TMP5,4))=0D + }=0D + Return(TMP5)=0D + }=0D +=0D + If(LEqual(NDID,6))=0D + {=0D + Name(TMP6,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP6,0))=0D + Store(Or(0x10000,DID2),Index(TMP6,1))=0D + Store(Or(0x10000,DID3),Index(TMP6,2))=0D + Store(Or(0x10000,DID4),Index(TMP6,3))=0D + Store(Or(0x10000,DID5),Index(TMP6,4))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP6,5))=0D + } Else {=0D + Store(Or(0x10000,DID6),Index(TMP6,5))=0D + }=0D + Return(TMP6)=0D + }=0D +=0D + If(LEqual(NDID,7))=0D + {=0D + Name(TMP7,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP7,0))=0D + Store(Or(0x10000,DID2),Index(TMP7,1))=0D + Store(Or(0x10000,DID3),Index(TMP7,2))=0D + Store(Or(0x10000,DID4),Index(TMP7,3))=0D + Store(Or(0x10000,DID5),Index(TMP7,4))=0D + Store(Or(0x10000,DID6),Index(TMP7,5))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP7,6))=0D + } Else {=0D + Store(Or(0x10000,DID7),Index(TMP7,6))=0D + }=0D + Return(TMP7)=0D + }=0D +=0D + If(LEqual(NDID,8))=0D + {=0D + Name(TMP8,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP8,0))=0D + Store(Or(0x10000,DID2),Index(TMP8,1))=0D + Store(Or(0x10000,DID3),Index(TMP8,2))=0D + Store(Or(0x10000,DID4),Index(TMP8,3))=0D + Store(Or(0x10000,DID5),Index(TMP8,4))=0D + Store(Or(0x10000,DID6),Index(TMP8,5))=0D + Store(Or(0x10000,DID7),Index(TMP8,6))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP8,7))=0D + } Else {=0D + Store(Or(0x10000,DID8),Index(TMP8,7))=0D + }=0D + Return(TMP8)=0D + }=0D +=0D + If(LEqual(NDID,9))=0D + {=0D + Name(TMP9,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMP9,0))=0D + Store(Or(0x10000,DID2),Index(TMP9,1))=0D + Store(Or(0x10000,DID3),Index(TMP9,2))=0D + Store(Or(0x10000,DID4),Index(TMP9,3))=0D + Store(Or(0x10000,DID5),Index(TMP9,4))=0D + Store(Or(0x10000,DID6),Index(TMP9,5))=0D + Store(Or(0x10000,DID7),Index(TMP9,6))=0D + Store(Or(0x10000,DID8),Index(TMP9,7))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMP9,8))=0D + } Else {=0D + Store(Or(0x10000,DID9),Index(TMP9,8))=0D + }=0D + Return(TMP9)=0D + }=0D +=0D + If(LEqual(NDID,0x0A))=0D + {=0D + Name(TMPA,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPA,0))=0D + Store(Or(0x10000,DID2),Index(TMPA,1))=0D + Store(Or(0x10000,DID3),Index(TMPA,2))=0D + Store(Or(0x10000,DID4),Index(TMPA,3))=0D + Store(Or(0x10000,DID5),Index(TMPA,4))=0D + Store(Or(0x10000,DID6),Index(TMPA,5))=0D + Store(Or(0x10000,DID7),Index(TMPA,6))=0D + Store(Or(0x10000,DID8),Index(TMPA,7))=0D + Store(Or(0x10000,DID9),Index(TMPA,8))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPA,9))=0D + } Else {=0D + Store(Or(0x10000,DIDA),Index(TMPA,9))=0D + }=0D + Return(TMPA)=0D + }=0D +=0D + If(LEqual(NDID,0x0B))=0D + {=0D + Name(TMPB,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPB,0))=0D + Store(Or(0x10000,DID2),Index(TMPB,1))=0D + Store(Or(0x10000,DID3),Index(TMPB,2))=0D + Store(Or(0x10000,DID4),Index(TMPB,3))=0D + Store(Or(0x10000,DID5),Index(TMPB,4))=0D + Store(Or(0x10000,DID6),Index(TMPB,5))=0D + Store(Or(0x10000,DID7),Index(TMPB,6))=0D + Store(Or(0x10000,DID8),Index(TMPB,7))=0D + Store(Or(0x10000,DID9),Index(TMPB,8))=0D + Store(Or(0x10000,DIDA),Index(TMPB,9))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPB,10))=0D + } Else {=0D + Store(Or(0x10000,DIDB),Index(TMPB,10))=0D + }=0D + Return(TMPB)=0D + }=0D +=0D + If(LEqual(NDID,0x0C))=0D + {=0D + Name(TMPC,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPC,0))=0D + Store(Or(0x10000,DID2),Index(TMPC,1))=0D + Store(Or(0x10000,DID3),Index(TMPC,2))=0D + Store(Or(0x10000,DID4),Index(TMPC,3))=0D + Store(Or(0x10000,DID5),Index(TMPC,4))=0D + Store(Or(0x10000,DID6),Index(TMPC,5))=0D + Store(Or(0x10000,DID7),Index(TMPC,6))=0D + Store(Or(0x10000,DID8),Index(TMPC,7))=0D + Store(Or(0x10000,DID9),Index(TMPC,8))=0D + Store(Or(0x10000,DIDA),Index(TMPC,9))=0D + Store(Or(0x10000,DIDB),Index(TMPC,10))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPC,11))=0D + } Else {=0D + Store(Or(0x10000,DIDC),Index(TMPC,11))=0D + }=0D + Return(TMPC)=0D + }=0D +=0D + If(LEqual(NDID,0x0D))=0D + {=0D + Name(TMPD,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPD,0))=0D + Store(Or(0x10000,DID2),Index(TMPD,1))=0D + Store(Or(0x10000,DID3),Index(TMPD,2))=0D + Store(Or(0x10000,DID4),Index(TMPD,3))=0D + Store(Or(0x10000,DID5),Index(TMPD,4))=0D + Store(Or(0x10000,DID6),Index(TMPD,5))=0D + Store(Or(0x10000,DID7),Index(TMPD,6))=0D + Store(Or(0x10000,DID8),Index(TMPD,7))=0D + Store(Or(0x10000,DID9),Index(TMPD,8))=0D + Store(Or(0x10000,DIDA),Index(TMPD,9))=0D + Store(Or(0x10000,DIDB),Index(TMPD,10))=0D + Store(Or(0x10000,DIDC),Index(TMPD,11))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPD,12))=0D + } Else {=0D + Store(Or(0x10000,DIDD),Index(TMPD,12))=0D + }=0D + Return(TMPD)=0D + }=0D +=0D + If(LEqual(NDID,0x0E))=0D + {=0D + Name(TMPE,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPE,0))=0D + Store(Or(0x10000,DID2),Index(TMPE,1))=0D + Store(Or(0x10000,DID3),Index(TMPE,2))=0D + Store(Or(0x10000,DID4),Index(TMPE,3))=0D + Store(Or(0x10000,DID5),Index(TMPE,4))=0D + Store(Or(0x10000,DID6),Index(TMPE,5))=0D + Store(Or(0x10000,DID7),Index(TMPE,6))=0D + Store(Or(0x10000,DID8),Index(TMPE,7))=0D + Store(Or(0x10000,DID9),Index(TMPE,8))=0D + Store(Or(0x10000,DIDA),Index(TMPE,9))=0D + Store(Or(0x10000,DIDB),Index(TMPE,10))=0D + Store(Or(0x10000,DIDC),Index(TMPE,11))=0D + Store(Or(0x10000,DIDD),Index(TMPE,12))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPE,13))=0D + } Else {=0D + Store(Or(0x10000,DIDE),Index(TMPE,13))=0D + }=0D + Return(TMPE)=0D + }=0D +=0D + If(LEqual(NDID,0x0F))=0D + {=0D + Name(TMPF,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPF,0))=0D + Store(Or(0x10000,DID2),Index(TMPF,1))=0D + Store(Or(0x10000,DID3),Index(TMPF,2))=0D + Store(Or(0x10000,DID4),Index(TMPF,3))=0D + Store(Or(0x10000,DID5),Index(TMPF,4))=0D + Store(Or(0x10000,DID6),Index(TMPF,5))=0D + Store(Or(0x10000,DID7),Index(TMPF,6))=0D + Store(Or(0x10000,DID8),Index(TMPF,7))=0D + Store(Or(0x10000,DID9),Index(TMPF,8))=0D + Store(Or(0x10000,DIDA),Index(TMPF,9))=0D + Store(Or(0x10000,DIDB),Index(TMPF,10))=0D + Store(Or(0x10000,DIDC),Index(TMPF,11))=0D + Store(Or(0x10000,DIDD),Index(TMPF,12))=0D + Store(Or(0x10000,DIDE),Index(TMPF,13))=0D + If (LEqual(IPTP,1)) {=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + //=0D + Store(0x00023480,Index(TMPF,14))=0D + } Else {=0D + Store(Or(0x10000,DIDF),Index(TMPF,14))=0D + }=0D + Return(TMPF)=0D + }=0D +=0D + If(LEqual(NDID,0x10))=0D + {=0D + Name(TMPG,Package() {=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF,=0D + 0xFFFFFFFF})=0D + Store(Or(0x10000,DID1),Index(TMPG,0))=0D + Store(Or(0x10000,DID2),Index(TMPG,1))=0D + Store(Or(0x10000,DID3),Index(TMPG,2))=0D + Store(Or(0x10000,DID4),Index(TMPG,3))=0D + Store(Or(0x10000,DID5),Index(TMPG,4))=0D + Store(Or(0x10000,DID6),Index(TMPG,5))=0D + Store(Or(0x10000,DID7),Index(TMPG,6))=0D + Store(Or(0x10000,DID8),Index(TMPG,7))=0D + Store(Or(0x10000,DID9),Index(TMPG,8))=0D + Store(Or(0x10000,DIDA),Index(TMPG,9))=0D + Store(Or(0x10000,DIDB),Index(TMPG,10))=0D + Store(Or(0x10000,DIDC),Index(TMPG,11))=0D + Store(Or(0x10000,DIDD),Index(TMPG,12))=0D + Store(Or(0x10000,DIDE),Index(TMPG,13))=0D + Store(Or(0x10000,DIDF),Index(TMPG,14))=0D + //=0D + // IGFX need report IPUA as GFX0 child=0D + // NDID can only be 0x10 if IPU is enabled=0D + //=0D + Store(0x00023480,Index(TMPG,15))=0D + Return(TMPG)=0D + }=0D +=0D + //=0D + // If nothing else, return Unknown LFP.=0D + // (Prevents compiler warning.)=0D + //=0D + Return(Package() {0x00000400})=0D +}=0D +=0D +Device(DD01)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID1),0x400))=0D + {=0D + Store(0x1, EDPV)=0D + Store(NXD1, NXDX)=0D + Store(DID1, DIDX)=0D + Return(1)=0D + }=0D + If(LEqual(DID1,0))=0D + {=0D + Return(1)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID1))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + Return(CDDS(DID1))=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD1)=0D + }=0D + Return(NDDS(DID1))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD02)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID2),0x400))=0D + {=0D + If(LEqual(And(0xF,DID2),0x1))=0D + {=0D + Store(0x2, EDPV)=0D + Store(NXD2, NXDY)=0D + Store(DID2, DIDY)=0D + Return(2)=0D + }=0D + Store(0x2, EDPV)=0D + Store(NXD2, NXDX)=0D + Store(DID2, DIDX)=0D + Return(2)=0D + }=0D + If(LEqual(DID2,0))=0D + {=0D + Return(2)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID2))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(LIDS,0))=0D + {=0D + Return(0x0)=0D + }=0D + Return(CDDS(DID2))=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + //=0D + // Return the Next State.=0D + //=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD2)=0D + }=0D + Return(NDDS(DID2))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD03)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID3),0x400))=0D + {=0D + Store(0x3, EDPV)=0D + Store(NXD3, NXDX)=0D + Store(DID3, DIDX)=0D + Return(3)=0D + }=0D + If(LEqual(DID3,0))=0D + {=0D + Return(3)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID3))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID3,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID3))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD3)=0D + }=0D + Return(NDDS(DID3))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD04)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID4),0x400))=0D + {=0D + Store(0x4, EDPV)=0D + Store(NXD4, NXDX)=0D + Store(DID4, DIDX)=0D + Return(4)=0D + }=0D + If(LEqual(DID4,0))=0D + {=0D + Return(4)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID4))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID4,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID4))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD4)=0D + }=0D + Return(NDDS(DID4))=0D + }=0D +=0D + //=0D + // Device Set State. (See table above.)=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD05)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID5),0x400))=0D + {=0D + Store(0x5, EDPV)=0D + Store(NXD5, NXDX)=0D + Store(DID5, DIDX)=0D + Return(5)=0D + }=0D + If(LEqual(DID5,0))=0D + {=0D + Return(5)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID5))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID5,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID5))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD5)=0D + }=0D + Return(NDDS(DID5))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD06)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID6),0x400))=0D + {=0D + Store(0x6, EDPV)=0D + Store(NXD6, NXDX)=0D + Store(DID6, DIDX)=0D + Return(6)=0D + }=0D + If(LEqual(DID6,0))=0D + {=0D + Return(6)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID6))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID6,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID6))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD6)=0D + }=0D + Return(NDDS(DID6))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD07)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID7),0x400))=0D + {=0D + Store(0x7, EDPV)=0D + Store(NXD7, NXDX)=0D + Store(DID7, DIDX)=0D + Return(7)=0D + }=0D + If(LEqual(DID7,0))=0D + {=0D + Return(7)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID7))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID7,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID7))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD7)=0D + }=0D + Return(NDDS(DID7))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD08)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID8),0x400))=0D + {=0D + Store(0x8, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DID8, DIDX)=0D + Return(8)=0D + }=0D + If(LEqual(DID8,0))=0D + {=0D + Return(8)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID8))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID8,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID8))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DID8))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD09)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DID9),0x400))=0D + {=0D + Store(0x9, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DID9, DIDX)=0D + Return(9)=0D + }=0D + If(LEqual(DID9,0))=0D + {=0D + Return(9)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DID9))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DID9,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DID9))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DID9))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0A)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDA),0x400))=0D + {=0D + Store(0xA, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDA, DIDX)=0D + Return(0x0A)=0D + }=0D + If(LEqual(DIDA,0))=0D + {=0D + Return(0x0A)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDA))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDA,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDA))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDA))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0B)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDB),0x400))=0D + {=0D + Store(0xB, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDB, DIDX)=0D + Return(0X0B)=0D + }=0D + If(LEqual(DIDB,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDB))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDB,0))=0D + {=0D + Return(0x0B)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDB))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDB))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0C)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDC),0x400))=0D + {=0D + Store(0xC, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDC, DIDX)=0D + Return(0X0C)=0D + }=0D + If(LEqual(DIDC,0))=0D + {=0D + Return(0x0C)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDC))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDC,0))=0D + {=0D + Return(0x0C)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDC))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDC))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0D)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDD),0x400))=0D + {=0D + Store(0xD, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDD, DIDX)=0D + Return(0X0D)=0D + }=0D + If(LEqual(DIDD,0))=0D + {=0D + Return(0x0D)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDD))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDD,0))=0D + {=0D + Return(0x0D)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDD))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDD))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0E)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDE),0x400))=0D + {=0D + Store(0xE, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDE, DIDX)=0D + Return(0X0E)=0D + }=0D + If(LEqual(DIDE,0))=0D + {=0D + Return(0x0E)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDE))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDE,0))=0D + {=0D + Return(0x0E)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDE))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDE))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +Device(DD0F)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(And(0x0F00,DIDF),0x400))=0D + {=0D + Store(0xF, EDPV)=0D + Store(NXD8, NXDX)=0D + Store(DIDF, DIDX)=0D + Return(0X0F)=0D + }=0D + If(LEqual(DIDF,0))=0D + {=0D + Return(0x0F)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDF))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(DIDC,0))=0D + {=0D + Return(0x0F)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDF))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXD8)=0D + }=0D + Return(NDDS(DIDF))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +}=0D +=0D +//=0D +//Device for eDP=0D +//=0D +Device(DD1F)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(EDPV, 0x0))=0D + {=0D + Return(0x1F)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDX))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(EDPV, 0x0))=0D + {=0D + Return(0x00)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDX))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXDX)=0D + }=0D + Return(NDDS(DIDX))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +=0D + //=0D + // Query List of Brightness Control Levels Supported.=0D + //=0D + Method(_BCL,0)=0D + {=0D + //=0D + // List of supported brightness levels in the following sequence.=0D + // Level when machine has full power.=0D + // Level when machine is on batteries.=0D + // Other supported levels.=0D + //=0D + If(CondRefOf(\PBCL)) {=0D + Return (PBCL())=0D + } Else {=0D + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1= 3, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, = 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,= 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69= , 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 8= 8, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})=0D + }=0D + }=0D +=0D + //=0D + // Set the Brightness Level.=0D + //=0D + Method (_BCM,1)=0D + {=0D + //=0D + // Set the requested level if it is between 0 and 100%.=0D + //=0D + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))=0D + {=0D + \_SB.PC00.GFX0.AINT(1, Arg0)=0D + Store(Arg0,BRTL) // Store Brightness Level.=0D + }=0D + }=0D +=0D + //=0D + // Brightness Query Current level.=0D + //=0D + Method (_BQC,0)=0D + {=0D + Return(BRTL)=0D + }=0D +=0D + //=0D + // Physical Location of Device=0D + //=0D + Method (_PLD,0)=0D + {=0D + If(CondRefOf(\PLD1)) {=0D + Return (PLD1())=0D + } Else {=0D + Return (DPLD)=0D + }=0D + }=0D +}=0D +=0D +//=0D +// Second Display=0D +//=0D +Device(DD2F)=0D +{=0D + //=0D + // Return Unique ID.=0D + //=0D + Method(_ADR,0,Serialized)=0D + {=0D + If(LEqual(EDPV, 0x0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(EDPV, 0x1))=0D + {=0D + Return(0x1F)=0D + }=0D + Else=0D + {=0D + Return(And(0xFFFF,DIDY))=0D + }=0D + }=0D +=0D + //=0D + // Return the Current Status.=0D + //=0D + Method(_DCS,0)=0D + {=0D + If(LEqual(EDPV, 0x0))=0D + {=0D + Return(0x00)=0D + }=0D + If(LEqual(EDPV, 0x1))=0D + {=0D + Return(0x0)=0D + }=0D + Else=0D + {=0D + Return(CDDS(DIDY))=0D + }=0D + }=0D +=0D + //=0D + // Query Graphics State (active or inactive).=0D + //=0D + Method(_DGS,0)=0D + {=0D + If(LAnd(LEqual(And(HGMD,0x7F),0x01),CondRefOf(SNXD)))=0D + {=0D + Return (NXDY)=0D + }=0D + Return(NDDS(DIDY))=0D + }=0D +=0D + //=0D + // Device Set State.=0D + //=0D + Method(_DSS,1)=0D + {=0D + DSST(Arg0)=0D + }=0D +=0D + //=0D + // Query List of Brightness Control Levels Supported.=0D + //=0D + Method(_BCL,0)=0D + {=0D + //=0D + // List of supported brightness levels in the following sequence.=0D + // Level when machine has full power.=0D + // Level when machine is on batteries.=0D + // Other supported levels.=0D + //=0D + If(CondRefOf(\PBCL)) {=0D + Return (PBCL())=0D + } Else {=0D + Return(Package(){80, 50, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 1= 3, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, = 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50,= 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, 66, 67, 68, 69= , 70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, 86, 87, 8= 8, 89, 90, 91, 92, 93, 94, 95, 96, 97, 98, 99, 100})=0D + }=0D + }=0D +=0D + //=0D + // Set the Brightness Level.=0D + //=0D + Method (_BCM,1)=0D + {=0D + //=0D + // Set the requested level if it is between 0 and 100%.=0D + //=0D + If(LAnd(LGreaterEqual(Arg0,0),LLessEqual(Arg0,100)))=0D + {=0D + \_SB.PC00.GFX0.AINT(1, Arg0)=0D + Store(Arg0,BRTL) // Store Brightness Level.=0D + }=0D + }=0D +=0D + //=0D + // Brightness Query Current level.=0D + //=0D + Method (_BQC,0)=0D + {=0D + Return(BRTL)=0D + }=0D +=0D + Method (_PLD,0)=0D + {=0D + If(CondRefOf(\PLD2)) {=0D + Return (PLD2())=0D + } Else {=0D + Return (DPLD)=0D + }=0D + }=0D +}=0D +=0D +Method(SDDL,1)=0D +{=0D + Increment(NDID)=0D + Store(And(Arg0,0xF0F),Local0)=0D + Or(0x80000000,Local0, Local1)=0D + If(LEqual(DIDL,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL2,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL3,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL4,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL5,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL6,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL7,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL8,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DDL9,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD10,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD11,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD12,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD13,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD14,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + If(LEqual(DD15,Local0))=0D + {=0D + Return(Local1)=0D + }=0D + Return(0)=0D +}=0D +=0D +Method(CDDS,1)=0D +{=0D + Store(And(Arg0,0xF0F),Local0)=0D +=0D + If(LEqual(0, Local0))=0D + {=0D + Return(0x1D)=0D + }=0D + If(LEqual(CADL, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL2, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL3, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL4, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL5, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL6, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL7, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + If(LEqual(CAL8, Local0))=0D + {=0D + Return(0x1F)=0D + }=0D + Return(0x1D)=0D +}=0D +=0D +Method(NDDS,1)=0D +{=0D + Store(And(Arg0,0xF0F),Local0)=0D +=0D + If(LEqual(0, Local0))=0D + {=0D + Return(0)=0D + }=0D + If(LEqual(NADL, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL2, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL3, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL4, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL5, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL6, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL7, Local0))=0D + {=0D + Return(1)=0D + }=0D + If(LEqual(NDL8, Local0))=0D + {=0D + Return(1)=0D + }=0D + Return(0)=0D +}=0D +=0D +//=0D +// Device Set State Table=0D +// BIT31 BIT30 Execution=0D +// 0 0 Don't implement.=0D +// 0 1 Cache change. Nothing to Implement.=0D +// 1 0 Don't Implement.=0D +// 1 1 Display Switch Complete. Implement.=0D +//=0D +Method(DSST,1)=0D +{=0D + If(LEqual(And(Arg0,0xC0000000),0xC0000000))=0D + {=0D + //=0D + // State change was performed by the=0D + // Video Drivers. Simply update the=0D + // New State.=0D + //=0D + Store(NSTE,CSTE)=0D + }=0D +}=0D +=0D +//=0D +// Include IGD OpRegion/Software SCI interrupt handler/DSM which is used b= y=0D +// the graphics drivers to request data from system BIOS.=0D +//=0D +include ("IgfxOpRn.asl")=0D +include ("IgfxDsm.asl")=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxCommon.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTab= les/IgfxCommon.asl new file mode 100644 index 0000000000..7325b9fdea --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxCom= mon.asl @@ -0,0 +1,480 @@ +/** @file=0D + IGD OpRegion/Software SCI Reference Code.=0D + This file contains ASL code with the purpose of handling events=0D + i.e. hotkeys and other system interrupts.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +//=0D +// Notes:=0D +// 1. The following routines are to be called from the appropriate event=0D +// handlers.=0D +// 2. This code cannot comprehend the exact implementation in the OEM's BI= OS.=0D +// Therefore, an OEM must call these methods from the existing event=0D +// handler infrastructure. Details on when/why to call each method is= =0D +// included in the method header under the "usage" section.=0D +//=0D +=0D +/************************************************************************;= =0D +;* ACPI Notification Methods=0D +;************************************************************************/= =0D +=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: PDRD=0D +;*=0D +;* Description: Check if the graphics driver is ready to process=0D +;* notifications and video extensions.=0D +;*=0D +;* Usage: This method is to be called prior to performing any=0D +;* notifications or handling video extensions.=0D +;* Ex: If (PDRD()) {Return (FAIL)}=0D +;*=0D +;* Input: None=0D +;*=0D +;* Output: None=0D +;*=0D +;* References: DRDY (Driver ready status), ASLP (Driver recommended=0D +;* sleep timeout value).=0D +;*=0D +;************************************************************************/= =0D +=0D +External(HNOT, MethodObj)=0D +=0D +Method(PDRD)=0D +{=0D + //=0D + // If DRDY is clear, the driver is not ready. If the return value is=0D + // !=3D0, do not perform any notifications or video extension handling.= =0D + //=0D + Return(LNot(DRDY))=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: PSTS=0D +;*=0D +;* Description: Check if the graphics driver has completed the previous=0D +;* "notify" command.=0D +;*=0D +;* Usage: This method is called before every "notify" command. A=0D +;* "notify" should only be set if the driver has completed th= e=0D +;* previous command. Else, ignore the event and exit the par= ent=0D +;* method.=0D +;* Ex: If (PSTS()) {Return (FAIL)}=0D +;*=0D +;* Input: None=0D +;*=0D +;* Output: None=0D +;*=0D +;* References: CSTS (Notification status), ASLP (Driver recommended sleep= =0D +;* timeout value).=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(PSTS)=0D +{=0D + If(LGreater(CSTS, 2))=0D + {=0D + //=0D + // Sleep for ASLP milliseconds if the status is not "success,=0D + // failure, or pending"=0D + //=0D + Sleep(ASLP)=0D + }=0D +=0D + Return(LEqual(CSTS, 3)) // Return True if still Dispatched=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: GNOT=0D +;*=0D +;* Description: Call the appropriate methods to query the graphics driver= =0D +;* status. If all methods return success, do a notification = of=0D +;* the graphics device.=0D +;*=0D +;* Usage: This method is to be called when a graphics device=0D +;* notification is required (display switch hotkey, etc).=0D +;*=0D +;* Input: Arg0 =3D Current event type:=0D +;* 1 =3D display switch=0D +;* 2 =3D lid=0D +;* 3 =3D dock=0D +;* Arg1 =3D Notification type:=0D +;* 0 =3D Re-enumeration=0D +;* 0x80 =3D Display switch=0D +;*=0D +;* Output: Returns 0 =3D success, 1 =3D failure=0D +;*=0D +;* References: PDRD and PSTS methods. OSYS (OS version)=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(GNOT, 2)=0D +{=0D + //=0D + // Check for 1. Driver loaded, 2. Driver ready.=0D + // If any of these cases is not met, skip this event and return failure.= =0D + //=0D + If(PDRD())=0D + {=0D + Return(0x1) // Return failure if driver not loaded.=0D + }=0D +=0D + Store(Arg0, CEVT) // Set up the current event value=0D + Store(3, CSTS) // CSTS=3DBIOS dispatched an event=0D +=0D + If(LAnd(LEqual(CHPD, 0), LEqual(Arg1, 0))) // Do not re-enum if driver s= upports hotplug=0D + {=0D + //=0D + // Re-enumerate the Graphics Device for non-XP operating systems.=0D + //=0D + Notify(\_SB.PC00.GFX0, Arg1)=0D + }=0D +=0D + If(CondRefOf(HNOT))=0D + {=0D + HNOT(Arg0) //Notification handler for Hybrid graphics=0D + }=0D + Else=0D + {=0D + Notify(\_SB.PC00.GFX0,0x80)=0D + }=0D +=0D + Return(0x0) // Return success=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: GHDS=0D +;*=0D +;* Description: Handle a hotkey display switching event (performs a=0D +;* Notify(GFX0, 0).=0D +;*=0D +;* Usage: This method must be called when a hotkey event occurs and = the=0D +;* purpose of that hotkey is to do a display switch.=0D +;*=0D +;* Input: Arg0 =3D Toggle table number.=0D +;*=0D +;* Output: Returns 0 =3D success, 1 =3D failure.=0D +;* CEVT and TIDX are indirect outputs.=0D +;*=0D +;* References: TIDX, GNOT=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(GHDS, 1)=0D +{=0D + Store(Arg0, TIDX) // Store the table number=0D + //=0D + // Call GNOT for CEVT =3D 1 =3D hotkey, notify value =3D 0=0D + //=0D + Return(GNOT(1, 0)) // Return stats from GNOT=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: GLID=0D +;*=0D +;* Description: Handle a lid event (performs the Notify(GFX0, 0), but not = the=0D +;* lid notify).=0D +;*=0D +;* Usage: This method must be called when a lid event occurs. A=0D +;* Notify(LID0, 0x80) must follow the call to this method.=0D +;*=0D +;* Input: Arg0 =3D Lid state:=0D +;* 0 =3D All closed=0D +;* 1 =3D internal LFP lid open=0D +;* 2 =3D external lid open=0D +;* 3 =3D both external and internal open=0D +;*=0D +;* Output: Returns 0=3Dsuccess, 1=3Dfailure.=0D +;* CLID and CEVT are indirect outputs.=0D +;*=0D +;* References: CLID, GNOT=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(GLID, 1)=0D +{=0D +=0D + If (LEqual(Arg0,1))=0D + {=0D + Store(3,CLID)=0D + }=0D + Else=0D + {=0D + Store(Arg0, CLID)=0D + }=0D + //=0D + //Store(Arg0, CLID) // Store the current lid state=0D + // Call GNOT for CEVT=3D2=3DLid, notify value =3D 0=0D + //=0D + if (GNOT(2, 0)) {=0D + Or (CLID, 0x80000000, CLID)=0D + Return (1) // Return Fail=0D + }=0D +=0D + Return (0) // Return Pass=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: GDCK=0D +;*=0D +;* Description: Handle a docking event by updating the current docking sta= tus=0D +;* and doing a notification.=0D +;*=0D +;* Usage: This method must be called when a docking event occurs.=0D +;*=0D +;* Input: Arg0 =3D Docking state:=0D +;* 0 =3D Undocked=0D +;* 1 =3D Docked=0D +;*=0D +;* Output: Returns 0=3Dsuccess, 1=3Dfailure.=0D +;* CDCK and CEVT are indirect outputs.=0D +;*=0D +;* References: CDCK, GNOT=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(GDCK, 1)=0D +{=0D + Store(Arg0, CDCK) // Store the current dock state=0D + //=0D + // Call GNOT for CEVT=3D4=3DDock, notify value =3D 0=0D + //=0D + Return(GNOT(4, 0)) // Return stats from GNOT=0D +}=0D +=0D +/************************************************************************;= =0D +;* ASLE Interrupt Methods=0D +;************************************************************************/= =0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: PARD=0D +;*=0D +;* Description: Check if the driver is ready to handle ASLE interrupts=0D +;* generate by the system BIOS.=0D +;*=0D +;* Usage: This method must be called before generating each ASLE=0D +;* interrupt.=0D +;*=0D +;* Input: None=0D +;*=0D +;* Output: Returns 0 =3D success, 1 =3D failure.=0D +;*=0D +;* References: ARDY (Driver readiness), ASLP (Driver recommended sleep=0D +;* timeout value)=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(PARD)=0D +{=0D + If(LNot(ARDY))=0D + {=0D + //=0D + // Sleep for ASLP milliseconds if the driver is not ready.=0D + //=0D + Sleep(ASLP)=0D + }=0D + //=0D + // If ARDY is clear, the driver is not ready. If the return value is=0D + // !=3D0, do not generate the ASLE interrupt.=0D + //=0D + Return(LNot(ARDY))=0D +}=0D +=0D +//=0D +// Intel Ultrabook Event Handler. Arg0 represents the Ultrabook Event Bit= # to pass=0D +// to the Intel Graphics Driver. Note that this is a serialized method, m= eaning=0D +// sumultaneous events are not allowed.=0D +//=0D +Method(IUEH,1,Serialized)=0D +{=0D + And(IUER,0xC0,IUER) // Clear all button events on entry.=0D + XOr(IUER,Shiftleft(1,Arg0),IUER) // Toggle status.=0D +=0D + If(LLessEqual(Arg0,4)) // Button Event?=0D + {=0D + Return(AINT(5,0)) // Generate event and return status.=0D +=0D + }=0D + Else // Indicator Event.=0D + {=0D + Return(AINT(Arg0,0)) // Generate event and return status.=0D + }=0D +}=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: AINT=0D +;*=0D +;* Description: Call the appropriate methods to generate an ASLE interrupt= .=0D +;* This process includes ensuring the graphics driver is read= y=0D +;* to process the interrupt, ensuring the driver supports the= =0D +;* interrupt of interest, and passing information about the e= vent=0D +;* to the graphics driver.=0D +;*=0D +;* Usage: This method must called to generate an ASLE interrupt.=0D +;*=0D +;* Input: Arg0 =3D ASLE command function code:=0D +;* 0 =3D Set ALS illuminance=0D +;* 1 =3D Set backlight brightness=0D +;* 2 =3D Do Panel Fitting=0D +;* 4 =3D Reserved=0D +;* 5 =3D Button Indicator Event=0D +;* 6 =3D Convertible Indicator Event=0D +;* 7 =3D Docking Indicator Event=0D +;* Arg1 =3D If Arg0 =3D 0, current ALS reading:=0D +;* 0 =3D Reading below sensor range=0D +;* 1-0xFFFE =3D Current sensor reading=0D +;* 0xFFFF =3D Reading above sensor range=0D +;* Arg1 =3D If Arg0 =3D 1, requested backlight percentage=0D +;*=0D +;* Output: Returns 0 =3D success, 1 =3D failure=0D +;*=0D +;* References: PARD method.=0D +;*=0D +;************************************************************************/= =0D +=0D +Method(AINT, 2)=0D +{=0D + //=0D + // Return failure if the requested feature is not supported by the=0D + // driver.=0D + //=0D + If(LNot(And(TCHE, ShiftLeft(1, Arg0))))=0D + {=0D + Return(0x1)=0D + }=0D + //=0D + // Return failure if the driver is not ready to handle an ASLE=0D + // interrupt.=0D + //=0D + If(PARD())=0D + {=0D + Return(0x1)=0D + }=0D + //=0D + // Handle Intel Ultrabook Events.=0D + //=0D + If(LAnd(LGreaterEqual(Arg0,5),LLessEqual(Arg0,7)))=0D + {=0D + Store(ShiftLeft(1,Arg0), ASLC) // Set Ultrbook Event [6:4].=0D + Store(0x01, ASLE) // Generate ASLE interrupt=0D +=0D + Store(0,Local2) // Use Local2 as a timeout counter. Intialize to zero= .=0D +=0D + While(LAnd(LLess(Local2,250),LNotEqual(ASLC,0))) // Wait 1 second or u= ntil Driver ACKs a success.=0D + {=0D + Sleep(4) // Delay 4 ms.=0D + Increment(Local2) // Increment Timeout.=0D + }=0D +=0D + Return(0) // Return success=0D + }=0D + //=0D + // Evaluate the first argument (Panel fitting, backlight brightness, or = ALS).=0D + //=0D + If(LEqual(Arg0, 2)) // Arg0 =3D 2, so request a panel fitting mo= de change.=0D + {=0D + If(CPFM) // If current mode field is non-zero use it.= =0D + {=0D + And(CPFM, 0x0F, Local0) // Create variables without reserved=0D + And(EPFM, 0x0F, Local1) // or valid bits.=0D +=0D + If(LEqual(Local0, 1)) // If current mode is centered,=0D + {=0D + If(And(Local1, 6)) // and if stretched is enabled,=0D + {=0D + Store(6, PFIT) // request stretched.=0D + }=0D + Else // Otherwise,=0D + {=0D + If(And(Local1, 8)) // if aspect ratio is enabled,=0D + {=0D + Store(8, PFIT) // request aspect ratio.=0D + }=0D + Else // Only centered mode is enabled=0D + {=0D + Store(1, PFIT) // so request centered. (No change.)=0D + }=0D + }=0D + }=0D + If(LEqual(Local0, 6)) // If current mode is stretched,=0D + {=0D + If(And(Local1, 8)) // and if aspect ratio is enabled,=0D + {=0D + Store(8, PFIT) // request aspect ratio.=0D + }=0D + Else // Otherwise,=0D + {=0D + If(And(Local1, 1)) // if centered is enabled,=0D + {=0D + Store(1, PFIT) // request centered.=0D + }=0D + Else // Only stretched mode is enabled=0D + {=0D + Store(6, PFIT) // so request stretched. (No change.)=0D + }=0D + }=0D + }=0D + If(LEqual(Local0, 8)) // If current mode is aspect ratio,=0D + {=0D + If(And(Local1, 1)) // and if centered is enabled,=0D + {=0D + Store(1, PFIT) // request centered.=0D + }=0D + Else // Otherwise,=0D + {=0D + If(And(Local1, 6)) // if stretched is enabled,=0D + {=0D + Store(6, PFIT) // request stretched.=0D + }=0D + Else // Only aspect ratio mode is enabled=0D + {=0D + Store(8, PFIT) // so request aspect ratio. (No change.)=0D + }=0D + }=0D + }=0D + }=0D + //=0D + // The following code for panel fitting (within the Else condition) is= retained for backward compatiblity.=0D + //=0D + Else // If CFPM field is zero use PFIT and toggle= the=0D + {=0D + Xor(PFIT,7,PFIT) // mode setting between stretched and center= ed only.=0D + }=0D + Or(PFIT,0x80000000,PFIT) // Set the valid bit for all cases.=0D + Store(4, ASLC) // Store "Panel fitting event" to ASLC[31:1]= =0D + }=0D + Else=0D + {=0D + If(LEqual(Arg0, 1)) // Arg0=3D1, so set the backlight brightness.=0D + {=0D + Store(Divide(Multiply(Arg1, 255), 100), BCLP) // Convert from percen= t to 0-255.=0D + Or(BCLP, 0x80000000, BCLP) // Set the valid bit.=0D + Store(2, ASLC) // Store "Backlight control event" to ASLC[31:1]=0D + }=0D + Else=0D + {=0D + If(LEqual(Arg0, 0)) // Arg0=3D0, so set the ALS illuminace=0D + {=0D + Store(Arg1, ALSI)=0D + Store(1, ASLC) // Store "ALS event" to ASLC[31:1]=0D + }=0D + Else=0D + {=0D + Return(0x1) // Unsupported function=0D + }=0D + }=0D + }=0D +=0D + Store(0x01, ASLE) // Generate ASLE interrupt=0D + Return(0x0) // Return success=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxDsm.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables= /IgfxDsm.asl new file mode 100644 index 0000000000..ecd87e8c1f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxDsm= .asl @@ -0,0 +1,398 @@ +/** @file=0D + IGD OpRegion/_DSM Reference Code.=0D + This file contains Get BIOS Data and Callback functions for=0D + the Integrated Graphics Device (IGD) OpRegion/DSM mechanism=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +External(\_SB.PC00.IMMC, MethodObj)=0D +External(\_SB.PC00.IMMD, MethodObj)=0D +=0D +//=0D +// _DSM Device Specific Method=0D +//=0D +// Arg0: UUID Unique function identifier=0D +// Arg1: Integer Revision Level=0D +// Arg2: Integer Function Index (1 =3D Return Supported Functions)=0D +// Arg3: Additional Inputs/Package Parameters Bits [31:0] input as {Byte0,= Byte1, Byte2, Byte3} to BIOS which is passed as 32 bit DWORD by Driver=0D +//=0D +Method (_DSM, 4, Serialized, 0, UnknownObj, {BuffObj, IntObj, IntObj, PkgO= bj}) {=0D +=0D + If (LEqual(Arg0, ToUUID ("3E5B41C6-EB1D-4260-9D15-C71FBADAE414"))) {=0D + //=0D + // _DSM Definition for Igd functions=0D + // Arguments:=0D + // Arg0: UUID: 3E5B41C6-EB1D-4260-9D15-C71FBADAE414=0D + // Arg1: Revision ID: 1=0D + // Arg2: Function Index: 16=0D + // Arg3: Additional Inputs Bits[31:0] Arg3 {Byte0, Byte1, Byte2, Byte3= }=0D + //=0D + // Return:=0D + // Success for simple notification, Opregion update for some routines = and a Package for AKSV=0D + //=0D + If (Lor(LEqual(Arg2,18),LEqual(Arg2,19))) {=0D + CreateDwordField(Arg3, 0x0, DDIN)=0D + CreateDwordField(Arg3, 0x4, BUF1)=0D + //=0D + // OPTS is return buffer from IOM mailbox -=0D + // Byte[0] is Status field.=0D + // BYTE[1] is HDP Count.=0D + //=0D + Name(OPTS, Buffer(4){0,0,0,0})=0D + CreateByteField(OPTS, 0x00, CMST) // Command Status field=0D + // Success - 0=0D + // Fail - 1=0D + CreateByteField(OPTS, 0x01, RTB1) // Return Buffer 1=0D +=0D + //=0D + // Gfx Empty Dongle Buffer is data for return DSM fun#=0D + // with below buffer format=0D + // Byte[0-3] is Data field.=0D + // Byte[4] is Status field.=0D + //=0D + Name(GEDB, Buffer(5){0,0,0,0,0})=0D + CreateDwordField(GEDB, 0x00, GEDF) // Gfx Empty Dongle Data Field=0D + CreateByteField(GEDB, 0x04, GESF) // Gfx Empty Dongle Status Field= =0D + // Success - 0=0D + // Fail - None 0=0D + }=0D +=0D + //=0D + // Switch by function index=0D + //=0D + Switch(ToInteger(Arg2)) {=0D + //=0D + // Function Index: 0=0D + // Standard query - A bitmask of functions supported=0D + //=0D + // Return: A bitmask of functions supported=0D + //=0D + Case (0)=0D + {=0D + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D + Store("iGfx Supported Functions Bitmap ", Debug)=0D +=0D + Return(0xDE7FF)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 1=0D + // Adapter Power State Notification=0D + // Arg3 Bits [7:0]: Adapter Power State bits [7:0] from Driver 00h = =3D D0; 01h =3D D1; 02h =3D D2; 04h =3D D3 (Cold/Hot); 08h =3D D4 (Hibernat= e Notification)=0D + // Return: Success=0D + //=0D + Case(1) {=0D + If (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D + Store(" Adapter Power State Notification ", Debug)=0D +=0D + //=0D + // Handle Low Power S0 Idle Capability if enabled=0D + //=0D + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {=0D + //=0D + // Call GUAM to trigger CS Entry=0D + // If Adapter Power State Notification =3D D1 (Arg3[0]=3D0x0= 1)=0D + //=0D + If (LEqual (And(DerefOf (Index (Arg3,0)), 0xFF), 0x01)) {=0D + // GUAM - Global User Absent Mode Notification Method=0D + \GUAM(One) // 0x01 - Power State Standby (CS Entry)=0D + }=0D + Store(And(DerefOf (Index (Arg3,1)), 0xFF), Local0)=0D + //=0D + // Call GUAM=0D + // If Display Turn ON Notification (Arg3 [1] =3D=3D 0) for CS = Exit=0D + //=0D + If (LEqual (Local0, 0)) {=0D + // GUAM - Global User Absent Mode Notification Method=0D + \GUAM(0)=0D + }=0D + }=0D +=0D + // Upon notification from driver that the Adapter Power State = =3D D0,=0D + // check if previous lid event failed. If it did, retry the lid= =0D + // event here.=0D + If(LEqual(DerefOf (Index (Arg3,0)), 0)) {=0D + Store(CLID, Local0)=0D + If(And(0x80000000,Local0)) {=0D + And(CLID, 0x0000000F, CLID)=0D + GLID(CLID)=0D + }=0D + }=0D + Return(0x01)=0D + }=0D + }=0D + //=0D + // Function Index: 2=0D + // Display Power State Notification=0D + // Arg3: Display Power State Bits [15:8]=0D + // 00h =3D On=0D + // 01h =3D Standby=0D + // 02h =3D Suspend=0D + // 04h =3D Off=0D + // 08h =3D Reduced On=0D + // Return: Success=0D + //=0D + Case(2) {=0D + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D +=0D + Store("Display Power State Notification ", Debug)=0D + Return(0x01)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 3=0D + // BIOS POST Completion Notification=0D + // Return: Success=0D + //=0D + Case(3) {=0D + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D + Store("BIOS POST Completion Notification ", Debug)=0D + Return(0x01) // Not supported, but no failure=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 4=0D + // Pre-Hires Set Mode=0D + // Return: Success=0D + //=0D + Case(4) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("Pre-Hires Set Mode ", Debug)=0D + Return(0x01) // Not supported, but no failure=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 5=0D + // Post-Hires Set Mode=0D + // Return: Success=0D + //=0D + Case(5) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("Post-Hires Set Mode ", Debug)=0D + Return(0x01) // Not supported, but no failure=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 6=0D + // SetDisplayDeviceNotification (Display Switch)=0D + // Return: Success=0D + //=0D + Case(6) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("SetDisplayDeviceNotification", Debug)=0D + Return(0x01) // Not supported, but no failure=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 7=0D + // SetBootDevicePreference=0D + // Return: Success=0D + //=0D + Case(7) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + // An OEM may elect to implement this method. In that cas= e,=0D + // the input values must be saved into non-volatile storage for= =0D + // parsing during the next boot. The following Sample code is I= ntel=0D + // validated implementation.=0D +=0D + Store("SetBootDevicePreference ", Debug)=0D + And(DerefOf (Index (Arg3,0)), 0xFF, IBTT) // Save the boot displ= ay to NVS=0D + Return(0x01)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 8=0D + // SetPanelPreference=0D + // Return: Success=0D + //=0D + Case(8) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + // An OEM may elect to implement this method. In that case,=0D + // the input values must be saved into non-volatile storage for= =0D + // parsing during the next boot. The following Sample code is I= ntel=0D + // validated implementation.=0D +=0D + Store("SetPanelPreference ", Debug)=0D +=0D + // Set the panel-related NVRAM variables based the input from th= e driver.=0D + And(DerefOf (Index (Arg3,0)), 0xFF, IPSC)=0D +=0D + // Change panel type if a change is requested by the driver (Cha= nge if=0D + // panel type input is non-zero). Zero=3DNo change requested.=0D + If(And(DerefOf (Index (Arg3,1)), 0xFF)) {=0D + And(DerefOf (Index (Arg3,1)), 0xFF, IPAT)=0D + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map=0D + }=0D + And(ShiftRight(DerefOf (Index (Arg3,2)), 4), 0x7, IBIA)=0D + Return(0x01) // Success=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 9=0D + // FullScreenDOS=0D + // Return: Success=0D + //=0D + Case(9) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("FullScreenDOS ", Debug)=0D + Return(0x01) // Not supported, but no failure=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 10=0D + // APM Complete=0D + // Return: Adjusted Lid State=0D + //=0D + Case(10) {=0D + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D +=0D + Store("APM Complete ", Debug)=0D + Store(ShiftLeft(LIDS, 8), Local0) // Report the lid state=0D + Add(Local0, 0x100, Local0) // Adjust the lid state, 0 =3D= Unknown=0D + Return(Local0)=0D + }=0D + }=0D +=0D + //=0D + //=0D + // Function Index: 13=0D + // GetBootDisplayPreference=0D + // Arg3 Bits [30:16] : Boot Device Ports=0D + // Arg3 Bits [7:0] : Boot Device Type=0D + // Return: Boot device port and Boot device type from saved configur= ation=0D + //=0D + Case(13) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D +=0D + Store("GetBootDisplayPreference ", Debug)=0D + Or(ShiftLeft(DerefOf (Index (Arg3,3)), 24), ShiftLeft(DerefOf (I= ndex (Arg3,2)), 16), Local0) // Combine Arg3 Bits [31:16]=0D + And(Local0, 0xEFFF0000, Local0)=0D + And(Local0, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), Local0)=0D + Or(IBTT, Local0, Local0) // Arg3 Bits [7:0] =3D Boot device type= =0D + Return(Local0)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 14=0D + // GetPanelDetails=0D + // Return: Different Panel Settings=0D + //=0D + Case(14) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("GetPanelDetails ", Debug)=0D +=0D + // Report the scaling setting=0D + // Bits [7:0] - Panel Scaling=0D + // Bits contain the panel scaling user setting from CMOS=0D + // 00h =3D On: Auto=0D + // 01h =3D On: Force Scaling=0D + // 02h =3D Off=0D + // 03h =3D Maintain Aspect Ratio=0D +=0D + Store(IPSC, Local0)=0D + Or(Local0, ShiftLeft(IPAT, 8), Local0)=0D +=0D + // Adjust panel type, 0 =3D VBT default=0D + // Bits [15:8] - Panel Type=0D + // Bits contain the panel type user setting from CMOS=0D + // 00h =3D Not Valid, use default Panel Type & Timings from VBT= =0D + // 01h - 0Fh =3D Panel Number=0D +=0D + Add(Local0, 0x100, Local0)=0D +=0D + // Report the lid state and Adjust it=0D + // Bits [16] - Lid State=0D + // Bits contain the current panel lid state=0D + // 0 =3D Lid Open=0D + // 1 =3D Lid Closed=0D +=0D + Or(Local0, ShiftLeft(LIDS, 16), Local0)=0D + Add(Local0, 0x10000, Local0)=0D +=0D + // Report the BIA setting=0D + // Bits [22:20] - Backlight Image Adaptation (BIA) Control=0D + // Bits contain the backlight image adaptation control user setti= ng from CMOS=0D + // 000 =3D VBT Default=0D + // 001 =3D BIA Disabled (BLC may still be enabled)=0D + // 010 - 110 =3D BIA Enabled at Aggressiveness Level [1 - 5]=0D +=0D + Or(Local0, ShiftLeft(IBIA, 20), Local0)=0D + Return(Local0)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 15=0D + // GetInternalGraphics=0D + // Return: Different Internal Grahics Settings=0D + //=0D +=0D + Case(15) {=0D + if (LEqual(Arg1, 1)){ // test Arg1 for Revision ID: 1=0D + Store("GetInternalGraphics ", Debug)=0D +=0D + Store(GIVD, Local0) // Local0[0] - VGA m= ode(1=3DVGA)=0D + Xor(Local0, 1, Local0) // Invert the VGA mode po= larity=0D +=0D + Or(Local0, ShiftLeft(GMFN, 1), Local0) // Local0[1] - # IGD= PCI functions-1=0D + // Local0[3:2] - Reser= ved=0D + // Local0[4] - IGD D= 3 support(0=3Dcold)=0D + // Local0[10:5] - Reser= ved=0D + Or(Local0, ShiftLeft(3, 11), Local0) // Local0[12:11] - DVMT = version (11b =3D 5.0)=0D +=0D + //=0D + // Report DVMT 5.0 Total Graphics memory size.=0D + //=0D + Or(Local0, ShiftLeft(IDMS, 17), Local0) // Bits 20:17 are for Gf= x total memory size=0D +=0D + // If the "Set Internal Graphics" call is supported, the modifie= d=0D + // settings flag must be programmed per the specification. This= means=0D + // that the flag must be set to indicate that system BIOS reques= ts=0D + // these settings. Once "Set Internal Graphics" is called, the= =0D + // modified settings flag must be cleared on all subsequent cal= ls to=0D + // this function.=0D +=0D + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Mu= st=0D + // take into account the current VCO.=0D +=0D + Or(ShiftLeft(DeRefOf(Index(DeRefOf(Index(CDCT, HVCO)), CDVL)), 2= 1),Local0, Local0)=0D + Return(Local0)=0D + }=0D + }=0D +=0D + //=0D + // Function Index: 16=0D + // GetAKSV=0D + // Retrun: 5 bytes of AKSV=0D + //=0D + Case(16) {=0D + if (LEqual(Arg1, 1)) { // test Arg1 for Revision ID: 1=0D +=0D + Store("GetAKSV ", Debug)=0D + Name (KSVP, Package()=0D + {=0D + 0x80000000,=0D + 0x8000=0D + })=0D + Store(KSV0, Index(KSVP,0)) // First four bytes of AKSV=0D + Store(KSV1, Index(KSVP,1)) // Fifth byte of AKSV=0D + Return(KSVP) // Success=0D + }=0D + }=0D + } // End of switch(Arg2)=0D + } // End of if (ToUUID("3E5B41C6-EB1D-4260-9D15-C71FBADAE414D"))=0D +=0D + Return (Buffer () {0x00})=0D +} // End of _DSM=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxOpGbda.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTab= les/IgfxOpGbda.asl new file mode 100644 index 0000000000..2b5f2393b0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpG= bda.asl @@ -0,0 +1,127 @@ +/** @file=0D + IGD OpRegion/Software SCI Reference Code.=0D + This file contains Get BIOS Data Area funciton support for=0D + the Integrated Graphics Device (IGD) OpRegion/Software SCI mechanism=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +Method (GBDA, 0, Serialized)=0D +{=0D + //=0D + // Supported calls: Sub-function 0=0D + //=0D + If (LEqual(GESF, 0))=0D + {=0D + //=0D + // Reference code is set to Intel's validated implementation.=0D + //=0D + Store(0x0000659, PARM)=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Requested callbacks: Sub-function 1=0D + //=0D + If (LEqual(GESF, 1))=0D + {=0D + //=0D + // Call back functions are where the driver calls the=0D + // system BIOS at function indicated event.=0D + //=0D + Store(0x300482, PARM)=0D + If(LEqual(S0ID, One)){=0D + Or(PARM, 0x100, PARM) //Request Fn 8 callback in CS systems=0D + }=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Get Boot display Preferences: Sub-function 4=0D + //=0D + If (LEqual(GESF, 4))=0D + {=0D + //=0D + // Get Boot Display Preferences function.=0D + //=0D + And(PARM, 0xEFFF0000, PARM) // PARM[30:16] =3D Boot device ports=0D + And(PARM, ShiftLeft(DeRefOf(Index(DBTB, IBTT)), 16), PARM)=0D + Or(IBTT, PARM, PARM) // PARM[7:0] =3D Boot device type=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Panel details: Sub-function 5=0D + //=0D + If (LEqual(GESF, 5))=0D + {=0D + //=0D + // Get Panel Details function.=0D + //=0D + Store(IPSC, PARM) // Report the scaling setting=0D + Or(PARM, ShiftLeft(IPAT, 8), PARM)=0D + Add(PARM, 0x100, PARM) // Adjust panel type, 0 =3D VBT default=0D + Or(PARM, ShiftLeft(LIDS, 16), PARM) // Report the lid state=0D + Add(PARM, 0x10000, PARM) // Adjust the lid state, 0 =3D Unknown=0D + Or(PARM, ShiftLeft(IBIA, 20), PARM) // Report the BIA setting=0D + Store(Zero, GESF)=0D + Return(SUCC)=0D + }=0D + //=0D + // Internal graphics: Sub-function 7=0D + //=0D + If (LEqual(GESF, 7))=0D + {=0D + Store(GIVD, PARM) // PARM[0] - VGA mode(1=3DVGA)=0D + Xor(PARM, 1, PARM) // Invert the VGA mode polarity=0D + Or(PARM, ShiftLeft(GMFN, 1), PARM) // PARM[1] - # IGD PCI functions-= 1=0D + // PARM[3:2] - Reserved=0D + // PARM[4] - IGD D3 support(0= =3Dcold)=0D + // PARM[10:5] - Reserved=0D + Or(PARM, ShiftLeft(3, 11), PARM) // PARM[12:11] - DVMT mode(11b =3D 5.= 0)=0D +=0D + //=0D + // Report DVMT 5.0 Total Graphics memory size.=0D + //=0D + Or(PARM, ShiftLeft(IDMS, 17), PARM) // Bits 20:17 are for Gfx total me= mory size=0D + //=0D + // If the "Set Internal Graphics" call is supported, the modified=0D + // settings flag must be programmed per the specification. This means= =0D + // that the flag must be set to indicate that system BIOS requests=0D + // these settings. Once "Set Internal Graphics" is called, the=0D + // modified settings flag must be cleared on all subsequent calls to= =0D + // this function.=0D + // Report the graphics frequency based on B0:D2:F0:RF0h[12]. Must=0D + // take into account the current VCO.=0D + //=0D + Or(ShiftLeft(Derefof(Index(Derefof(Index(CDCT, HVCO)), CDVL)), 21),PAR= M, PARM)=0D + Store(1, GESF) // Set the modified settings flag=0D + Return(SUCC)=0D + }=0D + //=0D + // Spread spectrum clocks: Sub-function 10=0D + //=0D + If (LEqual(GESF, 10))=0D + {=0D + Store(0, PARM) // Assume SSC is disabled=0D + If(ISSC)=0D + {=0D + Or(PARM, 3, PARM) // If SSC enabled, return SSC1+Enabled=0D + }=0D + Store(0, GESF) // Set the modified settings flag=0D + Return(SUCC) // Success=0D + }=0D +=0D + If (LEqual(GESF, 11))=0D + {=0D + Store(KSV0, PARM) // First four bytes of AKSV=0D + Store(KSV1, GESF) // Fifth byte of AKSV=0D +=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // A call to a reserved "Get BIOS data" function was received.=0D + //=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(CRIT) // Reserved, "Critical failure"=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxOpRn.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTable= s/IgfxOpRn.asl new file mode 100644 index 0000000000..410524b324 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpR= n.asl @@ -0,0 +1,314 @@ +/** @file=0D + IGD OpRegion/Software SCI Reference Code.=0D + This file contains the interrupt handler code for the Integrated=0D + Graphics Device (IGD) OpRegion/Software SCI mechanism.=0D + It defines OperationRegions to cover the IGD PCI configuration space=0D + as described in the IGD OpRegion specification.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +//=0D +//NOTES:=0D +//=0D +// (1) The code contained in this file inherits the scope in which it=0D +// was included. So BIOS developers must be sure to include this=0D +// file in the scope associated with the graphics device=0D +// (ex. \_SB.PC00.GFX0).=0D +// (2) Create a _L06 method under the GPE scope to handle the event=0D +// generated by the graphics driver. The _L06 method must call=0D +// the GSCI method in this file.=0D +// (3) The MCHP operation region assumes that _ADR and _BBN names=0D +// corresponding to bus 0, device0, function 0 have been declared=0D +// under the PC00 scope.=0D +// (4) Before the first execution of the GSCI method, the base address=0D +// of the GMCH SCI OpRegion must be programmed where the driver can=0D +// access it. A 32bit scratch register at 0xFC in the IGD PCI=0D +// configuration space (B0/D2/F0/R0FCh) is used for this purpose.=0D +=0D +// Define an OperationRegion to cover the GMCH PCI configuration space as= =0D +// described in the IGD OpRegion specificiation.=0D +//=0D +Scope(\_SB.PC00)=0D +{=0D + OperationRegion(MCHP, PCI_Config, 0x40, 0xC0)=0D + Field(MCHP, AnyAcc, NoLock, Preserve)=0D + {=0D + Offset(0x14),=0D + AUDE, 8,=0D +=0D + Offset(0x60), // Top of Memory register=0D + TASM, 10, // Total system memory (64MB gran)=0D + , 6,=0D + }=0D +}=0D +=0D +//=0D +// Define an OperationRegion to cover the IGD PCI configuration space as= =0D +// described in the IGD OpRegion specificiation.=0D +//=0D +OperationRegion(IGDP, PCI_Config, 0x40, 0xC0)=0D +Field(IGDP, AnyAcc, NoLock, Preserve)=0D +{=0D + Offset(0x10), // Mirror of gfx control reg=0D + , 1,=0D + GIVD, 1, // IGD VGA disable bit=0D + , 2,=0D + GUMA, 3, // Stolen memory size=0D + , 9,=0D + Offset(0x14),=0D + , 4,=0D + GMFN, 1, // Gfx function 1 enable=0D + , 27,=0D + Offset(0xA4),=0D + ASLE, 8, // Reg 0xE4, ASLE interrupt register=0D + , 24, // Only use first byte of ASLE reg=0D + Offset(0xA8), // Reg 0xE8, SWSCI control register=0D + GSSE, 1, // Graphics SCI event (1=3Devent pending)=0D + GSSB, 14, // Graphics SCI scratchpad bits=0D + GSES, 1, // Graphics event select (1=3DSCI)=0D + Offset(0xB0), // Gfx Clk Frequency and Gating Control=0D + , 12,=0D + CDVL, 1, // Core display clock value=0D + , 3, // Graphics Core Display Clock Select=0D + Offset(0xB5),=0D + LBPC, 8, // Legacy brightness control=0D + Offset(0xBC),=0D + ASLS, 32, // Reg 0xFC, Address of the IGD OpRegion=0D +}=0D +=0D +//=0D +// Define an OperationRegion to cover the IGD OpRegion layout.=0D +//=0D +OperationRegion(IGDM, SystemMemory, ASLB, 0x2000)=0D +Field(IGDM, AnyAcc, NoLock, Preserve)=0D +{=0D + //=0D + // OpRegion Header=0D + //=0D + SIGN, 128, // Signature-"IntelGraphicsMem"=0D + SIZE, 32, // OpRegion Size=0D + OVER, 32, // OpRegion Version=0D + SVER, 256, // System BIOS Version=0D + VVER, 128, // VBIOS Version=0D + GVER, 128, // Driver version=0D + MBOX, 32, // Mailboxes supported=0D + DMOD, 32, // Driver Model=0D + PCON, 32, // Platform Configuration=0D + DVER, 64, // GOP Version=0D + //=0D + // OpRegion Mailbox 1 (Public ACPI Methods)=0D + // Note: Mailbox 1 is normally reserved for desktop platforms.=0D + //=0D + Offset(0x100),=0D + DRDY, 32, // Driver readiness (ACPI notification)=0D + CSTS, 32, // Notification status=0D + CEVT, 32, // Current event=0D + Offset(0x120),=0D + DIDL, 32, // Supported display device ID list=0D + DDL2, 32, // Allows for 8 devices=0D + DDL3, 32,=0D + DDL4, 32,=0D + DDL5, 32,=0D + DDL6, 32,=0D + DDL7, 32,=0D + DDL8, 32,=0D + CPDL, 32, // Currently present display list=0D + CPL2, 32, // Allows for 8 devices=0D + CPL3, 32,=0D + CPL4, 32,=0D + CPL5, 32,=0D + CPL6, 32,=0D + CPL7, 32,=0D + CPL8, 32,=0D + CADL, 32, // Currently active display list=0D + CAL2, 32, // Allows for 8 devices=0D + CAL3, 32,=0D + CAL4, 32,=0D + CAL5, 32,=0D + CAL6, 32,=0D + CAL7, 32,=0D + CAL8, 32,=0D + NADL, 32, // Next active display list=0D + NDL2, 32, // Allows for 8 devices=0D + NDL3, 32,=0D + NDL4, 32,=0D + NDL5, 32,=0D + NDL6, 32,=0D + NDL7, 32,=0D + NDL8, 32,=0D + ASLP, 32, // ASL sleep timeout=0D + TIDX, 32, // Toggle table index=0D + CHPD, 32, // Current hot plug enable indicator=0D + CLID, 32, // Current lid state indicator=0D + CDCK, 32, // Current docking state indicator=0D + SXSW, 32, // Display switch notify on resume=0D + EVTS, 32, // Events supported by ASL (diag only)=0D + CNOT, 32, // Current OS notifications (diag only)=0D + NRDY, 32,=0D + //=0D + //Extended DIDL list=0D + //=0D + DDL9, 32,=0D + DD10, 32,=0D + DD11, 32,=0D + DD12, 32,=0D + DD13, 32,=0D + DD14, 32,=0D + DD15, 32,=0D + //=0D + //Extended Currently attached Display Device List CPD2=0D + //=0D + CPL9, 32,=0D + CP10, 32,=0D + CP11, 32,=0D + CP12, 32,=0D + CP13, 32,=0D + CP14, 32,=0D + CP15, 32,=0D + //=0D + // OpRegion Mailbox 2 (Software SCI Interface)=0D + //=0D + Offset(0x200), // SCIC=0D + SCIE, 1, // SCI entry bit (1=3Dcall unserviced)=0D + GEFC, 4, // Entry function code=0D + GXFC, 3, // Exit result=0D + GESF, 8, // Entry/exit sub-function/parameter=0D + , 16, // SCIC[31:16] reserved=0D + Offset(0x204), // PARM=0D + PARM, 32, // PARM register (extra parameters)=0D + DSLP, 32, // Driver sleep time out=0D + //=0D + // OpRegion Mailbox 3 (BIOS to Driver Notification)=0D + // Note: Mailbox 3 is normally reserved for desktop platforms.=0D + //=0D + Offset(0x300),=0D + ARDY, 32, // Driver readiness (power conservation)=0D + ASLC, 32, // ASLE interrupt command/status=0D + TCHE, 32, // Technology enabled indicator=0D + ALSI, 32, // Current ALS illuminance reading=0D + BCLP, 32, // Backlight brightness=0D + PFIT, 32, // Panel fitting state or request=0D + CBLV, 32, // Current brightness level=0D + BCLM, 320, // Backlight brightness level duty cycle mapping table=0D + CPFM, 32, // Current panel fitting mode=0D + EPFM, 32, // Enabled panel fitting modes=0D + PLUT, 592, // Optional. 74-byte Panel LUT Table=0D + PFMB, 32, // Optional. PWM Frequency and Minimum Brightness=0D + CCDV, 32, // Optional. Gamma, Brightness, Contrast values.=0D + PCFT, 32, // Optional. Power Conservation Features=0D + SROT, 32, // Supported rotation angle.=0D + IUER, 32, // Optional. Intel Ultrabook Event Register.=0D + FDSS, 64, // Optional. FFS Display Physical address=0D + FDSP, 32, // Optional. FFS Display Size=0D + STAT, 32, // State Indicator=0D + RVDA, 64, // Physical address of Raw VBT data=0D + RVDS, 32, // Size of Raw VBT data=0D + //=0D + // OpRegion Mailbox 4 (VBT)=0D + //=0D + Offset(0x400),=0D + RVBT, 0xC000, // 6K bytes maximum VBT image=0D + //=0D + // OpRegion Mailbox 5 (BIOS to Driver Notification Extension)=0D + //=0D + Offset(0x1C00),=0D + PHED, 32, // Panel Header=0D + BDDC, 2048, // Panel EDID (Max 256 bytes)=0D +=0D +}=0D +=0D +//=0D +// Convert boot display type into a port mask.=0D +//=0D +Name (DBTB, Package()=0D +{=0D + 0x0000, // Automatic=0D + 0x0007, // Port-0 : Integrated CRT=0D + 0x0038, // Port-1 : DVO-A, or Integrated LVDS=0D + 0x01C0, // Port-2 : SDVO-B, or SDVO-B/C=0D + 0x0E00, // Port-3 : SDVO-C=0D + 0x003F, // [CRT + DVO-A / Integrated LVDS]=0D + 0x01C7, // [CRT + SDVO-B] or [CRT + SDVO-B/C]=0D + 0x0E07, // [CRT + SDVO-C]=0D + 0x01F8, // [DVO-A / Integrated LVDS + SDVO-B]=0D + 0x0E38, // [DVO-A / Integrated LVDS + SDVO-C]=0D + 0x0FC0, // [SDVO-B + SDVO-C]=0D + 0x0000, // Reserved=0D + 0x0000, // Reserved=0D + 0x0000, // Reserved=0D + 0x0000, // Reserved=0D + 0x0000, // Reserved=0D + 0x7000, // Port-4: Integrated TV=0D + 0x7007, // [Integrated TV + CRT]=0D + 0x7038, // [Integrated TV + LVDS]=0D + 0x71C0, // [Integrated TV + DVOB]=0D + 0x7E00 // [Integrated TV + DVOC]=0D +})=0D +=0D +//=0D +// Core display clock value table.=0D +//=0D +Name (CDCT, Package()=0D +{=0D + Package() {228, 320},=0D + Package() {222, 333},=0D + Package() {222, 333},=0D + Package() { 0, 0},=0D + Package() {222, 333},=0D +})=0D +=0D +//=0D +// Defined exit result values:=0D +//=0D +Name (SUCC, 1) // Exit result: Success=0D +Name (NVLD, 2) // Exit result: Invalid parameter=0D +Name (CRIT, 4) // Exit result: Critical failure=0D +Name (NCRT, 6) // Exit result: Non-critical failure=0D +=0D +/************************************************************************;= =0D +;*=0D +;* Name: GSCI=0D +;*=0D +;* Description: Handles an SCI generated by the graphics driver. The=0D +;* PARM and SCIC input fields are parsed to determine the=0D +;* functionality requested by the driver. GBDA or SBCB=0D +;* is called based on the input data in SCIC.=0D +;*=0D +;* Usage: The method must be called in response to a GPE 06 event=0D +;* which will be generated by the graphics driver.=0D +;* Ex: Method(\_GPE._L06) {Return(\_SB.PC00.GFX0.GSCI())}=0D +;*=0D +;* Input: PARM and SCIC are indirect inputs=0D +;*=0D +;* Output: PARM and SIC are indirect outputs=0D +;*=0D +;* References: GBDA (Get BIOS Data method), SBCB (System BIOS Callback=0D +;* method)=0D +;*=0D +;************************************************************************/= =0D +=0D +Method (GSCI, 0, Serialized)=0D +{=0D + Include("IgfxOpGbda.asl") // "Get BIOS Data" Functions=0D + Include("IgfxOpSbcb.asl") // "System BIOS CallBacks"=0D +=0D + If (LEqual(GEFC, 4))=0D + {=0D + Store(GBDA(), GXFC) // Process Get BIOS Data functions=0D + }=0D +=0D + If (LEqual(GEFC, 6))=0D + {=0D + Store(SBCB(), GXFC) // Process BIOS Callback functions=0D + }=0D +=0D + Store(0, GEFC) // Wipe out the entry function code=0D + Store(1, CPSC) // Clear CPUSCI_STS to clear the PCH TCO SCI st= atus=0D + Store(0, GSSE) // Clear the SCI generation bit in PCI space.=0D + Store(0, SCIE) // Clr SCI serviced bit to signal completion=0D +=0D + Return(Zero)=0D +}=0D +=0D +Include("IgfxCommon.asl") // IGD SCI mobile features=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxOpSbcb.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTab= les/IgfxOpSbcb.asl new file mode 100644 index 0000000000..3c5d4d9862 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxOpS= bcb.asl @@ -0,0 +1,261 @@ +/** @file=0D + This file contains the system BIOS call back functionality for the=0D + OpRegion/Software SCI mechanism.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +Method (SBCB, 0, Serialized)=0D +{=0D + //=0D + // Supported Callbacks: Sub-function 0=0D + //=0D + If (LEqual(GESF, 0x0))=0D + {=0D + //=0D + // An OEM may support the driver->SBIOS status callbacks, but=0D + // the supported callbacks value must be modified. The code that is=0D + // executed upon reception of the callbacks must be also be updated=0D + // to perform the desired functionality.=0D + //=0D + Store(0x00000000, PARM) // No callbacks supported=0D + //Store(0x000787FD, PARM) // Used for Intel test implementaion=0D + Store(0x000F87DD, PARM)=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // "Success"=0D + }=0D + //=0D + // BIOS POST Completion: Sub-function 1=0D + //=0D + If (LEqual(GESF, 1))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Pre-Hires Set Mode: Sub-function 3=0D + //=0D + If (LEqual(GESF, 3))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Post-Hires Set Mode: Sub-function 4=0D + //=0D + If (LEqual(GESF, 4))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Display Switch: Sub-function 5=0D + //=0D + If (LEqual(GESF, 5))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Adapter Power State: Sub-function 7=0D + //=0D + If (LEqual(GESF, 7))=0D + {=0D + //=0D + // Handle Low Power S0 Idle Capability if enabled=0D + //=0D + If(LAnd(LEqual(S0ID, 1),LLess(OSYS, 2015))) {=0D + //=0D + // Call GUAM to trigger CS Entry=0D + // If Adapter Power State Notification =3D D1 (PARM[7:0]=3D0x01)=0D + //=0D + If (LEqual (And(PARM,0xFF), 0x01)) {=0D + // GUAM - Global User Absent Mode Notification Method=0D + \GUAM(One) // 0x01 - Power State Standby (CS Entry)=0D + }=0D + If (LEqual (And(PARM,0xFF), 0x00)) {=0D + // GUAM - Global User Absent Mode Notification Method=0D + \GUAM(0)=0D + }=0D + }=0D + //=0D + // Upon notification from driver that the Adapter Power State =3D D0,= =0D + // check if previous lid event failed. If it did, retry the lid=0D + // event here.=0D + //=0D + If(LEqual(PARM, 0))=0D + {=0D + Store(CLID, Local0)=0D + If(And(0x80000000,Local0))=0D + {=0D + And(CLID, 0x0000000F, CLID)=0D + GLID(CLID)=0D + }=0D + }=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Display Power State: Sub-function 8=0D + //=0D + If (LEqual(GESF, 8))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Set Boot Display: Sub-function 9=0D + //=0D + If (LEqual(GESF, 9))=0D + {=0D + //=0D + // An OEM may elect to implement this method. In that case,=0D + // the input values must be saved into non-volatile storage for=0D + // parsing during the next boot. The following Sample code is Intel=0D + // validated implementation.=0D + //=0D + And(PARM, 0xFF, IBTT) // Save the boot display to NVS=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Reserved, "Critical failure"=0D + }=0D + //=0D + // Set Panel Details: Sub-function 10 (0Ah)=0D + //=0D + If (LEqual(GESF, 10))=0D + {=0D + //=0D + // An OEM may elect to implement this method. In that case,=0D + // the input values must be saved into non-volatile storage for=0D + // parsing during the next boot. The following Sample code is Intel=0D + // validated implementation.=0D + // Set the panel-related NVRAM variables based the input from the driv= er.=0D + //=0D + And(PARM, 0xFF, IPSC)=0D + //=0D + // Change panel type if a change is requested by the driver (Change if= =0D + // panel type input is non-zero). Zero=3DNo change requested.=0D + //=0D + If(And(ShiftRight(PARM, 8), 0xFF))=0D + {=0D + And(ShiftRight(PARM, 8), 0xFF, IPAT)=0D + Decrement(IPAT) // 0 =3D no change, so fit to CMOS map=0D + }=0D + And(ShiftRight(PARM, 20), 0x7, IBIA)=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Set Internal Graphics: Sub-function 11 (0Bh)=0D + //=0D + If (LEqual(GESF, 11))=0D + {=0D + //=0D + // An OEM may elect to implement this method. In that case,=0D + // the input values must be saved into non-volatile storage for=0D + // parsing during the next boot. The following Sample code is Intel=0D + // validated implementation.=0D + //=0D + And(ShiftRight(PARM, 1), 1, IF1E) // Program the function 1 optio= n=0D + If(And(PARM, ShiftLeft(0xF, 13))) // Use fixed memory if fixed si= ze !=3D 0=0D + {=0D + //=0D + // Fixed memory=0D + //=0D + And(ShiftRight(PARM, 13), 0xF, IDMS) // Program fixed memory size=0D + }=0D + Else=0D + {=0D + //=0D + // DVMT memory=0D + //=0D + And(ShiftRight(PARM, 17), 0xF, IDMS) // Program fixed memory size=0D + }=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Post-Hires to DOS FS: Sub-function 16 (10h)=0D + //=0D + If (LEqual(GESF, 16))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // APM Complete: Sub-function 17 (11h)=0D + //=0D + If (LEqual(GESF, 17))=0D + {=0D + Store(ShiftLeft(LIDS, 8), PARM) // Report the lid state=0D + Add(PARM, 0x100, PARM) // Adjust the lid state, 0 =3D Unknown= =0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Set Spread Spectrum Clocks: Sub-function 18 (12h)=0D + //=0D + If (LEqual(GESF, 18))=0D + {=0D + //=0D + // An OEM may elect to implement this method. In that case,=0D + // the input values must be saved into non-volatile storage for=0D + // parsing during the next boot. The following Sample code is Intel=0D + // validated implementation.=0D + //=0D + If(And(PARM, 1))=0D + {=0D + If(LEqual(ShiftRight(PARM, 1), 1))=0D + {=0D + Store(1, ISSC) // Enable HW SSC, only for clock 1=0D + }=0D + Else=0D + {=0D + Store(Zero, GESF)=0D + Return(CRIT) // Failure, as the SSC clock must be 1=0D + }=0D + }=0D + Else=0D + {=0D + Store(0, ISSC) // Disable SSC=0D + }=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Success=0D + }=0D + //=0D + // Post VBE/PM Callback: Sub-function 19 (13h)=0D + //=0D + If (LEqual(GESF, 19))=0D + {=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Not supported, but no failure=0D + }=0D + //=0D + // Set PAVP Data: Sub-function 20 (14h)=0D + //=0D + If (LEqual(GESF, 20))=0D + {=0D + And(PARM, 0xF, PAVP) // Store PAVP info=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Store(Zero, PARM)=0D + Return(SUCC) // Success=0D + }=0D +=0D + //=0D + // A call to a reserved "System BIOS callbacks" function was received=0D + //=0D + Store(Zero, GESF) // Clear the exit parameter=0D + Return(SUCC) // Reserved, "Critical failure"=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxSsdt.asl b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTable= s/IgfxSsdt.asl new file mode 100644 index 0000000000..99130a853d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsd= t.asl @@ -0,0 +1,73 @@ +/** @file=0D + This file contains the Intel Graphics SSDT Table ASL code.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +DefinitionBlock (=0D + "IgfxSsdt.aml",=0D + "SSDT",=0D + 2,=0D + "INTEL ",=0D + "IgfxSsdt",=0D + 0x3000=0D + )=0D +{=0D + External(\_SB.PC00, DeviceObj)=0D + External(\_SB.PC00.GFX0, DeviceObj)=0D + External(\NDID)=0D + External(\DID1)=0D + External(\DID2)=0D + External(\DID3)=0D + External(\DID4)=0D + External(\DID5)=0D + External(\DID6)=0D + External(\DID7)=0D + External(\DID8)=0D + External(\DID9)=0D + External(\DIDA)=0D + External(\DIDB)=0D + External(\DIDC)=0D + External(\DIDD)=0D + External(\DIDE)=0D + External(\DIDF)=0D + External(\DIDX)=0D + External(\DIDY)=0D +=0D + External(\NXD1)=0D + External(\NXD2)=0D + External(\NXD3)=0D + External(\NXD4)=0D + External(\NXD5)=0D + External(\NXD6)=0D + External(\NXD7)=0D + External(\NXD8)=0D + External(\NXDY)=0D +=0D + External(\IPTP)=0D + External(\EDPV)=0D + External(\NXDX)=0D + External(\HGMD)=0D + External(\LIDS)=0D + External(\BRTL)=0D + External(\NSTE)=0D + External(\CSTE)=0D + External(\ASLB)=0D + External(\IBTT)=0D + External(\IPSC)=0D + External(\IPAT)=0D + External(\IBIA)=0D + External(\IDMS)=0D + External(\HVCO)=0D + External(\ISSC)=0D + External(\KSV0)=0D + External(\KSV1)=0D + External(\IF1E)=0D + External(\PAVP)=0D +=0D + Scope (\_SB.PC00.GFX0)=0D + {=0D + include("Igfx.asl")=0D + }=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/= IgfxSsdt.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTable= s/IgfxSsdt.inf new file mode 100644 index 0000000000..be28157cef --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/AcpiTables/IgfxSsd= t.inf @@ -0,0 +1,23 @@ +## @file=0D +# Component description file for the Igfx ACPI tables=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010005=0D +BASE_NAME =3D IgfxSsdt=0D +FILE_GUID =3D CE9CAA0E-8248-442C-9E57-50F212E2BAED=0D +MODULE_TYPE =3D USER_DEFINED=0D +VERSION_STRING =3D 1.0=0D +=0D +[Sources]=0D + IgfxSsdt.asl=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[FixedPcd]=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePriv= ate/Library/DxeGraphicsInitLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBloc= k/Graphics/IncludePrivate/Library/DxeGraphicsInitLib.h new file mode 100644 index 0000000000..0e9f119763 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Lib= rary/DxeGraphicsInitLib.h @@ -0,0 +1,53 @@ +/** @file=0D + Header file for DXE Graphics Init Lib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DXE_GRAPHICS_INIT_LIB_H_=0D +#define _DXE_GRAPHICS_INIT_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Initialize GT ACPI tables=0D +=0D + @param[in] ImageHandle - Handle for the image of this driver=0D + @param[in] SaPolicy - SA DXE Policy protocol=0D +=0D + @retval EFI_SUCCESS - GT ACPI initialization complete=0D + @retval EFI_NOT_FOUND - Dxe System Table not found.=0D + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully.=0D +**/=0D +EFI_STATUS=0D +GraphicsInit (=0D + IN EFI_HANDLE ImageHandle,=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + );=0D +=0D +/**=0D + Do Post GT PM Init Steps after VBIOS Initialization.=0D +=0D + @retval EFI_SUCCESS Succeed.=0D +**/=0D +EFI_STATUS=0D +PostPmInitEndOfDxe (=0D + VOID=0D + );=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePriv= ate/Library/DxeGraphicsPolicyLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBl= ock/Graphics/IncludePrivate/Library/DxeGraphicsPolicyLib.h new file mode 100644 index 0000000000..abb5dffc45 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Lib= rary/DxeGraphicsPolicyLib.h @@ -0,0 +1,71 @@ +/** @file=0D + Header file for the DXE Graphics Policy Init library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DXE_GRAPHICS_POLICY_LIB_H_=0D +#define _DXE_GRAPHICS_POLICY_LIB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define WORD_FIELD_VALID_BIT BIT15=0D +=0D +extern EFI_GUID gGraphicsDxeConfigGuid;=0D +=0D +/**=0D + This function prints the Graphics DXE phase policy.=0D +=0D + @param[in] SaPolicy - SA DXE Policy protocol=0D +**/=0D +VOID=0D +GraphicsDxePolicyPrint (=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + );=0D +=0D +/**=0D + This function Load default Graphics DXE policy.=0D +=0D + @param[in] ConfigBlockPointer The pointer to add Graphics config bloc= k=0D +**/=0D +VOID=0D +LoadIgdDxeDefault (=0D + IN VOID *ConfigBlockPointer=0D + );=0D +=0D +=0D +/**=0D + Get DXE Graphics config block table total size.=0D +=0D + @retval Size of DXE Graphics config block table=0D +**/=0D +UINT16=0D +EFIAPI=0D +GraphicsGetConfigBlockTotalSizeDxe (=0D + VOID=0D + );=0D +=0D +/**=0D + GraphicsAddConfigBlocksDxe add all DXE Graphics config block.=0D +=0D + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GraphicsAddConfigBlocksDxe (=0D + IN VOID *ConfigBlockTableAddress=0D + );=0D +=0D +#endif // _DXE_GRAPHICs_POLICY_LIBRARY_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePriv= ate/Library/DxeIgdOpRegionInitLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpB= lock/Graphics/IncludePrivate/Library/DxeIgdOpRegionInitLib.h new file mode 100644 index 0000000000..683893f940 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/IncludePrivate/Lib= rary/DxeIgdOpRegionInitLib.h @@ -0,0 +1,177 @@ +/** @file=0D + This is part of the implementation of an Intel Graphics drivers OpRegion= /=0D + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _DXE_IGD_OPREGION_INIT_LIB_H_=0D +#define _DXE_IGD_OPREGION_INIT_LIB_H_=0D +=0D +///=0D +/// Statements that include other header files.=0D +///=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +///=0D +/// Driver Consumed Protocol Prototypes=0D +///=0D +#include =0D +#include =0D +#include =0D +#include =0D +///=0D +/// Driver Produced Protocol Prototypes=0D +///=0D +#include =0D +=0D +#pragma pack(push, 1)=0D +///=0D +///=0D +/// OpRegion (Miscellaneous) defines.=0D +///=0D +/// OpRegion Header defines.=0D +///=0D +typedef UINT16 STRING_REF;=0D +#define HEADER_SIGNATURE "IntelGraphicsMem"=0D +#define HEADER_SIZE 0x2000=0D +#define HEADER_OPREGION_REV 0x00=0D +#define HEADER_MBOX_SUPPORT (HD_MBOX5 + HD_MBOX4 + HD_MBOX3 + HD_M= BOX2 + HD_MBOX1)=0D +#define HD_MBOX1 BIT0=0D +#define HD_MBOX2 BIT1=0D +#define HD_MBOX3 BIT2=0D +#define HD_MBOX4 BIT3=0D +#define HD_MBOX5 BIT4=0D +#define SVER_SIZE 32=0D +=0D +///=0D +/// OpRegion Mailbox 1 EQUates.=0D +///=0D +/// OpRegion Mailbox 3 EQUates.=0D +///=0D +#define ALS_ENABLE BIT0=0D +#define BACKLIGHT_BRIGHTNESS 0xFF=0D +#define FIELD_VALID_BIT BIT31=0D +#define PFIT_ENABLE BIT2=0D +#define PFIT_OPRN_AUTO 0x00000000=0D +#define PFIT_OPRN_SCALING 0x00000007=0D +#define PFIT_OPRN_OFF 0x00000000=0D +#define PFIT_SETUP_AUTO 0=0D +#define PFIT_SETUP_SCALING 1=0D +#define PFIT_SETUP_OFF 2=0D +#define INIT_BRIGHT_LEVEL 0x64=0D +#define PFIT_STRETCH 6=0D +=0D +///=0D +/// Video BIOS / VBT defines=0D +///=0D +#define OPTION_ROM_SIGNATURE 0xAA55=0D +#define VBIOS_LOCATION_PRIMARY 0xC0000=0D +=0D +#define VBT_SIGNATURE SIGNATURE_32 ('$', 'V', 'B', 'T')=0D +///=0D +/// Typedef stuctures=0D +///=0D +typedef struct {=0D + UINT16 Signature; /// 0xAA55=0D + UINT8 Size512;=0D + UINT8 Reserved[21];=0D + UINT16 PcirOffset;=0D + UINT16 VbtOffset;=0D +} INTEL_VBIOS_OPTION_ROM_HEADER;=0D +=0D +typedef struct {=0D + UINT32 Signature; /// "PCIR"=0D + UINT16 VendorId; /// 0x8086=0D + UINT16 DeviceId;=0D + UINT16 Reserved0;=0D + UINT16 Length;=0D + UINT8 Revision;=0D + UINT8 ClassCode[3];=0D + UINT16 ImageLength;=0D + UINT16 CodeRevision;=0D + UINT8 CodeType;=0D + UINT8 Indicator;=0D + UINT16 Reserved1;=0D +} INTEL_VBIOS_PCIR_STRUCTURE;=0D +=0D +typedef struct {=0D + UINT8 HeaderSignature[20];=0D + UINT16 HeaderVersion;=0D + UINT16 HeaderSize;=0D + UINT16 HeaderVbtSize;=0D + UINT8 HeaderVbtCheckSum;=0D + UINT8 HeaderReserved;=0D + UINT32 HeaderOffsetVbtDataBlock;=0D + UINT32 HeaderOffsetAim1;=0D + UINT32 HeaderOffsetAim2;=0D + UINT32 HeaderOffsetAim3;=0D + UINT32 HeaderOffsetAim4;=0D + UINT8 DataHeaderSignature[16];=0D + UINT16 DataHeaderVersion;=0D + UINT16 DataHeaderSize;=0D + UINT16 DataHeaderDataBlockSize;=0D + UINT8 CoreBlockId;=0D + UINT16 CoreBlockSize;=0D + UINT16 CoreBlockBiosSize;=0D + UINT8 CoreBlockBiosType;=0D + UINT8 CoreBlockReleaseStatus;=0D + UINT8 CoreBlockHWSupported;=0D + UINT8 CoreBlockIntegratedHW;=0D + UINT8 CoreBlockBiosBuild[4];=0D + UINT8 CoreBlockBiosSignOn[155];=0D +} VBIOS_VBT_STRUCTURE;=0D +#pragma pack(pop)=0D +///=0D +/// Driver Private Function definitions=0D +///=0D +=0D +/**=0D + Graphics OpRegion / Software SCI driver installation function.=0D +=0D + @retval EFI_SUCCESS - The driver installed without error.=0D + @retval EFI_ABORTED - The driver encountered an error and could not = complete=0D + installation of the ACPI tables.=0D +**/=0D +EFI_STATUS=0D +IgdOpRegionInit (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).= =0D + The VBT (Video BIOS Table) is a block of customizable data that is built= =0D + within the video BIOS and edited by customers.=0D +=0D + @retval EFI_SUCCESS - Video BIOS VBT information returned.=0D + @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosV= btPtr =3D NULL).=0D +**/=0D +EFI_STATUS=0D +GetVBiosVbtEndOfDxe (=0D + VOID=0D + );=0D +=0D +/**=0D + Update Graphics OpRegion after PCI enumeration.=0D +=0D + @retval EFI_SUCCESS - The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +UpdateIgdOpRegionEndOfDxe (=0D + VOID=0D + );=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsInitLib/DxeGraphicsInitLib.c b/Silicon/Intel/TigerlakeSilico= nPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsInitLib/DxeGraphicsInitLib.c new file mode 100644 index 0000000000..8769f34021 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= GraphicsInitLib/DxeGraphicsInitLib.c @@ -0,0 +1,135 @@ +/** @file=0D + DXE Library for Initializing SystemAgent Graphics ACPI table initializat= ion.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +=0D +=0D +typedef union {=0D + struct {=0D + UINT32 Low;=0D + UINT32 High;=0D + } Data32;=0D + UINT64 Data;=0D +} UINT64_STRUCT;=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT64_STRUCT mMchBarBase;=0D +GLOBAL_REMOVE_IF_UNREFERENCED GOP_COMPONENT_NAME2_PROTOCOL *GopComponentN= ame2Protocol =3D NULL;=0D +=0D +/**=0D + Do Post GT PM Init Steps after VBIOS Initialization.=0D +=0D + @retval EFI_SUCCESS Succeed.=0D +**/=0D +EFI_STATUS=0D +PostPmInitEndOfDxe (=0D + VOID=0D + )=0D +{=0D + CHAR16 *DriverVersion;=0D + UINTN Index;=0D + EFI_STATUS Status;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D +=0D + ///=0D + /// Get the platform setup policy.=0D + ///=0D + DriverVersion =3D NULL;=0D + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **) = &SaPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D +=0D + Status =3D gBS->LocateProtocol (&gGopComponentName2ProtocolGuid, NULL, (= VOID **)&GopComponentName2Protocol);=0D + if (!EFI_ERROR (Status)) {=0D + Status =3D GopComponentName2Protocol->GetDriverVersion (=0D + GopComponentName2Protocol,=0D + "en-US",=0D + &DriverVersion=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + for (Index =3D 0; (DriverVersion[Index] !=3D '\0'); Index++) {=0D + }=0D + Index =3D (Index+1)*2;=0D + CopyMem (GraphicsDxeConfig->GopVersion, DriverVersion, Index);=0D + }=0D + }=0D +=0D + ///=0D + /// Return final status=0D + ///=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D +Initialize GT ACPI tables=0D +=0D + @param[in] ImageHandle - Handle for the image of this driver=0D + @param[in] SaPolicy - SA DXE Policy protocol=0D +=0D + @retval EFI_SUCCESS - GT ACPI initialization complete=0D + @retval EFI_NOT_FOUND - Dxe System Table not found.=0D + @retval EFI_OUT_OF_RESOURCES - Mmio not allocated successfully.=0D +**/=0D +EFI_STATUS=0D +GraphicsInit (=0D + IN EFI_HANDLE ImageHandle,=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol;=0D +=0D + Status =3D EFI_SUCCESS;=0D + mMchBarBase.Data32.High =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (S= A_SEG_NUM, SA_MC_BUS, 0, 0, R_SA_MCHBAR + 4));=0D + mMchBarBase.Data32.Low =3D PciSegmentRead32 (PCI_SEGMENT_LIB_ADDRESS (S= A_SEG_NUM, SA_MC_BUS, 0, 0, R_SA_MCHBAR));=0D + mMchBarBase.Data &=3D (UINT64) ~BIT0;=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Locate the SA Global NVS Protocol.=0D + ///=0D + Status =3D gBS->LocateProtocol (&gSaNvsAreaProtocolGuid, NULL, (VOID **)= &SaNvsAreaProtocol);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Update IGD SA Global NVS=0D + ///=0D + DEBUG ((DEBUG_INFO, " Update Igd SA Global NVS Area.\n"));=0D +=0D + SaNvsAreaProtocol->Area->AlsEnable =3D GraphicsDxeCon= fig->AlsEnable;=0D + ///=0D + /// Initialize IGD state by checking if IGD Device 2 Function 0 is enabl= ed in the chipset=0D + ///=0D + if (PciSegmentRead16 (PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, SA_MC_BUS, 0,= 0, R_SA_DEVEN)) & B_SA_DEVEN_D2EN_MASK) {=0D + SaNvsAreaProtocol->Area->IgdState =3D 1;=0D + } else {=0D + SaNvsAreaProtocol->Area->IgdState =3D 0;=0D + }=0D +=0D + SaNvsAreaProtocol->Area->BrightnessPercentage =3D 100;=0D + SaNvsAreaProtocol->Area->IgdBootType =3D GraphicsDxeCon= fig->IgdBootType;=0D + SaNvsAreaProtocol->Area->IgdPanelType =3D GraphicsDxeCon= fig->IgdPanelType;=0D + SaNvsAreaProtocol->Area->IgdPanelScaling =3D GraphicsDxeCon= fig->IgdPanelScaling;=0D + ///=0D + /// Get SFF power mode platform data for the IGD driver. Flip the bit (= bitwise xor)=0D + /// since Setup value is opposite of NVS and IGD OpRegion value.=0D + ///=0D + SaNvsAreaProtocol->Area->IgdDvmtMemSize =3D GraphicsDxeCon= fig->IgdDvmtMemSize;=0D + SaNvsAreaProtocol->Area->IgdFunc1Enable =3D 0;=0D + SaNvsAreaProtocol->Area->IgdHpllVco =3D MmioRead8 (mMc= hBarBase.Data + 0xC0F) & 0x07;=0D + SaNvsAreaProtocol->Area->IgdSciSmiMode =3D 0;=0D + SaNvsAreaProtocol->Area->GfxTurboIMON =3D GraphicsDxeCon= fig->GfxTurboIMON;=0D + SaNvsAreaProtocol->Area->EdpValid =3D 0;=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsInitLib/DxeGraphicsInitLib.inf b/Silicon/Intel/TigerlakeSili= conPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsInitLib/DxeGraphicsInitLi= b.inf new file mode 100644 index 0000000000..78c115eb3c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= GraphicsInitLib/DxeGraphicsInitLib.inf @@ -0,0 +1,45 @@ +## @file=0D +# Component description file for the Dxe Graphics Init library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeGraphicsInitLib=0D +FILE_GUID =3D 2E889319-7361-4F6C-B181-EBD7AEF1DE6A=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_DRIVER=0D +LIBRARY_CLASS =3D DxeGraphicsInitLib=0D +=0D +[LibraryClasses]=0D +UefiLib=0D +UefiRuntimeServicesTableLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +PostCodeLib=0D +ConfigBlockLib=0D +IoLib=0D +PciSegmentLib=0D +BaseMemoryLib=0D +MemoryAllocationLib=0D +MmPciLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +DxeGraphicsInitLib.c=0D +=0D +[Guids]=0D +gGraphicsDxeConfigGuid ## CONSUMES=0D +=0D +[Pcd]=0D +=0D +[Protocols]=0D +gSaPolicyProtocolGuid ## CONSUMES=0D +gSaNvsAreaProtocolGuid ## CONSUMES=0D +gGopComponentName2ProtocolGuid ## CONSUMES=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.c b/Silicon/Intel/TigerlakeSi= liconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphicsPo= licyLib.c new file mode 100644 index 0000000000..fd284d5f42 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= GraphicsPolicyLib/DxeGraphicsPolicyLib.c @@ -0,0 +1,118 @@ +/** @file=0D + This file provide services for DXE phase Graphics policy default initial= ization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +/**=0D + This function prints the Graphics DXE phase policy.=0D +=0D + @param[in] SaPolicy - SA DXE Policy protocol=0D +**/=0D +VOID=0D +GraphicsDxePolicyPrint (=0D + IN SA_POLICY_PROTOCOL *SaPolicy=0D + )=0D +{=0D + EFI_STATUS Status;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D +=0D + //=0D + // Get requisite IP Config Blocks which needs to be used here=0D + //=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D +=0D + DEBUG_CODE_BEGIN ();=0D + DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) pr= int BEGIN -----------------\n"));=0D + DEBUG ((DEBUG_INFO, " Revision : %d\n", GraphicsDxeConfig->Header.Revisi= on));=0D + ASSERT (GraphicsDxeConfig->Header.Revision =3D=3D GRAPHICS_DXE_CONFIG_RE= VISION);=0D + DEBUG ((DEBUG_INFO, "\n------------------------ Graphics Policy (DXE) pr= int END -----------------\n"));=0D + DEBUG_CODE_END ();=0D +=0D + return;=0D +}=0D +=0D +=0D +/**=0D + This function Load default Graphics DXE policy.=0D +=0D + @param[in] ConfigBlockPointer The pointer to add Graphics config bloc= k=0D +**/=0D +VOID=0D +LoadIgdDxeDefault (=0D + IN VOID *ConfigBlockPointer=0D + )=0D +{=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D +=0D + GraphicsDxeConfig =3D ConfigBlockPointer;=0D + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Name =3D %g\n", &= GraphicsDxeConfig->Header.GuidHob.Name));=0D + DEBUG ((DEBUG_INFO, "GraphicsDxeConfig->Header.GuidHob.Header.HobLength = =3D 0x%x\n", GraphicsDxeConfig->Header.GuidHob.Header.HobLength));=0D + ///=0D + /// Initialize the Graphics configuration=0D + ///=0D + GraphicsDxeConfig->PlatformConfig =3D 1;=0D + GraphicsDxeConfig->AlsEnable =3D 2;=0D + GraphicsDxeConfig->BacklightControlSupport =3D 2;=0D + GraphicsDxeConfig->IgdBlcConfig =3D 2;=0D + GraphicsDxeConfig->IgdDvmtMemSize =3D 1;=0D + GraphicsDxeConfig->GfxTurboIMON =3D 31;=0D + ///=0D + /// Create a static Backlight Brightness Level Duty cycle Mapp= ing Table=0D + /// Possible 20 entries (example used 11), each 16 bits as follows:=0D + /// [15] =3D Field Valid bit, [14:08] =3D Level in Percentage (0-64h), [= 07:00] =3D Desired duty cycle (0 - FFh).=0D + ///=0D + GraphicsDxeConfig->BCLM[0] =3D (0x0000 + WORD_FIELD_VALID_BIT); ///< 0%= =0D + GraphicsDxeConfig->BCLM[1] =3D (0x0A19 + WORD_FIELD_VALID_BIT); ///< 10= %=0D + GraphicsDxeConfig->BCLM[2] =3D (0x1433 + WORD_FIELD_VALID_BIT); ///< 20= %=0D + GraphicsDxeConfig->BCLM[3] =3D (0x1E4C + WORD_FIELD_VALID_BIT); ///< 30= %=0D + GraphicsDxeConfig->BCLM[4] =3D (0x2866 + WORD_FIELD_VALID_BIT); ///< 40= %=0D + GraphicsDxeConfig->BCLM[5] =3D (0x327F + WORD_FIELD_VALID_BIT); ///< 50= %=0D + GraphicsDxeConfig->BCLM[6] =3D (0x3C99 + WORD_FIELD_VALID_BIT); ///< 60= %=0D + GraphicsDxeConfig->BCLM[7] =3D (0x46B2 + WORD_FIELD_VALID_BIT); ///< 70= %=0D + GraphicsDxeConfig->BCLM[8] =3D (0x50CC + WORD_FIELD_VALID_BIT); ///< 80= %=0D + GraphicsDxeConfig->BCLM[9] =3D (0x5AE5 + WORD_FIELD_VALID_BIT); ///< 90= %=0D + GraphicsDxeConfig->BCLM[10] =3D (0x64FF + WORD_FIELD_VALID_BIT); ///< 1= 00%=0D +}=0D +=0D +static COMPONENT_BLOCK_ENTRY mGraphicsDxeIpBlocks =3D {=0D + &gGraphicsDxeConfigGuid, sizeof (GRAPHICS_DXE_CONFIG), GRAPHICS_DXE_CONF= IG_REVISION, LoadIgdDxeDefault};=0D +=0D +=0D +/**=0D + Get DXE Graphics config block table total size.=0D +=0D + @retval Size of DXE Graphics config block table=0D +**/=0D +UINT16=0D +EFIAPI=0D +GraphicsGetConfigBlockTotalSizeDxe (=0D + VOID=0D + )=0D +{=0D + return mGraphicsDxeIpBlocks.Size;=0D +}=0D +=0D +/**=0D + GraphicsAddConfigBlocksDxe add all DXE Graphics config block.=0D +=0D + @param[in] ConfigBlockTableAddress The pointer to add SA config block= s=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GraphicsAddConfigBlocksDxe (=0D + IN VOID *ConfigBlockTableAddress=0D + )=0D +{=0D + EFI_STATUS Status;=0D + Status =3D AddComponentConfigBlocks (ConfigBlockTableAddress, &mGraphics= DxeIpBlocks, 1);=0D + return Status;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeGraphicsPolicyLib/DxeGraphicsPolicyLib.inf b/Silicon/Intel/Tigerlake= SiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeGraphicsPolicyLib/DxeGraphics= PolicyLib.inf new file mode 100644 index 0000000000..d3ac3c24a1 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= GraphicsPolicyLib/DxeGraphicsPolicyLib.inf @@ -0,0 +1,37 @@ +## @file=0D +# Component description file for the DXE Graphics Policy Init library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeGraphicsPolicyLib=0D +FILE_GUID =3D C6190599-287E-40F9-9B46-EE112A322EBF=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D DxeGraphicsPolicyLib=0D +=0D +[LibraryClasses]=0D +BaseMemoryLib=0D +UefiRuntimeServicesTableLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +PostCodeLib=0D +ConfigBlockLib=0D +HobLib=0D +SiConfigBlockLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +DxeGraphicsPolicyLib.c=0D +=0D +[Guids]=0D +gGraphicsDxeConfigGuid=0D +=0D +[Pcd]=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInit.c b/Silicon/Intel/TigerlakeSil= iconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOpRegio= nInit.c new file mode 100644 index 0000000000..0e12f62f4e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= IgdOpRegionInitLib/DxeIgdOpRegionInit.c @@ -0,0 +1,541 @@ +/** @file=0D + This is part of the implementation of an Intel Graphics drivers OpRegion= /=0D + Software SCI interface between system BIOS, ASL code, and Graphics drive= rs.=0D + The code in this file will load the driver and initialize the interface= =0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#define HEADER_OPREGION_VER_GEN9 0x0200=0D +#define HEADER_OPREGION_VER_GEN12 0x0201=0D +=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED IGD_OPREGION_PROTOCOL mIgdOpRegion= ;=0D +=0D +/**=0D + Get VBT data using SaPlaformPolicy=0D +=0D + @param[out] VbtFileBuffer Pointer to VBT data buffer.=0D +=0D + @retval EFI_SUCCESS VBT data was returned.=0D + @retval EFI_NOT_FOUND VBT data not found.=0D + @exception EFI_UNSUPPORTED Invalid signature in VBT data.=0D +**/=0D +EFI_STATUS=0D +GetIntegratedIntelVbtPtr (=0D + OUT VBIOS_VBT_STRUCTURE **VbtFileBuffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PHYSICAL_ADDRESS VbtAddress;=0D + UINT32 Size;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D +=0D + ///=0D + /// Get the SA policy.=0D + ///=0D + Status =3D gBS->LocateProtocol (=0D + &gSaPolicyProtocolGuid,=0D + NULL,=0D + (VOID **) &SaPolicy=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + VbtAddress =3D GraphicsDxeConfig->VbtAddress;=0D + Size =3D GraphicsDxeConfig->Size;=0D +=0D + if (VbtAddress =3D=3D 0x00000000) {=0D + return EFI_NOT_FOUND;=0D + } else {=0D + ///=0D + /// Check VBT signature=0D + ///=0D + *VbtFileBuffer =3D NULL;=0D + *VbtFileBuffer =3D (VBIOS_VBT_STRUCTURE *) (UINTN) VbtAddress;=0D + if ((*((UINT32 *) ((*VbtFileBuffer)->HeaderSignature))) !=3D VBT_SIGNA= TURE) {=0D + FreePool (*VbtFileBuffer);=0D + *VbtFileBuffer =3D NULL;=0D + return EFI_UNSUPPORTED;=0D + }=0D + }=0D + if (Size =3D=3D 0) {=0D + return EFI_NOT_FOUND;=0D + } else {=0D + ///=0D + /// Check VBT size=0D + ///=0D + if ((*VbtFileBuffer)->HeaderVbtSize > Size) {=0D + (*VbtFileBuffer)->HeaderVbtSize =3D (UINT16) Size;=0D + }=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Get a pointer to an uncompressed image of the Intel video BIOS.=0D +=0D + @Note: This function would only be called if the video BIOS at 0xC000 is= =0D + missing or not an Intel video BIOS. It may not be an Intel video= BIOS=0D + if the Intel graphic contoller is considered a secondary adapter.= =0D +=0D + @param[out] VBiosImage - Pointer to an uncompressed Intel video BIOS= . This pointer must=0D + be set to NULL if an uncompressed image of = the Intel Video BIOS=0D + is not obtainable.=0D +=0D + @retval EFI_SUCCESS - VBiosPtr is updated.=0D + @exception EFI_UNSUPPORTED - No Intel video BIOS found.=0D +**/=0D +EFI_STATUS=0D +GetIntegratedIntelVBiosPtr (=0D + OUT INTEL_VBIOS_OPTION_ROM_HEADER **VBiosImage=0D + )=0D +{=0D + EFI_HANDLE *HandleBuffer;=0D + UINTN HandleCount;=0D + UINTN Index;=0D + INTEL_VBIOS_PCIR_STRUCTURE *PcirBlockPtr;=0D + EFI_STATUS Status;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosRomImage;=0D +=0D + ///=0D + /// Set as if an umcompressed Intel video BIOS image was not obtainable.= =0D + ///=0D + VBiosRomImage =3D NULL;=0D +=0D + ///=0D + /// Get all PCI IO protocols=0D + ///=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiPciIoProtocolGuid,=0D + NULL,=0D + &HandleCount,=0D + &HandleBuffer=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Find the video BIOS by checking each PCI IO handle for an Intel vide= o=0D + /// BIOS OPROM.=0D + ///=0D + for (Index =3D 0; Index < HandleCount; Index++) {=0D + Status =3D gBS->HandleProtocol (=0D + HandleBuffer[Index],=0D + &gEfiPciIoProtocolGuid,=0D + (VOID **) &PciIo=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + VBiosRomImage =3D PciIo->RomImage;=0D +=0D + ///=0D + /// If this PCI device doesn't have a ROM image, skip to the next devi= ce.=0D + ///=0D + if (!VBiosRomImage) {=0D + continue;=0D + }=0D + ///=0D + /// Get pointer to PCIR structure=0D + ///=0D + PcirBlockPtr =3D (INTEL_VBIOS_PCIR_STRUCTURE *) ((UINT8 *) VBiosRomIma= ge + VBiosRomImage->PcirOffset);=0D +=0D + ///=0D + /// Check if we have an Intel video BIOS OPROM.=0D + ///=0D + if ((VBiosRomImage->Signature =3D=3D OPTION_ROM_SIGNATURE) &&=0D + (PcirBlockPtr->VendorId =3D=3D V_SA_MC_VID) &&=0D + (PcirBlockPtr->ClassCode[0] =3D=3D 0x00) &&=0D + (PcirBlockPtr->ClassCode[1] =3D=3D 0x00) &&=0D + (PcirBlockPtr->ClassCode[2] =3D=3D 0x03)=0D + ) {=0D + ///=0D + /// Found Intel video BIOS.=0D + ///=0D + *VBiosImage =3D VBiosRomImage;=0D + return EFI_SUCCESS;=0D + }=0D + }=0D + ///=0D + /// No Intel video BIOS found.=0D + ///=0D + ///=0D + /// Free any allocated buffers=0D + ///=0D + FreePool (HandleBuffer);=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + Get Intel video BIOS VBT information (i.e. Pointer to VBT and VBT size).= =0D + The VBT (Video BIOS Table) is a block of customizable data that is built= =0D + within the video BIOS and edited by customers.=0D +=0D + @retval EFI_SUCCESS - Video BIOS VBT information returned.=0D + @exception EFI_UNSUPPORTED - Could not find VBT information (*VBiosV= btPtr =3D NULL).=0D +**/=0D +EFI_STATUS=0D +GetVBiosVbtEndOfDxe (=0D + VOID=0D + )=0D +{=0D + INTEL_VBIOS_OPTION_ROM_HEADER *VBiosPtr;=0D + VBIOS_VBT_STRUCTURE *VBiosVbtPtr;=0D + EFI_STATUS Status;=0D + VBIOS_VBT_STRUCTURE *VbtFileBuffer;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D +=0D + VbtFileBuffer =3D NULL;=0D +=0D + ///=0D + /// Get the SA policy.=0D + ///=0D + Status =3D gBS->LocateProtocol (=0D + &gSaPolicyProtocolGuid,=0D + NULL,=0D + (VOID **) &SaPolicy=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + VBiosPtr =3D NULL;=0D + ///=0D + /// Try to get VBT from FV.=0D + ///=0D + GetIntegratedIntelVbtPtr (&VbtFileBuffer);=0D + if (VbtFileBuffer !=3D NULL) {=0D + ///=0D + /// Video BIOS not found, use VBT from SaPolicy=0D + ///=0D + DEBUG ((DEBUG_INFO, "VBT data found\n"));=0D + CopyMem (mIgdOpRegion.OpRegion->Header.DVER, GraphicsDxeConfig->GopVer= sion, sizeof(GraphicsDxeConfig->GopVersion));=0D + mIgdOpRegion.OpRegion->MBox3.RVDA =3D 0;=0D + mIgdOpRegion.OpRegion->MBox3.RVDS =3D 0;=0D + if ((VbtFileBuffer->HeaderVbtSize > 0x1800)) { // VBT > 6KB=0D + DEBUG ((DEBUG_INFO, "Extended VBT supported\n"));=0D + mIgdOpRegion.OpRegion->MBox3.RVDA =3D sizeof (IGD_OPREGION_STRUCTURE= ); // Relative offset at the end of Op-region.=0D + mIgdOpRegion.OpRegion->MBox3.RVDS =3D ((VbtFileBuffer->HeaderVbtSize= ) & (UINT32)~(0x1FF)) + 0x200; // Aligned VBT Data Size to 512 bytes.=0D + CopyMem ((CHAR8 *)(UINTN)(mIgdOpRegion.OpRegion) + sizeof (IGD_OPREG= ION_STRUCTURE), VbtFileBuffer, mIgdOpRegion.OpRegion->MBox3.RVDS);=0D + } else {=0D + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VbtFileBuffer, VbtFileBu= ffer->HeaderVbtSize);=0D + }=0D + return EFI_SUCCESS;=0D + }=0D +=0D + if (VBiosPtr =3D=3D NULL) {=0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "VBIOS found at 0x%X\n", VBiosPtr));=0D + VBiosVbtPtr =3D (VBIOS_VBT_STRUCTURE *) ((UINT8 *) VBiosPtr + VBiosPtr->= VbtOffset);=0D +=0D + if ((*((UINT32 *) (VBiosVbtPtr->HeaderSignature))) !=3D VBT_SIGNATURE) {= =0D + return EFI_UNSUPPORTED;=0D + }=0D +=0D + ///=0D + /// Initialize Video BIOS version with its build number.=0D + ///=0D + mIgdOpRegion.OpRegion->Header.VVER[0] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[0];=0D + mIgdOpRegion.OpRegion->Header.VVER[1] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[1];=0D + mIgdOpRegion.OpRegion->Header.VVER[2] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[2];=0D + mIgdOpRegion.OpRegion->Header.VVER[3] =3D VBiosVbtPtr->CoreBlockBiosBuil= d[3];=0D + CopyMem (mIgdOpRegion.OpRegion->MBox4.RVBT, VBiosVbtPtr, VBiosVbtPtr->He= aderVbtSize);=0D +=0D + ///=0D + /// Return final status=0D + ///=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Graphics OpRegion / Software SCI driver installation function.=0D +=0D + @param[in] void - None=0D + @retval EFI_SUCCESS - The driver installed without error.=0D + @retval EFI_ABORTED - The driver encountered an error and could not = complete=0D + installation of the ACPI tables.=0D +**/=0D +EFI_STATUS=0D +IgdOpRegionInit (=0D + VOID=0D + )=0D +{=0D + EFI_HANDLE Handle;=0D + EFI_STATUS Status;=0D + UINT32 DwordData;=0D + UINT64 IgdBaseAddress;=0D + SA_POLICY_PROTOCOL *SaPolicy;=0D + GRAPHICS_DXE_CONFIG *GraphicsDxeConfig;=0D + UINT8 Index;=0D + SYSTEM_AGENT_NVS_AREA_PROTOCOL *SaNvsAreaProtocol;=0D + VBIOS_VBT_STRUCTURE *VbtFileBuffer;=0D + UINT16 ExtendedVbtSize;=0D +=0D + ///=0D + /// Get the SA policy.=0D + ///=0D + Status =3D gBS->LocateProtocol (&gSaPolicyProtocolGuid, NULL, (VOID **)&= SaPolicy);=0D +=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +=0D + Status =3D GetConfigBlock ((VOID *) SaPolicy, &gGraphicsDxeConfigGuid, (= VOID *)&GraphicsDxeConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + VbtFileBuffer =3D NULL;=0D + ExtendedVbtSize =3D 0;=0D +=0D + GetIntegratedIntelVbtPtr (&VbtFileBuffer);=0D + ///=0D + /// Locate the SA Global NVS Protocol.=0D + ///=0D + Status =3D gBS->LocateProtocol (=0D + &gSaNvsAreaProtocolGuid,=0D + NULL,=0D + (VOID **) &SaNvsAreaProtocol=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Check if VBT size is >6KB then allocate an ACPI NVS memory buffer as= the IGD OpRegion + extended VBT size,=0D + /// zero initialize it, and set the IGD OpRegion pointer in the Global N= VS area structure.=0D + ///=0D + if ((VbtFileBuffer !=3D NULL) && (VbtFileBuffer->HeaderVbtSize > 0x1800)= ) {=0D + ExtendedVbtSize =3D ((VbtFileBuffer->HeaderVbtSize) & (UINT32)~(0x1FF)= ) + 0x200;=0D + }=0D +=0D + Status =3D (gBS->AllocatePool) (EfiACPIMemoryNVS, sizeof (IGD_OPREGION_S= TRUCTURE) + ExtendedVbtSize, (VOID **) &mIgdOpRegion.OpRegion);=0D + ASSERT_EFI_ERROR (Status);=0D + SetMem (mIgdOpRegion.OpRegion, sizeof (IGD_OPREGION_STRUCTURE) + Extende= dVbtSize, 0);=0D + SaNvsAreaProtocol->Area->IgdOpRegionAddress =3D (UINT32) (UINTN) (mIgdOp= Region.OpRegion);=0D +=0D + ///=0D + /// If IGD is disabled return=0D + ///=0D + IgdBaseAddress =3D PCI_SEGMENT_LIB_ADDRESS (SA_SEG_NUM, IGD_BUS_NUM, IGD= _DEV_NUM, IGD_FUN_NUM, 0);=0D + if (PciSegmentRead32 (IgdBaseAddress + 0) =3D=3D 0xFFFFFFFF) {=0D + return EFI_SUCCESS;=0D + }=0D + ///=0D + /// Initialize OpRegion Header=0D + ///=0D + CopyMem (mIgdOpRegion.OpRegion->Header.SIGN, HEADER_SIGNATURE, sizeof (H= EADER_SIGNATURE));=0D + ///=0D + /// Set OpRegion Size in KBs=0D + ///=0D + mIgdOpRegion.OpRegion->Header.SIZE =3D HEADER_SIZE / 1024;=0D + mIgdOpRegion.OpRegion->Header.OVER =3D (UINT32) (LShiftU64 (HEADER_OPREG= ION_VER_GEN12, 16) + LShiftU64 (HEADER_OPREGION_REV, 8));=0D +=0D + ///=0D + /// All Mailboxes are supported.=0D + ///=0D + mIgdOpRegion.OpRegion->Header.MBOX =3D HEADER_MBOX_SUPPORT;=0D +=0D + ///=0D + /// Initialize OpRegion Mailbox 1 (Public ACPI Methods).=0D + ///=0D + /// Note - The initial setting of mailbox 1 fields is implementation spe= cific.=0D + /// Adjust them as needed many even coming from user setting in setup.=0D + ///=0D + ///=0D + /// Initialize OpRegion Mailbox 3 (ASLE Interrupt and Power Conservation= ).=0D + ///=0D + /// Note - The initial setting of mailbox 3 fields is implementation spe= cific.=0D + /// Adjust them as needed many even coming from user setting in setup.=0D + ///=0D + ///=0D + /// Do not initialize TCHE. This field is written by the graphics driver= only.=0D + ///=0D + ///=0D + /// The ALSI field is generally initialized by ASL code by reading the e= mbedded controller.=0D + ///=0D + mIgdOpRegion.OpRegion->Header.PCON =3D GraphicsDxeConfig->PlatformConfig= ;=0D + mIgdOpRegion.OpRegion->Header.PCON =3D mIgdOpRegion.OpRegion->Header.PCO= N | 0x2;=0D +=0D + mIgdOpRegion.OpRegion->MBox3.BCLP =3D BACKLIGHT_BRIGHTNESS;=0D +=0D + mIgdOpRegion.OpRegion->MBox3.PFIT =3D (FIELD_VALID_BIT | PFIT_STRETCH);= =0D +=0D + ///=0D + /// Reporting to driver for VR IMON Calibration. Bits [5-1] values suppo= rted 14A to 31A.=0D + ///=0D + mIgdOpRegion.OpRegion->MBox3.PCFT =3D (SaNvsAreaProtocol->Area->GfxTurbo= IMON << 1) & 0x003E;=0D +=0D + ///=0D + /// Set Initial current Brightness=0D + ///=0D + mIgdOpRegion.OpRegion->MBox3.CBLV =3D (INIT_BRIGHT_LEVEL | FIELD_VALID_B= IT);=0D +=0D + ///=0D + /// Static Backlight Brightness Level Duty cycle Mapping Table=0D + ///=0D + for (Index =3D 0; Index < MAX_BCLM_ENTRIES; Index++) {=0D + mIgdOpRegion.OpRegion->MBox3.BCLM[Index] =3D GraphicsDxeConfig->BCLM[I= ndex];=0D + }=0D +=0D + mIgdOpRegion.OpRegion->MBox3.IUER =3D 0x00;=0D +=0D + if (!EFI_ERROR (Status)) {=0D + mIgdOpRegion.OpRegion->MBox3.IUER =3D GraphicsDxeConfig->IuerStatusVa= l;=0D + }=0D +=0D + ///=0D + /// Initialize hardware state:=0D + /// Set ASLS Register to the OpRegion physical memory address.=0D + /// Set SWSCI register bit 15 to a "1" to activate SCI interrupts.=0D + ///=0D + PciSegmentWrite32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET, (UINT32) (UINT= N) (mIgdOpRegion.OpRegion));=0D + PciSegmentAndThenOr16 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET, (UINT16) = ~(BIT0), BIT15);=0D +=0D + DwordData =3D PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_ASLS_OFFSET);= =0D + S3BootScriptSaveMemWrite (=0D + S3BootScriptWidthUint32,=0D + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_I= GD_ASLS_OFFSET),=0D + 1,=0D + &DwordData=0D + );=0D + DwordData =3D PciSegmentRead32 (IgdBaseAddress + R_SA_IGD_SWSCI_OFFSET);= =0D + S3BootScriptSaveMemWrite (=0D + S3BootScriptWidthUint32,=0D + (UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (IgdBaseAddress + R_SA_I= GD_SWSCI_OFFSET),=0D + 1,=0D + &DwordData=0D + );=0D +=0D + ///=0D + /// Install OpRegion / Software SCI protocol=0D + ///=0D + Handle =3D NULL;=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &Handle,=0D + &gIgdOpRegionProtocolGuid,=0D + &mIgdOpRegion,=0D + NULL=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Return final status=0D + ///=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Update Graphics OpRegion after PCI enumeration.=0D +=0D + @param[in] void - None=0D + @retval EFI_SUCCESS - The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +UpdateIgdOpRegionEndOfDxe (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN HandleCount;=0D + EFI_HANDLE *HandleBuffer;=0D + UINTN Index;=0D + EFI_PCI_IO_PROTOCOL *PciIo;=0D + PCI_TYPE00 Pci;=0D + UINTN Segment;=0D + UINTN Bus;=0D + UINTN Device;=0D + UINTN Function;=0D +=0D + Bus =3D 0;=0D + Device =3D 0;=0D + Function =3D 0;=0D +=0D + DEBUG ((DEBUG_INFO, "UpdateIgdOpRegionEndOfDxe\n"));=0D +=0D + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT8; //Set External Gfx Adapter= field is valid=0D + mIgdOpRegion.OpRegion->Header.PCON &=3D (UINT32) (~BIT7); //Assume No Ex= ternal Gfx Adapter=0D +=0D + ///=0D + /// Get all PCI IO protocols handles=0D + ///=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiPciIoProtocolGuid,=0D + NULL,=0D + &HandleCount,=0D + &HandleBuffer=0D + );=0D +=0D + if (!EFI_ERROR (Status)) {=0D + for (Index =3D 0; Index < HandleCount; Index++) {=0D + ///=0D + /// Get the PCI IO Protocol Interface corresponding to each handle=0D + ///=0D + Status =3D gBS->HandleProtocol (=0D + HandleBuffer[Index],=0D + &gEfiPciIoProtocolGuid,=0D + (VOID **) &PciIo=0D + );=0D +=0D + if (!EFI_ERROR (Status)) {=0D + ///=0D + /// Read the PCI configuration space=0D + ///=0D + Status =3D PciIo->Pci.Read (=0D + PciIo,=0D + EfiPciIoWidthUint32,=0D + 0,=0D + sizeof (Pci) / sizeof (UINT32),=0D + &Pci=0D + );=0D +=0D + ///=0D + /// Find the display controllers devices=0D + ///=0D + if (!EFI_ERROR (Status) && IS_PCI_DISPLAY (&Pci)) {=0D + Status =3D PciIo->GetLocation (=0D + PciIo,=0D + &Segment,=0D + &Bus,=0D + &Device,=0D + &Function=0D + );=0D +=0D + //=0D + // Assumption: Onboard devices will be sits on Bus no 0, while e= xternal devices will be sits on Bus no > 0=0D + //=0D + if (!EFI_ERROR (Status) && (Bus > 0)) {=0D + //External Gfx Adapter Detected and Available=0D + DEBUG ((DEBUG_INFO, "PCON - External Gfx Adapter Detected and = Available\n"));=0D + mIgdOpRegion.OpRegion->Header.PCON |=3D BIT7;=0D + break;=0D + }=0D + }=0D + }=0D + }=0D + }=0D +=0D + ///=0D + /// Free any allocated buffers=0D + ///=0D + if (HandleBuffer !=3D NULL) {=0D + FreePool (HandleBuffer);=0D + }=0D +=0D + ///=0D + /// Return final status=0D + ///=0D + return Status;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPriv= ate/DxeIgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf b/Silicon/Intel/Tigerla= keSiliconPkg/IpBlock/Graphics/LibraryPrivate/DxeIgdOpRegionInitLib/DxeIgdOp= RegionInitLib.inf new file mode 100644 index 0000000000..20c6265d8f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Graphics/LibraryPrivate/Dxe= IgdOpRegionInitLib/DxeIgdOpRegionInitLib.inf @@ -0,0 +1,49 @@ +## @file=0D +# Component description file for the Dxe IGD OpRegion library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D DxeIgdOpRegionInitLib=0D +FILE_GUID =3D 18D47D72-555E-475B-A4E4-AD20C3BD8B15=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_DRIVER=0D +UEFI_SPECIFICATION_VERSION =3D 2.00=0D +LIBRARY_CLASS =3D DxeIgdOpRegionInitLib=0D +=0D +[LibraryClasses]=0D +UefiLib=0D +UefiRuntimeServicesTableLib=0D +UefiBootServicesTableLib=0D +DebugLib=0D +PostCodeLib=0D +ConfigBlockLib=0D +PciSegmentLib=0D +BaseMemoryLib=0D +MemoryAllocationLib=0D +IoLib=0D +S3BootScriptLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Pcd]=0D +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D +=0D +[Sources]=0D +DxeIgdOpRegionInit.c=0D +=0D +[Guids]=0D +gGraphicsDxeConfigGuid ## CONSUMES=0D +=0D +[Protocols]=0D +gIgdOpRegionProtocolGuid ## PRODUCES=0D +gSaPolicyProtocolGuid ## CONSUMES=0D +gEfiPciIoProtocolGuid ## CONSUMES=0D +gSaNvsAreaProtocolGuid ## CONSUMES=0D --=20 2.24.0.windows.2