From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com [192.55.52.88]) by mx.groups.io with SMTP id smtpd.web11.5283.1612510913790136378 for ; Thu, 04 Feb 2021 23:41:54 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.88, mailfrom: heng.luo@intel.com) IronPort-SDR: DXLUmsk8OoB+zDEhsZEg1aOpkqifioYj3Yu8+hNy6jP5pTg5TIEurM0qTLFGZIFdB26iXQI3Bg 85CQczfyutvg== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200397273" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="200397273" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:51 -0800 IronPort-SDR: jHCs+LhZWupPQ0YWDDL44vNrx3AMJoQ8SE7yBPWBp32dUU8ckWTFG32AzinTDhJEHliIiOaXhQ BuQvSitlBYDQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260499" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:50 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Date: Fri, 5 Feb 2021 15:40:30 +0800 Message-Id: <20210205074045.3916-25-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/Psf/IncludePrivate * IpBlock/Psf/LibraryPrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/PsfLi= b.h | 520 +++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PeiDxe= SmmPsfLibVer2.inf | 40 ++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib= .c | 203 +++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib= Internal.h | 470 +++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/PsfLib= Ver2.c | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 1348 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/L= ibrary/PsfLib.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePriv= ate/Library/PsfLib.h new file mode 100644 index 0000000000..f333be48d2 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/IncludePrivate/Library/= PsfLib.h @@ -0,0 +1,520 @@ +/** @file=0D + Header file for PchPsfPrivateLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PSF_PRIVATE_LIB_H_=0D +#define _PCH_PSF_PRIVATE_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +typedef struct {=0D + UINT32 Id;=0D + PCH_SBI_PID SbPid;=0D +} PSF_SEGMENT;=0D +=0D +/**=0D + Get list of supported PSF segments.=0D +=0D + @param[out] PsfTable Array of supported PSF segments=0D + @param[out] PsfTableLength Length of PsfTable=0D +**/=0D +VOID=0D +PsfSegments (=0D + OUT PSF_SEGMENT **PsfTable,=0D + OUT UINT32 *PsfTableLength=0D + );=0D +=0D +//=0D +// Structure for storing data on both PSF SideBand Port ID and=0D +// PSF port register offset for specific device=0D +//=0D +typedef struct {=0D + PCH_SBI_PID PsfPid;=0D + UINT16 RegBase;=0D +} PSF_PORT;=0D +=0D +/**=0D + Disable device at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfDisableDevice (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Enable device at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfEnableDevice (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Hide PciCfgSpace of device at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfHideDevice (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Unhide PciCfgSpace of device at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfUnhideDevice (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Disable device BARs at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D + @param[in] BarDisMask BIT0-BAR0, BIT1-BAR1,...=0D + Mask corresponds to 32bit wide BARs=0D +**/=0D +VOID=0D +PsfDisableDeviceBar (=0D + IN PSF_PORT PsfPort,=0D + IN UINT32 BarDisMask=0D + );=0D +=0D +/**=0D + Enable device BARs at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D + @param[in] BarEnMask BIT0-BAR0, BIT1-BAR1,...=0D + Mask corresponds to 32bit wide BARs=0D +**/=0D +VOID=0D +PsfEnableDeviceBar (=0D + IN PSF_PORT PsfPort,=0D + IN UINT32 BarEnMask=0D + );=0D +=0D +/**=0D + Disable IDER device at PSF level=0D +**/=0D +VOID=0D +PsfDisableIderDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Enable SOL device at PSF level=0D +**/=0D +VOID=0D +PsfEnableSolDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable SOL device at PSF level=0D +**/=0D +VOID=0D +PsfDisableSolDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Set PMC ABASE value in PSF=0D +=0D + @param[in] Address Address for ACPI base.=0D +**/=0D +VOID=0D +PsfSetPmcAbase (=0D + IN UINT16 Address=0D + );=0D +=0D +/**=0D + Get PMC ABASE value from PSF=0D +=0D + @retval Address Address for ACPI base.=0D +**/=0D +UINT16=0D +PsfGetPmcAbase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get PMC PWRMBASE value from PSF=0D +=0D + @retval Address Address for PWRM base.=0D +**/=0D +UINT32=0D +PsfGetPmcPwrmBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Hide Cnvi WiFi device's PciCfgSpace at PSF level=0D +**/=0D +VOID=0D +PsfHideCnviWifiDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable Cnvi Wifi device at PSF level=0D +**/=0D +VOID=0D +PsfDisableCnviWifiDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable HDAudio device at PSF level=0D +**/=0D +VOID=0D +PsfDisableHdaDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable Dsp bar at PSF level=0D +**/=0D +VOID=0D +PsfDisableDspBar (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable THC device at PSF level=0D +=0D + @param[in] ThcNumber Touch Host Controller Number THC0 o= r THC1=0D +**/=0D +VOID=0D +PsfDisableThcDevice (=0D + IN UINT32 ThcNumber=0D + );=0D +=0D +/**=0D + Disable xDCI device at PSF level=0D +**/=0D +VOID=0D +PsfDisableXdciDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable xHCI device at PSF level=0D +**/=0D +VOID=0D +PsfDisableXhciDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable xHCI VTIO Phantom device at PSF level=0D +**/=0D +VOID=0D +PsfDisableXhciVtioDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable SATA device at PSF level=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +**/=0D +VOID=0D +PsfDisableSataDevice (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Return PSF_PORT for SCS eMMC device=0D +=0D + @retval PsfPort PSF PORT structure for SCS eMMC device=0D +**/=0D +PSF_PORT=0D +PsfScsEmmcPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for SCS SD Card device=0D +=0D + @retval PsfPort PSF PORT structure for SCS SD Card device=0D +**/=0D +PSF_PORT=0D +PsfScsSdCardPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for SCS UFS device=0D +=0D + @param[in] UfsNum UFS Device=0D +=0D + @retval PsfPort PSF PORT structure for SCS UFS device=0D +**/=0D +PSF_PORT=0D +PsfScsUfsPort (=0D + IN UINT32 UfsNum=0D + );=0D +=0D +/**=0D + Disable ISH device at PSF level=0D +**/=0D +VOID=0D +PsfDisableIshDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable FPAK device at PSF level=0D +**/=0D +VOID=0D +PsfDisableFpakDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable ISH BAR1 at PSF level=0D +**/=0D +VOID=0D +PsfDisableIshBar1 (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable GbE device at PSF level=0D +**/=0D +VOID=0D +PsfDisableGbeDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable SMBUS device at PSF level=0D +**/=0D +VOID=0D +PsfDisableSmbusDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable TraceHub ACPI devices at PSF level=0D +**/=0D +VOID=0D +PsfDisableTraceHubAcpiDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Hide TraceHub ACPI devices PciCfgSpace at PSF level=0D +**/=0D +VOID=0D +PsfHideTraceHubAcpiDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will hide TraceHub PciCfgSpace at PSF level=0D +**/=0D +VOID=0D +PsfHideTraceHubDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will unhide TraceHub PciCfgSpace at PSF level=0D +**/=0D +VOID=0D +PsfUnhideTraceHubDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will disable TraceHub device at PSF level=0D +**/=0D +VOID=0D +PsfDisableTraceHubDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + Configures rootspace 3 bus number for PCIe IMR use=0D +=0D + @param[in] Rs3Bus bus number=0D +**/=0D +VOID=0D +PsfSetRs3Bus (=0D + UINT8 Rs3Bus=0D + );=0D +=0D +/**=0D + Disable PCIe Root Port at PSF level=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +**/=0D +VOID=0D +PsfDisablePcieRootPort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Program PSF grant counts for SATA=0D + Call this before SATA ports are accessed for enumeration=0D +**/=0D +VOID=0D +PsfConfigureSataGrantCounts (=0D + VOID=0D + );=0D +=0D +/**=0D + Specifies the root port configuration of the=0D + PCIe controller. The number on the left of x=0D + signifies the number of root ports in the controller=0D + while value on the right is link width. N stands for=0D + the number of PCIe lanes per root port instance.=0D +**/=0D +typedef enum {=0D + PsfPcieCtrl4xn,=0D + PsfPcieCtrl1x2n_2xn,=0D + PsfPcieCtrl2xn_1x2n,=0D + PsfPcieCtrl2x2n,=0D + PsfPcieCtrl1x4n,=0D + PsfPcieCtrlUndefined=0D +} PSF_PCIE_CTRL_CONFIG;=0D +=0D +/**=0D + Program PSF grant counts for PCI express depending on controllers config= uration=0D +=0D + @param[in] PsfPcieCtrlConfigTable Table with PCIe controllers configur= ation=0D + @param[in] NumberOfPcieControllers Number of PCIe controllers. This is = also the size of PsfPcieCtrlConfig table=0D +**/=0D +VOID=0D +PsfConfigurePcieGrantCounts (=0D + IN PSF_PCIE_CTRL_CONFIG *PsfPcieCtrlConfigTable,=0D + IN UINT32 NumberOfPcieControllers=0D + );=0D +=0D +=0D +/**=0D + This function enables EOI message forwarding in PSF for PCIe ports=0D + for cases where IOAPIC is present behind this root port.=0D +=0D + @param[in] RpIndex Root port index (0 based)=0D +=0D + @retval Status=0D +**/=0D +EFI_STATUS=0D +PsfConfigurEoiForPciePort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +//=0D +// Structure for PSF Port Destination ID=0D +//=0D +typedef union {=0D + UINT32 RegVal;=0D + struct {=0D + UINT32 ChannelId : 8; // Channel ID=0D + UINT32 PortId : 7; // Port ID=0D + UINT32 PortGroupId : 1; // Port Group ID=0D + UINT32 PsfId : 8; // PSF ID=0D + UINT32 Rsvd : 7; // Reserved=0D + UINT32 ChanMap : 1; // Channel map=0D + } Fields;=0D +} PSF_PORT_DEST_ID;=0D +=0D +/**=0D + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id)=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval Destination ID=0D +**/=0D +PSF_PORT_DEST_ID=0D +PsfPcieDestinationId (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + PSF early initialization.=0D +**/=0D +VOID=0D +PsfEarlyInit (=0D + VOID=0D + );=0D +=0D +/**=0D + Assign new function number for PCIe Port Number.=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D + @param[in] NewFunction New Function number=0D +**/=0D +VOID=0D +PsfSetPcieFunction (=0D + IN UINT32 RpIndex,=0D + IN UINT32 NewFunction=0D + );=0D +=0D +/**=0D + This function enables PCIe Relaxed Order in PSF=0D +**/=0D +VOID=0D +PsfEnablePcieRelaxedOrder (=0D + VOID=0D + );=0D +=0D +=0D +/**=0D + Enable VTd support in PSF.=0D +**/=0D +VOID=0D +PchPsfEnableVtd (=0D + VOID=0D + );=0D +=0D +/**=0D + Disable PSF address-based peer-to-peer decoding.=0D +**/=0D +VOID=0D +PchPsfDisableP2pDecoding (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will hide PMC device at PSF level=0D +**/=0D +VOID=0D +PsfHidePmcDevice (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will disable D3:F0 device at PSF level for PCH-LP=0D +**/=0D +VOID=0D +PsfDisableD3F0 (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will disable PSF upstream completion tracking for HDAudio= on PCH-LP=0D +**/=0D +VOID=0D +PsfDisableUpstreamCompletionTrackingForHda (=0D + VOID=0D + );=0D +=0D +#endif // _PCH_PSF_PRIVATE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/P= sfLib/PeiDxeSmmPsfLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/P= sf/LibraryPrivate/PsfLib/PeiDxeSmmPsfLibVer2.inf new file mode 100644 index 0000000000..d8fc52444a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/P= eiDxeSmmPsfLibVer2.inf @@ -0,0 +1,40 @@ +## @file=0D +# PEI/DXE/SMM PCH PSF Private Lib for TigerLake PCH=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPsfLibTgl=0D +FILE_GUID =3D 28B03D2C-6FD5-4061-96B8-39E3F0402DE5=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D PsfLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + DebugLib=0D + PciSegmentLib=0D + PchInfoLib=0D + PchPcrLib=0D + SataLib=0D + CpuPcieInfoFruLib=0D + PchPciBdfLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D + PsfLib.c=0D + PsfLibVer2.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/P= sfLib/PsfLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPriva= te/PsfLib/PsfLib.c new file mode 100644 index 0000000000..1f0b11c11a --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/P= sfLib.c @@ -0,0 +1,203 @@ +/** @file=0D + This file contains PSF routines for RC usage=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "PsfLibInternal.h"=0D +#include =0D +=0D +/**=0D + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...)=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D +=0D + @retval PSF SideBand Port ID=0D +**/=0D +PCH_SBI_PID=0D +PsfSbPortId (=0D + UINT32 PsfId=0D + )=0D +{=0D + UINT32 PsfTableIndex;=0D + PSF_SEGMENT *PsfTable;=0D + UINT32 PsfTableSize;=0D +=0D + PsfSegments (&PsfTable, &PsfTableSize);=0D +=0D + for (PsfTableIndex =3D 0; PsfTableIndex < PsfTableSize; PsfTableIndex++)= {=0D + if (PsfTable[PsfTableIndex].Id =3D=3D PsfId) {=0D + return PsfTable[PsfTableIndex].SbPid;=0D + }=0D + }=0D +=0D + ASSERT (FALSE);=0D + return 0;=0D +}=0D +=0D +=0D +/**=0D + Get PCH Root PSF ID. This is the PSF segment to which OPDMI/DMI is conne= cted.=0D +=0D + @retval PsfId Root PSF ID=0D +**/=0D +UINT32=0D +PsfRootId (=0D + VOID=0D + )=0D +{=0D + PSF_SEGMENT *PsfTable;=0D + UINT32 PsfTableSize;=0D +=0D + PsfSegments (&PsfTable, &PsfTableSize);=0D +=0D + return PsfTable[0].Id;=0D +}=0D +=0D +/**=0D + Add EOI Target in a given PSF=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D + @param[in] TargetId EOI Target ID=0D +**/=0D +STATIC=0D +VOID=0D +PsfAddEoiTarget (=0D + UINT32 PsfId,=0D + PSF_PORT_DEST_ID TargetId=0D + )=0D +{=0D + UINT16 EoiTargetBase;=0D + UINT16 EoiControlBase;=0D + UINT8 NumOfEnabledTargets;=0D + UINT8 MaximalNumberOfTargets;=0D + PCH_SBI_PID PsfSbiPortId;=0D + UINT32 Data32;=0D + UINT8 TargetIndex;=0D +=0D + MaximalNumberOfTargets =3D PsfEoiRegData (PsfId, &EoiTargetBase, &EoiCon= trolBase);=0D + PsfSbiPortId =3D PsfSbPortId (PsfId);=0D +=0D + //=0D + // Get number of enabled agents from PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI= register=0D + //=0D + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiControlBase);=0D + NumOfEnabledTargets =3D (UINT8) (Data32 >> N_PCH_PSFX_PCR_MC_CONTROL_MCA= STX_NUMMC);=0D +=0D + //=0D + // Check if target was not already enabled=0D + // Targets from a different PSF segment are aggregated into single desti= nation on=0D + // current PSF segment.=0D + //=0D + for (TargetIndex =3D 0; TargetIndex < NumOfEnabledTargets; TargetIndex++= ) {=0D + Data32 =3D PchPcrRead32 (PsfSbiPortId, EoiTargetBase + TargetIndex * 4= );=0D + //=0D + // If target already added don't add it again=0D + //=0D + if (Data32 =3D=3D TargetId.RegVal) {=0D + ASSERT (FALSE);=0D + return;=0D + }=0D + //=0D + // If target is from different PSF segment than currently being analyz= ed=0D + // it is enough that its PsfID is matching=0D + //=0D + if ((Data32 & B_PCH_PSFX_PCR_TARGET_PSFID) >> N_PCH_PSFX_PCR_TARGET_PS= FID =3D=3D TargetId.Fields.PsfId) {=0D + return;=0D + }=0D + }=0D +=0D + //=0D + // Check if next one can be added=0D + //=0D + if (NumOfEnabledTargets >=3D MaximalNumberOfTargets) {=0D + ASSERT (FALSE);=0D + return;=0D + }=0D +=0D + //=0D + // Add next target=0D + // Configure Multicast Destination ID register with target device on PSF= .=0D + // Configuration must be done in next available PSF_MC_AGENT_MCAST0_RS0_= TGT_EOI register=0D + // so that other targets are not overridden. is known from the numb= er of multicast agents=0D + // in Multicast Control Register. Value programmed is based on=0D + // PsfID, PortGroupID, PortID and ChannelID of the target=0D + //=0D + PchPcrWrite32 (PsfSbiPortId, EoiTargetBase + NumOfEnabledTargets * 4, Ta= rgetId.RegVal);=0D +=0D + //=0D + // Enable new target=0D + // Configure PSF_x_PSF_MC_CONTROL_MCAST0_RS0_EOI, increase NumMc and set= MultCEn=0D + //=0D + NumOfEnabledTargets++;=0D + Data32 =3D (NumOfEnabledTargets << N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMM= C) | B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN;=0D + PchPcrWrite32 (PsfSbiPortId, EoiControlBase, Data32);=0D +}=0D +=0D +/**=0D + Enable EOI Target=0D +=0D + @param[in] TargetId Target ID=0D +**/=0D +STATIC=0D +VOID=0D +PsfEnableEoiTarget (=0D + PSF_PORT_DEST_ID TargetId=0D + )=0D +{=0D + UINT32 RootLevelPsf;=0D +=0D + RootLevelPsf =3D PsfRootId ();=0D +=0D + //=0D + // Enable EOI target in root PSF=0D + //=0D + PsfAddEoiTarget (RootLevelPsf, TargetId);=0D +=0D + //=0D + // Enable EOI target on other PSF segment if target=0D + // is not located on root PSF=0D + //=0D + if (TargetId.Fields.PsfId !=3D RootLevelPsf) {=0D + PsfAddEoiTarget (TargetId.Fields.PsfId, TargetId);=0D + }=0D +}=0D +=0D +/**=0D + This function enables EOI message forwarding in PSF for PCIe ports=0D + for cases where IOAPIC is present behind this root port.=0D +=0D + @param[in] RpIndex Root port index (0 based)=0D +=0D + @retval Status=0D +**/=0D +EFI_STATUS=0D +PsfConfigurEoiForPciePort (=0D + IN UINT32 RpIndex=0D + )=0D +{=0D + ASSERT (RpIndex < GetPchMaxPciePortNum ());=0D +=0D + //=0D + // If there is an IOAPIC discovered behind root port program PSF Multica= st registers=0D + // accordingly to CNL PCH BWG PSF EOI Multicast Configuration=0D + // Since there is a device behind RootPort to which EOI needs to be forw= arded=0D + // enable multicast (MULTCEN) and increase the number of multicast agent= s (NUMMC)=0D + // in Multicast Control Register.=0D + //=0D + PsfEnableEoiTarget (PsfPcieDestinationId (RpIndex));=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/P= sfLib/PsfLibInternal.h b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/Libr= aryPrivate/PsfLib/PsfLibInternal.h new file mode 100644 index 0000000000..9d636b5298 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/P= sfLibInternal.h @@ -0,0 +1,470 @@ +/** @file=0D + This file contains internal header for PSF lib usage=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PSF_PRIVATE_LIB_INTERNAL_H_=0D +#define _PCH_PSF_PRIVATE_LIB_INTERNAL_H_=0D +=0D +#include =0D +#include =0D +=0D +#define PSF_PORT_NULL ((PSF_PORT){0,0})=0D +#define PSF_IS_PORT_NULL(PsfPort) ((PsfPort.PsfPid =3D=3D 0) && (PsfPort.R= egBase =3D=3D 0))=0D +=0D +typedef struct {=0D + PCH_SBI_PID PsfPid;=0D + UINT32 RegisterAddress;=0D + UINT8 Fro;=0D +} PSF_PORT_RELAXED_ORDERING_CONFIG_REG;=0D +/**=0D + Disable bridge (e.g. PCIe Root Port) at PSF level=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfDisableBridge (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Disable bridge (e.g. PCIe Root Port) at PSF level in RS3=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfRs3DisableBridge (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Check if bridge (e.g. PCIe Root Port) is enabled at PSF level=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +=0D + @retval TRUE Bridge behind PSF Port is enabled=0D + FALSE Bridge behind PSF Port is disabled=0D +**/=0D +BOOLEAN=0D +PsfIsBridgeEnabled (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Disable device IOSpace at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfDisableDeviceIoSpace (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Enable device IOSpace at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfEnableDeviceIoSpace (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Disable device Memory Space at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfDisableDeviceMemSpace (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Enable device Memory Space at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D +**/=0D +VOID=0D +PsfEnableDeviceMemSpace (=0D + IN PSF_PORT PsfPort=0D + );=0D +=0D +/**=0D + Set device BARx address at PSF level=0D + Method not for bridges (e.g. PCIe Root Port)=0D +=0D + @param[in] PsfPort PSF PORT data structure=0D + @param[in] BarNum BAR Number (0:BAR0, 1:BAR1, ...)=0D + @param[in] BarValue 32bit BAR value=0D +**/=0D +VOID=0D +PsfSetDeviceBarValue (=0D + IN PSF_PORT PsfPort,=0D + IN UINT8 BarNum,=0D + IN UINT32 BarValue=0D + );=0D +=0D +/**=0D + Return PSF_PORT for TraceHub device=0D +=0D + @retval PsfPort PSF PORT structure for TraceHub device=0D +**/=0D +PSF_PORT=0D +PsfTraceHubPort (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will return PSF_PORT for TraceHub ACPI device=0D +=0D + @retval PsfPort PSF PORT structure for TraceHub ACPI device=0D +**/=0D +PSF_PORT=0D +PsfTraceHubAcpiDevPort (=0D + VOID=0D + );=0D +=0D +/**=0D + This procedure will return PSF_PORT for SOL device=0D +=0D + @retval PsfPort PSF PORT structure for SOL device=0D +**/=0D +PSF_PORT=0D +PsfSolPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for ISH device=0D +=0D + @retval PsfPort PSF PORT structure for ISH device=0D +**/=0D +PSF_PORT=0D +PsfIshPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for FPAK device=0D +=0D + @retval PsfPort PSF PORT structure for FPAK device=0D +**/=0D +PSF_PORT=0D +PsfFpakPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for CNVi device=0D +=0D + @retval PsfPort PSF PORT structure for CNVi device=0D +**/=0D +PSF_PORT=0D +PsfCnviPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return PSF_PORT for PMC device=0D +=0D + @retval PsfPort PSF PORT structure for PMC device=0D +**/=0D +PSF_PORT=0D +PsfPmcPort (=0D + VOID=0D + );=0D +=0D +/**=0D + Return second level PSF_PORT to which PCIE Root Port device is connected= (directly)=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe=0D +**/=0D +PSF_PORT=0D +PsfPcieSecondLevelPort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Return PSF_PORT at root PSF level to which PCIe Root Port device is conn= ected=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe=0D +=0D +**/=0D +PSF_PORT=0D +PsfRootPciePort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Return RS3 PSF_PORT at root PSF level to which PCIe Root Port device is = connected=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe=0D +**/=0D +PSF_PORT=0D +PsfRootRs3PciePort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Check if PCIe Root Port is enabled=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval TRUE PCIe Root Port is enabled=0D + FALSE PCIe Root Port is disabled=0D +**/=0D +BOOLEAN=0D +PsfIsPcieRootPortEnabled (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +//=0D +// Type of enpoint connected to PSF port.=0D +// PsfNullPort is used for ports which do not exist=0D +//=0D +typedef enum {=0D + PsfNullPort,=0D + PsfToPsfPort,=0D + PsfPcieCtrlPort=0D +} PSF_TOPO_PORT_TYPE;=0D +=0D +//=0D +// Structure for storing information on location in PSF topology=0D +// Every PSF node is identified by PsfID and PsfPortId=0D +//=0D +typedef struct {=0D + UINT8 PsfId;=0D + UINT8 PortId;=0D +} PSF_TOPO_PORT;=0D +=0D +#define PSF_TOPO_PORT_NULL ((PSF_TOPO_PORT){0, 0})=0D +#define PSF_IS_TOPO_PORT_NULL(PsfTopoPort) (((PsfTopoPort).PsfId =3D=3D 0)= && ((PsfTopoPort).PortId =3D=3D 0))=0D +=0D +//=0D +// This is optional field containing PSF port specific data=0D +//=0D +typedef union {=0D + UINT32 PcieCtrlIndex;=0D +} PSF_TOPO_PORT_DATA;=0D +=0D +//=0D +// Structure representing PSF port in PSF topology=0D +// If port is of PsfToPsfPort type Child will point to the first=0D +// port of sub PSF segment.=0D +//=0D +typedef struct PSF_TOPOLOGY {=0D + PSF_TOPO_PORT PsfPort;=0D + PSF_TOPO_PORT_TYPE PortType;=0D + CONST struct PSF_TOPOLOGY *Child;=0D + PSF_TOPO_PORT_DATA PortData;=0D +} PSF_TOPOLOGY;=0D +=0D +//=0D +// Tag for identifying last element of PSF_TOPOLOGY type array=0D +//=0D +#define PSF_TOPOLOGY_END {{0, 0}, PsfNullPort, NULL}=0D +=0D +/**=0D + Get PSF Pcie Tree topology=0D +=0D + @param[in] PsfTopology PSF Port from PSF PCIe tree topology=0D +=0D + @retval PsfTopology PSF PCIe tree topology=0D +**/=0D +CONST PSF_TOPOLOGY*=0D +PsfGetRootPciePsfTopology (=0D + VOID=0D + );=0D +=0D +//=0D +// Structure for storing data on PCIe controller to PSF assignment and Gra= ntCount register offsets=0D +//=0D +typedef struct {=0D + PCH_SBI_PID PsfPid;=0D + UINT16 DevGntCnt0Base;=0D + UINT16 TargetGntCntPg1Tgt0Base;=0D +} PSF_GRANT_COUNT_REG;=0D +=0D +/**=0D + Grant count regs data for PSF that is directly connected to PCIe Root Po= rts=0D +=0D + @param[in] Controller PCIe Root Port Controller index (0 based)=0D + @param[out] GrantCountReg Structure with PSF Grant Count register data= =0D +**/=0D +VOID=0D +PsfPcieGrantCountBaseReg (=0D + IN UINT8 Controller,=0D + OUT PSF_GRANT_COUNT_REG *GrantCountReg=0D + );=0D +=0D +/**=0D + Get Grant Count number (Device Grant Count and Target Grant Count)=0D + for PSF that is directly connected to PCIe Root Ports=0D +=0D + @param[in] Controller PCIe Root Port Controller index=0D + @param[in] Channel PCIe Root Port Channel index=0D + @param[out] DgcrNo Device Grant Count number=0D + @param[out] PgTgtNo Target Grant Count number=0D +**/=0D +VOID=0D +PsfPcieGrantCountNumber (=0D + IN UINT8 Controller,=0D + IN UINT8 Channel,=0D + OUT UINT8 *DgcrNo,=0D + OUT UINT8 *PgTgtNo=0D + );=0D +=0D +/**=0D + Grant count regs data for a given PSF-to-PSF port.=0D +=0D + @param[in] PsfTopoPort PSF-to-PSF port=0D +=0D + @param[out] GrantCountReg Structure with PSF Grant Count register d= ata=0D +**/=0D +VOID=0D +PsfSegmentGrantCountBaseReg (=0D + IN PSF_TOPO_PORT PsfTopoPort,=0D + OUT PSF_GRANT_COUNT_REG *GrantCountReg=0D + );=0D +=0D +/**=0D + Grant Count number (Device Grant Count and Target Grant Count) for a giv= en PSF-to-PSF port.=0D +=0D + @param[in] PsfTopoPort PSF-to-PSF port=0D + @param[out] DgcrNo Device Grant Count number=0D + @param[out] PgTgtNo Target Grant Count number=0D +**/=0D +VOID=0D +PsfSegmentGrantCountNumber (=0D + IN PSF_TOPO_PORT PsfTopoPort,=0D + OUT UINT8 *DgcrNo,=0D + OUT UINT8 *PgTgtNo=0D + );=0D +=0D +//=0D +// Do not override PSF Grant Count value and leave HW default setting=0D +//=0D +#define DEFAULT_PCIE_GRANT_COUNT 0xFF=0D +=0D +/**=0D + Get PSF SideBand Port ID from PSF ID (1 - PSF1, 2 - PSF2, ...)=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D +=0D + @retval PSF SideBand Port ID=0D +**/=0D +PCH_SBI_PID=0D +PsfSbPortId (=0D + UINT32 PsfId=0D + );=0D +=0D +/**=0D + Get EOI register data for given PSF ID=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D + @param[out] EoiTargetBase EOI Target register=0D + @param[out] EoiControlBase EOI Control register=0D +=0D + @retval MaxTargets Number of supported targets=0D +=0D +**/=0D +UINT8=0D +PsfEoiRegData (=0D + UINT32 PsfId,=0D + UINT16 *EoiTargetBase,=0D + UINT16 *EoiControlBase=0D + );=0D +=0D +/**=0D + Get MCTP register data for given PSF ID=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D + @param[out] MctpTargetBase MCTP Target register=0D + @param[out] MctpControlBase MCTP Control register=0D +=0D + @retval MaxTargets Number of supported targets=0D +=0D +**/=0D +UINT8=0D +PsfMctpRegData (=0D + UINT32 PsfId,=0D + UINT16 *MctpTargetBase,=0D + UINT16 *MctpControlBase=0D + );=0D +=0D +/**=0D + Check if MCTP is supported=0D +=0D + @retval TRUE MCTP is supported=0D + FALSE MCTP is not supported=0D +**/=0D +BOOLEAN=0D +PsfIsMctpSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Return the PSF (Root level) Function Config PSF_PORT for PCIe Root Port= =0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe Function Config=0D +**/=0D +PSF_PORT=0D +PsfRootPcieFunctionConfigPort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Return the PSF (Root level) RS3 Function Config PSF_PORT for PCIe Root P= ort=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe Function Config=0D +**/=0D +PSF_PORT=0D +PsfRootRs3PcieFunctionConfigPort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Return the PSF Function Config Second Level PSF_PORT for PCIe Root Port= =0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval PsfPort PSF PORT structure for PCIe Function Config=0D +**/=0D +PSF_PORT=0D +PsfPcieFunctionConfigSecondLevelPort (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + This function returns Psf Port Relaxed Ordering Configs=0D +=0D + @param[out] PsfPortRelaxedOrderingConfigRegs PC= H Series specific table=0D + @param[out] PsfPortRelaxedOrderingConfigRegsTableSize PC= H Series specific table size=0D + @param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecific PC= H type specific table=0D + @param[out] PsfPortRelaxedOrderingConfigRegsPchTypeSpecificTableSize PC= H type specific table size=0D +**/=0D +VOID=0D +GetPsfPortRelaxedOrderingTables (=0D + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** PsfPortRelaxedOrderingConfigRegs,= =0D + UINT32* PsfPortRelaxedOrderingConfigRegsT= ableSize,=0D + PSF_PORT_RELAXED_ORDERING_CONFIG_REG** PsfPortRelaxedOrderingConfigRegsP= chTypeSpecific,=0D + UINT32* PsfPortRelaxedOrderingConfigRegsP= chTypeSpecificTableSize=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/P= sfLib/PsfLibVer2.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryP= rivate/PsfLib/PsfLibVer2.c new file mode 100644 index 0000000000..fd21e5bed4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Psf/LibraryPrivate/PsfLib/P= sfLibVer2.c @@ -0,0 +1,115 @@ +/** @file=0D + This file contains internal PSF routines for PCH PSF VER2 lib usage=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "PsfLibInternal.h"=0D +#include =0D +=0D +=0D +/**=0D + Get EOI register data for given PSF ID=0D +=0D + @param[in] PsfId PSF ID (1 - PSF1, 2 - PSF2, ...)=0D + @param[out] EoiTargetBase EOI Target register=0D + @param[out] EoiControlBase EOI Control register=0D +=0D + @retval MaxTargets Number of supported targets=0D +=0D +**/=0D +UINT8=0D +PsfEoiRegData (=0D + UINT32 PsfId,=0D + UINT16 *EoiTargetBase,=0D + UINT16 *EoiControlBase=0D + )=0D +{=0D + UINT8 MaxTargets;=0D +=0D + MaxTargets =3D 0;=0D + *EoiTargetBase =3D 0;=0D + *EoiControlBase =3D 0;=0D +=0D + switch (PsfId) {=0D + case 1:=0D + break;=0D +=0D + case 3:=0D + break;=0D +=0D + case 7:=0D + break;=0D +=0D + case 8:=0D + break;=0D +=0D + case 9:=0D + break;=0D +=0D + default:=0D + break;=0D +=0D + }=0D + return MaxTargets;=0D +}=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED PSF_PORT_DEST_ID PchLpRpDestId[] =3D=0D +{=0D + {0x18000}, {0x18001}, {0x18002}, {0x18003}, // SPA: PSF1, PortID =3D 0=0D + {0x18100}, {0x18101}, {0x18102}, {0x18103}, // SPB: PSF1, PortID =3D 1=0D + {0x18200}, {0x18201}, {0x18202}, {0x18203}, // SPC: PSF1, PortID =3D 2=0D +};=0D +=0D +/**=0D + PCIe PSF port destination ID (psf_id:port_group_id:port_id:channel_id)=0D +=0D + @param[in] RpIndex PCIe Root Port Index (0 based)=0D +=0D + @retval Destination ID=0D +**/=0D +PSF_PORT_DEST_ID=0D +PsfPcieDestinationId (=0D + IN UINT32 RpIndex=0D + )=0D +{=0D + if (RpIndex < ARRAY_SIZE (PchLpRpDestId)) {=0D + return PchLpRpDestId[RpIndex];=0D + }=0D + ASSERT (FALSE);=0D + return (PSF_PORT_DEST_ID){0};=0D +}=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED PSF_SEGMENT mPchLpPsfTable[] =3D=0D +{=0D + {1, PID_PSF1},=0D + {2, PID_PSF2},=0D + {3, PID_PSF3},=0D + {4, PID_PSF4},=0D + {5, PID_CSME_PSF},=0D + {6, PID_PSF6}=0D +};=0D +=0D +/**=0D + Get list of supported PSF segments.=0D +=0D + @param[out] PsfTable Array of supported PSF segments=0D + @param[out] PsfTableLength Length of PsfTable=0D +**/=0D +VOID=0D +PsfSegments (=0D + OUT PSF_SEGMENT **PsfTable,=0D + OUT UINT32 *PsfTableLength=0D + )=0D +{=0D +*PsfTable =3D mPchLpPsfTable;=0D + *PsfTableLength =3D ARRAY_SIZE (mPchLpPsfTable);=0D +}=0D --=20 2.24.0.windows.2