From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5221.1612510911208301148 for ; Thu, 04 Feb 2021 23:41:54 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: SUzGSmFEeeZ3tlXnCYSIZ/101uUt/hAqvGXKOzLNgMjZdPicNKsizdyqpVty17pJT0oyBUbKhA Or29BBcivSPw== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200397276" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="200397276" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:53 -0800 IronPort-SDR: Bp9t4gs2qqY0/hdWXlq3WEZDjKb6Mvp2cUZB86Y0vDmxIep+RsGZ2oL6eTTGixUTKRN7x8zQZY 9/6DI4DaOJeQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260511" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:51 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Date: Fri, 5 Feb 2021 15:40:31 +0800 Message-Id: <20210205074045.3916-26-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * IpBlock/Sata/Library Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Pe= iDxeSmmSataLibVer2.inf | 32 ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Sa= taLib.c | 138 ++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataLib/Sa= taLibVer2.c | 83 ++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++ 3 files changed, 253 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeS= mmSataLib/PeiDxeSmmSataLibVer2.inf b/Silicon/Intel/TigerlakeSiliconPkg/IpBl= ock/Sata/Library/PeiDxeSmmSataLib/PeiDxeSmmSataLibVer2.inf new file mode 100644 index 0000000000..1c304fed59 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataL= ib/PeiDxeSmmSataLibVer2.inf @@ -0,0 +1,32 @@ +## @file=0D +# PEI/DXE/SMM PCH SATA library Ver2=0D +#=0D +# All function in this library is available for PEI, DXE, and SMM,=0D +# But do not support UEFI RUNTIME environment call.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmPchSataLibVer2=0D +FILE_GUID =3D 2519ADE8-D971-4551-8A8E-2EB55DFC555B=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D SataLib=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +PciSegmentLib=0D +PchInfoLib=0D +PchPciBdfLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D +SataLib.c=0D +SataLibVer2.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeS= mmSataLib/SataLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Librar= y/PeiDxeSmmSataLib/SataLib.c new file mode 100644 index 0000000000..49cba49910 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataL= ib/SataLib.c @@ -0,0 +1,138 @@ +/** @file=0D + Pch SATA library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get SATA controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +SataRegBase (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D +=0D + return SataPciCfgBase (SataCtrlIndex);=0D +}=0D +=0D +/**=0D + Get SATA controller's Port Present Status=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval Port Present Status=0D +**/=0D +UINT8=0D +GetSataPortPresentStatus (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D +=0D + return PciSegmentRead8 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_PCS = + 2);=0D +}=0D +=0D +/**=0D + Get SATA controller Function Disable Status=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval 0 SATA Controller is not Function Disabled=0D + @retval 1 SATA Controller is Function Disabled=0D +**/=0D +BOOLEAN=0D +SataControllerFunctionDisableStatus (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + UINT32 SataGc;=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D + SataGc =3D PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG= _SATAGC);=0D + return !!(SataGc & BIT10);=0D +}=0D +=0D +/**=0D + Get SATA controller ABAR size=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller ABAR size=0D +**/=0D +UINT32=0D +GetSataAbarSize (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + UINT32 SataGc;=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D + SataGc =3D PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG= _SATAGC);=0D +=0D + switch (SataGc & B_SATA_CFG_SATAGC_ASSEL) {=0D + case V_SATA_CFG_SATAGC_ASSEL_2K:=0D + return SIZE_2KB;=0D + break;=0D +=0D + case V_SATA_CFG_SATAGC_ASSEL_16K:=0D + return SIZE_16KB;=0D + break;=0D +=0D + case V_SATA_CFG_SATAGC_ASSEL_32K:=0D + return SIZE_32KB;=0D + break;=0D +=0D + case V_SATA_CFG_SATAGC_ASSEL_64K:=0D + return SIZE_64KB;=0D + break;=0D +=0D + case V_SATA_CFG_SATAGC_ASSEL_128K:=0D + return SIZE_128KB;=0D + break;=0D +=0D + case V_SATA_CFG_SATAGC_ASSEL_512K:=0D + return SIZE_256KB;=0D + break;=0D +=0D + default:=0D + return SIZE_2KB;=0D + break;=0D + }=0D +}=0D +=0D +/**=0D + Get SATA controller AHCI base address=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller AHCI base address=0D +**/=0D +UINT32=0D +GetSataAhciBase (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D +=0D + return PciSegmentRead32 (SataPciCfgBase (SataCtrlIndex) + R_SATA_CFG_AHC= I_BAR) & 0xFFFFF800;=0D +}=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeS= mmSataLib/SataLibVer2.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Li= brary/PeiDxeSmmSataLib/SataLibVer2.c new file mode 100644 index 0000000000..cde74e4e76 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/Sata/Library/PeiDxeSmmSataL= ib/SataLibVer2.c @@ -0,0 +1,83 @@ +/** @file=0D + Pch SATA library.=0D + All function in this library is available for PEI, DXE, and SMM,=0D + But do not support UEFI RUNTIME environment call.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Get Maximum Sata Controller Number=0D +=0D + @retval Maximum Sata Controller Number=0D +**/=0D +UINT8=0D +MaxSataControllerNum (=0D + VOID=0D + )=0D +{=0D + return 1;=0D +}=0D +=0D +/**=0D + Get Maximum Sata Port Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval Maximum Sata Port Number=0D +**/=0D +UINT8=0D +MaxSataPortNum (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D +=0D + return 2;=0D +}=0D +=0D +/**=0D + Check if SATA controller supports RST remapping=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval TRUE Controller supports remapping=0D + @retval FALSE Controller does not support remapping=0D +=0D +**/=0D +BOOLEAN=0D +IsRemappingSupportedOnSata (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + ASSERT (SataCtrlIndex < MaxSataControllerNum ());=0D +=0D + return FALSE;=0D +}=0D +=0D +/**=0D + Checks if SoC supports the SATA PGD power down on given=0D + SATA controller.=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval TRUE SATA PGD power down supported=0D + @retval FALSE SATA PGD power down not supported=0D +**/=0D +BOOLEAN=0D +IsSataPowerGatingSupported (=0D + IN UINT32 SataCtrlIndex=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D --=20 2.24.0.windows.2