From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web10.5201.1612510915343505036 for ; Thu, 04 Feb 2021 23:42:02 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: 8LZBwyXiUzAEZFhGZIieDcadRomnU0JkQ2LQSvdS90eVIiWaDaKyfZqZkV/JZhVqeuMwjMso7s XmEhgK5ktvbQ== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200397324" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="200397324" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:42:01 -0800 IronPort-SDR: xRDjoGwT4pHO0NZA9U03/1CtCjiPs17hJdE39evyyI8jgl1S7jy0H5TI6sGCts8DqrvNcX1ubk JoSSJ89LYImQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260762" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:42:00 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Date: Fri, 5 Feb 2021 15:40:36 +0800 Message-Id: <20210205074045.3916-31-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * Library/BasePciSegmentMultiSegLibPci * Library/BaseSiConfigBlockLib * Library/PeiDxeSmmMmPciLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/Bas= ePciSegmentMultiSegLibPci.inf | 38 +++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/Bas= ePciSegmentMultiSegLibPci.uni | 14 ++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPci/Pci= SegmentLib.c | 1280 ++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfi= gBlockLib.c | 86 ++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSiConfi= gBlockLib.inf | 33 +++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPci= Lib.c | 35 +++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmmMmPci= Lib.inf | 43 ++++++++++++++++++++++++++++++ 7 files changed, 1529 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/BasePciSegmentMultiSegLibPci.inf b/Silicon/Intel/TigerlakeSiliconP= kg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.inf new file mode 100644 index 0000000000..b04bce9cf0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPc= i/BasePciSegmentMultiSegLibPci.inf @@ -0,0 +1,38 @@ +## @file=0D +# Instance of PCI Segment Library based on PCI Library.=0D +#=0D +# PCI Segment Library that layers on top of the PCI Library which only=0D +# supports segment 0 and segment 1 PCI configuration access.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D BasePciSegmentMultiSegLibPci=0D + MODULE_UNI_FILE =3D BasePciSegmentMultiSegLibPci.uni=0D + FILE_GUID =3D AC65B409-DF03-466e-8D2B-6FCE1079F0B2= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D PciSegmentLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[Sources]=0D + PciSegmentLib.c=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PciLib=0D + DebugLib=0D + PcdLib=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/BasePciSegmentMultiSegLibPci.uni b/Silicon/Intel/TigerlakeSiliconP= kg/Library/BasePciSegmentMultiSegLibPci/BasePciSegmentMultiSegLibPci.uni new file mode 100644 index 0000000000..09bd0f5cfc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPc= i/BasePciSegmentMultiSegLibPci.uni @@ -0,0 +1,14 @@ +/** @file=0D + Instance of PCI Segment Library based on PCI Library.=0D +=0D + PCI Segment Library that layers on top of the PCI Library which only=0D + supports segment 0 and segment 1 PCI configuration access.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +=0D +#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI S= egment Library based on PCI Library."=0D +=0D +#string STR_MODULE_DESCRIPTION #language en-US "PCI Segment Libra= ry that layers on top of the PCI Library which only supports segment 0 and = segment 1 PCI configuration access."=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiS= egLibPci/PciSegmentLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePc= iSegmentMultiSegLibPci/PciSegmentLib.c new file mode 100644 index 0000000000..0d0c64be3f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BasePciSegmentMultiSegLibPc= i/PciSegmentLib.c @@ -0,0 +1,1280 @@ +/** @file=0D + PCI Segment Library that layers on top of the PCI Library which only=0D + supports segment 0 and segment 1 PCI configuration access.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Assert the validity of a PCI Segment address.=0D + A valid PCI Segment address should not contain 1's in bits 28..31 and 33= ..63=0D + and the segment should be 0 or 1.=0D +=0D + @param A The address to validate.=0D + @param M Additional bits to assert to be zero.=0D +=0D +**/=0D +#define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \=0D + ASSERT (((A) & (0xfffffffef0000000ULL | (M))) =3D=3D 0)=0D +=0D +/**=0D + Convert the PCI Segment library address to PCI library address.=0D + From ICL generation support the multiple segment, and the segment number= start from BIT28,=0D + So we convert the Segment Number offset from BIT32 to BIT28=0D +=0D + @param A The address to convert.=0D +**/=0D +#define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) ((A) | ((RShiftU64= ((A) & BIT32, 4)))))=0D +=0D +/**=0D + Register a PCI device so PCI configuration registers may be accessed aft= er=0D + SetVirtualAddressMap().=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Bus, Device, Function a= nd=0D + Register.=0D +=0D + @retval RETURN_SUCCESS The PCI device was registered for runti= me access.=0D + @retval RETURN_UNSUPPORTED An attempt was made to call this functi= on=0D + after ExitBootServices().=0D + @retval RETURN_UNSUPPORTED The resources required to access the PC= I device=0D + at runtime could not be mapped.=0D + @retval RETURN_OUT_OF_RESOURCES There are not enough resources availabl= e to=0D + complete the registration.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PciSegmentRegisterForRuntimeAccess (=0D + IN UINTN Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D + return PciRegisterForRuntimeAccess (PCI_SEGMENT_TO_PCI_ADDRESS (Address)= );=0D +}=0D +=0D +/**=0D + Reads an 8-bit PCI configuration register.=0D +=0D + Reads and returns the 8-bit PCI configuration register specified by Addr= ess.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D +=0D + @return The 8-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentRead8 (=0D + IN UINT64 Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D +=0D + return PciRead8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));=0D +}=0D +=0D +/**=0D + Writes an 8-bit PCI configuration register.=0D +=0D + Writes the 8-bit PCI configuration register specified by Address with th= e value specified by Value.=0D + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register.=0D + @param Value The value to write.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentWrite8 (=0D + IN UINT64 Address,=0D + IN UINT8 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);=0D +=0D + return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of an 8-bit PCI configuration register with an 8-b= it value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address,=0D + performs a bitwise OR between the read result and the value specified by= OrData,=0D + and writes the result to the 8-bit PCI configuration register specified = by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8) (PciSegm= entRead8 (Address) | OrData));=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + and writes the result to the 8-bit PCI configuration register specified = by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentAnd8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData=0D + )=0D +{=0D + return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & A= ndData));=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of an 8-bit PCI configuration register with an 8-= bit value,=0D + followed a bitwise OR with another 8-bit value.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData,=0D + and writes the result to the 8-bit PCI configuration register specified = by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentAndThenOr8 (=0D + IN UINT64 Address,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & = AndData) | OrData));=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in an 8-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentBitFieldRead8 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 8-bit register is returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentBitFieldWrite8 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 Value=0D + )=0D +{=0D + return PciSegmentWrite8 (=0D + Address,=0D + BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Va= lue)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 8-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentBitFieldOr8 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciSegmentWrite8 (=0D + Address,=0D + BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrDat= a)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 8-bit register.= =0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND between the read result and the value specified by AndData, = and=0D + writes the result to the 8-bit PCI configuration register specified by=0D + Address. The value written to the PCI configuration register is returned= .=0D + This function must guarantee that all PCI read and write operations are= =0D + serialized. Extra left bits in AndData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentBitFieldAnd8 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData=0D + )=0D +{=0D + return PciSegmentWrite8 (=0D + Address,=0D + BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndD= ata)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in an 8-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 8-bit port.=0D +=0D + Reads the 8-bit PCI configuration register specified by Address, perform= s a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 8-bit PCI=0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..7.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..7.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT8=0D +EFIAPI=0D +PciSegmentBitFieldAndThenOr8 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT8 AndData,=0D + IN UINT8 OrData=0D + )=0D +{=0D + return PciSegmentWrite8 (=0D + Address,=0D + BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit= , AndData, OrData)=0D + );=0D +}=0D +=0D +/**=0D + Reads a 16-bit PCI configuration register.=0D +=0D + Reads and returns the 16-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D +=0D + @return The 16-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentRead16 (=0D + IN UINT64 Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);=0D +=0D + return PciRead16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));=0D +}=0D +=0D +/**=0D + Writes a 16-bit PCI configuration register.=0D +=0D + Writes the 16-bit PCI configuration register specified by Address with t= he value specified by Value.=0D + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register.=0D + @param Value The value to write.=0D +=0D + @return The parameter of Value.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentWrite16 (=0D + IN UINT64 Address,=0D + IN UINT16 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);=0D +=0D + return PciWrite16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 16-bit PCI configuration register with=0D + a 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 16-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device, F= unction and=0D + Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) = | OrData));=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + and writes the result to the 16-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentAnd16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData=0D + )=0D +{=0D + return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) = & AndData));=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 16-bit PCI configuration register with a 16-= bit value,=0D + followed a bitwise OR with another 16-bit value.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData,=0D + and writes the result to the 16-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentAndThenOr16 (=0D + IN UINT64 Address,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address)= & AndData) | OrData));=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 16-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentBitFieldRead16 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 16-bit register is returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentBitFieldWrite16 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 Value=0D + )=0D +{=0D + return PciSegmentWrite16 (=0D + Address,=0D + BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, = Value)=0D + );=0D +}=0D +=0D +/**=0D + Reads the 16-bit PCI configuration register specified by Address,=0D + performs a bitwise OR between the read result and the value specified by= OrData,=0D + and writes the result to the 16-bit PCI configuration register specified= by Address.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentBitFieldOr16 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentWrite16 (=0D + Address,=0D + BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrD= ata)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR,= =0D + and writes the result back to the bit field in the 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address,=0D + performs a bitwise OR between the read result and the value specified by= OrData,=0D + and writes the result to the 16-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D + Extra left bits in OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 16-bit boundary, then ASSERT().=0D + If StartBit is greater than 7, then ASSERT().=0D + If EndBit is greater than 7, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + The ordinal of the least significant bit in a byte is = bit 0.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + The ordinal of the most significant bit in a byte is b= it 7.=0D + @param AndData The value to AND with the read value from the PCI conf= iguration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentBitFieldAnd16 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData=0D + )=0D +{=0D + return PciSegmentWrite16 (=0D + Address,=0D + BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, An= dData)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 16-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 16-bit port.=0D +=0D + Reads the 16-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 16-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 15, then ASSERT().=0D + If EndBit is greater than 15, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..15.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..15.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT16=0D +EFIAPI=0D +PciSegmentBitFieldAndThenOr16 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT16 AndData,=0D + IN UINT16 OrData=0D + )=0D +{=0D + return PciSegmentWrite16 (=0D + Address,=0D + BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndB= it, AndData, OrData)=0D + );=0D +}=0D +=0D +/**=0D + Reads a 32-bit PCI configuration register.=0D +=0D + Reads and returns the 32-bit PCI configuration register specified by Add= ress.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D +=0D + @return The 32-bit PCI configuration register specified by Address.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentRead32 (=0D + IN UINT64 Address=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);=0D +=0D + return PciRead32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));=0D +}=0D +=0D +/**=0D + Writes a 32-bit PCI configuration register.=0D +=0D + Writes the 32-bit PCI configuration register specified by Address with t= he value specified by Value.=0D + Value is returned. This function must guarantee that all PCI read and w= rite operations are serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Devic= e, Function, and Register.=0D + @param Value The value to write.=0D +=0D + @return The parameter of Value.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentWrite32 (=0D + IN UINT64 Address,=0D + IN UINT32 Value=0D + )=0D +{=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);=0D +=0D + return PciWrite32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);=0D +}=0D +=0D +/**=0D + Performs a bitwise OR of a 32-bit PCI configuration register with a 32-b= it value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address,=0D + performs a bitwise OR between the read result and the value specified by= OrData,=0D + and writes the result to the 32-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);= =0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + and writes the result to the 32-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentAnd32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData=0D + )=0D +{=0D + return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData)= ;=0D +}=0D +=0D +/**=0D + Performs a bitwise AND of a 32-bit PCI configuration register with a 32-= bit value,=0D + followed a bitwise OR with another 32-bit value.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address,=0D + performs a bitwise AND between the read result and the value specified b= y AndData,=0D + performs a bitwise OR between the result of the AND operation and the va= lue specified by OrData,=0D + and writes the result to the 32-bit PCI configuration register specified= by Address.=0D + The value written to the PCI configuration register is returned.=0D + This function must guarantee that all PCI read and write operations are = serialized.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D +=0D + @param Address The address that encodes the PCI Segment, Bus, Device,= Function, and Register.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentAndThenOr32 (=0D + IN UINT64 Address,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData= ) | OrData);=0D +}=0D +=0D +/**=0D + Reads a bit field of a PCI configuration register.=0D +=0D + Reads the bit field in a 32-bit PCI configuration register. The bit fiel= d is=0D + specified by the StartBit and the EndBit. The value of the bit field is= =0D + returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to read.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D +=0D + @return The value of the bit field read from the PCI configuration regis= ter.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentBitFieldRead32 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit=0D + )=0D +{=0D + return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);=0D +}=0D +=0D +/**=0D + Writes a bit field to a PCI configuration register.=0D +=0D + Writes Value to the bit field of the PCI configuration register. The bit= =0D + field is specified by the StartBit and the EndBit. All other bits in the= =0D + destination PCI configuration register are preserved. The new value of t= he=0D + 32-bit register is returned.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If Value is larger than the bitmask value range specified by StartBit an= d EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param Value The new value of the bit field.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentBitFieldWrite32 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 Value=0D + )=0D +{=0D + return PciSegmentWrite32 (=0D + Address,=0D + BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, = Value)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, = and=0D + writes the result back to the bit field in the 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise OR between the read result and the value specified by=0D + OrData, and writes the result to the 32-bit PCI configuration register=0D + specified by Address. The value written to the PCI configuration registe= r is=0D + returned. This function must guarantee that all PCI read and write opera= tions=0D + are serialized. Extra left bits in OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param OrData The value to OR with the PCI configuration register.=0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentBitFieldOr32 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentWrite32 (=0D + Address,=0D + BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrD= ata)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit PCI configuration register, performs a bit= wise=0D + AND, and writes the result back to the bit field in the 32-bit register.= =0D +=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a bitwise=0D + AND between the read result and the value specified by AndData, and writ= es the result=0D + to the 32-bit PCI configuration register specified by Address. The value= written to=0D + the PCI configuration register is returned. This function must guarante= e that all PCI=0D + read and write operations are serialized. Extra left bits in AndData ar= e stripped.=0D + If any reserved bits in Address are set, then ASSERT().=0D + If Address is not aligned on a 32-bit boundary, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentBitFieldAnd32 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData=0D + )=0D +{=0D + return PciSegmentWrite32 (=0D + Address,=0D + BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, An= dData)=0D + );=0D +}=0D +=0D +/**=0D + Reads a bit field in a 32-bit port, performs a bitwise AND followed by a= =0D + bitwise OR, and writes the result back to the bit field in the=0D + 32-bit port.=0D +=0D + Reads the 32-bit PCI configuration register specified by Address, perfor= ms a=0D + bitwise AND followed by a bitwise OR between the read result and=0D + the value specified by AndData, and writes the result to the 32-bit PCI= =0D + configuration register specified by Address. The value written to the PC= I=0D + configuration register is returned. This function must guarantee that al= l PCI=0D + read and write operations are serialized. Extra left bits in both AndDat= a and=0D + OrData are stripped.=0D +=0D + If any reserved bits in Address are set, then ASSERT().=0D + If StartBit is greater than 31, then ASSERT().=0D + If EndBit is greater than 31, then ASSERT().=0D + If EndBit is less than StartBit, then ASSERT().=0D + If AndData is larger than the bitmask value range specified by StartBit = and EndBit, then ASSERT().=0D + If OrData is larger than the bitmask value range specified by StartBit a= nd EndBit, then ASSERT().=0D +=0D + @param Address The PCI configuration register to write.=0D + @param StartBit The ordinal of the least significant bit in the bit fi= eld.=0D + Range 0..31.=0D + @param EndBit The ordinal of the most significant bit in the bit fie= ld.=0D + Range 0..31.=0D + @param AndData The value to AND with the PCI configuration register.= =0D + @param OrData The value to OR with the result of the AND operation.= =0D +=0D + @return The value written back to the PCI configuration register.=0D +=0D +**/=0D +UINT32=0D +EFIAPI=0D +PciSegmentBitFieldAndThenOr32 (=0D + IN UINT64 Address,=0D + IN UINTN StartBit,=0D + IN UINTN EndBit,=0D + IN UINT32 AndData,=0D + IN UINT32 OrData=0D + )=0D +{=0D + return PciSegmentWrite32 (=0D + Address,=0D + BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndB= it, AndData, OrData)=0D + );=0D +}=0D +=0D +/**=0D + Reads a range of PCI configuration registers into a caller supplied buff= er.=0D +=0D + Reads the range of PCI configuration registers specified by StartAddress= and=0D + Size into the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be read. Size is=0D + returned. When possible 32-bit PCI configuration read cycles are used to= read=0D + from StartAdress to StartAddress + Size. Due to alignment restrictions, = 8-bit=0D + and 16-bit PCI configuration read cycles may be used at the beginning an= d the=0D + end of the range.=0D +=0D + If any reserved bits in StartAddress are set, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Segment,= Bus, Device,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer receiving the data read.=0D +=0D + @return Size=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciSegmentReadBuffer (=0D + IN UINT64 StartAddress,=0D + IN UINTN Size,=0D + OUT VOID *Buffer=0D + )=0D +{=0D + UINTN ReturnValue;=0D +=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);=0D + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D +=0D + if (Size =3D=3D 0) {=0D + return Size;=0D + }=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + //=0D + // Save Size for return=0D + //=0D + ReturnValue =3D Size;=0D +=0D + if ((StartAddress & BIT0) !=3D 0) {=0D + //=0D + // Read a byte if StartAddress is byte aligned=0D + //=0D + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress);=0D + StartAddress +=3D sizeof (UINT8);=0D + Size -=3D sizeof (UINT8);=0D + Buffer =3D (UINT8*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) {=0D + //=0D + // Read a word if StartAddress is word aligned=0D + //=0D + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + while (Size >=3D sizeof (UINT32)) {=0D + //=0D + // Read as many double words as possible=0D + //=0D + WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));=0D + StartAddress +=3D sizeof (UINT32);=0D + Size -=3D sizeof (UINT32);=0D + Buffer =3D (UINT32*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16)) {=0D + //=0D + // Read the last remaining word if exist=0D + //=0D + WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*)Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT8)) {=0D + //=0D + // Read the last remaining byte if exist=0D + //=0D + *(volatile UINT8 *)Buffer =3D PciSegmentRead8 (StartAddress);=0D + }=0D +=0D + return ReturnValue;=0D +}=0D +=0D +/**=0D + Copies the data in a caller supplied buffer to a specified range of PCI= =0D + configuration space.=0D +=0D + Writes the range of PCI configuration registers specified by StartAddres= s and=0D + Size from the buffer specified by Buffer. This function only allows the = PCI=0D + configuration registers from a single PCI function to be written. Size i= s=0D + returned. When possible 32-bit PCI configuration write cycles are used t= o=0D + write from StartAdress to StartAddress + Size. Due to alignment restrict= ions,=0D + 8-bit and 16-bit PCI configuration write cycles may be used at the begin= ning=0D + and the end of the range.=0D +=0D + If any reserved bits in StartAddress are set, then ASSERT().=0D + If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().=0D + If Size > 0 and Buffer is NULL, then ASSERT().=0D +=0D + @param StartAddress The starting address that encodes the PCI Segment,= Bus, Device,=0D + Function and Register.=0D + @param Size The size in bytes of the transfer.=0D + @param Buffer The pointer to a buffer containing the data to wri= te.=0D +=0D + @return The parameter of Size.=0D +=0D +**/=0D +UINTN=0D +EFIAPI=0D +PciSegmentWriteBuffer (=0D + IN UINT64 StartAddress,=0D + IN UINTN Size,=0D + IN VOID *Buffer=0D + )=0D +{=0D + UINTN ReturnValue;=0D +=0D + ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);=0D + ASSERT (((StartAddress & 0xFFF) + Size) <=3D 0x1000);=0D +=0D + if (Size =3D=3D 0) {=0D + return 0;=0D + }=0D +=0D + ASSERT (Buffer !=3D NULL);=0D +=0D + //=0D + // Save Size for return=0D + //=0D + ReturnValue =3D Size;=0D +=0D + if ((StartAddress & BIT0) !=3D 0) {=0D + //=0D + // Write a byte if StartAddress is byte aligned=0D + //=0D + PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);=0D + StartAddress +=3D sizeof (UINT8);=0D + Size -=3D sizeof (UINT8);=0D + Buffer =3D (UINT8*) Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16) && (StartAddress & BIT1) !=3D 0) {=0D + //=0D + // Write a word if StartAddress is word aligned=0D + //=0D + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*) Buffer + 1;=0D + }=0D +=0D + while (Size >=3D sizeof (UINT32)) {=0D + //=0D + // Write as many double words as possible=0D + //=0D + PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));=0D + StartAddress +=3D sizeof (UINT32);=0D + Size -=3D sizeof (UINT32);=0D + Buffer =3D (UINT32*) Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT16)) {=0D + //=0D + // Write the last remaining word if exist=0D + //=0D + PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));=0D + StartAddress +=3D sizeof (UINT16);=0D + Size -=3D sizeof (UINT16);=0D + Buffer =3D (UINT16*) Buffer + 1;=0D + }=0D +=0D + if (Size >=3D sizeof (UINT8)) {=0D + //=0D + // Write the last remaining byte if exist=0D + //=0D + PciSegmentWrite8 (StartAddress, *(UINT8*) Buffer);=0D + }=0D +=0D + return ReturnValue;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib= /BaseSiConfigBlockLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiC= onfigBlockLib/BaseSiConfigBlockLib.c new file mode 100644 index 0000000000..4644de9b74 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSi= ConfigBlockLib.c @@ -0,0 +1,86 @@ +/** @file=0D + This file is BaseSiConfigBlockLib library is used to add config blocks=0D + to config block header.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +/**=0D + GetComponentConfigBlockTotalSize get config block table total size.=0D +=0D + @param[in] ComponentBlocks Component blocks array=0D + @param[in] TotalBlockCount Number of blocks=0D +=0D + @retval Size of config block table=0D +**/=0D +UINT16=0D +EFIAPI=0D +GetComponentConfigBlockTotalSize (=0D + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,=0D + IN UINT16 TotalBlockCount=0D + )=0D +{=0D + UINT16 TotalBlockSize;=0D + UINT16 BlockCount;=0D +=0D + TotalBlockSize =3D 0;=0D + for (BlockCount =3D 0 ; BlockCount < TotalBlockCount; BlockCount++) {=0D + TotalBlockSize +=3D (UINT32) ComponentBlocks[BlockCount].Size;=0D + DEBUG ((DEBUG_INFO, "TotalBlockSize after adding Block[0x%x]=3D 0x%x\n= ", BlockCount, TotalBlockSize));=0D + }=0D +=0D + return TotalBlockSize;=0D +}=0D +=0D +/**=0D + AddComponentConfigBlocks add all config blocks.=0D +=0D + @param[in] ConfigBlockTableAddress The pointer to add config blocks=0D + @param[in] ComponentBlocks Config blocks array=0D + @param[in] TotalBlockCount Number of blocks=0D +=0D + @retval EFI_SUCCESS The policy default is initialized.= =0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create b= uffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +AddComponentConfigBlocks (=0D + IN VOID *ConfigBlockTableAddress,=0D + IN COMPONENT_BLOCK_ENTRY *ComponentBlocks,=0D + IN UINT16 TotalBlockCount=0D + )=0D +{=0D + UINT16 BlockCount;=0D + VOID *ConfigBlockPointer;=0D + CONFIG_BLOCK ConfigBlockBuf;=0D + EFI_STATUS Status;=0D +=0D + Status =3D EFI_SUCCESS;=0D +=0D + //=0D + // Initialize ConfigBlockPointer to NULL=0D + //=0D + ConfigBlockPointer =3D NULL;=0D + //=0D + // Loop to identify each config block from ComponentBlocks[] Table and a= dd each of them=0D + //=0D + for (BlockCount =3D 0; BlockCount < TotalBlockCount; BlockCount++) {=0D + ZeroMem (&ConfigBlockBuf, sizeof (CONFIG_BLOCK));=0D + CopyMem (&(ConfigBlockBuf.Header.GuidHob.Name), ComponentBlocks[BlockC= ount].Guid, sizeof (EFI_GUID));=0D + ConfigBlockBuf.Header.GuidHob.Header.HobLength =3D ComponentBlocks[Blo= ckCount].Size;=0D + ConfigBlockBuf.Header.Revision =3D ComponentBlocks[BlockCount].= Revision;=0D + ConfigBlockPointer =3D (VOID *)&ConfigBlockBuf;=0D + Status =3D AddConfigBlock ((VOID *)ConfigBlockTableAddress, (VOID *)&C= onfigBlockPointer);=0D + ASSERT_EFI_ERROR (Status);=0D + ComponentBlocks[BlockCount].LoadDefault (ConfigBlockPointer);=0D + }=0D + return Status;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib= /BaseSiConfigBlockLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseS= iConfigBlockLib/BaseSiConfigBlockLib.inf new file mode 100644 index 0000000000..e23b2d342f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/BaseSiConfigBlockLib/BaseSi= ConfigBlockLib.inf @@ -0,0 +1,33 @@ +## @file=0D +# Component description file for the BaseSiConfigBlockLib library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D BaseSiConfigBlockLib=0D +FILE_GUID =3D 6C068D0F-F48E-48CB-B369-433E507AF4A2=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D SiConfigBlockLib=0D +=0D +=0D +[LibraryClasses]=0D +DebugLib=0D +IoLib=0D +ConfigBlockLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +BaseSiConfigBlockLib.c=0D +=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pe= iDxeSmmMmPciLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPc= iLib/PeiDxeSmmMmPciLib.c new file mode 100644 index 0000000000..48e14dc9ee --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmm= MmPciLib.c @@ -0,0 +1,35 @@ +/** @file=0D + This file contains routines that get PCI Express Address=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This procedure will get PCIE address=0D +=0D + @param[in] Bus Pci Bus Number=0D + @param[in] Device Pci Device Number=0D + @param[in] Function Pci Function Number=0D +=0D + @retval PCIE address=0D +**/=0D +UINTN=0D +EFIAPI=0D +MmPciBase (=0D + IN UINT32 Bus,=0D + IN UINT32 Device,=0D + IN UINT32 Function=0D + )=0D +{=0D + ASSERT ((Bus <=3D 0xFF) && (Device <=3D 0x1F) && (Function <=3D 0x7));=0D +=0D +#ifdef FSP_FLAG=0D + return ((UINTN) PcdGet64 (PcdSiPciExpressBaseAddress) + (UINTN) (Bus << = 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12));=0D +#else=0D + return ((UINTN) PcdGet64 (PcdPciExpressBaseAddress) + (UINTN) (Bus << = 20) + (UINTN) (Device << 15) + (UINTN) (Function << 12));=0D +#endif=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/Pe= iDxeSmmMmPciLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMm= PciLib/PeiDxeSmmMmPciLib.inf new file mode 100644 index 0000000000..353b97f3f6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Library/PeiDxeSmmMmPciLib/PeiDxeSmm= MmPciLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# Component description file for the PeiDxeSmmMmPciLib=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D PeiDxeSmmMmPciLib=0D +FILE_GUID =3D D03D6670-A032-11E2-9E96-0800200C9A66=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D MmPciLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +PcdLib=0D +DebugLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Pcd]=0D +gSiPkgTokenSpaceGuid.PcdSiPciExpressBaseAddress=0D +=0D +[FixedPcd]=0D +gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D +=0D +[Sources]=0D +PeiDxeSmmMmPciLib.c=0D --=20 2.24.0.windows.2