From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga01.intel.com (mga01.intel.com []) by mx.groups.io with SMTP id smtpd.web10.5201.1612510915343505036 for ; Thu, 04 Feb 2021 23:42:05 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: DwUBBLAV0TmVT3IHgg6XKJQZzE0Je0hlzM95LjgzbcoGTRTLRtR0glEyHrZui/n4TlHiiBiq87 bfxCGG/HTTzg== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="200397348" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="200397348" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:42:05 -0800 IronPort-SDR: P93v4eSveXVCKOs0yl4np95rSp43sn3u4hFgbJRzXYbYXc3vDYoD4h/rPX/0UpDuSfxjn9KOhZ NUPO7oTUKrXA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260806" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:42:04 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 33/40] TigerlakeSiliconPkg/Pch: Add Pch private library instances Date: Fri, 5 Feb 2021 15:40:38 +0800 Message-Id: <20210205074045.3916-33-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following files: * Pch/LibraryPrivate/BaseSiScheduleResetLib * Pch/LibraryPrivate/SmmPchPrivateLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLi= b/BaseSiScheduleResetLib.c | 171 ++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleResetLi= b/BaseSiScheduleResetLib.inf | 37 +++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmP= chPrivateLib.c | 57 ++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib/SmmP= chPrivateLib.inf | 31 +++++++++++++++++++++++++++++++ 4 files changed, 296 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiSch= eduleResetLib/BaseSiScheduleResetLib.c b/Silicon/Intel/TigerlakeSiliconPkg/= Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.c new file mode 100644 index 0000000000..1880244a01 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRe= setLib/BaseSiScheduleResetLib.c @@ -0,0 +1,171 @@ +/** @file=0D + Reset scheduling library services=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + This function returns SiScheduleResetHob for library use=0D +**/=0D +STATIC=0D +SI_SCHEDULE_RESET_HOB *=0D +SiScheduleGetResetData (=0D + VOID=0D + )=0D +{=0D + STATIC SI_SCHEDULE_RESET_HOB *SiScheduleResetHob =3D NULL;=0D + SI_SCHEDULE_RESET_HOB *SiScheduleResetHobTemp;=0D + VOID *HobPtr;=0D +=0D + if (SiScheduleResetHob !=3D NULL) {=0D + return SiScheduleResetHob;=0D + }=0D +=0D + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid);=0D + if (HobPtr =3D=3D NULL) {=0D + SiScheduleResetHobTemp =3D BuildGuidHob (&gSiScheduleResetHobGuid, siz= eof (SI_SCHEDULE_RESET_HOB));=0D + if (SiScheduleResetHobTemp =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return SiScheduleResetHobTemp;=0D + }=0D + SiScheduleResetHobTemp->ResetType =3D 0xFF;=0D + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Init SiScheduleResetHob\= n"));=0D + } else {=0D + SiScheduleResetHobTemp =3D (SI_SCHEDULE_RESET_HOB*) GET_GUID_HOB_DATA = (HobPtr);=0D + }=0D + SiScheduleResetHob =3D SiScheduleResetHobTemp;=0D + return SiScheduleResetHobTemp;=0D +}=0D +=0D +/**=0D + This function updates the reset information in SiScheduleResetHob=0D + @param[in] ResetType UEFI defined reset type.=0D + @param[in] ResetData Optional element used to introduce a platfor= m specific reset.=0D + The exact type of the reset is defined by t= he EFI_GUID that follows=0D + the Null-terminated Unicode string.=0D +**/=0D +VOID=0D +SiScheduleResetSetType (=0D + IN EFI_RESET_TYPE ResetType,=0D + IN PCH_RESET_DATA *ResetData OPTIONAL=0D + )=0D +{=0D + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob;=0D + if (ResetType > EfiResetPlatformSpecific) {=0D + DEBUG ((DEBUG_INFO, "Unsupported Reset Type Requested\n"));=0D + return;=0D + }=0D + SiScheduleResetHob =3D SiScheduleGetResetData ();=0D + if (SiScheduleResetHob =3D=3D NULL) {=0D + return;=0D + }=0D + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : Current Reset Type =3D 0x%= x\n", SiScheduleResetHob->ResetType));=0D + if (SiScheduleResetHob->ResetType =3D=3D ResetType) {=0D + DEBUG ((DEBUG_INFO, "Current Reset Type is same as requested Reset Typ= e\n"));=0D + return;=0D + }=0D + if (SiScheduleResetHob->ResetType =3D=3D 0xFF) {=0D + // Init Reset Type to lowest ResetType=0D + SiScheduleResetHob->ResetType =3D EfiResetWarm;=0D + }=0D + //=0D + // ResetType Priority set as : ResetPlatformSpecific(3) > ResetShutdown(= 2) > ResetCold(0) > ResetWarm(1)=0D + //=0D + switch (ResetType) {=0D + case EfiResetWarm:=0D + break;=0D +=0D + case EfiResetCold:=0D + if (SiScheduleResetHob->ResetType =3D=3D EfiResetWarm) {=0D + SiScheduleResetHob->ResetType =3D ResetType;=0D + }=0D + break;=0D +=0D + case EfiResetShutdown:=0D + if (SiScheduleResetHob->ResetType < ResetType)=0D + SiScheduleResetHob->ResetType =3D ResetType;=0D + break;=0D +=0D + case EfiResetPlatformSpecific:=0D + SiScheduleResetHob->ResetType =3D ResetType;=0D + SiScheduleResetHob->ResetData =3D *ResetData;=0D + break;=0D + }=0D + DEBUG ((DEBUG_INFO, "SiScheduleResetSetType : New Reset Type =3D 0x%x\n"= , SiScheduleResetHob->ResetType));=0D +}=0D +=0D +/**=0D + This function returns TRUE or FALSE depending on whether a reset is requ= ired based on SiScheduleResetHob=0D +=0D + @retval BOOLEAN The function returns FALSE if no reset is requ= ired=0D +**/=0D +BOOLEAN=0D +SiScheduleResetIsRequired (=0D + VOID=0D + )=0D +{=0D + VOID *HobPtr;=0D +=0D + HobPtr =3D NULL;=0D + HobPtr =3D GetFirstGuidHob (&gSiScheduleResetHobGuid);=0D + if (HobPtr =3D=3D NULL) {=0D + return FALSE;=0D + }=0D + return TRUE;=0D +}=0D +=0D +/**=0D + This function performs reset based on SiScheduleResetHob=0D +=0D + @retval BOOLEAN The function returns FALSE if no reset is requ= ired=0D +**/=0D +BOOLEAN=0D +SiScheduleResetPerformReset (=0D + VOID=0D + )=0D +{=0D + UINTN DataSize;=0D + SI_SCHEDULE_RESET_HOB *SiScheduleResetHob;=0D +=0D + if (!SiScheduleResetIsRequired ()) {=0D + return FALSE;=0D + }=0D + SiScheduleResetHob =3D SiScheduleGetResetData ();=0D +=0D + if (SiScheduleResetHob =3D=3D NULL) {=0D + return TRUE;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "SiScheduleResetPerformReset : Reset Type =3D 0x%x\n= ", SiScheduleResetHob->ResetType));=0D + switch (SiScheduleResetHob->ResetType) {=0D + case EfiResetWarm:=0D + ResetWarm ();=0D + break;=0D +=0D + case EfiResetCold:=0D + ResetCold ();=0D + break;=0D +=0D + case EfiResetShutdown:=0D + ResetShutdown ();=0D + break;=0D +=0D + case EfiResetPlatformSpecific:=0D + DataSize =3D sizeof (PCH_RESET_DATA);=0D + ResetPlatformSpecific (DataSize, &SiScheduleResetHob->ResetData);=0D + break;=0D + }=0D + // Code should never reach here=0D + ASSERT (FALSE);=0D + return TRUE;=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiSch= eduleResetLib/BaseSiScheduleResetLib.inf b/Silicon/Intel/TigerlakeSiliconPk= g/Pch/LibraryPrivate/BaseSiScheduleResetLib/BaseSiScheduleResetLib.inf new file mode 100644 index 0000000000..4363a752a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/BaseSiScheduleRe= setLib/BaseSiScheduleResetLib.inf @@ -0,0 +1,37 @@ +## @file=0D +# Component description file for Si Reset Schedule Library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D BaseSiScheduleResetLib=0D +FILE_GUID =3D E6F3D551-36C0-4737-80C7-47FC57593163=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D BASE=0D +LIBRARY_CLASS =3D SiScheduleResetLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF=0D +#=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +HobLib=0D +ResetSystemLib=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Guids]=0D +gSiScheduleResetHobGuid=0D +=0D +[Sources]=0D +BaseSiScheduleResetLib.c=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPri= vateLib/SmmPchPrivateLib.c b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryP= rivate/SmmPchPrivateLib/SmmPchPrivateLib.c new file mode 100644 index 0000000000..46cf735860 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib= /SmmPchPrivateLib.c @@ -0,0 +1,57 @@ +/** @file=0D + PCH SMM private lib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Set InSmm.Sts bit=0D +**/=0D +VOID=0D +PchSetInSmmSts (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D +=0D + ///=0D + /// Read memory location FED30880h OR with 00000001h, place the result i= n EAX,=0D + /// and write data to lower 32 bits of MSR 1FEh (sample code available)= =0D + ///=0D + Data32 =3D MmioRead32 (0xFED30880);=0D + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 | BIT0);=0D + ///=0D + /// Read FED30880h back to ensure the setting went through.=0D + ///=0D + Data32 =3D MmioRead32 (0xFED30880);=0D +}=0D +=0D +/**=0D + Clear InSmm.Sts bit=0D +**/=0D +VOID=0D +PchClearInSmmSts (=0D + VOID=0D + )=0D +{=0D + UINT32 Data32;=0D +=0D + ///=0D + /// Read memory location FED30880h AND with FFFFFFFEh, place the result = in EAX,=0D + /// and write data to lower 32 bits of MSR 1FEh (sample code available)= =0D + ///=0D + Data32 =3D MmioRead32 (0xFED30880);=0D + AsmWriteMsr32 (MSR_SPCL_CHIPSET_USAGE, Data32 & (UINT32) (~BIT0));=0D + ///=0D + /// Read FED30880h back to ensure the setting went through.=0D + ///=0D + Data32 =3D MmioRead32 (0xFED30880);=0D +}=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPri= vateLib/SmmPchPrivateLib.inf b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Librar= yPrivate/SmmPchPrivateLib/SmmPchPrivateLib.inf new file mode 100644 index 0000000000..6d4c3a5729 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/LibraryPrivate/SmmPchPrivateLib= /SmmPchPrivateLib.inf @@ -0,0 +1,31 @@ +## @file=0D +# PCH SMM private lib.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +INF_VERSION =3D 0x00010017=0D +BASE_NAME =3D SmmPchPrivateLib=0D +FILE_GUID =3D FE6495FB-7AA9-4A24-BF3E-4698F7BCE0EE=0D +VERSION_STRING =3D 1.0=0D +MODULE_TYPE =3D DXE_SMM_DRIVER=0D +LIBRARY_CLASS =3D SmmPchPrivateLib=0D +=0D +=0D +[LibraryClasses]=0D +BaseLib=0D +IoLib=0D +DebugLib=0D +=0D +=0D +[Packages]=0D +MdePkg/MdePkg.dec=0D +TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +=0D +[Sources]=0D +SmmPchPrivateLib.c=0D --=20 2.24.0.windows.2