From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web12.5213.1612510882795645881 for ; Thu, 04 Feb 2021 23:41:22 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: heng.luo@intel.com) IronPort-SDR: 7FWHrGMIa5ky9AUlCakS3GjpIy/OzfxGHaUn9gKh8MmGBwbtUh8Qh18KQd7VEP1dgvxvR4WEMP H9wnRzipefSg== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543602" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543602" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:22 -0800 IronPort-SDR: OZMUeiNZop+dYJvtCdZPSOKDzmJhlbtB63WWz0+6UeFCq8vo0DeS+wzC7Ti+tk8P2rHfdf1dY6 j6uE0ZuKCuFQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260228" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:21 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Date: Fri, 5 Feb 2021 15:40:09 +0800 Message-Id: <20210205074045.3916-4-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds header files common to CPU modules. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h = | 83 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLibPreM= emConfig.h | 148 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestConfig= .h | 52 ++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtBasi= cConfig.h | 226 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtCust= omConfig.h | 76 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtPsys= Config.h | 36 ++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgmtTest= Config.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurityPreMe= mConfig.h | 63 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConfig.h = | 51 +++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h = | 12 ++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h = | 21 +++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h = | 23 +++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h = | 18 ++++++++++++++++++ 13 files changed, 959 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConf= ig.h new file mode 100644 index 0000000000..d837500a38 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfig.h @@ -0,0 +1,83 @@ +/** @file=0D + CPU Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_CONFIG_H_=0D +#define _CPU_CONFIG_H_=0D +=0D +#define CPU_CONFIG_REVISION 3=0D +=0D +extern EFI_GUID gCpuConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Add SmbiosType4MaxSpeedOverride.=0D + Revision 3:=0D + - Add AvxDisable & Avx3Disable.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + UINT32 MicrocodePatchRegionSize;=0D + EFI_PHYSICAL_ADDRESS MicrocodePatchAddress; ///< Pointer to microcod= e patch that is suitable for this processor.=0D + /**=0D + Enable or Disable Advanced Encryption Standard (AES) feature.=0D + For some countries, this should be disabled for legal reasons.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 AesEnable : 1;=0D + /**=0D + Enable or Disable Trusted Execution Technology (TXT) feature.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 TxtEnable : 1;=0D + UINT32 SkipMpInit : 1; ///< For Fsp only, Silic= on Initialization will skip MP Initialization (including BSP) if enabled. F= or non-FSP, this should always be 0.=0D + /**=0D + Enable or Disable or Auto for PPIN Support to view Protected Processor= Inventory Number.=0D + - 0: Disable=0D + - 1: Enable=0D + - 2: Auto : Feature is based on End Of Manufacturing (EOM) flag. If= EOM is set, it is disabled.=0D + **/=0D + UINT32 PpinSupport : 2;=0D + /**=0D + Enable or Disable #AC machine check on split lock.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 AcSplitLock : 1;=0D + /**=0D + Enable or Disable Avx.=0D + - 1: Disable=0D + - 0: Enable=0D + **/=0D + UINT32 AvxDisable : 1;=0D + /**=0D + Enable or Disable Avx3.=0D + - 1: Disable=0D + - 0: Enable=0D + **/=0D + UINT32 Avx3Disable : 1;=0D + UINT32 RsvdBits : 24; ///< Reserved for future= use=0D + /**=0D + Provide the option for platform to override the MaxSpeed field of Smbi= os Type 4.=0D + Value 4000 means 4000MHz.=0D + If this value is not zero, it dominates the field.=0D + If this value is zero, CPU RC will update the field according to the m= ax radio.=0D + default is 0.=0D + **/=0D + UINT16 SmbiosType4MaxSpeedOverride;=0D + UINT8 Reserved0[2]; ///< Reserved for future= use=0D +} CPU_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuC= onfigLibPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Conf= igBlock/CpuConfigLibPreMemConfig.h new file mode 100644 index 0000000000..bf3f436ddd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuConfigLi= bPreMemConfig.h @@ -0,0 +1,148 @@ +/** @file=0D + CPU Security PreMemory Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_CONFIG_LIB_PREMEM_CONFIG_H_=0D +#define _CPU_CONFIG_LIB_PREMEM_CONFIG_H_=0D +=0D +#define CPU_CONFIG_LIB_PREMEM_CONFIG_REVISION 6=0D +=0D +extern EFI_GUID gCpuConfigLibPreMemConfigGuid;=0D +=0D +#define BOOT_FREQUENCY_MAX_BATTERY_PERF 0=0D +#define BOOT_FREQUENCY_MAX_NON_TURBO_PERF 1=0D +#define BOOT_FREQUENCY_TURBO_PERF 2=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Config Library PreMemory Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Expand the supported number of processor cores (ActiveCoreCount1).=0D + Revision 3:=0D + - Added PECI Sx and C10 Reset.=0D + Revision 4:=0D + - Added ActiveSmallCoreCount.=0D + Revision 5:=0D + - Added CrashLogGprs=0D + Revision 6:=0D + - Added ConfigTdpLevel=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + UINT32 HyperThreading : 1; ///< Enable or Disable Hyper Thre= ading; 0: Disable; 1: Enable.=0D + /**=0D + Sets the boot frequency starting from reset vector.=0D + - 0: Maximum battery performance.=0D + - 1: Maximum non-turbo performance=0D + -2: Turbo performance.=0D + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode.=0D + **/=0D + UINT32 BootFrequency : 2;=0D + /**=0D + Number of processor cores to enable.=0D + - 0: All cores=0D + - 1: 1 core=0D + - 2: 2 cores=0D + - 3: 3 cores=0D + **/=0D + UINT32 ActiveCoreCount : 3; ///< @deprecated due to core acti= ve number limitaion.=0D + UINT32 JtagC10PowerGateDisable : 1; ///< False: JTAG is power gated i= n C10 state. True: keeps the JTAG power up during C10 and deeper power stat= es for debug purpose. 0: False<\b>; 1: True.=0D + UINT32 BistOnReset : 1; ///< (Test) Enable or Disa= ble BIST on Reset; 0: Disable; 1: Enable.=0D + /**=0D + Enable or Disable Virtual Machine Extensions (VMX) feature.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 VmxEnable : 1;=0D + /**=0D + Processor Early Power On Configuration FCLK setting.=0D + - 0: 800 MHz (ULT/ULX).=0D + - 1: 1 GHz (DT/Halo). Not supported on ULT/ULX.=0D + - 2: 400 MHz.=0D + - 3: Reserved.=0D + **/=0D + UINT32 FClkFrequency : 2;=0D + /**=0D + Enable or Disable CrashLog feature=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 CrashLogEnable : 1;=0D +=0D + /**=0D + Enable or Disable Total Memory Encryption (TME) feature.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 TmeEnable : 1;=0D +=0D + UINT32 DebugInterfaceEnable : 2; ///< Enable or Disable processor = debug features; 0: Disable; 1: Enable; 2: No Change.=0D + UINT32 DebugInterfaceLockEnable : 1; ///< Lock or Unlock debug interfa= ce features; 0: Disable; 1: Enable.=0D +=0D + /**=0D + Number of big cores in processor to enable. And support up to 16 cores= .=0D + - 0: All cores=0D + - 1: 1 core=0D + - 2: 2 cores=0D + - 3: 3 cores=0D + **/=0D + UINT32 ActiveCoreCount1 : 4;=0D +=0D + /**=0D + Enables a mailbox command to resolve rare PECI related Sx issues.=0D + @note This should only be used on systems that observe PECI Sx issues.=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 PeciSxReset : 1;=0D +=0D + /**=0D + Enables the mailbox command to resolve PECI reset issues during Pkg-C10 = exit.=0D + If Enabled, BIOS will send the CPU message to disable peci reset on C10 = exit.=0D + The default value is 1: Enable for CML, and 0: Disable for= all other CPU's=0D + - 0: Disable=0D + - 1: Enable=0D + **/=0D + UINT32 PeciC10Reset : 1;=0D +=0D + /**=0D + Number of small cores in processor to enable. And support the enabling= of up to 63 cores.=0D + - 0: All cores=0D + - 1: 1 core=0D + - 2: 2 cores=0D + - 3: 3 cores=0D + **/=0D + UINT32 ActiveSmallCoreCount : 6;=0D +=0D + /**=0D + Enable or Disable CrashLog GPRs dump=0D + - 0: Disable=0D + - 1: Gprs Enabled, Smm Gprs Enabled=0D + 2: Gprs Enabled, Smm Gprs Disabled=0D + **/=0D + UINT32 CrashLogGprs : 2;=0D +=0D + UINT32 RsvdBits : 2;=0D +=0D + /**=0D + CpuRatio - Max non-turbo ratio (Flexible Ratio Boot) is set to CpuRati= o. 0: Disabled If disabled, doesn't override max-non turbo ratio.=0D + **/=0D + UINT8 CpuRatio;=0D + /**=0D + Configuration for boot TDP selection; 0: TDP Nominal; 1: TDP Do= wn; 2: TDP Up.=0D + **/=0D + UINT8 ConfigTdpLevel;=0D + UINT8 Reserved[2]; ///< Reserved for alignment=0D + UINT32 ElixirSpringsPatchAddr; ///< Address of Elixir Springs Pa= tch(es)=0D + UINT32 ElixirSpringsPatchSize; ///< Elixir Springs Patch(es) Siz= e.=0D +} CPU_CONFIG_LIB_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_CONFIG_LIB_PREMEM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuP= idTestConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/= CpuPidTestConfig.h new file mode 100644 index 0000000000..4fcb92cb27 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPidTestC= onfig.h @@ -0,0 +1,52 @@ +/** @file=0D + CPU PID Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_PID_TEST_CONFIG_H_=0D +#define _CPU_PID_TEST_CONFIG_H_=0D +=0D +#define CPU_PID_TEST_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gCpuPidTestConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + PID Tuning Configuration Structure.=0D + Domain is mapped to Kp =3D 0, Ki =3D 1, Kd =3D 2.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + UINT16 Ratl[3]; ///< RATL setting, in 1/= 256 units. Range is 0 - 65280=0D + UINT16 VrTdcVr0[3]; ///< VR Thermal Design C= urrent for VR0. In 1/256 units. Range is 0 - 65280=0D + UINT16 VrTdcVr1[3]; ///< VR Thermal Design C= urrent for VR1. In 1/256 units. Range is 0 - 65280=0D + UINT16 VrTdcVr2[3]; ///< VR Thermal Design C= urrent for VR2. In 1/256 units. Range is 0 - 65280=0D + UINT16 VrTdcVr3[3]; ///< VR Thermal Design C= urrent for VR3. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPsysPl1Msr[3]; ///< Power Budget Manage= ment Psys PL1 MSR. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPsysPl1MmioPcs[3]; ///< Power Budget Manage= ment Psys PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPsysPl2Msr[3]; ///< Power Budget Manage= ment Psys PL2 MSR. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPsysPl2MmioPcs[3]; ///< Power Budget Manage= ment Psys PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPkgPl1Msr[3]; ///< Power Budget Manage= ment Package PL1 MSR. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPkgPl1MmioPcs[3]; ///< Power Budget Manage= ment Package PL1 MMIO/PCS. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPkgPl2Msr[3]; ///< Power Budget Manage= ment Package PL2 MSR. In 1/256 units. Range is 0 - 65280=0D + UINT16 PbmPkgPl2MmioPcs[3]; ///< Power Budget Manage= ment Package PL2 MMIO/PCS. In 1/256 units. Range is 0 - 65280=0D + UINT16 DdrPl1Msr[3]; ///< DDR PL1 MSR. In 1/2= 56 units. Range is 0 - 65280=0D + UINT16 DdrPl1MmioPcs[3]; ///< DDR PL1 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280=0D + UINT16 DdrPl2Msr[3]; ///< DDR PL2 MSR. In 1/2= 56 units. Range is 0 - 65280=0D + UINT16 DdrPl2MmioPcs[3]; ///< DDR PL2 MMIO/PCS. I= n 1/256 units. Range is 0 - 65280=0D + /**=0D + Enable or Disable PID Tuning programming flow.=0D + If disabled, all other policies in this config block are ignored.=0D + **/=0D + UINT8 PidTuning;=0D + UINT8 Rsvd; ///< Reserved for DWORD = alignment.=0D +} CPU_PID_TEST_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_PID_TEST_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuP= owerMgmtBasicConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Confi= gBlock/CpuPowerMgmtBasicConfig.h new file mode 100644 index 0000000000..0255d49bdf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm= tBasicConfig.h @@ -0,0 +1,226 @@ +/** @file=0D + CPU Power Management Basic Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POWER_MGMT_BASIC_CONFIG_H_=0D +#define _CPU_POWER_MGMT_BASIC_CONFIG_H_=0D +=0D +#define CPU_POWER_MGMT_BASIC_CONFIG_REVISION 5=0D +=0D +extern EFI_GUID gCpuPowerMgmtBasicConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Power Management Basic Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Changed EnableItbm default to be disable=0D + - Deprecated EnableItbmDriver due to Platform doesn't have ITBMT OS driv= er=0D + Revision 3:=0D + - Add ApplyConfigTdp for TDP initialization settings based on non-cTDP o= r cTDP=0D + Revision 4:=0D + - Add Hwp Lock support=0D + Revision 5:=0D + - Add VccInDemotionOverride and VccInDemotionMs=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + Sets the boot frequency starting from reset vector.=0D + - 0: Maximum battery performance.=0D + - 1: Maximum non-turbo performance.=0D + - 2: Turbo performance.=0D + @note If Turbo is selected BIOS will start in max non-turbo mode and swi= tch to Turbo mode.=0D + **/=0D + UINT32 BootFrequency : 2; //@deprecated=0D + UINT32 SkipSetBootPState : 1; ///< Choose whether to s= kip SetBootPState function for all APs; 0: Do not skip; 1: Skip.=0D + /**=0D + Enable or Disable Intel Speed Shift Technology.=0D + Enabling allows for processor control of P-state transitions.=0D + 0: Disable; 1: Enable; Bit 1 is ignored.=0D + @note Currently this feature is recommended to be enabled only on win10= =0D + **/=0D + UINT32 Hwp : 2;=0D + /**=0D + Hardware Duty Cycle Control configuration. 0: Disabled; 1: Enabled 2-3:Reserved=0D + HDC enables the processor to autonomously force components to enter into= an idle state to lower effective frequency.=0D + This allows for increased package level C6 residency.=0D + @note Currently this feature is recommended to be enabled only on win10= =0D + **/=0D + UINT32 HdcControl : 2;=0D + UINT32 PowerLimit2 : 1; ///< Enable or Disable s= hort duration Power Limit (PL2). 0: Disable; 1: Enable=0D + UINT32 TurboPowerLimitLock : 1; ///< MSR 0x610[63] and 0= x618[63]: Locks all Turbo power limit settings to read-only; 0: Disable<= /b>; 1: Enable (Lock).=0D + UINT32 PowerLimit3DutyCycle : 8; ///< Package PL3 Duty Cy= cle. Specifies the PL3 duty cycle percentage, Range 0-100. Default: 0.=0D + UINT32 PowerLimit3Lock : 1; ///< Package PL3 MSR 615= h lock; 0: Disable; 1: Enable (Lock).=0D + UINT32 PowerLimit4Lock : 1; ///< Package PL4 MSR 601= h lock; 0: Disable; 1: Enable (Lock).=0D + /**=0D + Tcc Offset Clamp for Runtime Average Temperature Limit (RATL) allows CPU= to throttle below P1.=0D + For Y SKU, the recommended default for this policy is 1: Enabled,= which indicates throttling below P1 is allowed.=0D + For all other SKUs the recommended default are 0: Disabled.=0D + **/=0D + UINT32 TccOffsetClamp : 1;=0D + UINT32 TccOffsetLock : 1; ///< Tcc Offset Lock for= Runtime Average Temperature Limit (RATL) to lock temperature target MSR 1A= 2h; 0: Disabled; 1: Enabled (Lock).=0D + UINT32 TurboMode : 1; ///< Enable or Disable T= urbo Mode. Disable; 1: Enable=0D + UINT32 HwpInterruptControl : 1; ///< Set HW P-State Inte= rrupts Enabled for MISC_PWR_MGMT MSR 0x1AA[7]; 0: Disable; 1: Enabl= e.=0D + UINT32 ApplyConfigTdp : 1; ///< Switch TDP applied = setting based on non-cTDP or TDP; 0: non-cTDP; 1: cTDP.=0D + UINT32 HwpLock : 1; ///< HWP Lock in MISC PW= R MGMT MSR 1AAh; 0: Disable; 1: Enable (Lock).=0D + UINT32 VccInDemotionOverride : 1; ///< Enable VccIn Demoti= on Override configuration. 0: Disable; 1: Enable.=0D + UINT32 RsvdBits : 6; ///< Reserved for future= use.=0D +=0D + /**=0D + 1-Core Ratio Limit: LFM to Fused 1-Core Ratio Limit. For overclocking p= arts: LFM to Fused 1-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 1-Core Ratio Limit Must be greater than or equal to 2-Core Rat= io Limit, 3-Core Ratio Limit, 4-Core Ratio Limit.=0D + **/=0D + UINT8 OneCoreRatioLimit;=0D + /**=0D + 2-Core Ratio Limit: LFM to Fused 2-Core Ratio Limit, For overclocking p= art: LFM to Fused 2-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 2-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 TwoCoreRatioLimit;=0D + /**=0D + 3-Core Ratio Limit: LFM to Fused 3-Core Ratio Limit, For overclocking p= art: LFM to Fused 3-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 3-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 ThreeCoreRatioLimit;=0D + /**=0D + 4-Core Ratio Limit: LFM to Fused 4-Core Ratio Limit, For overclocking p= art: LFM to Fused 4-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 4-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 FourCoreRatioLimit;=0D + /**=0D + 5-Core Ratio Limit: LFM to Fused 5-Core Ratio Limit, For overclocking p= art: LFM to Fused 5-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 5-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 FiveCoreRatioLimit;=0D + /**=0D + 6-Core Ratio Limit: LFM to Fused 6-Core Ratio Limit, For overclocking p= art: LFM to Fused 6-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 6-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 SixCoreRatioLimit;=0D + /**=0D + 7-Core Ratio Limit: LFM to Fused 7-Core Ratio Limit, For overclocking p= art: LFM to Fused 7-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 7-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 SevenCoreRatioLimit;=0D + /**=0D + 8-Core Ratio Limit: LFM to Fused 8-Core Ratio Limit, For overclocking p= art: LFM to Fused 8-Core Ratio Limit + OC Bins.=0D + Note: OC Bins =3D 7 means fully unlocked, so range is LFM to 83.=0D + - This 8-Core Ratio Limit Must be Less than or equal to 1-Core Ratio = Limit.=0D + **/=0D + UINT8 EightCoreRatioLimit;=0D + /**=0D + TCC Activation Offset. Offset from factory set TCC activation temperatur= e at which the Thermal Control Circuit must be activated.=0D + TCC will be activated at (TCC Activation Temperature - TCC Activation Of= fset), in degrees Celcius.=0D + For Y SKU, the recommended default for this policy is 10=0D + For all other SKUs the recommended default are 0, causing TCC to = activate at TCC Activation temperature.=0D + @note The policy is recommended for validation purpose only.=0D + **/=0D + UINT8 TccActivationOffset;=0D + /**=0D + Intel Turbo Boost Max Technology 3.0=0D + Enabling it on processors with OS support will allow OS to exploit the d= iversity in max turbo frequency of the cores.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableItbm : 1;=0D + /**=0D + @deprecated: Platform doesn't have Intel Turbo Boost Max Technology 3.0 = Driver=0D + Enabling it will load the driver upon ACPI device with HID =3D INT3510.= =0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableItbmDriver : 1;=0D + /**=0D + Per Core P State OS control mode=0D + Disabling will set PCU_MISC_CONFIG (Command 0x06) Bit 31 =3D 1. When set= , the highest core request is used for all other core requests.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnablePerCorePState : 1;=0D + /**=0D + HwP Autonomous Per Core P State=0D + Disabling will set Bit 30 =3D 1, command 0x11. When set, autonomous will= request the same value=0D + for all cores all the time.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableHwpAutoPerCorePstate : 1;=0D + /**=0D + HwP Autonomous EPP grouping.=0D + Disabling will set Bit 29 =3D 1, command 0x11. When set, autonomous will= not necesarrily request the same value=0D + for all cores with same EPP.=0D + Enabling will clean Bit 29 =3D 0, command 0x11. Autonomous will request = same values for all cores with same EPP.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableHwpAutoEppGrouping : 1;=0D + /**=0D + EPB override over PECI=0D + Enable by sending pcode command 0x2b , subcommand 0x3 to 1.=0D + This will allow OOB EPB PECI override control.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableEpbPeciOverride : 1;=0D + /**=0D + Support for Fast MSR for IA32_HWP_REQUEST.=0D + On systems with HwP enabled, if this feature is available as indicated b= y MSR 0x65F[0] =3D 1,=0D + set MSR 0x657[0] =3D 1.=0D + 0: Disable; 1: Enable;=0D + **/=0D + UINT8 EnableFastMsrHwpReq : 1;=0D + UINT8 ReservedBits1 : 1; ///< Reserved for future= use.=0D + UINT8 MinRingRatioLimit; ///< Minimum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default=0D + UINT8 MaxRingRatioLimit; ///< Maximum Ring Ratio = Limit. Range from 0 to Max Turbo Ratio. 0 =3D AUTO/HW Default=0D + /**=0D + Package Long duration turbo mode power limit (PL1).=0D + Default is the TDP power limit of processor. Units are based on POWER_MG= MT_CONFIG.CustomPowerUnit.=0D + **/=0D + UINT16 PowerLimit1;=0D + /**=0D + Package Short duration turbo mode power limit (PL2). Allows for short ex= cursions above TDP power limit.=0D + Default =3D 1.25 * TDP Power Limit. Units are based on POWER_MGMT_CONFIG= .CustomPowerUnit.=0D + **/=0D + UINT16 PowerLimit2Power;=0D + /**=0D + Package PL3 power limit. PL3 is the CPU Peak Power Occurences Limit.=0D + Default: 0. Range 0-65535. Units are based on POWER_MGMT_CONFIG.C= ustomPowerUnit.=0D + **/=0D + UINT16 PowerLimit3;=0D + /**=0D + Package PL4 power limit. PL4 is a Preemptive CPU Package Peak Power Limi= t, it will never be exceeded.=0D + Power is premptively lowered before limit is reached. Default: 0.= Range 0-65535.=0D + Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.=0D + **/=0D + UINT16 PowerLimit4;=0D + /**=0D + Package Long duration turbo mode power limit (PL1) time window in second= s.=0D + Used in calculating the average power over time.=0D + Mobile: 28s=0D + Desktop: 8s=0D + Range: 0 - 128s=0D + **/=0D + UINT32 PowerLimit1Time;=0D + UINT32 PowerLimit3Time; ///< Package PL3 time wi= ndow. Range from 3ms to 64ms.=0D + /**=0D + Tcc Offset Time Window can range from 5ms to 448000ms for Runtime Averag= e Temperature Limit (RATL).=0D + For Y SKU, the recommended default for this policy is 5000: 5 seconds= , For all other SKUs the recommended default are 0: Disabled=0D + **/=0D + UINT32 TccOffsetTimeWindowForRatl;=0D + /**=0D + Customize the VccIn Demotion in ms accordingly. Values used by OEM expec= ted to be in lower end of 1-30 ms range.=0D + Value 1 means 1ms, value 2 means 2ms, and so on. Value 0 will disable Vc= cIn Demotion knob.=0D + It's 30ms by silicon default.=0D + **/=0D + UINT32 VccInDemotionMs;=0D +} CPU_POWER_MGMT_BASIC_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_POWER_MGMT_BASIC_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuP= owerMgmtCustomConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Conf= igBlock/CpuPowerMgmtCustomConfig.h new file mode 100644 index 0000000000..e1a5bcc684 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm= tCustomConfig.h @@ -0,0 +1,76 @@ +/** @file=0D + CPU Power Managment Custom Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POWER_MGMT_CUSTOM_CONFIG_H_=0D +#define _CPU_POWER_MGMT_CUSTOM_CONFIG_H_=0D +=0D +#define CPU_POWER_MGMT_CUSTOM_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gCpuPowerMgmtCustomConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +///=0D +/// Defines the maximum number of custom ratio states supported.=0D +///=0D +#define MAX_CUSTOM_RATIO_TABLE_ENTRIES 40=0D +#define MAX_16_CUSTOM_RATIO_TABLE_ENTRIES 16=0D +=0D +///=0D +/// Defines the maximum number of custom ConfigTdp entries supported.=0D +/// @warning: Changing this define would cause DWORD alignment issues in p= olicy structures.=0D +///=0D +#define MAX_CUSTOM_CTDP_ENTRIES 3=0D +=0D +///=0D +/// This structure is used to describe the custom processor ratio table de= sired by the platform.=0D +///=0D +typedef struct {=0D + UINT8 MaxRatio; ///< The maxi= mum ratio of the custom ratio table.=0D + UINT8 NumberOfEntries; ///< The numb= er of custom ratio state entries, ranges from 2 to 40 for a valid custom ra= tio table.=0D + UINT8 Rsvd0[2]; ///< Reserved= for DWORD alignment.=0D + UINT32 Cpuid; ///< The CPU = ID for which this custom ratio table applies.=0D + UINT8 StateRatio[MAX_CUSTOM_RATIO_TABLE_ENTRIES]; ///< The proc= essor ratios in the custom ratio table.=0D + ///=0D + /// If there are more than 16 total entries in the StateRatio table, the= n use these 16 entries to fill max 16 table.=0D + /// @note If NumberOfEntries is 16 or less, or the first entry of this t= able is 0, then this table is ignored,=0D + /// and up to the top 16 values from the StateRatio table is used instea= d.=0D + ///=0D + UINT8 StateRatioMax16[MAX_16_CUSTOM_RATIO_TABLE_ENTRIES];=0D +#if ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_TABLE_ENTRIES) = % 4)=0D + UINT8 Rsvd1[4 - ((MAX_CUSTOM_RATIO_TABLE_ENTRIES + MAX_16_CUSTOM_RATIO_= TABLE_ENTRIES) % 4)]; ///< If needed, add padding for dword alignment.=0D +#endif=0D +} PPM_CUSTOM_RATIO_TABLE;=0D +=0D +///=0D +/// PPM Custom ConfigTdp Settings=0D +///=0D +typedef struct _PPM_CUSTOM_CTDP_TABLE {=0D + UINT32 CustomPowerLimit1Time : 8; ///< Short term Power= Limit time window value for custom cTDP level.=0D + UINT32 CustomTurboActivationRatio : 8; ///< Turbo Activation= Ratio for custom cTDP level.=0D + UINT32 RsvdBits : 16; ///< Bits reserved fo= r DWORD alignment.=0D + UINT16 CustomPowerLimit1; ///< Short term Power= Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cu= stomPowerUnit.=0D + UINT16 CustomPowerLimit2; ///< Long term Power = Limit value for custom cTDP level. Units are based on POWER_MGMT_CONFIG.Cus= tomPowerUnit.=0D +} PPM_CUSTOM_CTDP_TABLE;=0D +=0D +/**=0D + CPU Power Management Custom Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; = ///< Config Block Header=0D + PPM_CUSTOM_RATIO_TABLE CustomRatioTable; = ///< Custom Processor Ratio Table Instance=0D + PPM_CUSTOM_CTDP_TABLE CustomConfigTdpTable[MAX_CUSTOM_CTDP_ENTRIES]; = ///< Custom ConfigTdp Settings Instance=0D + UINT32 ConfigTdpLock : 1; = ///< Lock the ConfigTdp mode settings from runtime changes; 0: Dis= able; 1: Enable.=0D + UINT32 ConfigTdpBios : 1; = ///< Configure whether to load Configurable TDP SSDT; 0: Disable; 1: Enable.=0D + UINT32 RsvdBits : 30; = ///< Reserved for future use=0D +} CPU_POWER_MGMT_CUSTOM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_POWER_MGMT_CUSTOM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuP= owerMgmtPsysConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Config= Block/CpuPowerMgmtPsysConfig.h new file mode 100644 index 0000000000..f1ceb8f43b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm= tPsysConfig.h @@ -0,0 +1,36 @@ +/** @file=0D + CPU Power Management Psys(Platform) Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POWER_MGMT_PSYS_CONFIG_H_=0D +#define _CPU_POWER_MGMT_PSYS_CONFIG_H_=0D +=0D +#define CPU_POWER_MGMT_PSYS_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gCpuPowerMgmtPsysConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Power Management Psys(Platform) Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + UINT32 PsysPowerLimit1 : 1; ///< MSR 0x65C[15]: PL1 = Enable activates the PL1 value to limit average platform power=0D + UINT32 PsysPowerLimit1Time : 8; ///< MSR 0x65C[23:17]: P= L1 timewindow in seconds.=0D + UINT32 PsysPowerLimit2 : 1; ///< MSR 0x65C[47]: PL2 = Enable activates the PL2 value to limit average platform power=0D + UINT32 RsvdBits : 22; ///< Reserved for future= use.=0D + UINT16 PsysPowerLimit1Power; ///< MSR 0x65C[14:0]: Pl= atform PL1 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.=0D + UINT16 PsysPowerLimit2Power; ///< MSR 0x65C[46:32]]: = Platform PL2 power. Units are based on POWER_MGMT_CONFIG.CustomPowerUnit.=0D + UINT16 PsysPmax; ///< PCODE MMIO Mailbox:= Platform Power Pmax. 0 - Auto Specified in 1/8 Watt increments. 0-1= 024 Watts. Value of 800 =3D 100W.=0D + UINT8 Rsvd[2]; ///< Reserved for future= use and config block alignment=0D +} CPU_POWER_MGMT_PSYS_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_POWER_MGMT_PSYS_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuP= owerMgmtTestConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Config= Block/CpuPowerMgmtTestConfig.h new file mode 100644 index 0000000000..bd641f27c5 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuPowerMgm= tTestConfig.h @@ -0,0 +1,150 @@ +/** @file=0D + CPU Power Management Test Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POWER_MGMT_TEST_CONFIG_H_=0D +#define _CPU_POWER_MGMT_TEST_CONFIG_H_=0D +=0D +#define CPU_POWER_MGMT_TEST_CONFIG_REVISION 4=0D +=0D +extern EFI_GUID gCpuPowerMgmtTestConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +///=0D +/// PPM Package C State Limit=0D +///=0D +typedef enum {=0D + PkgC0C1 =3D 0,=0D + PkgC2,=0D + PkgC3,=0D + PkgC6,=0D + PkgC7,=0D + PkgC7s,=0D + PkgC8,=0D + PkgC9,=0D + PkgC10,=0D + PkgCMax,=0D + PkgCpuDefault =3D 254,=0D + PkgAuto =3D 255=0D +} MAX_PKG_C_STATE;=0D +=0D +///=0D +/// PPM Package C State Time Limit=0D +///=0D +typedef enum {=0D + TimeUnit1ns =3D 0,=0D + TimeUnit32ns,=0D + TimeUnit1024ns,=0D + TimeUnit32768ns,=0D + TimeUnit1048576ns,=0D + TimeUnit33554432ns,=0D + TimeUnitMax=0D +} C_STATE_TIME_UNIT;=0D +=0D +///=0D +/// Custom Power Units. User can choose to enter in watts or 125 milliwatt= increments.=0D +///=0D +typedef enum {=0D + PowerUnitWatts =3D 0, ///< in Watts.=0D + PowerUnit125MilliWatts, ///< in 125 milliwatt increments. Example: 90 po= wer units times 125 mW equals 11.250 W.=0D + PowerUnitMax=0D +} CUSTOM_POWER_UNIT;=0D +=0D +///=0D +/// PPM Interrupt Redirection Mode Selection=0D +///=0D +typedef enum {=0D + PpmIrmFixedPriority =3D 0,=0D + PpmIrmRoundRobin,=0D + PpmIrmHashVector,=0D + PpmIrmReserved1,=0D + PpmIrmReserved2,=0D + PpmIrmReserved3,=0D + PpmIrmReserved4,=0D + PpmIrmNoChange=0D +} PPM_IRM_SETTING;=0D +=0D +/**=0D + CPU Power Management Test Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Add CstateLatencyControl0TimeUnit for WHL only=0D + - Add CstateLatencyControl0Irtl for WHL only=0D + Revision 3:=0D + - Change C State LatencyContol to Auto as default.=0D + Revision 4:=0D + - Deprecate ConfigTdpLevel. Move to premem.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Confi= g Block Header=0D + UINT32 Eist : 1; ///< Offset 28-31 Enabl= e or Disable Intel SpeedStep Technology. 0: Disable; 1: Enable=0D + UINT32 EnergyEfficientPState : 1; ///< Enabl= e or Disable Energy Efficient P-state will be applied in Turbo mode. Disabl= e; 1: Enable=0D + UINT32 EnergyEfficientTurbo : 1; ///< Enabl= e or Disable Energy Efficient Turbo, will be applied in Turbo mode. Disable= ; 1: Enable=0D + UINT32 TStates : 1; ///< Enabl= e or Disable T states; 0: Disable; 1: Enable.=0D + UINT32 BiProcHot : 1; ///< Enabl= e or Disable Bi-Directional PROCHOT#; 0: Disable; 1: Enable.=0D + UINT32 DisableProcHotOut : 1; ///< Enabl= e or Disable PROCHOT# signal being driven externally; 0: Disable; 1: Ena= ble.=0D + UINT32 ProcHotResponse : 1; ///< Enabl= e or Disable PROCHOT# Response; 0: Disable; 1: Enable.=0D + UINT32 DisableVrThermalAlert : 1; ///< Enabl= e or Disable VR Thermal Alert; 0: Disable; 1: Enable.=0D + UINT32 EnableAllThermalFunctions : 1; ///< Enabl= e or Disable Thermal Reporting through ACPI tables; 0: Disable; 1: Enabl= e.=0D + UINT32 ThermalMonitor : 1; ///< Enabl= e or Disable Thermal Monitor; 0: Disable; 1: Enable.=0D + UINT32 Cx : 1; ///< Enabl= e or Disable CPU power states (C-states). 0: Disable; 1: Enable=0D + UINT32 PmgCstCfgCtrlLock : 1; ///< If en= abled, sets MSR 0xE2[15]; 0: Disable; 1: Enable.=0D + UINT32 C1e : 1; ///< Enabl= e or Disable Enhanced C-states. 0: Disable; 1: Enable=0D + UINT32 C1AutoDemotion : 1; ///< Enabl= e or Disable C6/C7 auto demotion to C1. 0: Disabled; 1: C1 Auto demotion= =0D + UINT32 C1UnDemotion : 1; ///< Enabl= e or Disable C1UnDemotion. 0: Disabled; 1: C1 Auto undemotion=0D + UINT32 C3AutoDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C6/C7 auto demotion to C3 0: Disabled; 1= : C3 Auto demotion=0D + UINT32 C3UnDemotion : 1; ///< [Coff= eeLake Only] Enable or Disable C3UnDemotion. 0: Disabled; 1: C3 Auto und= emotion=0D + UINT32 PkgCStateDemotion : 1; ///< Enabl= e or Disable Package Cstate Demotion. Disable; 1: Enable [WhiskeyLak= e] Disable; 1: Enable=0D + UINT32 PkgCStateUnDemotion : 1; ///< Enabl= e or Disable Package Cstate UnDemotion. Disable; 1: Enable [WhiskeyL= ake] Disable; 1: Enable=0D + UINT32 CStatePreWake : 1; ///< Enabl= e or Disable CState-Pre wake. Disable; 1: Enable=0D + UINT32 TimedMwait : 1; ///< Enabl= e or Disable TimedMwait Support. Disable; 1: Enable=0D + UINT32 CstCfgCtrIoMwaitRedirection : 1; ///< Enabl= e or Disable IO to MWAIT redirection; 0: Disable; 1: Enable.=0D + UINT32 ProcHotLock : 1; ///< If en= abled, sets MSR 0x1FC[23]; 0: Disable; 1: Enable.=0D + UINT32 RaceToHalt : 1; ///< Enabl= e or Disable Race To Halt feature; 0: Disable; 1: Enable . RTH will = dynamically increase CPU frequency in order to enter pkg C-State faster to = reduce overall power. (RTH is controlled through MSR 1FC bit 20)=0D + UINT32 ConfigTdpLevel : 8; ///< @depr= ecated. Move to premem phase.=0D + UINT16 CstateLatencyControl1Irtl; ///< Offset 32-33 Inter= rupt Response Time Limit of LatencyContol1 MSR 0x60B[9:0].0 is Auto.= =0D + UINT16 CstateLatencyControl2Irtl; ///< Offset 34-35 Inter= rupt Response Time Limit of LatencyContol2 MSR 0x60C[9:0].0 is Auto.= =0D + UINT16 CstateLatencyControl3Irtl; ///< Offset 36-37 Inter= rupt Response Time Limit of LatencyContol3 MSR 0x633[9:0].0 is Auto.= =0D + UINT16 CstateLatencyControl4Irtl; ///< Offset 38-39 Inter= rupt Response Time Limit of LatencyContol4 MSR 0x634[9:0].0 is Auto.= =0D + UINT16 CstateLatencyControl5Irtl; ///< Offset 40-41 Inter= rupt Response Time Limit of LatencyContol5 MSR 0x635[9:0].0 is Auto.= =0D + // Due to the removal of CstateLatencyControl0Irtl, PkgCStateLimit is no= t aligned to 32-bit address.=0D + UINT8 Rsvd1[2]; ///< Offset 42-43 Reser= ved for config block alignment.=0D + MAX_PKG_C_STATE PkgCStateLimit; ///< Offset 44 This = field is used to set the Max Pkg Cstate. Default set to Auto which limits t= he Max Pkg Cstate to deep C-state.=0D + /**=0D + @todo: The following enums have to be replaced with policies.=0D + **/=0D + C_STATE_TIME_UNIT Reserved; ///< Offset 45 Reser= ved for config block alignment.=0D + C_STATE_TIME_UNIT CstateLatencyControl1TimeUnit; ///< Offset 46 TimeU= nit for Latency Control1 MSR 0x60B[12:10]; 2: 1024ns.=0D + C_STATE_TIME_UNIT CstateLatencyControl2TimeUnit; ///< Offset 47 TimeU= nit for Latency Control2 MSR 0x60C[12:10]; 2: 1024ns.=0D + C_STATE_TIME_UNIT CstateLatencyControl3TimeUnit; ///< Offset 48 TimeU= nit for Latency Control3 MSR 0x633[12:10]; 2: 1024ns.=0D + C_STATE_TIME_UNIT CstateLatencyControl4TimeUnit; ///< Offset 49 TimeU= nit for Latency Control4 MSR 0x634[12:10]; 2: 1024ns.=0D + C_STATE_TIME_UNIT CstateLatencyControl5TimeUnit; ///< Offset 50 TimeU= nit for Latency Control5 MSR 0x635[12:10]; 2: 1024ns.=0D + /**=0D + Offset 51 Default power unit in watts or in 125 milliwatt increments.=0D + - 0: PowerUnitWatts.=0D + - 1: PowerUnit125MilliWatts.=0D + **/=0D + CUSTOM_POWER_UNIT CustomPowerUnit;=0D + /**=0D + Offset 52 Interrupt Redirection Mode Select.=0D + - 0: Fixed priority. //Default under CNL.=0D + - 1: Round robin.=0D + - 2: Hash vector.=0D + - 4: PAIR with fixed priority. //Default under KBL, not available und= er CNL.=0D + - 5: PAIR with round robin. //Not available under CNL.=0D + - 6: PAIR with hash vector. //Not available under CNL.=0D + - 7: No change.=0D + **/=0D + PPM_IRM_SETTING PpmIrmSetting;=0D + // Move the padding to previous offset to align the structure at 32-bit = address.=0D + UINT8 Rsvd[4]; ///< Offset 53-56 Reserv= ed for future use and config block alignment=0D +} CPU_POWER_MGMT_TEST_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_POWER_MGMT_TEST_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuS= ecurityPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Confi= gBlock/CpuSecurityPreMemConfig.h new file mode 100644 index 0000000000..24614fe497 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuSecurity= PreMemConfig.h @@ -0,0 +1,63 @@ +/** @file=0D + CPU Security PreMemory Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_SECURITY_PREMEM_CONFIG_H_=0D +#define _CPU_SECURITY_PREMEM_CONFIG_H_=0D +=0D +#define CPU_SECURITY_PREMEM_CONFIG_REVISION 1=0D +=0D +extern EFI_GUID gCpuSecurityPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Security PreMemory Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Heade= r=0D + UINT32 PrmrrSize; ///< PRMRR Size.Soft= ware Control: 0x0 32MB: 0x2000000, 64MB: 0x4000000, 128 MB: 0x8000000,= 256 MB: 0x10000000, 512 MB: 0x20000000=0D + UINT16 BiosSize; ///< Flash information = for BIOS Guard: BIOS Size in KB.=0D + UINT8 Reserved[2]; ///< Reserved for futur= e use=0D +/**=0D + Enable or Disable BIOS Guard; 0: Disable; 1: Enable.=0D + - This is an optional feature and can be opted out.=0D + - If this policy is set to Disabled, the policies in the BIOS_GUARD_CO= NFIG will be ignored.=0D + - If PeiBiosGuardLibNull is used, this policy will have no effect.=0D +**/=0D + UINT32 BiosGuard : 1;=0D + UINT32 BiosGuardToolsInterface : 1; ///< BIOS Guard Tools = Interface; 0: Disable, 1:Enable=0D +/**=0D + Enable or Disable Software Guard Extensions; 0: Disable; 1: Enab= le.=0D + - This is an optional feature and can be opted out.=0D + - If this policy is set to Disabled, the policies in the CPU_SGX_CONFI= G will be ignored.=0D + - If BaseSoftwareGuardLibNull is used, this policy will have no effect= .=0D +**/=0D + UINT32 EnableSgx : 1;=0D +/**=0D + Enable or Disable Trusted Execution Technology; 0: Disable; 1: E= nable.=0D + - This is an optional feature and can be opted out.=0D + - If this policy is set to Disabled, the policies in the CPU_TXT_PREME= M_CONFIG will be ignored.=0D + - If PeiTxtLibNull is used, this policy will have no effect.=0D +**/=0D + UINT32 Txt : 1;=0D + UINT32 SkipStopPbet : 1; ///< (Test) Ski= p Stop PBET Timer; 0: Disable; 1: Enable.=0D + ///=0D + /// (Test) This policy indicates whether or not BIOS should alloc= ate PRMRR memory for C6DRAM power gating feature.=0D + /// - 0: Don't allocate any PRMRR memory for C6DRAM power gating featur= e.=0D + /// - 1: Allocate PRMRR memory for C6DRAM power gating feature.= =0D + ///=0D + UINT32 EnableC6Dram : 1;=0D + UINT32 ResetAux : 1; ///< (Test) Res= et Auxiliary content, 0: Disabled, 1: Enabled=0D + UINT32 TxtAcheckRequest : 1; ///< (Test) Ach= eckRequest 0: Disabled, 1: Enabled. When Enabled, it will call Achec= k regardless of crashcode value=0D + UINT32 RsvdBits : 24; ///< Reserved for futu= re use=0D +} CPU_SECURITY_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_SECURITY_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuT= estConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/Cpu= TestConfig.h new file mode 100644 index 0000000000..ee946290e0 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/ConfigBlock/CpuTestConf= ig.h @@ -0,0 +1,51 @@ +/** @file=0D + CPU Test Config Block.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_TEST_CONFIG_H_=0D +#define _CPU_TEST_CONFIG_H_=0D +=0D +#define CPU_TEST_CONFIG_REVISION 2=0D +=0D +extern EFI_GUID gCpuTestConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + CPU Test Configuration Structure.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Removed Voltage Optimization feature.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + UINT32 MlcStreamerPrefetcher : 1; ///< Enab= le or Disable MLC Streamer Prefetcher; 0: Disable; 1: Enable.=0D + UINT32 MlcSpatialPrefetcher : 1; ///< Enab= le or Disable MLC Spatial Prefetcher; 0: Disable; 1: Enable.=0D + UINT32 MonitorMwaitEnable : 1; ///< Enab= le or Disable Monitor /MWAIT instructions; 0: Disable; 1: Enable.=0D + UINT32 MachineCheckEnable : 1; ///< Enab= le or Disable initialization of machine check registers; 0: Disable; 1: = Enable.=0D + UINT32 ProcessorTraceOutputScheme : 1; ///< Cont= rol on Processor Trace output scheme; 0: Single Range Output; 1: ToP= A Output.=0D + UINT32 ProcessorTraceEnable : 1; ///< Enab= le or Disable Processor Trace feature; 0: Disable; 1: Enable.=0D + UINT32 ThreeStrikeCounterDisable : 1; ///< Disa= ble Three strike counter; 0: FALSE; 1: TRUE.=0D + UINT32 RsvdBits : 25; ///< Res= erved for future use=0D + /**=0D + Base address of memory region allocated for Processor Trace.=0D + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB.=0D + - NULL: Disable=0D + **/=0D + EFI_PHYSICAL_ADDRESS ProcessorTraceMemBase;=0D + /**=0D + Length in bytes of memory region allocated for Processor Trace.=0D + Processor Trace requires 2^N alignment and size in bytes per thread, = from 4KB to 128MB.=0D + - 0: Disable=0D + **/=0D + UINT32 ProcessorTraceMemLength;=0D + UINT8 Reserved0[4];=0D +} CPU_TEST_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _CPU_TEST_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h b/Si= licon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h new file mode 100644 index 0000000000..5d5e4df071 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuAccess.h @@ -0,0 +1,12 @@ +/** @file=0D + Macros to simplify and abstract the interface to CPU configuration.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPUACCESS_H_=0D +#define _CPUACCESS_H_=0D +=0D +#include "CpuDataStruct.h"=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h = b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h new file mode 100644 index 0000000000..ba9a840e54 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuDataStruct.h @@ -0,0 +1,21 @@ +/** @file=0D + This file declares various data structures used in CPU reference code.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _CPU_DATA_STRUCT_H=0D +#define _CPU_DATA_STRUCT_H=0D +=0D +///=0D +/// Structure to hold the return value of AsmCpuid instruction=0D +///=0D +typedef struct {=0D + UINT32 RegEax; ///< Value of EAX.=0D + UINT32 RegEbx; ///< Value of EBX.=0D + UINT32 RegEcx; ///< Value of ECX.=0D + UINT32 RegEdx; ///< Value of EDX.=0D +} EFI_CPUID_REGISTER;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.= h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h new file mode 100644 index 0000000000..1178f68d0c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/CpuPolicyCommon.h @@ -0,0 +1,23 @@ +/** @file=0D + CPU Policy Structure definition which will contain several config blocks= during runtime.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _CPU_POLICY_COMMON_H_=0D +#define _CPU_POLICY_COMMON_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#endif // _CPU_POLICY_COMMON_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonM= sr.h b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h new file mode 100644 index 0000000000..a2cd1db1d6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Cpu/Include/Register/CommonMsr.h @@ -0,0 +1,18 @@ +=0D +/** @file=0D + CommonMsr.h=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _COMMONMSR_h=0D +#define _COMMONMSR_h=0D +#include =0D +=0D +/**=0D + Special Chipset Usage MSR=0D +**/=0D +#define MSR_SPCL_CHIPSET_USAGE 0x000001FE=0D +=0D +#endif /* _COMMONMSR_h */=0D --=20 2.24.0.windows.2