From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [Patch V3 05/40] TigerlakeSiliconPkg/Pch: Add include headers
Date: Fri, 5 Feb 2021 15:40:10 +0800 [thread overview]
Message-ID: <20210205074045.3916-5-heng.luo@intel.com> (raw)
In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com>
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171
Adds the following header files:
* Pch/Include
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h | 64 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h | 38 ++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h | 72 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h | 258 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h | 590 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h | 552 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h | 21 +++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h | 184 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h | 134 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h | 144 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h | 166 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h | 40 ++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h | 132 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h | 150 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h | 16 ++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++
Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h | 66 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
28 files changed, 3431 insertions(+)
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
new file mode 100644
index 0000000000..d1e10c3422
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionConfig.h
@@ -0,0 +1,55 @@
+/** @file
+ FlashProtection policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _FLASH_PROTECTION_CONFIG_H_
+#define _FLASH_PROTECTION_CONFIG_H_
+
+#define FLASH_PROTECTION_CONFIG_REVISION 1
+extern EFI_GUID gFlashProtectionConfigGuid;
+
+#pragma pack (push,1)
+
+//
+// Flash Protection Range Register
+//
+#define PCH_FLASH_PROTECTED_RANGES 5
+
+/**
+ Protected Flash Range
+**/
+typedef struct {
+ UINT32 WriteProtectionEnable : 1; ///< Write or erase is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 ReadProtectionEnable : 1; ///< Read is blocked by hardware. <b>0: Disable</b>; 1: Enable.
+ UINT32 RsvdBits : 30; ///< Reserved
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be FFFh for limit comparison
+ **/
+ UINT16 ProtectedRangeLimit;
+ /**
+ The address of the upper limit of protection
+ This is a left shifted address by 12 bits with address bits 11:0 are assumed to be 0
+ **/
+ UINT16 ProtectedRangeBase;
+} PROTECTED_RANGE;
+
+/**
+ The PCH provides a method for blocking writes and reads to specific ranges
+ in the SPI flash when the Protected Ranges are enabled.
+ PROTECTED_RANGE is used to specify if flash protection are enabled,
+ the write protection enable bit and the read protection enable bit,
+ and to specify the upper limit and lower base for each register
+ Platform code is responsible to get the range base by PchGetSpiRegionAddresses routine,
+ and set the limit and base accordingly.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< Protected Flash Ranges
+} PCH_FLASH_PROTECTION_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _FLASH_PROTECTION_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
new file mode 100644
index 0000000000..ec27845a48
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h
@@ -0,0 +1,57 @@
+/** @file
+ HSIO policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HSIO_CONFIG_H_
+#define _HSIO_CONFIG_H_
+#define HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated
+extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated
+
+#define HSIO_CONFIG_REVISION 1
+extern EFI_GUID gHsioConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+
+ /**
+ <b>(Test)</b>
+ 0- Disable, disable will prevent the HSIO version check and ChipsetInit HECI message from being sent
+ <b>1- Enable</b> ChipsetInit HECI message
+ **/
+ UINT8 ChipsetInitMessage;
+ /**
+ <b>(Test)</b>
+ <b>0- Disable</b>
+ 1- Enable When enabled, this is used to bypass the reset after ChipsetInit HECI message.
+ **/
+ UINT8 BypassPhySyncReset;
+ UINT8 RsvdBytes[2];
+
+} PCH_HSIO_PREMEM_CONFIG;
+
+
+/**
+ The PCH_HSIO_CONFIG block provides HSIO message related settings.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Policy used to point to the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
+ **/
+ UINT32 ChipsetInitBinPtr;
+ /**
+ Policy used to indicate the size of the Base (+ OEM) ChipsetInit binary used to sync between BIOS and CSME
+ **/
+ UINT32 ChipsetInitBinLen;
+} PCH_HSIO_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
new file mode 100644
index 0000000000..bc23f3e1a6
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h
@@ -0,0 +1,58 @@
+/** @file
+ HSIO pcie policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HSIO_PCIE_CONFIG_H_
+#define _HSIO_PCIE_CONFIG_H_
+
+#include <PchLimits.h>
+
+#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHsioPciePreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane
+**/
+typedef struct {
+ //
+ // HSIO Rx Eq
+ // Refer to the EDS for recommended values.
+ // Note that these setting are per-lane and not per-port
+ //
+ UINT32 HsioRxSetCtleEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 Set CTLE Value
+ UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set CTLE Value
+ UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value
+ UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value
+ UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value
+ UINT32 RsvdBits0 : 4; ///< Reserved Bits
+
+ UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting
+ UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setting
+ UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< <b>0: Disable</b>; 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setting
+ UINT32 RsvdBits1 : 11; ///< Reserved Bits
+} PCH_HSIO_PCIE_LANE_CONFIG;
+
+///
+/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO for PCIe lanes
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of HSIO for PCIe lanes.
+ ///
+ PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];
+} PCH_HSIO_PCIE_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_PCIE_LANE_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
new file mode 100644
index 0000000000..21b0d7ff63
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h
@@ -0,0 +1,64 @@
+/** @file
+ Hsio Sata policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _HSIO_SATA_CONFIG_H_
+#define _HSIO_SATA_CONFIG_H_
+
+#define HSIO_SATA_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gHsioSataPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane
+**/
+typedef struct {
+ //
+ // HSIO Rx Eq
+ //
+ UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< <b>0: Disable</b>; 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override
+ UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiver Equalization Boost Magnitude Adjustment value
+ //
+ // HSIO Tx Eq
+ //
+ UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value
+ UINT32 RsvdBits0 : 4; ///< Reserved bits
+
+ UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment
+ UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value override
+ UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment
+ UINT32 HsioTxGen1DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting
+
+ UINT32 HsioTxGen2DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting
+ UINT32 RsvdBits1 : 4; ///< Reserved bits
+
+ UINT32 HsioTxGen3DeEmphEnable : 1; ///< <b>0: Disable</b>; 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value override
+ UINT32 RsvdBits2 : 25; ///< Reserved bits
+} PCH_HSIO_SATA_PORT_LANE;
+
+///
+/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the SATA controller.
+///
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ ///
+ /// These members describe the configuration of HSIO for SATA lanes.
+ ///
+ PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];
+} PCH_HSIO_SATA_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _HSIO_SATA_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h
new file mode 100644
index 0000000000..23f116cf3d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h
@@ -0,0 +1,61 @@
+/** @file
+ Lock down policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LOCK_DOWN_CONFIG_H_
+#define _LOCK_DOWN_CONFIG_H_
+
+#define LOCK_DOWN_CONFIG_REVISION 1
+extern EFI_GUID gLockDownConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
+ for security requirement.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ <b>(Test)</b> Enable SMI_LOCK bit to prevent writes to the Global SMI Enable bit. 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 GlobalSmi : 1;
+ /**
+ <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
+ Top Swap bit and the General Control and Status Registers Boot BIOS Straps.
+ Intel strongly recommends that BIOS sets the BIOS Interface Lock Down bit. Enabling this bit
+ will mitigate malicious software attempts to replace the system BIOS with its own code.
+ 0: Disable; <b>1: Enable</b>.
+ **/
+ UINT32 BiosInterface : 1;
+ /**
+ Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
+ for the BIOS region protection. When it is enabled, the BIOS Region can only be
+ modified from SMM.
+ If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
+ in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
+ then the InSMM.STS is a don't care.
+ The BIOS must set the EISS bit while BIOS Guard support is enabled.
+ In recovery path, platform can temporary disable EISS for SPI programming in
+ PEI phase or early DXE phase.
+ When PcdSmmVariableEnable is FALSE, to support BIOS regions update outside of SMM,
+ the BiosLock must be set to Disabled by platform.
+ 0: Disable; <b>1: Enable.</b>
+ **/
+ UINT32 BiosLock : 1;
+ /**
+ <b>(Test)</b> This test option when set will force all GPIO pads to be unlocked
+ before BIOS transitions to POSTBOOT_SAI. This option should not be enabled in production
+ configuration and used only for debug purpose when free runtime reconfiguration of
+ GPIO pads is needed.
+ <b>0: Disable</b>; 1: Enable.
+ **/
+ UINT32 UnlockGpioPads : 1;
+ UINT32 RsvdBits0 : 28; ///< Reserved bits
+} PCH_LOCK_DOWN_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LOCK_DOWN_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
new file mode 100644
index 0000000000..3fc64aa056
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h
@@ -0,0 +1,38 @@
+/** @file
+ Lpc policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _LPC_CONFIG_H_
+#define _LPC_CONFIG_H_
+
+#define LPC_PREMEM_CONFIG_REVISION 1
+extern EFI_GUID gLpcPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+/**
+ This structure contains the policies which are related to LPC.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Enhance the port 8xh decoding.
+ Original LPC only decodes one byte of port 80h, with this enhancement LPC can decode word or dword of port 80h-83h.
+ @note: this will occupy one LPC generic IO range register. While this is enabled, read from port 80h always return 0x00.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 EnhancePort8xhDecoding : 1;
+ /**
+ Hardware Autonomous Enable.
+ When enabled, LPC will automatically engage power gating when it has reached its idle condition.
+ 0: Disable, <b>1: Enable</b>
+ **/
+ UINT32 LpcPmHAE : 1;
+ UINT32 RsvdBits : 30; ///< Reserved bits
+} PCH_LPC_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _LPC_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
new file mode 100644
index 0000000000..da77abc1b3
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig.h
@@ -0,0 +1,72 @@
+/** @file
+ PCH General policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_GENERAL_CONFIG_H_
+#define _PCH_GENERAL_CONFIG_H_
+
+#define PCH_GENERAL_CONFIG_REVISION 1
+#define PCH_GENERAL_PREMEM_CONFIG_REVISION 2
+
+extern EFI_GUID gPchGeneralConfigGuid;
+extern EFI_GUID gPchGeneralPreMemConfigGuid;
+
+#pragma pack (push,1)
+
+enum PCH_RESERVED_PAGE_ROUTE {
+ PchReservedPageToLpc, ///< Port 80h cycles are sent to LPC.
+ PchReservedPageToPcie ///< Port 80h cycles are sent to PCIe.
+};
+
+/**
+ PCH General Configuration
+ <b>Revision 1</b>: - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ This member describes whether or not the Compatibility Revision ID (CRID) feature
+ of PCH should be enabled. <b>0: Disable</b>; 1: Enable
+ **/
+ UINT32 Crid : 1;
+ /**
+ Set to enable low latency of legacy IO.
+ Some systems require lower IO latency irrespective of power.
+ This is a tradeoff between power and IO latency.
+ @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent
+ and ITSS Clock Gating are forced to disabled.
+ <b>0: Disable</b>, 1: Enable
+ **/
+ UINT32 LegacyIoLowLatency : 1;
+ UINT32 RsvdBits0 : 30; ///< Reserved bits
+} PCH_GENERAL_CONFIG;
+
+/**
+ PCH General Pre-Memory Configuration
+ <b>Revision 1</b>: - Initial version.
+ <b>Revision 2</b>: - Added GpioOverride.
+**/
+typedef struct {
+ CONFIG_BLOCK_HEADER Header; ///< Config Block Header
+ /**
+ Control where the Port 80h cycles are sent, <b>0: LPC</b>; 1: PCI.
+ **/
+ UINT32 Port80Route : 1;
+ UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC for A0 PO
+ /**
+ Gpio override Level
+ -- <b>0: Disable</b>;
+ - 1: Override Level 1 - only skips GpioSetNativePadByFunction
+ - 2: Override Level 2 - skips GpioSetNativePadByFunction and GpioSetPadMode
+ Additional policy that allows GPIO configuration to be done by external means.
+ If equal to 1 PCH will skip every Pad configuration.
+ **/
+ UINT32 GpioOverride : 3;
+ UINT32 RsvdBits0 : 27; ///< Reserved bits
+} PCH_GENERAL_PREMEM_CONFIG;
+
+#pragma pack (pop)
+
+#endif // _PCH_GENERAL_CONFIG_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
new file mode 100644
index 0000000000..94509a80fe
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.h
@@ -0,0 +1,258 @@
+/** @file
+ Header file for PchCycleDecodingLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_CYCLE_DECODING_LIB_H_
+#define _PCH_CYCLE_DECODING_LIB_H_
+
+
+/**
+ Get PCH TCO base address.
+
+ @param[out] Address Address of TCO base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid pointer passed.
+**/
+EFI_STATUS
+PchTcoBaseGet (
+ OUT UINT16 *Address
+ );
+
+///
+/// structure of LPC general IO range register
+/// It contains base address, address mask, and enable status.
+///
+typedef struct {
+ UINT32 BaseAddr :16;
+ UINT32 Length :15;
+ UINT32 Enable : 1;
+} PCH_LPC_GEN_IO_RANGE;
+
+#define PCH_LPC_GEN_IO_RANGE_MAX 4
+#define ESPI_CS1_GEN_IO_RANGE_MAX 1
+
+///
+/// structure of LPC general IO range register list
+/// It lists all LPC general IO ran registers supported by PCH.
+///
+typedef struct {
+ PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];
+} PCH_LPC_GEN_IO_RANGE_LIST;
+
+/**
+ Set PCH LPC/eSPI generic IO range.
+ For generic IO range, the base address must align to 4 and less than 0xFFFF, and the length must be power of 2
+ and less than or equal to 256. Moreover, the address must be length aligned.
+ This function basically checks the address and length, which should not overlap with all other generic ranges.
+ If no more generic range register available, it returns out of resource error.
+ This cycle decoding is also required on DMI side.
+ Some IO ranges below 0x100 have fixed target. The target might be ITSS,RTC,LPC,PMC or terminated inside P2SB
+ but all predefined and can't be changed. IO range below 0x100 will be rejected in this function except below ranges:
+ 0x00-0x1F,
+ 0x44-0x4B,
+ 0x54-0x5F,
+ 0x68-0x6F,
+ 0x80-0x8F,
+ 0xC0-0xFF
+ Steps of programming generic IO range:
+ 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.
+ 2. Program LPC/eSPI Generic IO Range in DMI
+
+ @param[in] Address Address for generic IO range base address.
+ @param[in] Length Length of generic IO range.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcGenIoRangeSet (
+ IN UINT16 Address,
+ IN UINTN Length
+ );
+
+/**
+ Set PCH LPC/eSPI memory range decoding.
+ This cycle decoding is required to be set on DMI side
+ Programming steps:
+ 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].
+ 3. Program LPC Memory Range in DMI
+
+ @param[in] Address Address for memory base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_OUT_OF_RESOURCES No more generic range available.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcMemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ Set PCH eSPI CS1# memory range decoding.
+ This cycle decoding is required to be set on DMI side
+ Programming steps:
+ 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory decoding first before changing base address.
+ 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].
+ 3. Program eSPI Memory Range in DMI
+
+ @param[in] Address Address for memory for decoding.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address or length passed.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1MemRangeSet (
+ IN UINT32 Address
+ );
+
+/**
+ Get PCH LPC/eSPI memory range decoding address.
+
+ @param[out] Address Address of LPC/eSPI memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+**/
+EFI_STATUS
+PchLpcMemRangeGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Get PCH eSPI CS1# memory range decoding address.
+
+ @param[out] Address Address of eSPI CS1# memory decoding base address.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid base address passed.
+ @retval EFI_UNSUPPORTED eSPI secondary slave not supported
+**/
+EFI_STATUS
+PchEspiCs1MemRangeGet (
+ OUT UINT32 *Address
+ );
+
+/**
+ Set PCH BIOS range deocding.
+ This will check General Control and Status bit 10 (GCS.BBS) to identify SPI or LPC/eSPI and program BDE register accordingly.
+ Please check EDS for detail of BiosDecodeEnable bit definition.
+ bit 15: F8-FF Enable
+ bit 14: F0-F8 Enable
+ bit 13: E8-EF Enable
+ bit 12: E0-E8 Enable
+ bit 11: D8-DF Enable
+ bit 10: D0-D7 Enable
+ bit 9: C8-CF Enable
+ bit 8: C0-C7 Enable
+ bit 7: Legacy F Segment Enable
+ bit 6: Legacy E Segment Enable
+ bit 5: Reserved
+ bit 4: Reserved
+ bit 3: 70-7F Enable
+ bit 2: 60-6F Enable
+ bit 1: 50-5F Enable
+ bit 0: 40-4F Enable
+ This cycle decoding is allowed to set when DMIC.SRL is 0.
+ Programming steps:
+ 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable.
+ if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDecodeEnable.
+ 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same value programmed in LPC/eSPI or SPI PCI Offset D8h.
+
+ @param[in] BiosDecodeEnable Bios decode enable setting.
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchBiosDecodeEnableSet (
+ IN UINT16 BiosDecodeEnable
+ );
+
+/**
+ Set PCH LPC IO decode ranges.
+ Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value programmed in LPC offset 80h.
+ Please check EDS for detail of Lpc IO decode ranges bit definition.
+ Bit 12: FDD range
+ Bit 9:8: LPT range
+ Bit 6:4: ComB range
+ Bit 2:0: ComA range
+
+ @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcIoDecodeRangesSet (
+ IN UINT16 LpcIoDecodeRanges
+ );
+
+/**
+ Set PCH LPC and eSPI CS0# IO enable decoding.
+ Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offset 82h.
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.
+
+ @param[in] LpcIoEnableDecoding LPC IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMIC.SRL is set.
+**/
+EFI_STATUS
+PchLpcIoEnableDecodingSet (
+ IN UINT16 LpcIoEnableDecoding
+ );
+
+/**
+ Set PCH eSPI CS1# IO enable decoding.
+ Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0h (eSPI CS1#).
+ Note: Bit[15:10] of the source decode register is Read-Only. The IO range indicated by the Enables field
+ in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive agent for handling.
+ Please check EDS for detail of eSPI IO decode ranges bit definition.
+
+ @param[in] IoEnableDecoding eSPI IO enable decoding bit settings.
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_UNSUPPORTED DMI configuration is locked
+**/
+EFI_STATUS
+PchEspiCs1IoEnableDecodingSet (
+ IN UINT16 IoEnableDecoding
+ );
+
+/**
+ Get IO APIC regsiters base address.
+
+ @param[out] IoApicBase Buffer of IO APIC regsiter address
+
+ @retval EFI_SUCCESS Successfully completed.
+**/
+EFI_STATUS
+PchIoApicBaseGet (
+ OUT UINT32 *IoApicBase
+ );
+
+/**
+ Get HPET base address.
+ This function will be unavailable after P2SB is hidden by PSF.
+
+ @param[out] HpetBase Buffer of HPET base address
+
+ @retval EFI_SUCCESS Successfully completed.
+ @retval EFI_INVALID_PARAMETER Invalid offset passed.
+**/
+EFI_STATUS
+PchHpetBaseGet (
+ OUT UINT32 *HpetBase
+ );
+
+#endif // _PCH_CYCLE_DECODING_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
new file mode 100644
index 0000000000..c8aee81a8b
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h
@@ -0,0 +1,590 @@
+/** @file
+ Header file for PchInfoLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_INFO_LIB_H_
+#define _PCH_INFO_LIB_H_
+
+#include <Hda.h>
+#include <Uefi/UefiBaseType.h>
+
+typedef UINT8 PCH_STEPPING;
+
+typedef UINT8 PCH_SERIES;
+#define PCH_LP 2
+
+typedef UINT8 PCH_GENERATION;
+#define TGL_PCH 5
+
+typedef enum {
+ RstUnsupported = 0,
+ RstPremium,
+ RstOptane,
+ RstMaxMode
+} RST_MODE;
+
+/**
+ Return Pch stepping type
+
+ @retval PCH_STEPPING Pch stepping type
+**/
+PCH_STEPPING
+PchStepping (
+ VOID
+ );
+
+/**
+ Return Pch Series
+
+ @retval PCH_SERIES Pch Series
+**/
+PCH_SERIES
+PchSeries (
+ VOID
+ );
+
+/**
+ Return Pch Generation
+
+ @retval PCH_GENERATION Pch Generation
+**/
+PCH_GENERATION
+PchGeneration (
+ VOID
+ );
+
+/**
+ Check if this is TGL PCH generation
+
+ @retval TRUE It's TGL PCH
+ @retval FALSE It's not TGL PCH
+**/
+BOOLEAN
+IsTglPch (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Root Port Number
+
+ @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number
+**/
+UINT8
+GetPchMaxPciePortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Controller Number
+
+ @retval Pch Maximum Pcie Controller Number
+**/
+UINT8
+GetPchMaxPcieControllerNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie Clock Number
+
+ @retval Pch Maximum Pcie Clock Number
+**/
+UINT8
+GetPchMaxPcieClockNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Pcie ClockReq Number
+
+ @retval Pch Maximum Pcie ClockReq Number
+**/
+UINT8
+GetPchMaxPcieClockReqNum (
+ VOID
+ );
+
+/**
+ Get Pch Usb2 Maximum Physical Port Number
+
+ @retval Pch Usb2 Maximum Physical Port Number
+**/
+UINT8
+GetPchUsb2MaxPhysicalPortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb2 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb2 Port Number of XHCI Controller
+**/
+UINT8
+GetPchXhciMaxUsb2PortNum (
+ VOID
+ );
+
+/**
+ Get Pch Usb3 Maximum Physical Port Number
+
+ @retval Pch Usb3 Maximum Physical Port Number
+**/
+UINT8
+GetPchUsb3MaxPhysicalPortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Usb3 Port Number of XHCI Controller
+
+ @retval Pch Maximum Usb3 Port Number of XHCI Controller
+**/
+UINT8
+GetPchXhciMaxUsb3PortNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO I2C controllers number
+
+ @retval Pch Maximum Serial IO I2C controllers number
+**/
+UINT8
+GetPchMaxSerialIoI2cControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO SPI controllers number
+
+ @retval Pch Maximum Serial IO SPI controllers number
+**/
+UINT8
+GetPchMaxSerialIoSpiControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO UART controllers number
+
+ @retval Pch Maximum Serial IO UART controllers number
+**/
+UINT8
+GetPchMaxSerialIoUartControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Serial IO SPI Chip Selects count
+
+ @retval Pch Maximum Serial IO SPI Chip Selects nu,ber
+**/
+UINT8
+GetPchMaxSerialIoSpiChipSelectsNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH UART Controller number
+
+ @retval Pch Maximum ISH UART controllers number
+**/
+UINT8
+GetPchMaxIshUartControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH I2C Controller number
+
+ @retval Pch Maximum ISH I2C controllers number
+**/
+UINT8
+GetPchMaxIshI2cControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH I3C Controller number
+
+ @retval Pch Maximum ISH I3C controllers number
+**/
+UINT8
+GetPchMaxIshI3cControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH SPI Controller number
+
+ @retval Pch Maximum ISH SPI controllers number
+**/
+UINT8
+GetPchMaxIshSpiControllersNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH SPI Controller Cs pins number
+
+ @retval Pch Maximum ISH SPI controller Cs pins number
+**/
+UINT8
+GetPchMaxIshSpiControllerCsPinsNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ISH GP number
+
+ @retval Pch Maximum ISH GP number
+**/
+UINT8
+GetPchMaxIshGpNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum ME Applet count
+
+ @retval Pch Maximum ME Applet number
+**/
+UINT8
+GetPchMaxMeAppletCount (
+ VOID
+ );
+
+/**
+Get Pch Maximum ME Session count
+
+@retval Pch Maximum ME Sesion number
+**/
+UINT8
+GetPchMaxMeSessionCount(
+ VOID
+);
+
+/**
+ Get Pch Maximum Type C Port Number
+
+ @retval Pch Maximum Type C Port Number
+**/
+UINT8
+GetPchMaxTypeCPortNum (
+ VOID
+ );
+
+#define PCH_STEPPING_STR_LENGTH_MAX 3
+
+/**
+ Get PCH stepping ASCII string.
+ Function determines major and minor stepping versions and writes them into a buffer.
+ The return string is zero terminated
+
+ @param [out] Buffer Output buffer of string
+ @param [in] BufferSize Buffer size.
+ Must not be less then PCH_STEPPING_STR_LENGTH_MAX
+
+ @retval EFI_SUCCESS String copied successfully
+ @retval EFI_INVALID_PARAMETER The stepping is not supported, or parameters are NULL
+ @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small
+**/
+EFI_STATUS
+PchGetSteppingStr (
+ OUT CHAR8 *Buffer,
+ IN UINT32 BufferSize
+ );
+
+/**
+ Get PCH series ASCII string.
+ The return string is zero terminated.
+
+ @retval Static ASCII string of PCH Series
+**/
+CHAR8*
+PchGetSeriesStr (
+ );
+
+/**
+ Check if this chipset supports eMMC controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchEmmcSupported (
+ VOID
+ );
+
+/**
+ Check if this chipset supports SD controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchSdCardSupported (
+ VOID
+ );
+
+/**
+ Check if this chipset supports THC controller
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchThcSupported (
+ VOID
+ );
+
+/**
+ Check if this chipset supports HSIO BIOS Sync
+
+ @retval BOOLEAN TRUE if supported, FALSE otherwise
+**/
+BOOLEAN
+IsPchChipsetInitSyncSupported (
+ VOID
+ );
+
+/**
+ Gets the maximum number of UFS controller supported by this chipset.
+
+ @return Number of supported UFS controllers
+**/
+UINT8
+PchGetMaxUfsNum (
+ VOID
+ );
+
+/**
+ Check whether integrated LAN controller is supported.
+
+ @retval TRUE GbE is supported in PCH
+ @retval FALSE GbE is not supported by PCH
+**/
+BOOLEAN
+PchIsGbeSupported (
+ VOID
+ );
+
+/**
+ Check whether integrated TSN is supported.
+
+ @retval TRUE TSN is supported in current PCH
+ @retval FALSE TSN is not supported on current PCH
+**/
+BOOLEAN
+PchIsTsnSupported (
+ VOID
+ );
+
+/**
+ Check whether ISH is supported.
+
+ @retval TRUE ISH is supported in PCH
+ @retval FALSE ISH is not supported by PCH
+**/
+BOOLEAN
+PchIsIshSupported (
+ VOID
+ );
+
+/**
+ Check whether ATX Shutdown (PS_ON) is supported.
+
+ @retval TRUE ATX Shutdown (PS_ON) is supported in PCH
+ @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH
+**/
+BOOLEAN
+IsPchPSOnSupported (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Hda Sndw Link
+
+ @retval Pch Maximum Hda Sndw Link
+**/
+UINT8
+GetPchHdaMaxSndwLinkNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Hda Ssp Link
+
+ @retval Pch Maximum Hda Ssp Link
+**/
+UINT8
+GetPchHdaMaxSspLinkNum (
+ VOID
+ );
+
+/**
+ Get Pch Maximum Hda Dmic Link
+
+ @retval Pch Maximum Hda Dmic Link
+**/
+UINT8
+GetPchHdaMaxDmicLinkNum (
+ VOID
+ );
+
+/**
+ Check if given Audio Interface is supported
+
+ @param[in] AudioLinkType Link type support to be checked
+ @param[in] AudioLinkIndex Link number
+
+ @retval TRUE Link supported
+ @retval FALSE Link not supported
+**/
+BOOLEAN
+IsAudioInterfaceSupported (
+ IN HDAUDIO_LINK_TYPE AudioLinkType,
+ IN UINT32 AudioLinkIndex
+ );
+
+/**
+ Check if given Display Audio Link T-Mode is supported
+
+ @param[in] Tmode T-mode support to be checked
+
+ @retval TRUE T-mode supported
+ @retval FALSE T-mode not supported
+**/
+BOOLEAN
+IsAudioIDispTmodeSupported (
+ IN HDAUDIO_IDISP_TMODE Tmode
+ );
+
+/**
+ Check if link between PCH and CPU is an P-DMI
+
+ @retval TRUE P-DMI link
+ @retval FALSE Not an P-DMI link
+**/
+BOOLEAN
+IsPchWithPdmi (
+ VOID
+ );
+
+/**
+ Check if link between PCH and CPU is an OP-DMI
+
+ @retval TRUE OP-DMI link
+ @retval FALSE Not an OP-DMI link
+**/
+BOOLEAN
+IsPchWithOpdmi (
+ VOID
+ );
+
+/**
+ Check if link between PCH and CPU is an F-DMI
+
+ @retval TRUE F-DMI link
+ @retval FALSE Not an F-DMI link
+**/
+BOOLEAN
+IsPchWithFdmi (
+ VOID
+ );
+
+/**
+ Get Pch Maximum THC count
+
+ @retval Pch Maximum THC count number
+**/
+UINT8
+GetPchMaxThcCount (
+ VOID
+ );
+
+typedef enum {
+ SataSosc125Mhz = 0,
+ SataSosc120Mhz,
+ SataSosc100Mhz,
+ SataSosc25Mhz,
+ SataSosc19p2Mhz,
+ SataSoscUnsupported
+} SATA_SOSC_CLK_FREQ;
+
+/**
+ Returns a frequency of the sosc_clk signal.
+ All SATA controllers on the system are assumed to
+ work on the same sosc_clk frequency.
+
+ @retval Frequency of the sosc_clk signal.
+**/
+SATA_SOSC_CLK_FREQ
+GetSataSoscClkFreq (
+ VOID
+ );
+
+/**
+ Check if SATA support should be awake after function disable
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsSataSupportWakeAfterFunctionDisable (
+ VOID
+ );
+
+
+//
+// USB2 PHY reference frequencies values (MHz)
+//
+typedef enum {
+ FREQ_19_2 = 0u,
+ FREQ_24_0,
+ FREQ_96_0,
+ FREQ_MAX
+} USB2_PHY_REF_FREQ;
+
+/**
+ Returns USB2 PHY Reference Clock frequency value used by PCH
+ This defines what electrical tuning parameters shall be used
+ during USB2 PHY initialization programming
+
+ @retval Frequency reference clock for USB2 PHY
+**/
+USB2_PHY_REF_FREQ
+GetUsb2PhyRefFreq (
+ VOID
+ );
+
+/**
+ return support status for P2SB PCR 20-bit addressing
+
+ @retval TRUE
+ @retval FALSE
+**/
+BOOLEAN
+IsP2sb20bPcrSupported (
+ VOID
+ );
+
+/**
+ Check if SPI in a given PCH generation supports an Extended BIOS Range Decode
+
+ @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode
+**/
+BOOLEAN
+IsExtendedBiosRangeDecodeSupported (
+ VOID
+ );
+
+/**
+ Returns DMI target for current PCH SPI
+
+ @retval PCH SPI DMI target
+**/
+UINT16
+GetPchSpiDmiTarget (
+ VOID
+ );
+#endif // _PCH_INFO_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h
new file mode 100644
index 0000000000..85456653de
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h
@@ -0,0 +1,552 @@
+/** @file
+ Header file for PchPciBdfLib.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCI_BDF_LIB_H_
+#define _PCH_PCI_BDF_LIB_H_
+
+
+/**
+ Get eSPI controller address that can be passed to the PCI Segment Library functions.
+
+ @retval eSPI controller address in PCI Segment Library representation
+**/
+UINT64
+EspiPciCfgBase (
+ VOID
+ );
+
+/**
+ Get GbE controller address that can be passed to the PCI Segment Library functions.
+
+ @retval GbE controller address in PCI Segment Library representation
+**/
+UINT64
+GbePciCfgBase (
+ VOID
+ );
+
+/**
+ Returns Gigabit Ethernet PCI Device Number
+
+ @retval GbE device number
+**/
+UINT8
+GbeDevNumber (
+ VOID
+ );
+
+/**
+ Returns Gigabit Ethernet PCI Function Number
+
+ @retval GbE function number
+**/
+UINT8
+GbeFuncNumber (
+ VOID
+ );
+
+/**
+ Get HDA controller address that can be passed to the PCI Segment Library functions.
+
+ @retval HDA controller address in PCI Segment Library representation
+**/
+UINT64
+HdaPciCfgBase (
+ VOID
+ );
+
+/**
+ Get HDA PCI device number
+
+ @retval PCI dev number
+**/
+UINT8
+HdaDevNumber (
+ VOID
+ );
+
+/**
+ Get HDA PCI function number
+
+ @retval PCI fun number
+**/
+UINT8
+HdaFuncNumber (
+ VOID
+ );
+
+
+/**
+ Get P2SB controller address that can be passed to the PCI Segment Library functions.
+
+ @retval P2SB controller address in PCI Segment Library representation
+**/
+UINT64
+P2sbPciCfgBase (
+ VOID
+ );
+
+/**
+ Get P2SB PCI device number
+
+ @retval PCI dev number
+**/
+UINT8
+P2sbDevNumber (
+ VOID
+ );
+
+/**
+ Returns SPI PCI Config Space base address
+
+ @retval UINT64 SPI Config Space base address
+**/
+UINT64
+SpiPciCfgBase (
+ VOID
+ );
+
+/**
+ Returns SPI Device number
+
+ @retval UINT8 PCH SPI Device number
+**/
+UINT8
+SpiDevNumber (
+ VOID
+ );
+
+/**
+ Returns SPI Function number
+
+ @retval UINT8 PCH SPI Function number
+**/
+UINT8
+SpiFuncNumber (
+ VOID
+ );
+
+/**
+ Get XHCI controller address that can be passed to the PCI Segment Library functions.
+
+ @retval XHCI controller address in PCI Segment Library representation
+**/
+UINT64
+PchXhciPciCfgBase (
+ VOID
+ );
+
+/**
+ Get XHCI controller PCIe Device Number
+
+ @retval XHCI controller PCIe Device Number
+**/
+UINT8
+PchXhciDevNumber (
+ VOID
+ );
+
+/**
+ Get XHCI controller PCIe Function Number
+
+ @retval XHCI controller PCIe Function Number
+**/
+UINT8
+PchXhciFuncNumber (
+ VOID
+ );
+
+/**
+ Get XDCI controller address that can be passed to the PCI Segment Library functions.
+
+ @retval XDCI controller address in PCI Segment Library representation
+**/
+UINT64
+PchXdciPciCfgBase (
+ VOID
+ );
+
+/**
+ Get XDCI controller PCIe Device Number
+
+ @retval XDCI controller PCIe Device Number
+**/
+UINT8
+PchXdciDevNumber (
+ VOID
+ );
+
+/**
+ Get XDCI controller PCIe Function Number
+
+ @retval XDCI controller PCIe Function Number
+**/
+UINT8
+PchXdciFuncNumber (
+ VOID
+ );
+
+/**
+ Get SMBUS controller address that can be passed to the PCI Segment Library functions.
+
+ @retval SMBUS controller address in PCI Segment Library representation
+**/
+UINT64
+SmbusPciCfgBase (
+ VOID
+ );
+
+/**
+ Return DMA Smbus Device Number
+
+ @retval DMA Smbus Device Number
+**/
+UINT8
+SmbusDmaDevNumber (
+ VOID
+ );
+
+/**
+ Return DMA Smbus Function Number
+
+ @retval DMA Smbus Function Number
+**/
+UINT8
+SmbusDmaFuncNumber (
+ VOID
+ );
+
+/**
+ Get DMA SMBUS controller address that can be passed to the PCI Segment Library functions.
+
+ @retval DMA SMBUS controller address in PCI Segment Library representation
+**/
+UINT64
+SmbusDmaPciCfgBase (
+ VOID
+ );
+
+/**
+ Return Smbus Device Number
+
+ @retval Smbus Device Number
+**/
+UINT8
+SmbusDevNumber (
+ VOID
+ );
+
+/**
+ Return Smbus Function Number
+
+ @retval Smbus Function Number
+**/
+UINT8
+SmbusFuncNumber (
+ VOID
+ );
+
+/**
+ Gets SATA controller PCIe config space base address
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe config space base address
+**/
+UINT64
+SataPciCfgBase (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets SATA controller PCIe Device Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe Device Number
+**/
+UINT8
+SataDevNumber (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Gets SATA controller PCIe Function Number
+
+ @param[in] SataCtrlIndex SATA controller index
+
+ @retval SATA controller PCIe Function Number
+**/
+UINT8
+SataFuncNumber (
+ IN UINT32 SataCtrlIndex
+ );
+
+/**
+ Returns PCH LPC device PCI base address.
+
+ @retval PCH LPC PCI base address.
+**/
+UINT64
+LpcPciCfgBase (
+ VOID
+ );
+
+/**
+ Get LPC controller PCIe Device Number
+
+ @retval LPC controller PCIe Device Number
+**/
+UINT8
+LpcDevNumber (
+ VOID
+ );
+
+/**
+ Get Thermal Device PCIe Device Number
+
+ @retval Thermal Device PCIe Device Number
+**/
+UINT8
+ThermalDevNumber (
+ VOID
+ );
+
+/**
+ Get Thermal Device PCIe Function Number
+
+ @retval Thermal Device PCIe Function Number
+**/
+UINT8
+ThermalFuncNumber (
+ VOID
+ );
+
+/**
+ Returns Thermal Device PCI base address.
+
+ @retval Thermal Device PCI base address.
+**/
+UINT64
+ThermalPciCfgBase (
+ VOID
+ );
+
+/**
+ Get LPC controller PCIe Function Number
+
+ @retval LPC controller PCIe Function Number
+**/
+UINT8
+LpcFuncNumber (
+ VOID
+ );
+
+/**
+ Get Serial IO I2C controller PCIe Device Number
+
+ @param[in] I2cNumber Serial IO I2C controller index
+
+ @retval Serial IO I2C controller PCIe Device Number
+**/
+UINT8
+SerialIoI2cDevNumber (
+ IN UINT8 I2cNumber
+ );
+
+/**
+ Get Serial IO I2C controller PCIe Function Number
+
+ @param[in] I2cNumber Serial IO I2C controller index
+
+ @retval Serial IO I2C controller PCIe Function Number
+**/
+UINT8
+SerialIoI2cFuncNumber (
+ IN UINT8 I2cNumber
+ );
+
+/**
+ Get Serial IO I2C controller address that can be passed to the PCI Segment Library functions.
+
+ @param[in] I2cNumber Serial IO I2C controller index
+
+ @retval Serial IO I2C controller address in PCI Segment Library representation
+**/
+UINT64
+SerialIoI2cPciCfgBase (
+ IN UINT8 I2cNumber
+ );
+
+/**
+ Get Serial IO SPI controller PCIe Device Number
+
+ @param[in] I2cNumber Serial IO SPI controller index
+
+ @retval Serial IO SPI controller PCIe Device Number
+**/
+UINT8
+SerialIoSpiDevNumber (
+ IN UINT8 SpiNumber
+ );
+
+/**
+ Get Serial IO SPI controller PCIe Function Number
+
+ @param[in] SpiNumber Serial IO SPI controller index
+
+ @retval Serial IO SPI controller PCIe Function Number
+**/
+UINT8
+SerialIoSpiFuncNumber (
+ IN UINT8 SpiNumber
+ );
+
+/**
+ Get Serial IO SPI controller address that can be passed to the PCI Segment Library functions.
+
+ @param[in] SpiNumber Serial IO SPI controller index
+
+ @retval Serial IO SPI controller address in PCI Segment Library representation
+**/
+UINT64
+SerialIoSpiPciCfgBase (
+ IN UINT8 SpiNumber
+ );
+
+/**
+ Get Serial IO UART controller PCIe Device Number
+
+ @param[in] UartNumber Serial IO UART controller index
+
+ @retval Serial IO UART controller PCIe Device Number
+**/
+UINT8
+SerialIoUartDevNumber (
+ IN UINT8 UartNumber
+ );
+
+/**
+ Get Serial IO UART controller PCIe Function Number
+
+ @param[in] UartNumber Serial IO UART controller index
+
+ @retval Serial IO UART controller PCIe Function Number
+**/
+UINT8
+SerialIoUartFuncNumber (
+ IN UINT8 UartNumber
+ );
+
+/**
+ Get Serial IO UART controller address that can be passed to the PCI Segment Library functions.
+
+ @param[in] UartNumber Serial IO UART controller index
+
+ @retval Serial IO UART controller address in PCI Segment Library representation
+**/
+UINT64
+SerialIoUartPciCfgBase (
+ IN UINT8 UartNumber
+ );
+
+/**
+ Get PCH PCIe controller PCIe Device Number
+
+ @param[in] RpIndex Root port physical number. (0-based)
+
+ @retval PCH PCIe controller PCIe Device Number
+**/
+UINT8
+PchPcieRpDevNumber (
+ IN UINTN RpIndex
+ );
+
+/**
+ Get PCH PCIe controller PCIe Function Number
+
+ @param[in] RpIndex Root port physical number. (0-based)
+
+ @retval PCH PCIe controller PCIe Function Number
+**/
+UINT8
+PchPcieRpFuncNumber (
+ IN UINTN RpIndex
+ );
+
+/**
+ Get PCH PCIe controller address that can be passed to the PCI Segment Library functions.
+
+ @param[in] RpIndex PCH PCIe Root Port physical number. (0-based)
+
+ @retval PCH PCIe controller address in PCI Segment Library representation
+**/
+UINT64
+PchPcieRpPciCfgBase (
+ IN UINT32 RpIndex
+ );
+
+/**
+ Get HECI1 PCI device number
+
+ @retval PCI dev number
+**/
+UINT8
+PchHeci1DevNumber (
+ VOID
+ );
+
+/**
+ Get HECI1 PCI function number
+
+ @retval PCI fun number
+**/
+UINT8
+PchHeci1FuncNumber (
+ VOID
+ );
+
+/**
+ Get HECI1 controller address that can be passed to the PCI Segment Library functions.
+
+ @retval HECI1 controller address in PCI Segment Library representation
+**/
+UINT64
+PchHeci1PciCfgBase (
+ VOID
+ );
+
+/**
+ Get HECI3 PCI device number
+
+ @retval PCI dev number
+**/
+UINT8
+PchHeci3DevNumber (
+ VOID
+ );
+
+/**
+ Get HECI3 PCI function number
+
+ @retval PCI fun number
+**/
+UINT8
+PchHeci3FuncNumber (
+ VOID
+ );
+
+/**
+ Get HECI3 controller address that can be passed to the PCI Segment Library functions.
+
+ @retval HECI3 controller address in PCI Segment Library representation
+**/
+UINT64
+PchHeci3PciCfgBase (
+ VOID
+ );
+
+#endif //_PCH_PCI_BDF_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h
new file mode 100644
index 0000000000..845bb19a65
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h
@@ -0,0 +1,70 @@
+/** @file
+ This file contains definitions of PCH Info HOB.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_INFO_HOB_H_
+#define _PCH_INFO_HOB_H_
+
+extern EFI_GUID gPchInfoHobGuid;
+
+#define PCH_INFO_HOB_REVISION 4
+
+#pragma pack (push,1)
+/**
+ This structure is used to provide the information of PCH controller.
+
+ <b>Revision 1</b>:
+ - Initial version.
+ <b>Revision 2</b>:
+ - Add CridSupport, CridOrgRid, and CridNewRid.
+ <b>Revision 3</b>:
+ - Add Thc0Strap.
+ <b>Revision 4</b>
+ - Removed GbePciePortNumber
+**/
+typedef struct {
+ /**
+ This member specifies the revision of the PCH Info HOB. This field is used
+ to indicate backwards compatible changes to the protocol. Platform code that
+ consumes this protocol must read the correct revision value to correctly interpret
+ the content of the protocol fields.
+ **/
+ UINT8 Revision;
+ UINT8 PcieControllerCfg[6];
+ /**
+ THC strap disable/enable status
+ **/
+ UINT8 Thc0Strap;
+ UINT32 PciePortFuses;
+ /**
+ Bit map for PCIe Root Port Lane setting. If bit is set it means that
+ corresponding Root Port has its lane enabled.
+ BIT0 - RP0, BIT1 - RP1, ...
+ This information needs to be passed through HOB as FIA registers
+ are not accessible with POSTBOOT_SAI
+ **/
+ UINT32 PciePortLaneEnabled;
+ /**
+ Publish Hpet BDF and IoApic BDF information for VTD.
+ **/
+ UINT32 HpetBusNum : 8;
+ UINT32 HpetDevNum : 5;
+ UINT32 HpetFuncNum : 3;
+ UINT32 IoApicBusNum : 8;
+ UINT32 IoApicDevNum : 5;
+ UINT32 IoApicFuncNum : 3;
+ /**
+ Publish the CRID information.
+ **/
+ UINT32 CridOrgRid : 8;
+ UINT32 CridNewRid : 8;
+ UINT32 CridSupport : 1;
+ UINT32 Rsvdbits : 15;
+} PCH_INFO_HOB;
+
+#pragma pack (pop)
+
+#endif // _PCH_INFO_HOB_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h
new file mode 100644
index 0000000000..04ad17c8bd
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h
@@ -0,0 +1,67 @@
+/** @file
+ Build time limits of PCH resources.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_LIMITS_H_
+#define _PCH_LIMITS_H_
+/*
+ * Defines povided in this file are indended to be used only where static value
+ * is needed. They are set to values which allow to accomodate multiple projects
+ * needs. Where runtime usage is possible please used dedicated functions from
+ * PchInfoLib to retrieve accurate values
+ */
+
+//
+// PCIe limits
+//
+#define PCH_MAX_PCIE_ROOT_PORTS 24
+#define PCH_MAX_PCIE_CONTROLLERS 6
+
+//
+// PCIe clocks limits
+//
+#define PCH_MAX_PCIE_CLOCKS 16
+
+//
+// RST PCIe Storage Cycle Router limits
+//
+#define PCH_MAX_RST_PCIE_STORAGE_CR 3
+
+//
+// SATA limits
+//
+#define PCH_MAX_SATA_CONTROLLERS 3
+#define PCH_MAX_SATA_PORTS 8
+
+//
+// SerialIo limits
+//
+#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8
+#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7
+#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2
+#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7
+
+//
+// ISH limits
+//
+#define PCH_MAX_ISH_GP_PINS 8
+#define PCH_MAX_ISH_UART_CONTROLLERS 2
+#define PCH_MAX_ISH_I2C_CONTROLLERS 3
+#define PCH_MAX_ISH_SPI_CONTROLLERS 1
+#define PCH_MAX_ISH_SPI_CS_PINS 1
+//
+// HDA limits
+//
+#define PCH_MAX_HDA_SDI 2
+#define PCH_MAX_HDA_SSP_LINK_NUM 6
+#define PCH_MAX_HDA_SNDW_LINK_NUM 4
+
+//
+// Number of eSPI slaves
+//
+#define PCH_MAX_ESPI_SLAVES 2
+
+#endif // _PCH_LIMITS_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h
new file mode 100644
index 0000000000..7b749818fa
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h
@@ -0,0 +1,55 @@
+/** @file
+ PCH configuration based on PCH policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_POLICY_COMMON_H_
+#define _PCH_POLICY_COMMON_H_
+
+#include <ConfigBlock.h>
+#include <UsbConfig.h>
+#include <Usb2PhyConfig.h>
+#include <Usb3HsioConfig.h>
+
+#include "PchLimits.h"
+#include "ConfigBlock/PchGeneralConfig.h"
+#include <PchPcieRpConfig.h>
+#include <IoApicConfig.h>
+#include <SataConfig.h>
+#include <RstConfig.h>
+#include <PchDmiConfig.h>
+#include "ConfigBlock/FlashProtectionConfig.h"
+#include <InterruptConfig.h>
+#include <HdAudioConfig.h>
+#include <IshConfig.h>
+#include <GbeConfig.h>
+#include "ConfigBlock/LockDownConfig.h"
+#include "P2sbConfig.h"
+#include <PmConfig.h>
+#include <ScsConfig.h>
+#include <SerialIoConfig.h>
+#include <ThcConfig.h>
+#include <ThermalConfig.h>
+#include <EspiConfig.h>
+#include <CnviConfig.h>
+#include <IehConfig.h>
+#include <PsfConfig.h>
+#include <FivrConfig.h>
+#include <AdrConfig.h>
+#include <RtcConfig.h>
+#include <HybridStorageConfig.h>
+#include <SpiConfig.h>
+
+#ifndef FORCE_ENABLE
+#define FORCE_ENABLE 1
+#endif
+#ifndef FORCE_DISABLE
+#define FORCE_DISABLE 2
+#endif
+#ifndef PLATFORM_POR
+#define PLATFORM_POR 0
+#endif
+
+
+#endif // _PCH_POLICY_COMMON_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
new file mode 100644
index 0000000000..25e99d3a68
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h
@@ -0,0 +1,56 @@
+/** @file
+ PCH configuration based on PCH policy
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PREMEM_POLICY_COMMON_H_
+#define _PCH_PREMEM_POLICY_COMMON_H_
+
+#include <ConfigBlock.h>
+
+#include "PchLimits.h"
+#include "ConfigBlock/PchGeneralConfig.h"
+#include <DciConfig.h>
+#include <WatchDogConfig.h>
+#include <SmbusConfig.h>
+#include "ConfigBlock/LpcConfig.h"
+#include "ConfigBlock/HsioPcieConfig.h"
+#include "ConfigBlock/HsioSataConfig.h"
+#include "ConfigBlock/HsioConfig.h"
+
+#pragma pack (push,1)
+
+#ifndef FORCE_ENABLE
+#define FORCE_ENABLE 1
+#endif
+#ifndef FORCE_DISABLE
+#define FORCE_DISABLE 2
+#endif
+#ifndef PLATFORM_POR
+#define PLATFORM_POR 0
+#endif
+
+/**
+ PCH Policy revision number
+ Any backwards compatible changes to this structure will result in an update in the revision number
+**/
+#define PCH_PREMEM_POLICY_REVISION 1
+
+/**
+ PCH Policy PPI\n
+ All PCH config block change history will be listed here\n\n
+
+ - <b>Revision 1</b>:
+ - Initial version.\n
+**/
+typedef struct _PCH_PREMEM_POLICY {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader;
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+} PCH_PREMEM_POLICY;
+
+#pragma pack (pop)
+
+#endif // _PCH_PREMEM_POLICY_COMMON_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h
new file mode 100644
index 0000000000..4573a11520
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h
@@ -0,0 +1,21 @@
+/** @file
+ PCH Reset Platform Specific definitions.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_
+#define _PCH_RESET_PLATFORM_SPECIFIC_H_
+
+#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET"
+#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFIC_RESET_STRING) / sizeof (UINT16))
+
+extern EFI_GUID gPchGlobalResetGuid;
+
+typedef struct _RESET_DATA {
+ CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH];
+ EFI_GUID Guid;
+} PCH_RESET_DATA;
+
+#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_
+
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h
new file mode 100644
index 0000000000..4d6241c32b
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h
@@ -0,0 +1,184 @@
+/** @file
+ PCH IO TrapEx Dispatch Protocol
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _IO_TRAP_EX_DISPATCH_H_
+#define _IO_TRAP_EX_DISPATCH_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gIoTrapExDispatchProtocolGuid;
+
+typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL IO_TRAP_EX_DISPATCH_PROTOCOL;
+
+/**
+ IO Trap Ex valid types
+**/
+typedef enum {
+ IoTrapExTypeWrite,
+ IoTrapExTypeRead,
+ IoTrapExTypeReadWrite,
+ IoTrapExTypeMaximum
+} IO_TRAP_EX_DISPATCH_TYPE;
+
+/**
+ IO Trap Ex context structure containing information about the
+ IO trap Ex event that should invoke the handler.
+ ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for any byte access.
+
+ Here are some examples for the usage.
+ 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with BYTE/WORD/DWORD read/write access:
+ Address = 0x2000
+ Length = 0x100
+ Type = IoTrapExTypeReadWrite
+ ByteEnable = 0x00 (BE is not matter)
+ ByteEnableMask = 0x0F (BEM 0xF for any BYTE/WORD/DWORD access)
+ 2. To trigger the TRAP for port 0x61 with BYTE read access:
+ Address = 0x60
+ Length = 4
+ Type = IoTrapExTypeRead
+ ByteEnable = 0x02 (BE is 0010b to trap only second byte of every DWORD)
+ ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)
+ 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access:
+ Address = 0x60
+ Length = 8
+ Type = IoTrapExTypeWrite
+ ByteEnable = 0x01 (BE is 0001b to trap only first byte of every DWORD)
+ ByteEnableMask = 0x00 (BEM doesn't mask any BE bit)
+**/
+typedef struct {
+ /**
+ The Address must be dword alignment.
+ **/
+ UINT16 Address;
+ UINT16 Length;
+ IO_TRAP_EX_DISPATCH_TYPE Type;
+ /**
+ Bitmap to enable trap for each byte of every dword alignment address.
+ The Io Trap Address must be dword alignment for ByteEnable.
+ E.g. 0001b for first byte, 0010b for second byte, 1100b for third and fourth byte.
+ **/
+ UINT8 ByteEnable;
+ /**
+ ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for any byte access.
+ The Io Trap Address must be dword alignment for ByteEnableMask.
+ **/
+ UINT8 ByteEnableMask;
+} IO_TRAP_EX_REGISTER_CONTEXT;
+
+/**
+ Callback function for an PCH IO TRAP EX handler dispatch.
+
+ @param[in] Address DWord-aligned address of the trapped cycle.
+ @param[in] ByteEnable This is the DWord-aligned byte enables associated with the trapped cycle.
+ A 1 in any bit location indicates that the corresponding byte is enabled in the cycle.
+ @param[in] WriteCycle TRUE = Write cycle; FALSE = Read cycle
+ @param[in] WriteData DWord of I/O write data. This field is undefined after trapping a read cycle.
+ The byte of WriteData is only valid if the corresponding bits in ByteEnable is 1.
+ E.g.
+ If ByteEnable is 0001b, then only first byte of WriteData is valid.
+ If ByteEnable is 0010b, then only second byte of WriteData is valid.
+**/
+typedef
+VOID
+(EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) (
+ IN UINT16 Address,
+ IN UINT8 ByteEnable,
+ IN BOOLEAN WriteCycle,
+ IN UINT32 WriteData
+ );
+
+/**
+ Register a new IO Trap Ex SMI dispatch function.
+ The caller will provide information of IO trap setting via the context.
+ Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
+ This is the function to extend the IoTrap capability, and it's expected
+ to handle the special ByteEnable and ByteEnableMask setting.
+ This register function will occupy one IoTrap register if possible.
+ And it only support one handler for one IoTrap event.
+ The Address of context MUST NOT be 0, and MUST be dword alignment.
+ The Length of context MUST not less than 4, and MUST be power of 2.
+ The ByteEnable and ByteEnableMask MUST not be zero at the same time.
+ if the IO Trap handler is not used. It also enable the IO Trap Range to generate
+ SMI.
+ Caller must take care of reserving the IO addresses in ACPI.
+
+ @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source.
+ @param[in] RegisterContext Pointer to the dispatch function's context.
+ The caller fills this context in before calling
+ the register function to indicate to the register
+ function the IO trap Ex SMI source for which the dispatch
+ function should be invoked. This MUST not be NULL.
+ @param[out] DispatchHandle Handle of dispatch function.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_OUT_OF_RESOURCES Insufficient resources are available
+ @retval EFI_INVALID_PARAMETER Address requested is already in use.
+ @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLock event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) (
+ IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,
+ IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction,
+ IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a SMI source dispatch function.
+ This function is unsupported.
+
+ @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTOCOL instance.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_UNSUPPORTED The function is unsupported.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) (
+ IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for the IO trap Extention protocol.
+ This protocol exposes full IO TRAP capability for ByteEnable and ByteEnableMask setting.
+ Platform code should fully control the ByteEnable and ByteEnableMake while using this protocol.
+
+ Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
+ This is the function to extend the IoTrap capability, and it's expected
+ to handle the special ByteEnable and ByteEnableMask setting.
+
+ The protocol is low level, It returns PSTH trapped cycle. This might not be safe for multithread
+ if more than one thread triggers the same IOTRAP at the same time.
+**/
+struct _IO_TRAP_EX_DISPATCH_PROTOCOL {
+ /**
+ Register function for PCH IO TRAP EX DISPATCH PROTOCOL.
+ The caller will provide information of IO trap setting via the context.
+ Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.
+ This is the function to extend the IoTrap capability, and it's expected
+ to handle the special ByteEnable and ByteEnableMask setting.
+ This register function will occupy one IoTrap register if possible.
+ And it only support one handler for one IoTrap event.
+ The Address of context MUST NOT be 0, and MUST be dword alignment.
+ The Length of context MUST not less than 4, and MUST be power of 2.
+ The ByteEnable and ByteEnableMask MUST not be zero at the same time.
+ if the IO Trap handler is not used. It also enable the IO Trap Range to
+ generate SMI.
+ **/
+ IO_TRAP_EX_DISPATCH_REGISTER Register;
+ /**
+ Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL.
+ **/
+ IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister;
+};
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h
new file mode 100644
index 0000000000..136734d9ff
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.h
@@ -0,0 +1,134 @@
+/** @file
+ APIs of PCH ACPI SMI Dispatch Protocol.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_
+#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PROTOCOL;
+
+//
+// Member functions
+//
+
+/**
+ Callback function for an PCH ACPI SMI handler dispatch.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by register function.
+
+**/
+typedef
+VOID
+(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) (
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Register a child SMI source dispatch function for PCH ACPI SMI events.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param[out] DispatchHandle Handle of dispatch function, for when interfacing
+ with the parent SMM driver.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) (
+ IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,
+ IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent ACPI SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) (
+ IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for PCH ACPI SMIs Dispatch Protocol
+ The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH ACPI related SMIs.
+ It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow.
+**/
+struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ /**
+ Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL.
+ **/
+ PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister;
+ /**
+ Pme
+ The event is triggered by hardware when the PME# signal goes active.
+ Additionally, the event is only triggered when SCI_EN is not set.
+ **/
+ PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister;
+ /**
+ PmeB0
+ The event is triggered PCH when any internal device with PCI Power Management
+ capabilities on bus 0 asserts the equivalent of the PME# signal.
+ Additionally, the event is only triggered when SCI_EN is not set.
+ The following are internal devices which can set this bit:
+ Intel HD Audio, Intel Management Engine "maskable" wake events, Integrated LAN,
+ SATA, xHCI, Intel SST
+ **/
+ PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register;
+ /**
+ RtcAlarm
+ The event is triggered by hardware when the RTC generates an alarm
+ (assertion of the IRQ8# signal).
+ **/
+ PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister;
+ /**
+ TmrOverflow
+ The event is triggered any time bit 22 of the 24-bit timer goes high
+ (bits are numbered from 0 to 23).
+ This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 02h, bit 0) is set,
+ then the setting of the TMROF_STS bit will additionally generate an SMI#
+ Additionally, the event is only triggered when SCI_EN is not set.
+ **/
+ PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister;
+};
+
+/**
+ PCH ACPI SMI dispatch revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_ACPI_SMI_DISPATCH_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h
new file mode 100644
index 0000000000..4ea48c3fcd
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.h
@@ -0,0 +1,144 @@
+/** @file
+ SmmEspiDispatch Protocol
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_
+#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchEspiSmiDispatchProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTOCOL;
+
+//
+// Member functions
+//
+
+/**
+ Callback function for an PCH eSPI SMI handler dispatch.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by register function.
+**/
+typedef
+VOID
+(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) (
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Generic function to register different types of eSPI SMI types
+
+ @param[in] This Not used
+ @param[in] DispatchFunction The callback to execute
+ @param[out] DispatchHandle The handle for this callback registration
+
+ @retval EFI_SUCCESS Registration successful
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+ @retval others Registration failed
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_ESPI_SMI_REGISTER) (
+ IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,
+ IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ eSPI SMI Dispatch Protocol instance to unregister a callback based on handle
+
+ @param[in] This Not used
+ @param[in] DispatchHandle Handle acquired during registration
+
+ @retval EFI_SUCCESS Unregister successful
+ @retval EFI_INVALID_PARAMETER DispatchHandle is null
+ @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has bad pointer
+ @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in database
+ @retval EFI_ACCESS_DENIED Unregistration is done after end of DXE
+**/
+
+typedef
+EFI_STATUS
+(EFIAPI *PCH_ESPI_SMI_UNREGISTER) (
+ IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for PCH eSPI SMIs Dispatch Protocol
+ The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH eSPI related SMIs.
+ It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserted SMIs
+**/
+struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ /**
+ Unregister eSPI SMI events
+ **/
+ PCH_ESPI_SMI_UNREGISTER UnRegister;
+ /**
+ Register a BIOS Write Protect event
+ **/
+ PCH_ESPI_SMI_REGISTER BiosWrProtectRegister;
+ /**
+ Register a BIOS Write Report event
+ **/
+ PCH_ESPI_SMI_REGISTER BiosWrReportRegister;
+ /**
+ Register a Peripheral Channel Non Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister;
+ /**
+ Register a Peripheral Channel Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER PcErrFatalRegister;
+ /**
+ Register a Virtual Wire Non Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister;
+ /**
+ Register a Virtual Wire Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER VwErrFatalRegister;
+ /**
+ Register a Flash Channel Non Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister;
+ /**
+ Register a Flash Channel Fatal Error event
+ **/
+ PCH_ESPI_SMI_REGISTER FlashErrFatalRegister;
+ /**
+ Register a Link Error event
+ **/
+ PCH_ESPI_SMI_REGISTER LnkErrType1Register;
+ /**
+ Register a SMI handler for Espi slaver
+ This routine will also lock down ESPI_SMI_LOCK bit after registration and prevent
+ this handler from unregistration.
+ On platform that supports more than 1 device through another chip select (SPT-H),
+ the SMI handler itself needs to inspect both the eSPI devices' interrupt status registers
+ (implementation specific for each Slave) in order to identify and service the cause.
+ After servicing it, it has to clear the Slaves' internal SMI# status registers
+ **/
+ PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister;
+};
+
+/**
+ PCH ESPI SMI dispatch revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_ESPI_SMI_DISPATCH_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h
new file mode 100644
index 0000000000..b75b9ab45d
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.h
@@ -0,0 +1,166 @@
+/** @file
+ APIs of PCH PCIE SMI Dispatch Protocol.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
+#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchPcieSmiDispatchProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PROTOCOL;
+
+typedef enum {
+ PchRpIndex0 = 0,
+ PchRpIndex1 = 1,
+ PchRpIndex2 = 2,
+ PchRpIndex3 = 3,
+ PchRpIndex4 = 4,
+ PchRpIndex5 = 5,
+ PchRpIndex6 = 6,
+ PchRpIndex7 = 7,
+ PchRpIndex8 = 8,
+ PchRpIndex9 = 9,
+ PchRpIndex10 = 10,
+ PchRpIndex11 = 11,
+ PchRpIndex12 = 12,
+ PchRpIndex13 = 13,
+ PchRpIndex14 = 14,
+ PchRpIndex15 = 15,
+ PchRpIndex16 = 16,
+ PchRpIndex17 = 17,
+ PchRpIndex18 = 18,
+ PchRpIndex19 = 19,
+ PchRpIndex20 = 20,
+ PchRpIndex21 = 21,
+ PchRpIndex22 = 22,
+ PchRpIndex23 = 23,
+ /**
+ Quantity of PCH and CPU PCIe ports, as well as their encoding in this enum, may change between
+ silicon generations and series. Do not assume that PCH port 0 will be always encoded by 0.
+ Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style to be forward-compatible
+ **/
+ CpuRpIndex0 = 0x40,
+ CpuRpIndex1 = 0x41,
+ CpuRpIndex2 = 0x42,
+ CpuRpIndex3 = 0x43
+} PCIE_COMBINED_RPINDEX;
+
+//
+// Member functions
+//
+
+typedef struct {
+ UINT8 RpIndex; ///< Root port index (0-based), 0: RP1, 1: RP2, n: RP(N+1)
+ UINT8 BusNum; ///< Root port pci bus number
+ UINT8 DevNum; ///< Root port pci device number
+ UINT8 FuncNum; ///< Root port pci function number
+} PCH_PCIE_SMI_RP_CONTEXT;
+
+/**
+ Callback function for an PCH PCIE RP SMI handler dispatch.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by register function.
+ @param[in] RpContext Pointer of PCH PCIE Root Port context.
+
+**/
+typedef
+VOID
+(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (
+ IN EFI_HANDLE DispatchHandle,
+ IN PCH_PCIE_SMI_RP_CONTEXT *RpContext
+ );
+
+/**
+ Register a child SMI source dispatch function for PCH PCIERP SMI events.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for PCH RP index and CPU RP index.
+ 0: RP1, 1: RP2, n: RP(N+1)
+ @param[out] DispatchHandle Handle of dispatch function, for when interfacing
+ with the parent SMM driver.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (
+ IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
+ IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction,
+ IN UINTN RpIndex,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent PCIE SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) (
+ IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for PCH PCIE SMIs Dispatch Protocol
+ The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH PCIE related SMIs.
+ It contains SMI types of HotPlug, LinkActive, and Link EQ.
+**/
+struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ /**
+ Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.
+ **/
+ PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister;
+ /**
+ PcieRpXHotPlug
+ The event is triggered when PCIE root port Hot-Plug Presence Detect.
+ **/
+ PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister;
+ /**
+ PcieRpXLinkActive
+ The event is triggered when Hot-Plug Link Active State Changed.
+ **/
+ PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister;
+ /**
+ PcieRpXLinkEq
+ The event is triggered when Device Requests Software Link Equalization.
+ **/
+ PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister;
+};
+
+/**
+ PCH PCIE SMI dispatch revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_PCIE_SMI_DISPATCH_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h
new file mode 100644
index 0000000000..ba7cbdb23e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h
@@ -0,0 +1,40 @@
+/** @file
+ Interface definition details between Pch and platform drivers during DXE phase.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_POLICY_H_
+#define _PCH_POLICY_H_
+
+#include <ConfigBlock.h>
+#include <Library/ConfigBlockLib.h>
+#include "../IncludePrivate/PchConfigHob.h" // To Be corrected
+#include <Library/HobLib.h>
+
+extern EFI_GUID gPchPolicyProtocolGuid;
+
+#define PCH_POLICY_PROTOCOL_REVISION 1
+
+
+/**
+ PCH DXE Policy
+
+ The PCH_POLICY_PROTOCOL producer drvier is recommended to
+ set all the PCH_POLICY_PROTOCOL size buffer zero before init any member parameter,
+ this clear step can make sure no random value for those unknown new version parameters.
+
+ Make sure to update the Revision if any change to the protocol, including the existing
+ internal structure definations.\n
+ Note: Here revision will be bumped up when adding/removing any config block under this structure.\n
+ <b>Revision 1</b>:
+ - Initial version.
+**/
+typedef struct {
+ CONFIG_BLOCK_TABLE_HEADER TableHeader;
+/*
+ Individual Config Block Structures are added here in memory as part of AddConfigBlock()
+*/
+} PCH_POLICY_PROTOCOL;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
new file mode 100644
index 0000000000..12b5f8117b
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h
@@ -0,0 +1,132 @@
+/** @file
+ APIs of PCH SMI Dispatch Protocol.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_
+#define _PCH_SMI_DISPATCH_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSmiDispatchProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCOL;
+
+//
+// Member functions
+//
+
+/**
+ Callback function for an PCH SMI handler dispatch.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by register function.
+
+**/
+typedef
+VOID
+(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) (
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Register a child SMI source dispatch function for specific PCH SMI dispatch event.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param[out] DispatchHandle Handle of dispatch function, for when interfacing
+ with the parent SMM driver.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SMI_DISPATCH_REGISTER) (
+ IN PCH_SMI_DISPATCH_PROTOCOL *This,
+ IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) (
+ IN PCH_SMI_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for PCH specific SMIs Dispatch Protocol
+ The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH misc SMIs.
+ It contains legacy SMIs and new PCH SMI types like:
+ SerialIrq, McSmi, Smbus, ...
+**/
+struct _PCH_SMI_DISPATCH_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ /**
+ Smi unregister function for PCH SMI DISPATCH PROTOCOL.
+ **/
+ PCH_SMI_DISPATCH_UNREGISTER UnRegister;
+ /**
+ SerialIrq
+ The event is triggered while the SMI# was caused by the SERIRQ decoder.
+ **/
+ PCH_SMI_DISPATCH_REGISTER SerialIrqRegister;
+ /**
+ McSmi
+ The event is triggered if there has been an access to the power management
+ microcontroller range (62h or 66h) and the Microcontroller Decode Enable #1 bit
+ in the LPC Bridge I/O Enables configuration register is 1 .
+ **/
+ PCH_SMI_DISPATCH_REGISTER McSmiRegister;
+ /**
+ SmBus
+ The event is triggered while the SMI# was caused by:
+ 1. The SMBus Slave receiving a message that an SMI# should be caused, or
+ 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and the
+ SMBALERT_DIS bit is cleared, or
+ 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY_INTREN and
+ the SMB_SMI_EN bits are set, or
+ 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 state.
+ **/
+ PCH_SMI_DISPATCH_REGISTER SmbusRegister;
+ /**
+ SPI Asynchronous
+ When registered, the flash controller will generate an SMI when it blocks a BIOS write or erase.
+ **/
+ PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister;
+};
+
+/**
+ PCH SMI dispatch revision number
+
+ Revision 1: Initial version
+**/
+#define PCH_SMI_DISPATCH_REVISION 1
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h
new file mode 100644
index 0000000000..9f2793634e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl.h
@@ -0,0 +1,65 @@
+/** @file
+ PCH SMM IO Trap Control Protocol
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_
+#define _PCH_SMM_IO_TRAP_CONTROL_H_
+
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSmmIoTrapControlGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_PROTOCOL;
+
+//
+// Related Definitions
+//
+
+//
+// Member functions
+//
+
+/**
+ The Prototype of Pause and Resume IoTrap callback function.
+
+ @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_PROTOCOL instance.
+ @param[in] DispatchHandle Handle of the child service to change state.
+
+ @retval EFI_SUCCESS This operation is complete.
+ @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.
+ @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) (
+ IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for the SMM IO trap pause and resume protocol
+ This protocol provides the functions to runtime control the IoTrap SMI enabled/disable.
+ This applys the capability to the DispatchHandle which returned by IoTrap callback
+ registration, and the DispatchHandle which must be MergeDisable = TRUE and Address != 0.
+ Besides, when S3 resuem, it only restores the state of IoTrap callback registration.
+ The Paused/Resume state won't be restored after S3 resume.
+**/
+struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL {
+ /**
+ This runtime pauses a registered IoTrap handler.
+ **/
+ PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause;
+ /**
+ This runtime resumes a registered IoTrap handler.
+ **/
+ PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume;
+};
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
new file mode 100644
index 0000000000..a7b44c5f7e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimerControl.h
@@ -0,0 +1,65 @@
+/** @file
+ PCH SMM Periodic Timer Control Protocol
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
+#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
+
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchSmmPeriodicTimerControlGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL;
+
+//
+// Related Definitions
+//
+
+//
+// Member functions
+//
+
+/**
+ The Prototype of Pause and Resume SMM PERIODIC TIMER function.
+
+ @param[in] This Pointer to the PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL instance.
+ @param[in] DispatchHandle Handle of the child service to change state.
+
+ @retval EFI_SUCCESS This operation is complete.
+ @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.
+ @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED.
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) (
+ IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for the SMM PERIODIC TIMER pause and resume protocol
+ This protocol provides the functions to runtime control the SM periodic timer enabled/disable.
+ This applies the capability to the DispatchHandle which returned by SMM periodic timer callback
+ registration.
+ Besides, when S3 resume, it only restores the state of callback registration.
+ The Paused/Resume state won't be restored after S3 resume.
+**/
+struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL {
+ /**
+ This runtime pauses the registered periodic timer handler.
+ **/
+ PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause;
+ /**
+ This runtime resumes the registered periodic timer handler.
+ **/
+ PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume;
+};
+
+#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
new file mode 100644
index 0000000000..b443484f39
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h
@@ -0,0 +1,150 @@
+/** @file
+ APIs of PCH TCO SMI Dispatch Protocol.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_
+#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID gPchTcoSmiDispatchProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PROTOCOL;
+
+//
+// Member functions
+//
+
+/**
+ Callback function for an PCH TCO SMI handler dispatch.
+
+ @param[in] DispatchHandle The unique handle assigned to this handler by register function.
+
+**/
+typedef
+VOID
+(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) (
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Register a child SMI source dispatch function for PCH TCO SMI events.
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchFunction Pointer to dispatch function to be invoked for
+ this SMI source
+ @param[out] DispatchHandle Handle of dispatch function, for when interfacing
+ with the parent SMM driver.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ registered and the SMI source has been enabled.
+ @retval EFI_DEVICE_ERROR The driver was unable to enable the SMI source.
+ @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) to manage this child.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) (
+ IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,
+ IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction,
+ OUT EFI_HANDLE *DispatchHandle
+ );
+
+/**
+ Unregister a child SMI source dispatch function with a parent TCO SMM driver
+
+ @param[in] This Protocol instance pointer.
+ @param[in] DispatchHandle Handle of dispatch function to deregister.
+
+ @retval EFI_SUCCESS The dispatch function has been successfully
+ unregistered and the SMI source has been disabled
+ if there are no other registered child dispatch
+ functions for this SMI source.
+ @retval EFI_INVALID_PARAMETER Handle is invalid.
+ @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event has been triggered
+**/
+typedef
+EFI_STATUS
+(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) (
+ IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,
+ IN EFI_HANDLE DispatchHandle
+ );
+
+/**
+ Interface structure for PCH TCO SMIs Dispatch Protocol
+ The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch function for PCH TCO related SMIs.
+ It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, and BiowWp.
+**/
+struct _PCH_TCO_SMI_DISPATCH_PROTOCOL {
+ /**
+ This member specifies the revision of this structure. This field is used to
+ indicate backwards compatible changes to the protocol.
+ **/
+ UINT8 Revision;
+ /**
+ Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL.
+ **/
+ PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister;
+ /**
+ Mch
+ The event is triggered when PCH received a DMI special cycle message using DMI indicating that
+ it wants to cause an SMI.
+ The software must read the processor to determine the reason for the SMI.
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER MchRegister;
+ /**
+ TcoTimeout
+ The event is triggered by PCH to indicate that the SMI was caused by the TCO timer reaching 0.
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister;
+ /**
+ OsTco
+ The event is triggered when software caused an SMI# by writing to the TCO_DAT_IN register (TCOBASE + 02h).
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister;
+ /**
+ Nmi
+ The event is triggered by the PCH when an SMI# occurs because an event occurred that would otherwise have
+ caused an NMI (because NMI2SMI_EN is set)
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister;
+ /**
+ IntruderDectect
+ The event is triggered by PCH to indicate that an intrusion was detected.
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister;
+ /**
+ SpiBiosWp
+ This event is triggered when SMI# was caused by the TCO logic and
+ SPI flash controller asserted Synchronous SMI by BIOS lock enable set.
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister;
+ /**
+ LpcBiosWp
+ This event is triggered when SMI# was caused by the TCO logic and
+ LPC/eSPI BIOS lock enable set.
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister;
+ /**
+ NewCentury
+ This event is triggered when SMI# was caused by the TCO logic and
+ year of RTC date rolls over a century (99 to 00).
+ **/
+ PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister;
+};
+
+/**
+ PCH TCO SMI dispatch revision number
+
+ Revision 1: Initial version
+ Revision 2: Add NEWCENTURY support
+**/
+#define PCH_TCO_SMI_DISPATCH_REVISION 2
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h
new file mode 100644
index 0000000000..679cb17f6c
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h
@@ -0,0 +1,16 @@
+/** @file
+ Generic register definitions for PCH.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_H_
+#define _PCH_REGS_H_
+
+///
+/// The default PCH PCI segment and bus number
+///
+#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0
+#define DEFAULT_PCI_BUS_NUMBER_PCH 0
+
+#endif //_PCH_REGS_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
new file mode 100644
index 0000000000..32dd88be0e
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h
@@ -0,0 +1,145 @@
+/** @file
+ Register names for PCH LPC/eSPI device
+
+Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_LPC_H_
+#define _PCH_REGS_LPC_H_
+
+#define B_LPC_CFG_DID 0xFFE0
+
+//
+// PCI to LPC Bridge Registers
+//
+
+#define R_LPC_CFG_IOD 0x80
+#define V_LPC_CFG_IOD_COMB_2F8 1
+#define V_LPC_CFG_IOD_COMA_3F8 0
+#define V_LPC_CFG_IOD_COMA_2F8 1
+#define R_LPC_CFG_IOE 0x82
+#define B_LPC_CFG_IOE_SE BIT12 ///< Super I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.
+#define B_LPC_CFG_IOE_KE BIT10 ///< Keyboard Enable, Enables decoding of the keyboard I/O locations 60h and 64h to LPC.
+#define B_LPC_CFG_IOE_PPE BIT2 ///< Parallel Port Enable, Enables decoding of the LPT range to LPC. Range is selected by LIOD.LPT.
+#define B_LPC_CFG_IOE_CBE BIT1 ///< Com Port B Enable, Enables decoding of the COMB range to LPC. Range is selected LIOD.CB.
+#define B_LPC_CFG_IOE_CAE BIT0 ///< Com Port A Enable, Enables decoding of the COMA range to LPC. Range is selected LIOD.CA.
+#define R_LPC_CFG_ULKMC 0x94
+#define B_LPC_CFG_ULKMC_A20PASSEN BIT5
+#define B_LPC_CFG_ULKMC_64WEN BIT3
+#define B_LPC_CFG_ULKMC_64REN BIT2
+#define B_LPC_CFG_ULKMC_60WEN BIT1
+#define B_LPC_CFG_ULKMC_60REN BIT0
+#define R_LPC_CFG_LGMR 0x98
+#define B_LPC_CFG_LGMR_MA 0xFFFF0000
+#define B_LPC_CFG_LGMR_LMRD_EN BIT0
+#define R_ESPI_CFG_CS1IORE 0xA0
+#define R_ESPI_CFG_CS1GMR1 0xA8
+
+#define R_LPC_CFG_BDE 0xD8 ///< BIOS decode enable
+
+//
+// APM Registers
+//
+#define R_PCH_IO_APM_CNT 0xB2
+#define R_PCH_IO_APM_STS 0xB3
+
+#define R_LPC_CFG_BC 0xDC ///< Bios Control
+#define S_LPC_CFG_BC 1
+#define N_LPC_CFG_BC_LE 1
+#define B_LPC_CFG_BC_WPD BIT0 ///< Write Protect Disable
+
+#define R_ESPI_CFG_PCBC 0xDC ///< Peripheral Channel BIOS Control
+#define S_ESPI_CFG_PCBC 4 ///< Peripheral Channel BIOS Control register size
+#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIOS Write Report Enable
+#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIOS Write Report Status
+#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIOS Write Protect Disable Status
+#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIOS Write Protect Disable Status bit position
+#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSPI Enable Pin Strap
+#define B_ESPI_CFG_PCBC_LE BIT1 ///< Lock Enable
+#define N_ESPI_CFG_PCBC_LE 1
+
+//
+// eSPI slave registers
+//
+#define B_ESPI_SLAVE_BME BIT2 ///< Bus Master Enable
+
+//
+// Reset Generator I/O Port
+//
+#define R_PCH_IO_RST_CNT 0xCF9
+#define V_PCH_IO_RST_CNT_FULLRESET 0x0E
+#define V_PCH_IO_RST_CNT_HARDRESET 0x06
+
+//
+// eSPI PCR Registers
+//
+#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///< Slave Configuration Register and Link Control
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///< Slave Configuration Register Access Enable
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///< Slave Configuration Register Access Status
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///< Slave Configuration Register Access Status bit position
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///< IOSF-SB eSPI Link Configuration Lock
+#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///< No errors (transaction completed successfully)
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///< Slave ID
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///< Slave ID bit position
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///< Slave Configuration Register Access Type
+#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///< Slave Configuration Register Access Type bit position
+#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///< Slave Configuration Register Address
+#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///< Slave Configuration Register Data
+
+#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Peripheral Channel Error for Slave 0
+#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
+#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual Wire Channel Error for Slave 0
+#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash Access Channel Error for Slave 0
+#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blocked (SAFBLK)
+#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fatal Error Reporting Enable bits
+#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fatal Error Reporting Enable bit position
+#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable Non-Fatal Error Reporting as SMI
+#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal Error Status
+#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal Error Reporting Enable bits
+#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal Error Reporting Enable bit position
+#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable Fatal Error Reporting as SMI
+#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal Error Status
+#define S_ESPI_PCR_XERR 4 ///< Channel register sizes
+#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Peripheral Channel Unsupported Request Detected
+#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Error for Slave 0
+#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Error for Slave 0 register size
+#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Link and Slave Channel Recovery Required
+#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal Error Type 1 Reporting Enable
+#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal Error Type 1 Reporting Enable bit position
+#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable Fatal Error Type 1 Reporting as SMI
+#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fatal Error Type 1 Status
+#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Error for Slave 1
+#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI Enabled Strap
+#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI Enabled Strap bit position
+#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI Sofstraps Register 0
+#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# Enable
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
new file mode 100644
index 0000000000..dc32f1e5b3
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h
@@ -0,0 +1,50 @@
+/** @file
+ Register definition for PSF component
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PSF_H_
+#define _PCH_REGS_PSF_H_
+//
+// PSFx segment registers
+//
+
+#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1
+#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0
+
+//
+// PSFx PCRs definitions
+//
+#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000
+#define N_PCH_PSFX_PCR_TARGET_PSFID 16
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
new file mode 100644
index 0000000000..2007eae44f
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h
@@ -0,0 +1,66 @@
+/** @file
+ Register definition for PSTH component
+
+ Conventions:
+
+ - Register definition format:
+ Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_RegisterName
+ - Prefix:
+ Definitions beginning with "R_" are registers
+ Definitions beginning with "B_" are bits within registers
+ Definitions beginning with "V_" are meaningful values within the bits
+ Definitions beginning with "S_" are register size
+ Definitions beginning with "N_" are the bit position
+ - [GenerationName]:
+ Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.).
+ Register name without GenerationName applies to all generations.
+ - [ComponentName]:
+ This field indicates the component name that the register belongs to (e.g. PCH, SA etc.)
+ Register name without ComponentName applies to all components.
+ Register that is specific to -LP denoted by "_PCH_LP_" in component name.
+ - SubsystemName:
+ This field indicates the subsystem name of the component that the register belongs to
+ (e.g. PCIE, USB, SATA, GPIO, PMC etc.).
+ - RegisterSpace:
+ MEM - MMIO space register of subsystem.
+ IO - IO space register of subsystem.
+ PCR - Private configuration register of subsystem.
+ CFG - PCI configuration space register of subsystem.
+ - RegisterName:
+ Full register name.
+
+ Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_REGS_PSTH_H_
+#define _PCH_REGS_PSTH_H_
+
+//
+// Private chipset regsiter (Memory space) offset definition
+// The PCR register defines is used for PCR MMIO programming and PCH SBI programming as well.
+//
+
+//
+// PSTH and IO Trap PCRs (PID:PSTH)
+//
+#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH control register
+#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF primary trunk clock gating enable
+#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap status regsiter
+#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped cycle
+#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Write#: 1=Read, 0=Write
+#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active high byte enables
+#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap cycle I/O address
+#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped write data
+#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0 register
+#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1 register
+#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2 register
+#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3 register
+#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 for 32 bit access, Read/Write mask
+#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 for 32 bit access, Read/Write#, 1=Read, 0=Write
+#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 for 32 bit access, 16bit shift for Read/Write field
+#define N_PSTH_PCR_TRPREG_BEM 36
+#define N_PSTH_PCR_TRPREG_BE 32
+#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO Address
+#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and SMI# Enable
+
+#endif
--
2.24.0.windows.2
next prev parent reply other threads:[~2021-02-05 7:41 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-02-05 7:40 [Patch V3 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-05 7:40 ` [Patch V3 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-05 7:40 ` [Patch V3 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-05 7:40 ` [Patch V3 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-05 7:40 ` Heng Luo [this message]
2021-02-05 7:40 ` [Patch V3 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Heng Luo
2021-02-05 7:40 ` [Patch V3 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Heng Luo
2021-02-05 7:40 ` [Patch V3 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-05 7:40 ` [Patch V3 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-05 7:40 ` [Patch V3 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-05 7:40 ` [Patch V3 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-05 7:40 ` [Patch V3 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-05 7:40 ` [Patch V3 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-05 7:40 ` [Patch V3 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-05 7:40 ` [Patch V3 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-05 7:40 ` [Patch V3 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-05 7:40 ` [Patch V3 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-05 7:40 ` [Patch V3 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-05 7:40 ` [Patch V3 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-05 7:40 ` [Patch V3 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-05 7:40 ` [Patch V3 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-05 7:40 ` [Patch V3 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-05 7:40 ` [Patch V3 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-05 7:40 ` [Patch V3 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-05 7:40 ` [Patch V3 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-05 7:40 ` [Patch V3 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-05 7:40 ` [Patch V3 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-05 7:40 ` [Patch V3 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-05 7:40 ` [Patch V3 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-05 7:40 ` [Patch V3 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-05 7:40 ` [Patch V3 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-05 7:40 ` [Patch V3 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-05 7:40 ` [Patch V3 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-05 7:40 ` [Patch V3 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-05 7:40 ` [Patch V3 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-05 7:40 ` [Patch V3 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-05 7:40 ` [Patch V3 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-05 7:40 ` [Patch V3 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-05 7:40 ` [Patch V3 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-05 7:40 ` [Patch V3 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-05 18:36 ` Nate DeSimone
2021-02-05 18:57 ` Chaganty, Rangasai V
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