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Feb 2021 23:41:22 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 05/40] TigerlakeSiliconPkg/Pch: Add include headers Date: Fri, 5 Feb 2021 15:40:10 +0800 Message-Id: <20210205074045.3916-5-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Pch/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtectionC= onfig.h | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h = | 57 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieConfig.h= | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataConfig.h= | 64 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownConfig.h= | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h = | 38 ++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralConfig= .h | 72 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodingLib.= h | 258 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h = | 590 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h = | 552 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h = | 70 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h = | 67 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h = | 55 +++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h = | 56 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecific.h = | 21 +++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispatch.h = | 184 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDispatch.= h | 134 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDispatch.= h | 144 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDispatch.= h | 166 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h = | 40 ++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch.h = | 132 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapControl= .h | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodicTimer= Control.h | 65 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispatch.h= | 150 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h = | 16 ++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h = | 145 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h = | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h = | 66 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++ 28 files changed, 3431 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Flas= hProtectionConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigB= lock/FlashProtectionConfig.h new file mode 100644 index 0000000000..d1e10c3422 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/FlashProtec= tionConfig.h @@ -0,0 +1,55 @@ +/** @file=0D + FlashProtection policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _FLASH_PROTECTION_CONFIG_H_=0D +#define _FLASH_PROTECTION_CONFIG_H_=0D +=0D +#define FLASH_PROTECTION_CONFIG_REVISION 1=0D +extern EFI_GUID gFlashProtectionConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +//=0D +// Flash Protection Range Register=0D +//=0D +#define PCH_FLASH_PROTECTED_RANGES 5=0D +=0D +/**=0D + Protected Flash Range=0D +**/=0D +typedef struct {=0D + UINT32 WriteProtectionEnable : 1; ///< Write or = erase is blocked by hardware. 0: Disable; 1: Enable.=0D + UINT32 ReadProtectionEnable : 1; ///< Read is b= locked by hardware. 0: Disable; 1: Enable.=0D + UINT32 RsvdBits : 30; ///< Reserved= =0D + /**=0D + The address of the upper limit of protection=0D + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be FFFh for limit comparison=0D + **/=0D + UINT16 ProtectedRangeLimit;=0D + /**=0D + The address of the upper limit of protection=0D + This is a left shifted address by 12 bits with address bits 11:0 are a= ssumed to be 0=0D + **/=0D + UINT16 ProtectedRangeBase;=0D +} PROTECTED_RANGE;=0D +=0D +/**=0D + The PCH provides a method for blocking writes and reads to specific rang= es=0D + in the SPI flash when the Protected Ranges are enabled.=0D + PROTECTED_RANGE is used to specify if flash protection are enabled,=0D + the write protection enable bit and the read protection enable bit,=0D + and to specify the upper limit and lower base for each register=0D + Platform code is responsible to get the range base by PchGetSpiRegionAdd= resses routine,=0D + and set the limit and base accordingly.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< C= onfig Block Header=0D + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES]; ///< P= rotected Flash Ranges=0D +} PCH_FLASH_PROTECTION_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _FLASH_PROTECTION_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Hsio= Config.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioCo= nfig.h new file mode 100644 index 0000000000..ec27845a48 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioConfig.h @@ -0,0 +1,57 @@ +/** @file=0D + HSIO policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HSIO_CONFIG_H_=0D +#define _HSIO_CONFIG_H_=0D +#define HSIO_PREMEM_CONFIG_REVISION 1 //@deprecated=0D +extern EFI_GUID gHsioPreMemConfigGuid; //@deprecated=0D +=0D +#define HSIO_CONFIG_REVISION 1=0D +extern EFI_GUID gHsioConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PCH_HSIO_PREMEM_CONFIG block provides HSIO message related settings.= =0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D +=0D + /**=0D + (Test)=0D + 0- Disable, disable will prevent the HSIO version check and ChipsetInit = HECI message from being sent=0D + 1- Enable ChipsetInit HECI message=0D + **/=0D + UINT8 ChipsetInitMessage;=0D + /**=0D + (Test)=0D + 0- Disable=0D + 1- Enable When enabled, this is used to bypass the reset after ChipsetIn= it HECI message.=0D + **/=0D + UINT8 BypassPhySyncReset;=0D + UINT8 RsvdBytes[2];=0D +=0D +} PCH_HSIO_PREMEM_CONFIG;=0D +=0D +=0D +/**=0D + The PCH_HSIO_CONFIG block provides HSIO message related settings.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header=0D + /**=0D + Policy used to point to the Base (+ OEM) ChipsetInit binary used to sy= nc between BIOS and CSME=0D + **/=0D + UINT32 ChipsetInitBinPtr;=0D + /**=0D + Policy used to indicate the size of the Base (+ OEM) ChipsetInit binar= y used to sync between BIOS and CSME=0D + **/=0D + UINT32 ChipsetInitBinLen;=0D +} PCH_HSIO_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _HSIO_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Hsio= PcieConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Hs= ioPcieConfig.h new file mode 100644 index 0000000000..bc23f3e1a6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioPcieCon= fig.h @@ -0,0 +1,58 @@ +/** @file=0D + HSIO pcie policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HSIO_PCIE_CONFIG_H_=0D +#define _HSIO_PCIE_CONFIG_H_=0D +=0D +#include =0D +=0D +#define HSIO_PCIE_PREMEM_CONFIG_REVISION 1=0D +extern EFI_GUID gHsioPciePreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PCH_HSIO_PCIE_LANE_CONFIG describes HSIO settings for PCIe lane=0D +**/=0D +typedef struct {=0D + //=0D + // HSIO Rx Eq=0D + // Refer to the EDS for recommended values.=0D + // Note that these setting are per-lane and not per-port=0D + //=0D + UINT32 HsioRxSetCtleEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 Set CTLE Value=0D + UINT32 HsioRxSetCtle : 6; ///< PCH PCIe Gen 3 Set = CTLE Value=0D + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output Downscale Amplitude Adjustment value ove= rride=0D + UINT32 HsioTxGen1DownscaleAmp : 6; ///< PCH PCIe Gen 1 TX O= utput Downscale Amplitude Adjustment value=0D + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output Downscale Amplitude Adjustment value ove= rride=0D + UINT32 HsioTxGen2DownscaleAmp : 6; ///< PCH PCIe Gen 2 TX O= utput Downscale Amplitude Adjustment value=0D + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 3 TX Output Downscale Amplitude Adjustment value ove= rride=0D + UINT32 HsioTxGen3DownscaleAmp : 6; ///< PCH PCIe Gen 3 TX O= utput Downscale Amplitude Adjustment value=0D + UINT32 RsvdBits0 : 4; ///< Reserved Bits=0D +=0D + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 1 TX Output De-Emphasis Adjustment Setting value ove= rride=0D + UINT32 HsioTxGen1DeEmph : 6; ///< PCH PCIe Gen 1 TX O= utput De-Emphasis Adjustment Setting=0D + UINT32 HsioTxGen2DeEmph3p5Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -3.5dB Mode De-Emphasis Adjustment Setti= ng value override=0D + UINT32 HsioTxGen2DeEmph3p5 : 6; ///< PCH PCIe Gen 2 TX O= utput -3.5dB Mode De-Emphasis Adjustment Setting=0D + UINT32 HsioTxGen2DeEmph6p0Enable : 1; ///< 0: Disable; = 1: Enable PCH PCIe Gen 2 TX Output -6.0dB Mode De-Emphasis Adjustment Setti= ng value override=0D + UINT32 HsioTxGen2DeEmph6p0 : 6; ///< PCH PCIe Gen 2 TX O= utput -6.0dB Mode De-Emphasis Adjustment Setting=0D + UINT32 RsvdBits1 : 11; ///< Reserved Bits=0D +} PCH_HSIO_PCIE_LANE_CONFIG;=0D +=0D +///=0D +/// The PCH_HSIO_PCIE_CONFIG block describes the configuration of the HSIO= for PCIe lanes=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + ///=0D + /// These members describe the configuration of HSIO for PCIe lanes.=0D + ///=0D + PCH_HSIO_PCIE_LANE_CONFIG Lane[PCH_MAX_PCIE_ROOT_PORTS];=0D +} PCH_HSIO_PCIE_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _HSIO_PCIE_LANE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Hsio= SataConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Hs= ioSataConfig.h new file mode 100644 index 0000000000..21b0d7ff63 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/HsioSataCon= fig.h @@ -0,0 +1,64 @@ +/** @file=0D + Hsio Sata policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _HSIO_SATA_CONFIG_H_=0D +#define _HSIO_SATA_CONFIG_H_=0D +=0D +#define HSIO_SATA_PREMEM_CONFIG_REVISION 1=0D +extern EFI_GUID gHsioSataPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PCH_HSIO_SATA_PORT_LANE describes HSIO settings for SATA Port lane=0D +**/=0D +typedef struct {=0D + //=0D + // HSIO Rx Eq=0D + //=0D + UINT32 HsioRxGen1EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override=0D + UINT32 HsioRxGen1EqBoostMag : 6; ///< SATA 1.5 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value=0D + UINT32 HsioRxGen2EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override=0D + UINT32 HsioRxGen2EqBoostMag : 6; ///< SATA 3.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value=0D + UINT32 HsioRxGen3EqBoostMagEnable : 1; ///< 0: Disable; = 1: Enable Receiver Equalization Boost Magnitude Adjustment Value override=0D + UINT32 HsioRxGen3EqBoostMag : 6; ///< SATA 6.0 Gb/sReceiv= er Equalization Boost Magnitude Adjustment value=0D + //=0D + // HSIO Tx Eq=0D + //=0D + UINT32 HsioTxGen1DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output Downscale Amplitude Adjustment value over= ride=0D + UINT32 HsioTxGen1DownscaleAmp : 6; ///< SATA 1.5 Gb/s TX Ou= tput Downscale Amplitude Adjustment value=0D + UINT32 RsvdBits0 : 4; ///< Reserved bits=0D +=0D + UINT32 HsioTxGen2DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride=0D + UINT32 HsioTxGen2DownscaleAmp : 6; ///< SATA 3.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment=0D + UINT32 HsioTxGen3DownscaleAmpEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output Downscale Amplitude Adjustment value over= ride=0D + UINT32 HsioTxGen3DownscaleAmp : 6; ///< SATA 6.0 Gb/s TX Ou= tput Downscale Amplitude Adjustment=0D + UINT32 HsioTxGen1DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 1.5 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride=0D + UINT32 HsioTxGen1DeEmph : 6; ///< SATA 1.5 Gb/s TX Ou= tput De-Emphasis Adjustment Setting=0D +=0D + UINT32 HsioTxGen2DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 3.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride=0D + UINT32 HsioTxGen2DeEmph : 6; ///< SATA 3.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting=0D + UINT32 RsvdBits1 : 4; ///< Reserved bits=0D +=0D + UINT32 HsioTxGen3DeEmphEnable : 1; ///< 0: Disable; = 1: Enable SATA 6.0 Gb/s TX Output De-Emphasis Adjustment Setting value over= ride=0D + UINT32 HsioTxGen3DeEmph : 6; ///< SATA 6.0 Gb/s TX Ou= tput De-Emphasis Adjustment Setting value override=0D + UINT32 RsvdBits2 : 25; ///< Reserved bits=0D +} PCH_HSIO_SATA_PORT_LANE;=0D +=0D +///=0D +/// The PCH_HSIO_SATA_CONFIG block describes the HSIO configuration of the= SATA controller.=0D +///=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + ///=0D + /// These members describe the configuration of HSIO for SATA lanes.=0D + ///=0D + PCH_HSIO_SATA_PORT_LANE PortLane[PCH_MAX_SATA_PORTS];=0D +} PCH_HSIO_SATA_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _HSIO_SATA_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Lock= DownConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/Lo= ckDownConfig.h new file mode 100644 index 0000000000..23f116cf3d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LockDownCon= fig.h @@ -0,0 +1,61 @@ +/** @file=0D + Lock down policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _LOCK_DOWN_CONFIG_H_=0D +#define _LOCK_DOWN_CONFIG_H_=0D +=0D +#define LOCK_DOWN_CONFIG_REVISION 1=0D +extern EFI_GUID gLockDownConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH=0D + for security requirement.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + (Test) Enable SMI_LOCK bit to prevent writes to the Global SMI = Enable bit. 0: Disable; 1: Enable.=0D + **/=0D + UINT32 GlobalSmi : 1;=0D + /**=0D + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register=0D + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps.=0D + Intel strongly recommends that BIOS sets the BIOS Interface Lock Down = bit. Enabling this bit=0D + will mitigate malicious software attempts to replace the system BIOS w= ith its own code.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 BiosInterface : 1;=0D + /**=0D + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5])=0D + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be=0D + modified from SMM.=0D + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be = '1' also=0D + in order to write to BIOS regions of SPI Flash. If this EISS bit is cl= ear,=0D + then the InSMM.STS is a don't care.=0D + The BIOS must set the EISS bit while BIOS Guard support is enabled.=0D + In recovery path, platform can temporary disable EISS for SPI programm= ing in=0D + PEI phase or early DXE phase.=0D + When PcdSmmVariableEnable is FALSE, to support BIOS regions update out= side of SMM,=0D + the BiosLock must be set to Disabled by platform.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 BiosLock : 1;=0D + /**=0D + (Test) This test option when set will force all GPIO pads to be= unlocked=0D + before BIOS transitions to POSTBOOT_SAI. This option should not be ena= bled in production=0D + configuration and used only for debug purpose when free runtime reconf= iguration of=0D + GPIO pads is needed.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 UnlockGpioPads : 1;=0D + UINT32 RsvdBits0 : 28; ///< Reserved bits=0D +} PCH_LOCK_DOWN_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _LOCK_DOWN_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcC= onfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConf= ig.h new file mode 100644 index 0000000000..3fc64aa056 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/LpcConfig.h @@ -0,0 +1,38 @@ +/** @file=0D + Lpc policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _LPC_CONFIG_H_=0D +#define _LPC_CONFIG_H_=0D +=0D +#define LPC_PREMEM_CONFIG_REVISION 1=0D +extern EFI_GUID gLpcPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure contains the policies which are related to LPC.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + Enhance the port 8xh decoding.=0D + Original LPC only decodes one byte of port 80h, with this enhancement = LPC can decode word or dword of port 80h-83h.=0D + @note: this will occupy one LPC generic IO range register. While this = is enabled, read from port 80h always return 0x00.=0D + 0: Disable, 1: Enable=0D + **/=0D + UINT32 EnhancePort8xhDecoding : 1;=0D + /**=0D + Hardware Autonomous Enable.=0D + When enabled, LPC will automatically engage power gating when it has re= ached its idle condition.=0D + 0: Disable, 1: Enable=0D + **/=0D + UINT32 LpcPmHAE : 1;=0D + UINT32 RsvdBits : 30; ///< Reserved bits=0D +} PCH_LPC_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _LPC_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchG= eneralConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/= PchGeneralConfig.h new file mode 100644 index 0000000000..da77abc1b3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/ConfigBlock/PchGeneralC= onfig.h @@ -0,0 +1,72 @@ +/** @file=0D + PCH General policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_GENERAL_CONFIG_H_=0D +#define _PCH_GENERAL_CONFIG_H_=0D +=0D +#define PCH_GENERAL_CONFIG_REVISION 1=0D +#define PCH_GENERAL_PREMEM_CONFIG_REVISION 2=0D +=0D +extern EFI_GUID gPchGeneralConfigGuid;=0D +extern EFI_GUID gPchGeneralPreMemConfigGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +enum PCH_RESERVED_PAGE_ROUTE {=0D + PchReservedPageToLpc, ///< Port 80h cycles are sent to= LPC.=0D + PchReservedPageToPcie ///< Port 80h cycles are sent to= PCIe.=0D +};=0D +=0D +/**=0D + PCH General Configuration=0D + Revision 1: - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + This member describes whether or not the Compatibility Revision ID (CR= ID) feature=0D + of PCH should be enabled. 0: Disable; 1: Enable=0D + **/=0D + UINT32 Crid : 1;=0D + /**=0D + Set to enable low latency of legacy IO.=0D + Some systems require lower IO latency irrespective of power.=0D + This is a tradeoff between power and IO latency.=0D + @note: Once this is enabled, DmiAspm, Pcie DmiAspm in SystemAgent=0D + and ITSS Clock Gating are forced to disabled.=0D + 0: Disable, 1: Enable=0D + **/=0D + UINT32 LegacyIoLowLatency : 1;=0D + UINT32 RsvdBits0 : 30; ///< Reserved bits=0D +} PCH_GENERAL_CONFIG;=0D +=0D +/**=0D + PCH General Pre-Memory Configuration=0D + Revision 1: - Initial version.=0D + Revision 2: - Added GpioOverride.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Config Block Header= =0D + /**=0D + Control where the Port 80h cycles are sent, 0: LPC; 1: PCI.=0D + **/=0D + UINT32 Port80Route : 1;=0D + UINT32 IotgPllSscEn : 1; ///< Need to disable CPU Side SSC = for A0 PO=0D + /**=0D + Gpio override Level=0D + -- 0: Disable;=0D + - 1: Override Level 1 - only skips GpioSetNativePadByFunction=0D + - 2: Override Level 2 - skips GpioSetNativePadByFunction and GpioSetP= adMode=0D + Additional policy that allows GPIO configuration to be done by externa= l means.=0D + If equal to 1 PCH will skip every Pad configuration.=0D + **/=0D + UINT32 GpioOverride : 3;=0D + UINT32 RsvdBits0 : 27; ///< Reserved bits=0D +} PCH_GENERAL_PREMEM_CONFIG;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PCH_GENERAL_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycle= DecodingLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCy= cleDecodingLib.h new file mode 100644 index 0000000000..94509a80fe --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchCycleDecodin= gLib.h @@ -0,0 +1,258 @@ +/** @file=0D + Header file for PchCycleDecodingLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_CYCLE_DECODING_LIB_H_=0D +#define _PCH_CYCLE_DECODING_LIB_H_=0D +=0D +=0D +/**=0D + Get PCH TCO base address.=0D +=0D + @param[out] Address Address of TCO base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid pointer passed.=0D +**/=0D +EFI_STATUS=0D +PchTcoBaseGet (=0D + OUT UINT16 *Address=0D + );=0D +=0D +///=0D +/// structure of LPC general IO range register=0D +/// It contains base address, address mask, and enable status.=0D +///=0D +typedef struct {=0D + UINT32 BaseAddr :16;=0D + UINT32 Length :15;=0D + UINT32 Enable : 1;=0D +} PCH_LPC_GEN_IO_RANGE;=0D +=0D +#define PCH_LPC_GEN_IO_RANGE_MAX 4=0D +#define ESPI_CS1_GEN_IO_RANGE_MAX 1=0D +=0D +///=0D +/// structure of LPC general IO range register list=0D +/// It lists all LPC general IO ran registers supported by PCH.=0D +///=0D +typedef struct {=0D + PCH_LPC_GEN_IO_RANGE Range[PCH_LPC_GEN_IO_RANGE_MAX];=0D +} PCH_LPC_GEN_IO_RANGE_LIST;=0D +=0D +/**=0D + Set PCH LPC/eSPI generic IO range.=0D + For generic IO range, the base address must align to 4 and less than 0xF= FFF, and the length must be power of 2=0D + and less than or equal to 256. Moreover, the address must be length alig= ned.=0D + This function basically checks the address and length, which should not = overlap with all other generic ranges.=0D + If no more generic range register available, it returns out of resource = error.=0D + This cycle decoding is also required on DMI side.=0D + Some IO ranges below 0x100 have fixed target. The target might be ITSS,R= TC,LPC,PMC or terminated inside P2SB=0D + but all predefined and can't be changed. IO range below 0x100 will be re= jected in this function except below ranges:=0D + 0x00-0x1F,=0D + 0x44-0x4B,=0D + 0x54-0x5F,=0D + 0x68-0x6F,=0D + 0x80-0x8F,=0D + 0xC0-0xFF=0D + Steps of programming generic IO range:=0D + 1. Program LPC/eSPI PCI Offset 84h ~ 93h of Mask, Address, and Enable.=0D + 2. Program LPC/eSPI Generic IO Range in DMI=0D +=0D + @param[in] Address Address for generic IO range base = address.=0D + @param[in] Length Length of generic IO range.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_OUT_OF_RESOURCES No more generic range available.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcGenIoRangeSet (=0D + IN UINT16 Address,=0D + IN UINTN Length=0D + );=0D +=0D +/**=0D + Set PCH LPC/eSPI memory range decoding.=0D + This cycle decoding is required to be set on DMI side=0D + Programming steps:=0D + 1. Program LPC PCI Offset 98h [0] to [0] to disable memory decoding firs= t before changing base address.=0D + 2. Program LPC PCI Offset 98h [31:16, 0] to [Address, 1].=0D + 3. Program LPC Memory Range in DMI=0D +=0D + @param[in] Address Address for memory base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_OUT_OF_RESOURCES No more generic range available.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcMemRangeSet (=0D + IN UINT32 Address=0D + );=0D +=0D +/**=0D + Set PCH eSPI CS1# memory range decoding.=0D + This cycle decoding is required to be set on DMI side=0D + Programming steps:=0D + 1. Program eSPI PCI Offset A8h (eSPI CS1#) [0] to [0] to disable memory = decoding first before changing base address.=0D + 2. Program eSPI PCI Offset A8h (eSPI CS1#) [31:16, 0] to [Address, 1].=0D + 3. Program eSPI Memory Range in DMI=0D +=0D + @param[in] Address Address for memory for decoding.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address or length pas= sed.=0D + @retval EFI_UNSUPPORTED eSPI secondary slave not supported= =0D +**/=0D +EFI_STATUS=0D +PchEspiCs1MemRangeSet (=0D + IN UINT32 Address=0D + );=0D +=0D +/**=0D + Get PCH LPC/eSPI memory range decoding address.=0D +=0D + @param[out] Address Address of LPC/eSPI memory decodin= g base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address passed.=0D +**/=0D +EFI_STATUS=0D +PchLpcMemRangeGet (=0D + OUT UINT32 *Address=0D + );=0D +=0D +/**=0D + Get PCH eSPI CS1# memory range decoding address.=0D +=0D + @param[out] Address Address of eSPI CS1# memory decodi= ng base address.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid base address passed.=0D + @retval EFI_UNSUPPORTED eSPI secondary slave not supported= =0D +**/=0D +EFI_STATUS=0D +PchEspiCs1MemRangeGet (=0D + OUT UINT32 *Address=0D + );=0D +=0D +/**=0D + Set PCH BIOS range deocding.=0D + This will check General Control and Status bit 10 (GCS.BBS) to identify = SPI or LPC/eSPI and program BDE register accordingly.=0D + Please check EDS for detail of BiosDecodeEnable bit definition.=0D + bit 15: F8-FF Enable=0D + bit 14: F0-F8 Enable=0D + bit 13: E8-EF Enable=0D + bit 12: E0-E8 Enable=0D + bit 11: D8-DF Enable=0D + bit 10: D0-D7 Enable=0D + bit 9: C8-CF Enable=0D + bit 8: C0-C7 Enable=0D + bit 7: Legacy F Segment Enable=0D + bit 6: Legacy E Segment Enable=0D + bit 5: Reserved=0D + bit 4: Reserved=0D + bit 3: 70-7F Enable=0D + bit 2: 60-6F Enable=0D + bit 1: 50-5F Enable=0D + bit 0: 40-4F Enable=0D + This cycle decoding is allowed to set when DMIC.SRL is 0.=0D + Programming steps:=0D + 1. if GCS.BBS is 0 (SPI), program SPI PCI offset D8h to BiosDecodeEnable= .=0D + if GCS.BBS is 1 (LPC/eSPi), program LPC/eSPI PCI offset D8h to BiosDe= codeEnable.=0D + 2. program LPC/eSPI/SPI BIOS Decode Enable, PCR[DMI] + 2744h to the same= value programmed in LPC/eSPI or SPI PCI Offset D8h.=0D +=0D + @param[in] BiosDecodeEnable Bios decode enable setting.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D +**/=0D +EFI_STATUS=0D +PchBiosDecodeEnableSet (=0D + IN UINT16 BiosDecodeEnable=0D + );=0D +=0D +/**=0D + Set PCH LPC IO decode ranges.=0D + Program LPC I/O Decode Ranges, PCR[DMI] + 2770h[15:0] to the same value = programmed in LPC offset 80h.=0D + Please check EDS for detail of Lpc IO decode ranges bit definition.=0D + Bit 12: FDD range=0D + Bit 9:8: LPT range=0D + Bit 6:4: ComB range=0D + Bit 2:0: ComA range=0D +=0D + @param[in] LpcIoDecodeRanges Lpc IO decode ranges bit settings.= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcIoDecodeRangesSet (=0D + IN UINT16 LpcIoDecodeRanges=0D + );=0D +=0D +/**=0D + Set PCH LPC and eSPI CS0# IO enable decoding.=0D + Setup I/O Enables in DMI to the same value program in LPC/eSPI PCI offse= t 82h.=0D + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field=0D + in LPC/eSPI PCI offset 82h[13:10] is always forwarded by DMI to subtract= ive agent for handling.=0D + Please check EDS for detail of LPC/eSPI IO decode ranges bit definition.= =0D +=0D + @param[in] LpcIoEnableDecoding LPC IO enable decoding bit setting= s.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMIC.SRL is set.=0D +**/=0D +EFI_STATUS=0D +PchLpcIoEnableDecodingSet (=0D + IN UINT16 LpcIoEnableDecoding=0D + );=0D +=0D +/**=0D + Set PCH eSPI CS1# IO enable decoding.=0D + Setup I/O Enables in DMI to the same value program in eSPI PCI offset A0= h (eSPI CS1#).=0D + Note: Bit[15:10] of the source decode register is Read-Only. The IO rang= e indicated by the Enables field=0D + in eSPI PCI offset A0h[13:10] is always forwarded by DMI to subtractive = agent for handling.=0D + Please check EDS for detail of eSPI IO decode ranges bit definition.=0D +=0D + @param[in] IoEnableDecoding eSPI IO enable decoding bit settin= gs.=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_UNSUPPORTED DMI configuration is locked=0D +**/=0D +EFI_STATUS=0D +PchEspiCs1IoEnableDecodingSet (=0D + IN UINT16 IoEnableDecoding=0D + );=0D +=0D +/**=0D + Get IO APIC regsiters base address.=0D +=0D + @param[out] IoApicBase Buffer of IO APIC regsiter address= =0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D +**/=0D +EFI_STATUS=0D +PchIoApicBaseGet (=0D + OUT UINT32 *IoApicBase=0D + );=0D +=0D +/**=0D + Get HPET base address.=0D + This function will be unavailable after P2SB is hidden by PSF.=0D +=0D + @param[out] HpetBase Buffer of HPET base address=0D +=0D + @retval EFI_SUCCESS Successfully completed.=0D + @retval EFI_INVALID_PARAMETER Invalid offset passed.=0D +**/=0D +EFI_STATUS=0D +PchHpetBaseGet (=0D + OUT UINT32 *HpetBase=0D + );=0D +=0D +#endif // _PCH_CYCLE_DECODING_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoL= ib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h new file mode 100644 index 0000000000..c8aee81a8b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchInfoLib.h @@ -0,0 +1,590 @@ +/** @file=0D + Header file for PchInfoLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_INFO_LIB_H_=0D +#define _PCH_INFO_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +typedef UINT8 PCH_STEPPING;=0D +=0D +typedef UINT8 PCH_SERIES;=0D +#define PCH_LP 2=0D +=0D +typedef UINT8 PCH_GENERATION;=0D +#define TGL_PCH 5=0D +=0D +typedef enum {=0D + RstUnsupported =3D 0,=0D + RstPremium,=0D + RstOptane,=0D + RstMaxMode=0D +} RST_MODE;=0D +=0D +/**=0D + Return Pch stepping type=0D +=0D + @retval PCH_STEPPING Pch stepping type=0D +**/=0D +PCH_STEPPING=0D +PchStepping (=0D + VOID=0D + );=0D +=0D +/**=0D + Return Pch Series=0D +=0D + @retval PCH_SERIES Pch Series=0D +**/=0D +PCH_SERIES=0D +PchSeries (=0D + VOID=0D + );=0D +=0D +/**=0D + Return Pch Generation=0D +=0D + @retval PCH_GENERATION Pch Generation=0D +**/=0D +PCH_GENERATION=0D +PchGeneration (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if this is TGL PCH generation=0D +=0D + @retval TRUE It's TGL PCH=0D + @retval FALSE It's not TGL PCH=0D +**/=0D +BOOLEAN=0D +IsTglPch (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Pcie Root Port Number=0D +=0D + @retval PcieMaxRootPort Pch Maximum Pcie Root Port Number=0D +**/=0D +UINT8=0D +GetPchMaxPciePortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Pcie Controller Number=0D +=0D + @retval Pch Maximum Pcie Controller Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieControllerNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Pcie Clock Number=0D +=0D + @retval Pch Maximum Pcie Clock Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieClockNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Pcie ClockReq Number=0D +=0D + @retval Pch Maximum Pcie ClockReq Number=0D +**/=0D +UINT8=0D +GetPchMaxPcieClockReqNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Usb2 Maximum Physical Port Number=0D +=0D + @retval Pch Usb2 Maximum Physical Port Number=0D +**/=0D +UINT8=0D +GetPchUsb2MaxPhysicalPortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Usb2 Port Number of XHCI Controller=0D +=0D + @retval Pch Maximum Usb2 Port Number of XHCI Controller=0D +**/=0D +UINT8=0D +GetPchXhciMaxUsb2PortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Usb3 Maximum Physical Port Number=0D +=0D + @retval Pch Usb3 Maximum Physical Port Number=0D +**/=0D +UINT8=0D +GetPchUsb3MaxPhysicalPortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Usb3 Port Number of XHCI Controller=0D +=0D + @retval Pch Maximum Usb3 Port Number of XHCI Controller=0D +**/=0D +UINT8=0D +GetPchXhciMaxUsb3PortNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Serial IO I2C controllers number=0D +=0D + @retval Pch Maximum Serial IO I2C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoI2cControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Serial IO SPI controllers number=0D +=0D + @retval Pch Maximum Serial IO SPI controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoSpiControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Serial IO UART controllers number=0D +=0D + @retval Pch Maximum Serial IO UART controllers number=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoUartControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Serial IO SPI Chip Selects count=0D +=0D + @retval Pch Maximum Serial IO SPI Chip Selects nu,ber=0D +**/=0D +UINT8=0D +GetPchMaxSerialIoSpiChipSelectsNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH UART Controller number=0D +=0D + @retval Pch Maximum ISH UART controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshUartControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH I2C Controller number=0D +=0D + @retval Pch Maximum ISH I2C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshI2cControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH I3C Controller number=0D +=0D + @retval Pch Maximum ISH I3C controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshI3cControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH SPI Controller number=0D +=0D + @retval Pch Maximum ISH SPI controllers number=0D +**/=0D +UINT8=0D +GetPchMaxIshSpiControllersNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH SPI Controller Cs pins number=0D +=0D + @retval Pch Maximum ISH SPI controller Cs pins number=0D +**/=0D +UINT8=0D +GetPchMaxIshSpiControllerCsPinsNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ISH GP number=0D +=0D + @retval Pch Maximum ISH GP number=0D +**/=0D +UINT8=0D +GetPchMaxIshGpNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum ME Applet count=0D +=0D + @retval Pch Maximum ME Applet number=0D +**/=0D +UINT8=0D +GetPchMaxMeAppletCount (=0D + VOID=0D + );=0D +=0D +/**=0D +Get Pch Maximum ME Session count=0D +=0D +@retval Pch Maximum ME Sesion number=0D +**/=0D +UINT8=0D +GetPchMaxMeSessionCount(=0D + VOID=0D +);=0D +=0D +/**=0D + Get Pch Maximum Type C Port Number=0D +=0D + @retval Pch Maximum Type C Port Number=0D +**/=0D +UINT8=0D +GetPchMaxTypeCPortNum (=0D + VOID=0D + );=0D +=0D +#define PCH_STEPPING_STR_LENGTH_MAX 3=0D +=0D +/**=0D + Get PCH stepping ASCII string.=0D + Function determines major and minor stepping versions and writes them in= to a buffer.=0D + The return string is zero terminated=0D +=0D + @param [out] Buffer Output buffer of string=0D + @param [in] BufferSize Buffer size.=0D + Must not be less then PCH_STEPPING= _STR_LENGTH_MAX=0D +=0D + @retval EFI_SUCCESS String copied successfully=0D + @retval EFI_INVALID_PARAMETER The stepping is not supported, or = parameters are NULL=0D + @retval EFI_BUFFER_TOO_SMALL Input buffer size is too small=0D +**/=0D +EFI_STATUS=0D +PchGetSteppingStr (=0D + OUT CHAR8 *Buffer,=0D + IN UINT32 BufferSize=0D + );=0D +=0D +/**=0D + Get PCH series ASCII string.=0D + The return string is zero terminated.=0D +=0D + @retval Static ASCII string of PCH Series=0D +**/=0D +CHAR8*=0D +PchGetSeriesStr (=0D + );=0D +=0D +/**=0D + Check if this chipset supports eMMC controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchEmmcSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if this chipset supports SD controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchSdCardSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if this chipset supports THC controller=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchThcSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if this chipset supports HSIO BIOS Sync=0D +=0D + @retval BOOLEAN TRUE if supported, FALSE otherwise=0D +**/=0D +BOOLEAN=0D +IsPchChipsetInitSyncSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Gets the maximum number of UFS controller supported by this chipset.=0D +=0D + @return Number of supported UFS controllers=0D +**/=0D +UINT8=0D +PchGetMaxUfsNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Check whether integrated LAN controller is supported.=0D +=0D + @retval TRUE GbE is supported in PCH=0D + @retval FALSE GbE is not supported by PCH=0D +**/=0D +BOOLEAN=0D +PchIsGbeSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check whether integrated TSN is supported.=0D +=0D + @retval TRUE TSN is supported in current PCH=0D + @retval FALSE TSN is not supported on current PCH=0D +**/=0D +BOOLEAN=0D +PchIsTsnSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check whether ISH is supported.=0D +=0D + @retval TRUE ISH is supported in PCH=0D + @retval FALSE ISH is not supported by PCH=0D +**/=0D +BOOLEAN=0D +PchIsIshSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check whether ATX Shutdown (PS_ON) is supported.=0D +=0D + @retval TRUE ATX Shutdown (PS_ON) is supported in PCH=0D + @retval FALSE ATX Shutdown (PS_ON) is not supported by PCH=0D +**/=0D +BOOLEAN=0D +IsPchPSOnSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Hda Sndw Link=0D +=0D + @retval Pch Maximum Hda Sndw Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxSndwLinkNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Hda Ssp Link=0D +=0D + @retval Pch Maximum Hda Ssp Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxSspLinkNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum Hda Dmic Link=0D +=0D + @retval Pch Maximum Hda Dmic Link=0D +**/=0D +UINT8=0D +GetPchHdaMaxDmicLinkNum (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if given Audio Interface is supported=0D +=0D + @param[in] AudioLinkType Link type support to be checked=0D + @param[in] AudioLinkIndex Link number=0D +=0D + @retval TRUE Link supported=0D + @retval FALSE Link not supported=0D +**/=0D +BOOLEAN=0D +IsAudioInterfaceSupported (=0D + IN HDAUDIO_LINK_TYPE AudioLinkType,=0D + IN UINT32 AudioLinkIndex=0D + );=0D +=0D +/**=0D + Check if given Display Audio Link T-Mode is supported=0D +=0D + @param[in] Tmode T-mode support to be checked=0D +=0D + @retval TRUE T-mode supported=0D + @retval FALSE T-mode not supported=0D +**/=0D +BOOLEAN=0D +IsAudioIDispTmodeSupported (=0D + IN HDAUDIO_IDISP_TMODE Tmode=0D + );=0D +=0D +/**=0D + Check if link between PCH and CPU is an P-DMI=0D +=0D + @retval TRUE P-DMI link=0D + @retval FALSE Not an P-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithPdmi (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if link between PCH and CPU is an OP-DMI=0D +=0D + @retval TRUE OP-DMI link=0D + @retval FALSE Not an OP-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithOpdmi (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if link between PCH and CPU is an F-DMI=0D +=0D + @retval TRUE F-DMI link=0D + @retval FALSE Not an F-DMI link=0D +**/=0D +BOOLEAN=0D +IsPchWithFdmi (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Pch Maximum THC count=0D +=0D + @retval Pch Maximum THC count number=0D +**/=0D +UINT8=0D +GetPchMaxThcCount (=0D + VOID=0D + );=0D +=0D +typedef enum {=0D + SataSosc125Mhz =3D 0,=0D + SataSosc120Mhz,=0D + SataSosc100Mhz,=0D + SataSosc25Mhz,=0D + SataSosc19p2Mhz,=0D + SataSoscUnsupported=0D +} SATA_SOSC_CLK_FREQ;=0D +=0D +/**=0D + Returns a frequency of the sosc_clk signal.=0D + All SATA controllers on the system are assumed to=0D + work on the same sosc_clk frequency.=0D +=0D + @retval Frequency of the sosc_clk signal.=0D +**/=0D +SATA_SOSC_CLK_FREQ=0D +GetSataSoscClkFreq (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if SATA support should be awake after function disable=0D +=0D + @retval TRUE=0D + @retval FALSE=0D +**/=0D +BOOLEAN=0D +IsSataSupportWakeAfterFunctionDisable (=0D + VOID=0D + );=0D +=0D +=0D +//=0D +// USB2 PHY reference frequencies values (MHz)=0D +//=0D +typedef enum {=0D + FREQ_19_2 =3D 0u,=0D + FREQ_24_0,=0D + FREQ_96_0,=0D + FREQ_MAX=0D +} USB2_PHY_REF_FREQ;=0D +=0D +/**=0D + Returns USB2 PHY Reference Clock frequency value used by PCH=0D + This defines what electrical tuning parameters shall be used=0D + during USB2 PHY initialization programming=0D +=0D + @retval Frequency reference clock for USB2 PHY=0D +**/=0D +USB2_PHY_REF_FREQ=0D +GetUsb2PhyRefFreq (=0D + VOID=0D + );=0D +=0D +/**=0D + return support status for P2SB PCR 20-bit addressing=0D +=0D + @retval TRUE=0D + @retval FALSE=0D +**/=0D +BOOLEAN=0D +IsP2sb20bPcrSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Check if SPI in a given PCH generation supports an Extended BIOS Range D= ecode=0D +=0D + @retval TRUE or FALSE if PCH supports Extended BIOS Range Decode=0D +**/=0D +BOOLEAN=0D +IsExtendedBiosRangeDecodeSupported (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns DMI target for current PCH SPI=0D +=0D + @retval PCH SPI DMI target=0D +**/=0D +UINT16=0D +GetPchSpiDmiTarget (=0D + VOID=0D + );=0D +#endif // _PCH_INFO_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBd= fLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib= .h new file mode 100644 index 0000000000..85456653de --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Library/PchPciBdfLib.h @@ -0,0 +1,552 @@ +/** @file=0D + Header file for PchPciBdfLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCI_BDF_LIB_H_=0D +#define _PCH_PCI_BDF_LIB_H_=0D +=0D +=0D +/**=0D + Get eSPI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval eSPI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +EspiPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get GbE controller address that can be passed to the PCI Segment Library= functions.=0D +=0D + @retval GbE controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +GbePciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Device Number=0D +=0D + @retval GbE device number=0D +**/=0D +UINT8=0D +GbeDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Gigabit Ethernet PCI Function Number=0D +=0D + @retval GbE function number=0D +**/=0D +UINT8=0D +GbeFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HDA controller address that can be passed to the PCI Segment Library= functions.=0D +=0D + @retval HDA controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +HdaPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HDA PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +HdaDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HDA PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +HdaFuncNumber (=0D + VOID=0D + );=0D +=0D +=0D +/**=0D + Get P2SB controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval P2SB controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +P2sbPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get P2SB PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +P2sbDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI PCI Config Space base address=0D +=0D + @retval UINT64 SPI Config Space base address=0D +**/=0D +UINT64=0D +SpiPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI Device number=0D +=0D + @retval UINT8 PCH SPI Device number=0D +**/=0D +UINT8=0D +SpiDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns SPI Function number=0D +=0D + @retval UINT8 PCH SPI Function number=0D +**/=0D +UINT8=0D +SpiFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XHCI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval XHCI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchXhciPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XHCI controller PCIe Device Number=0D +=0D + @retval XHCI controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchXhciDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XHCI controller PCIe Function Number=0D +=0D + @retval XHCI controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchXhciFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XDCI controller address that can be passed to the PCI Segment Librar= y functions.=0D +=0D + @retval XDCI controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchXdciPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XDCI controller PCIe Device Number=0D +=0D + @retval XDCI controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchXdciDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get XDCI controller PCIe Function Number=0D +=0D + @retval XDCI controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchXdciFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get SMBUS controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval SMBUS controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +SmbusPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Return DMA Smbus Device Number=0D +=0D + @retval DMA Smbus Device Number=0D +**/=0D +UINT8=0D +SmbusDmaDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Return DMA Smbus Function Number=0D +=0D + @retval DMA Smbus Function Number=0D +**/=0D +UINT8=0D +SmbusDmaFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get DMA SMBUS controller address that can be passed to the PCI Segment L= ibrary functions.=0D +=0D + @retval DMA SMBUS controller address in PCI Segment Library representati= on=0D +**/=0D +UINT64=0D +SmbusDmaPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Return Smbus Device Number=0D +=0D + @retval Smbus Device Number=0D +**/=0D +UINT8=0D +SmbusDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Return Smbus Function Number=0D +=0D + @retval Smbus Function Number=0D +**/=0D +UINT8=0D +SmbusFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Gets SATA controller PCIe config space base address=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller PCIe config space base address=0D +**/=0D +UINT64=0D +SataPciCfgBase (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Gets SATA controller PCIe Device Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller PCIe Device Number=0D +**/=0D +UINT8=0D +SataDevNumber (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Gets SATA controller PCIe Function Number=0D +=0D + @param[in] SataCtrlIndex SATA controller index=0D +=0D + @retval SATA controller PCIe Function Number=0D +**/=0D +UINT8=0D +SataFuncNumber (=0D + IN UINT32 SataCtrlIndex=0D + );=0D +=0D +/**=0D + Returns PCH LPC device PCI base address.=0D +=0D + @retval PCH LPC PCI base address.=0D +**/=0D +UINT64=0D +LpcPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get LPC controller PCIe Device Number=0D +=0D + @retval LPC controller PCIe Device Number=0D +**/=0D +UINT8=0D +LpcDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Thermal Device PCIe Device Number=0D +=0D + @retval Thermal Device PCIe Device Number=0D +**/=0D +UINT8=0D +ThermalDevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Thermal Device PCIe Function Number=0D +=0D + @retval Thermal Device PCIe Function Number=0D +**/=0D +UINT8=0D +ThermalFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Returns Thermal Device PCI base address.=0D +=0D + @retval Thermal Device PCI base address.=0D +**/=0D +UINT64=0D +ThermalPciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get LPC controller PCIe Function Number=0D +=0D + @retval LPC controller PCIe Function Number=0D +**/=0D +UINT8=0D +LpcFuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get Serial IO I2C controller PCIe Device Number=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoI2cDevNumber (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Get Serial IO I2C controller PCIe Function Number=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoI2cFuncNumber (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Get Serial IO I2C controller address that can be passed to the PCI Segme= nt Library functions.=0D +=0D + @param[in] I2cNumber Serial IO I2C controller index=0D +=0D + @retval Serial IO I2C controller address in PCI Segment Library represen= tation=0D +**/=0D +UINT64=0D +SerialIoI2cPciCfgBase (=0D + IN UINT8 I2cNumber=0D + );=0D +=0D +/**=0D + Get Serial IO SPI controller PCIe Device Number=0D +=0D + @param[in] I2cNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoSpiDevNumber (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Get Serial IO SPI controller PCIe Function Number=0D +=0D + @param[in] SpiNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoSpiFuncNumber (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Get Serial IO SPI controller address that can be passed to the PCI Segme= nt Library functions.=0D +=0D + @param[in] SpiNumber Serial IO SPI controller index=0D +=0D + @retval Serial IO SPI controller address in PCI Segment Library represen= tation=0D +**/=0D +UINT64=0D +SerialIoSpiPciCfgBase (=0D + IN UINT8 SpiNumber=0D + );=0D +=0D +/**=0D + Get Serial IO UART controller PCIe Device Number=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller PCIe Device Number=0D +**/=0D +UINT8=0D +SerialIoUartDevNumber (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Get Serial IO UART controller PCIe Function Number=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller PCIe Function Number=0D +**/=0D +UINT8=0D +SerialIoUartFuncNumber (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Get Serial IO UART controller address that can be passed to the PCI Segm= ent Library functions.=0D +=0D + @param[in] UartNumber Serial IO UART controller index=0D +=0D + @retval Serial IO UART controller address in PCI Segment Library represe= ntation=0D +**/=0D +UINT64=0D +SerialIoUartPciCfgBase (=0D + IN UINT8 UartNumber=0D + );=0D +=0D +/**=0D + Get PCH PCIe controller PCIe Device Number=0D +=0D + @param[in] RpIndex Root port physical number. (0-based)=0D +=0D + @retval PCH PCIe controller PCIe Device Number=0D +**/=0D +UINT8=0D +PchPcieRpDevNumber (=0D + IN UINTN RpIndex=0D + );=0D +=0D +/**=0D + Get PCH PCIe controller PCIe Function Number=0D +=0D + @param[in] RpIndex Root port physical number. (0-based)=0D +=0D + @retval PCH PCIe controller PCIe Function Number=0D +**/=0D +UINT8=0D +PchPcieRpFuncNumber (=0D + IN UINTN RpIndex=0D + );=0D +=0D +/**=0D + Get PCH PCIe controller address that can be passed to the PCI Segment Li= brary functions.=0D +=0D + @param[in] RpIndex PCH PCIe Root Port physical number. (0-based)= =0D +=0D + @retval PCH PCIe controller address in PCI Segment Library representatio= n=0D +**/=0D +UINT64=0D +PchPcieRpPciCfgBase (=0D + IN UINT32 RpIndex=0D + );=0D +=0D +/**=0D + Get HECI1 PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +PchHeci1DevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HECI1 PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +PchHeci1FuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HECI1 controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval HECI1 controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchHeci1PciCfgBase (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HECI3 PCI device number=0D +=0D + @retval PCI dev number=0D +**/=0D +UINT8=0D +PchHeci3DevNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HECI3 PCI function number=0D +=0D + @retval PCI fun number=0D +**/=0D +UINT8=0D +PchHeci3FuncNumber (=0D + VOID=0D + );=0D +=0D +/**=0D + Get HECI3 controller address that can be passed to the PCI Segment Libra= ry functions.=0D +=0D + @retval HECI3 controller address in PCI Segment Library representation=0D +**/=0D +UINT64=0D +PchHeci3PciCfgBase (=0D + VOID=0D + );=0D +=0D +#endif //_PCH_PCI_BDF_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h b/S= ilicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h new file mode 100644 index 0000000000..845bb19a65 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchInfoHob.h @@ -0,0 +1,70 @@ +/** @file=0D + This file contains definitions of PCH Info HOB.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_INFO_HOB_H_=0D +#define _PCH_INFO_HOB_H_=0D +=0D +extern EFI_GUID gPchInfoHobGuid;=0D +=0D +#define PCH_INFO_HOB_REVISION 4=0D +=0D +#pragma pack (push,1)=0D +/**=0D + This structure is used to provide the information of PCH controller.=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Add CridSupport, CridOrgRid, and CridNewRid.=0D + Revision 3:=0D + - Add Thc0Strap.=0D + Revision 4=0D + - Removed GbePciePortNumber=0D +**/=0D +typedef struct {=0D + /**=0D + This member specifies the revision of the PCH Info HOB. This field is = used=0D + to indicate backwards compatible changes to the protocol. Platform cod= e that=0D + consumes this protocol must read the correct revision value to correct= ly interpret=0D + the content of the protocol fields.=0D + **/=0D + UINT8 Revision;=0D + UINT8 PcieControllerCfg[6];=0D + /**=0D + THC strap disable/enable status=0D + **/=0D + UINT8 Thc0Strap;=0D + UINT32 PciePortFuses;=0D + /**=0D + Bit map for PCIe Root Port Lane setting. If bit is set it means that=0D + corresponding Root Port has its lane enabled.=0D + BIT0 - RP0, BIT1 - RP1, ...=0D + This information needs to be passed through HOB as FIA registers=0D + are not accessible with POSTBOOT_SAI=0D + **/=0D + UINT32 PciePortLaneEnabled;=0D + /**=0D + Publish Hpet BDF and IoApic BDF information for VTD.=0D + **/=0D + UINT32 HpetBusNum : 8;=0D + UINT32 HpetDevNum : 5;=0D + UINT32 HpetFuncNum : 3;=0D + UINT32 IoApicBusNum : 8;=0D + UINT32 IoApicDevNum : 5;=0D + UINT32 IoApicFuncNum : 3;=0D + /**=0D + Publish the CRID information.=0D + **/=0D + UINT32 CridOrgRid : 8;=0D + UINT32 CridNewRid : 8;=0D + UINT32 CridSupport : 1;=0D + UINT32 Rsvdbits : 15;=0D +} PCH_INFO_HOB;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PCH_INFO_HOB_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h b/Si= licon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h new file mode 100644 index 0000000000..04ad17c8bd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchLimits.h @@ -0,0 +1,67 @@ +/** @file=0D + Build time limits of PCH resources.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_LIMITS_H_=0D +#define _PCH_LIMITS_H_=0D +/*=0D + * Defines povided in this file are indended to be used only where static = value=0D + * is needed. They are set to values which allow to accomodate multiple pr= ojects=0D + * needs. Where runtime usage is possible please used dedicated functions = from=0D + * PchInfoLib to retrieve accurate values=0D + */=0D +=0D +//=0D +// PCIe limits=0D +//=0D +#define PCH_MAX_PCIE_ROOT_PORTS 24=0D +#define PCH_MAX_PCIE_CONTROLLERS 6=0D +=0D +//=0D +// PCIe clocks limits=0D +//=0D +#define PCH_MAX_PCIE_CLOCKS 16=0D +=0D +//=0D +// RST PCIe Storage Cycle Router limits=0D +//=0D +#define PCH_MAX_RST_PCIE_STORAGE_CR 3=0D +=0D +//=0D +// SATA limits=0D +//=0D +#define PCH_MAX_SATA_CONTROLLERS 3=0D +#define PCH_MAX_SATA_PORTS 8=0D +=0D +//=0D +// SerialIo limits=0D +//=0D +#define PCH_MAX_SERIALIO_I2C_CONTROLLERS 8=0D +#define PCH_MAX_SERIALIO_SPI_CONTROLLERS 7=0D +#define PCH_MAX_SERIALIO_SPI_CHIP_SELECTS 2=0D +#define PCH_MAX_SERIALIO_UART_CONTROLLERS 7=0D +=0D +//=0D +// ISH limits=0D +//=0D +#define PCH_MAX_ISH_GP_PINS 8=0D +#define PCH_MAX_ISH_UART_CONTROLLERS 2=0D +#define PCH_MAX_ISH_I2C_CONTROLLERS 3=0D +#define PCH_MAX_ISH_SPI_CONTROLLERS 1=0D +#define PCH_MAX_ISH_SPI_CS_PINS 1=0D +//=0D +// HDA limits=0D +//=0D +#define PCH_MAX_HDA_SDI 2=0D +#define PCH_MAX_HDA_SSP_LINK_NUM 6=0D +#define PCH_MAX_HDA_SNDW_LINK_NUM 4=0D +=0D +//=0D +// Number of eSPI slaves=0D +//=0D +#define PCH_MAX_ESPI_SLAVES 2=0D +=0D +#endif // _PCH_LIMITS_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.= h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h new file mode 100644 index 0000000000..7b749818fa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPolicyCommon.h @@ -0,0 +1,55 @@ +/** @file=0D + PCH configuration based on PCH policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_POLICY_COMMON_H_=0D +#define _PCH_POLICY_COMMON_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include "PchLimits.h"=0D +#include "ConfigBlock/PchGeneralConfig.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "ConfigBlock/FlashProtectionConfig.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "ConfigBlock/LockDownConfig.h"=0D +#include "P2sbConfig.h"=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#ifndef FORCE_ENABLE=0D +#define FORCE_ENABLE 1=0D +#endif=0D +#ifndef FORCE_DISABLE=0D +#define FORCE_DISABLE 2=0D +#endif=0D +#ifndef PLATFORM_POR=0D +#define PLATFORM_POR 0=0D +#endif=0D +=0D +=0D +#endif // _PCH_POLICY_COMMON_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyC= ommon.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyComm= on.h new file mode 100644 index 0000000000..25e99d3a68 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchPreMemPolicyCommon.h @@ -0,0 +1,56 @@ +/** @file=0D + PCH configuration based on PCH policy=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PREMEM_POLICY_COMMON_H_=0D +#define _PCH_PREMEM_POLICY_COMMON_H_=0D +=0D +#include =0D +=0D +#include "PchLimits.h"=0D +#include "ConfigBlock/PchGeneralConfig.h"=0D +#include =0D +#include =0D +#include =0D +#include "ConfigBlock/LpcConfig.h"=0D +#include "ConfigBlock/HsioPcieConfig.h"=0D +#include "ConfigBlock/HsioSataConfig.h"=0D +#include "ConfigBlock/HsioConfig.h"=0D +=0D +#pragma pack (push,1)=0D +=0D +#ifndef FORCE_ENABLE=0D +#define FORCE_ENABLE 1=0D +#endif=0D +#ifndef FORCE_DISABLE=0D +#define FORCE_DISABLE 2=0D +#endif=0D +#ifndef PLATFORM_POR=0D +#define PLATFORM_POR 0=0D +#endif=0D +=0D +/**=0D + PCH Policy revision number=0D + Any backwards compatible changes to this structure will result in an upd= ate in the revision number=0D +**/=0D +#define PCH_PREMEM_POLICY_REVISION 1=0D +=0D +/**=0D + PCH Policy PPI\n=0D + All PCH config block change history will be listed here\n\n=0D +=0D + - Revision 1:=0D + - Initial version.\n=0D +**/=0D +typedef struct _PCH_PREMEM_POLICY {=0D + CONFIG_BLOCK_TABLE_HEADER TableHeader;=0D +/*=0D + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock()=0D +*/=0D +} PCH_PREMEM_POLICY;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _PCH_PREMEM_POLICY_COMMON_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatform= Specific.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatform= Specific.h new file mode 100644 index 0000000000..4573a11520 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/PchResetPlatformSpecifi= c.h @@ -0,0 +1,21 @@ +/** @file=0D + PCH Reset Platform Specific definitions.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_RESET_PLATFORM_SPECIFIC_H_=0D +#define _PCH_RESET_PLATFORM_SPECIFIC_H_=0D +=0D +#define PCH_PLATFORM_SPECIFIC_RESET_STRING L"PCH_RESET"=0D +#define PCH_RESET_DATA_STRING_MAX_LENGTH (sizeof (PCH_PLATFORM_SPECIFI= C_RESET_STRING) / sizeof (UINT16))=0D +=0D +extern EFI_GUID gPchGlobalResetGuid;=0D +=0D +typedef struct _RESET_DATA {=0D + CHAR16 Description[PCH_RESET_DATA_STRING_MAX_LENGTH];=0D + EFI_GUID Guid;=0D +} PCH_RESET_DATA;=0D +=0D +#endif // _PCH_RESET_PLATFORM_SPECIFIC_H_=0D +=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapE= xDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrap= ExDispatch.h new file mode 100644 index 0000000000..4d6241c32b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/IoTrapExDispat= ch.h @@ -0,0 +1,184 @@ +/** @file=0D + PCH IO TrapEx Dispatch Protocol=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _IO_TRAP_EX_DISPATCH_H_=0D +#define _IO_TRAP_EX_DISPATCH_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gIoTrapExDispatchPro= tocolGuid;=0D +=0D +typedef struct _IO_TRAP_EX_DISPATCH_PROTOCOL IO_TRAP_EX_DISPATCH_= PROTOCOL;=0D +=0D +/**=0D + IO Trap Ex valid types=0D +**/=0D +typedef enum {=0D + IoTrapExTypeWrite,=0D + IoTrapExTypeRead,=0D + IoTrapExTypeReadWrite,=0D + IoTrapExTypeMaximum=0D +} IO_TRAP_EX_DISPATCH_TYPE;=0D +=0D +/**=0D + IO Trap Ex context structure containing information about the=0D + IO trap Ex event that should invoke the handler.=0D + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b for = any byte access.=0D +=0D + Here are some examples for the usage.=0D + 1. To trigger the TRAP for the IO address from 0x2000 to 0x20FF with BY= TE/WORD/DWORD read/write access:=0D + Address =3D 0x2000=0D + Length =3D 0x100=0D + Type =3D IoTrapExTypeReadWrite=0D + ByteEnable =3D 0x00 (BE is not matter)=0D + ByteEnableMask =3D 0x0F (BEM 0xF for any BYTE/WORD/DWORD access)=0D + 2. To trigger the TRAP for port 0x61 with BYTE read access:=0D + Address =3D 0x60=0D + Length =3D 4=0D + Type =3D IoTrapExTypeRead=0D + ByteEnable =3D 0x02 (BE is 0010b to trap only second byte of eve= ry DWORD)=0D + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit)=0D + 3. To trigger the TRAP for port 0x60 and 0x64 with BYTE write access:=0D + Address =3D 0x60=0D + Length =3D 8=0D + Type =3D IoTrapExTypeWrite=0D + ByteEnable =3D 0x01 (BE is 0001b to trap only first byte of ever= y DWORD)=0D + ByteEnableMask =3D 0x00 (BEM doesn't mask any BE bit)=0D +**/=0D +typedef struct {=0D + /**=0D + The Address must be dword alignment.=0D + **/=0D + UINT16 Address;=0D + UINT16 Length;=0D + IO_TRAP_EX_DISPATCH_TYPE Type;=0D + /**=0D + Bitmap to enable trap for each byte of every dword alignment address.= =0D + The Io Trap Address must be dword alignment for ByteEnable.=0D + E.g. 0001b for first byte, 0010b for second byte, 1100b for third and = fourth byte.=0D + **/=0D + UINT8 ByteEnable;=0D + /**=0D + ByteEnableMask bitwise to ignore the ByteEnable setting. E.g. 1111b fo= r any byte access.=0D + The Io Trap Address must be dword alignment for ByteEnableMask.=0D + **/=0D + UINT8 ByteEnableMask;=0D +} IO_TRAP_EX_REGISTER_CONTEXT;=0D +=0D +/**=0D + Callback function for an PCH IO TRAP EX handler dispatch.=0D +=0D + @param[in] Address DWord-aligned address of the trapp= ed cycle.=0D + @param[in] ByteEnable This is the DWord-aligned byte ena= bles associated with the trapped cycle.=0D + A 1 in any bit location indicates = that the corresponding byte is enabled in the cycle.=0D + @param[in] WriteCycle TRUE =3D Write cycle; FALSE =3D Re= ad cycle=0D + @param[in] WriteData DWord of I/O write data. This fiel= d is undefined after trapping a read cycle.=0D + The byte of WriteData is only vali= d if the corresponding bits in ByteEnable is 1.=0D + E.g.=0D + If ByteEnable is 0001b, then only = first byte of WriteData is valid.=0D + If ByteEnable is 0010b, then only = second byte of WriteData is valid.=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *IO_TRAP_EX_DISPATCH_CALLBACK) (=0D + IN UINT16 Address,=0D + IN UINT8 ByteEnable,=0D + IN BOOLEAN WriteCycle,=0D + IN UINT32 WriteData=0D + );=0D +=0D +/**=0D + Register a new IO Trap Ex SMI dispatch function.=0D + The caller will provide information of IO trap setting via the context.= =0D + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.=0D + This is the function to extend the IoTrap capability, and it's expected= =0D + to handle the special ByteEnable and ByteEnableMask setting.=0D + This register function will occupy one IoTrap register if possible.=0D + And it only support one handler for one IoTrap event.=0D + The Address of context MUST NOT be 0, and MUST be dword alignment.=0D + The Length of context MUST not less than 4, and MUST be power of 2.=0D + The ByteEnable and ByteEnableMask MUST not be zero at the same time.=0D + if the IO Trap handler is not used. It also enable the IO Trap Range to = generate=0D + SMI.=0D + Caller must take care of reserving the IO addresses in ACPI.=0D +=0D + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance.=0D + @param[in] DispatchFunction Pointer to dispatch function to be invok= ed for=0D + this SMI source.=0D + @param[in] RegisterContext Pointer to the dispatch function's conte= xt.=0D + The caller fills this context in before = calling=0D + the register function to indicate to the= register=0D + function the IO trap Ex SMI source for w= hich the dispatch=0D + function should be invoked. This MUST n= ot be NULL.=0D + @param[out] DispatchHandle Handle of dispatch function.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been successfu= lly=0D + registered and the SMI source has been e= nabled.=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources are available=0D + @retval EFI_INVALID_PARAMETER Address requested is already in use.=0D + @retval EFI_ACCESS_DENIED Return access denied if the SmmReadyToLo= ck event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *IO_TRAP_EX_DISPATCH_REGISTER) (=0D + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,=0D + IN IO_TRAP_EX_DISPATCH_CALLBACK DispatchFunction,=0D + IN IO_TRAP_EX_REGISTER_CONTEXT *RegisterContext,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + Unregister a SMI source dispatch function.=0D + This function is unsupported.=0D +=0D + @param[in] This Pointer to the IO_TRAP_EX_DISPATCH_PROTO= COL instance.=0D + @param[in] DispatchHandle Handle of dispatch function to deregiste= r.=0D +=0D + @retval EFI_UNSUPPORTED The function is unsupported.=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *IO_TRAP_EX_DISPATCH_UNREGISTER) (=0D + IN IO_TRAP_EX_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for the IO trap Extention protocol.=0D + This protocol exposes full IO TRAP capability for ByteEnable and ByteEna= bleMask setting.=0D + Platform code should fully control the ByteEnable and ByteEnableMake whi= le using this protocol.=0D +=0D + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.=0D + This is the function to extend the IoTrap capability, and it's expected= =0D + to handle the special ByteEnable and ByteEnableMask setting.=0D +=0D + The protocol is low level, It returns PSTH trapped cycle. This might not= be safe for multithread=0D + if more than one thread triggers the same IOTRAP at the same time.=0D +**/=0D +struct _IO_TRAP_EX_DISPATCH_PROTOCOL {=0D + /**=0D + Register function for PCH IO TRAP EX DISPATCH PROTOCOL.=0D + The caller will provide information of IO trap setting via the context= .=0D + Please consider to use EfiSmmIoTrapDispatch2Protocol as possible.=0D + This is the function to extend the IoTrap capability, and it's expecte= d=0D + to handle the special ByteEnable and ByteEnableMask setting.=0D + This register function will occupy one IoTrap register if possible.=0D + And it only support one handler for one IoTrap event.=0D + The Address of context MUST NOT be 0, and MUST be dword alignment.=0D + The Length of context MUST not less than 4, and MUST be power of 2.=0D + The ByteEnable and ByteEnableMask MUST not be zero at the same time.=0D + if the IO Trap handler is not used. It also enable the IO Trap Range t= o=0D + generate SMI.=0D + **/=0D + IO_TRAP_EX_DISPATCH_REGISTER Register;=0D + /**=0D + Unregister function for PCH IO TRAP EX DISPATCH PROTOCOL.=0D + **/=0D + IO_TRAP_EX_DISPATCH_UNREGISTER UnRegister;=0D +};=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpi= SmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchA= cpiSmiDispatch.h new file mode 100644 index 0000000000..136734d9ff --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchAcpiSmiDisp= atch.h @@ -0,0 +1,134 @@ +/** @file=0D + APIs of PCH ACPI SMI Dispatch Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_=0D +#define _PCH_ACPI_SMI_DISPATCH_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchAcpiSmiDispatchProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL PCH_ACPI_SMI_DISPATCH_PR= OTOCOL;=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + Callback function for an PCH ACPI SMI handler dispatch.=0D +=0D + @param[in] DispatchHandle The unique handle assigned to this= handler by register function.=0D +=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *PCH_ACPI_SMI_DISPATCH_CALLBACK) (=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Register a child SMI source dispatch function for PCH ACPI SMI events.=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for=0D + this SMI source=0D + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing=0D + with the parent SMM driver.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + registered and the SMI source has = been enabled.=0D + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source.=0D + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_ACPI_SMI_DISPATCH_REGISTER) (=0D + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,=0D + IN PCH_ACPI_SMI_DISPATCH_CALLBACK DispatchFunction,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + Unregister a child SMI source dispatch function with a parent ACPI SMM d= river=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchHandle Handle of dispatch function to der= egister.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + unregistered and the SMI source ha= s been disabled=0D + if there are no other registered c= hild dispatch=0D + functions for this SMI source.=0D + @retval EFI_INVALID_PARAMETER Handle is invalid.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_ACPI_SMI_DISPATCH_UNREGISTER) (=0D + IN PCH_ACPI_SMI_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for PCH ACPI SMIs Dispatch Protocol=0D + The PCH ACPI SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH ACPI related SMIs.=0D + It contains SMI types of Pme, RtcAlarm, PmeB0, and Time overflow.=0D +**/=0D +struct _PCH_ACPI_SMI_DISPATCH_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + /**=0D + Smi unregister function for PCH ACPI SMI DISPATCH PROTOCOL.=0D + **/=0D + PCH_ACPI_SMI_DISPATCH_UNREGISTER UnRegister;=0D + /**=0D + Pme=0D + The event is triggered by hardware when the PME# signal goes active.=0D + Additionally, the event is only triggered when SCI_EN is not set.=0D + **/=0D + PCH_ACPI_SMI_DISPATCH_REGISTER PmeRegister;=0D + /**=0D + PmeB0=0D + The event is triggered PCH when any internal device with PCI Power Man= agement=0D + capabilities on bus 0 asserts the equivalent of the PME# signal.=0D + Additionally, the event is only triggered when SCI_EN is not set.=0D + The following are internal devices which can set this bit:=0D + Intel HD Audio, Intel Management Engine "maskable" wake events, Integr= ated LAN,=0D + SATA, xHCI, Intel SST=0D + **/=0D + PCH_ACPI_SMI_DISPATCH_REGISTER PmeB0Register;=0D + /**=0D + RtcAlarm=0D + The event is triggered by hardware when the RTC generates an alarm=0D + (assertion of the IRQ8# signal).=0D + **/=0D + PCH_ACPI_SMI_DISPATCH_REGISTER RtcAlarmRegister;=0D + /**=0D + TmrOverflow=0D + The event is triggered any time bit 22 of the 24-bit timer goes high=0D + (bits are numbered from 0 to 23).=0D + This will occur every 2.3435 seconds. When the TMROF_EN bit (ABASE + 0= 2h, bit 0) is set,=0D + then the setting of the TMROF_STS bit will additionally generate an SM= I#=0D + Additionally, the event is only triggered when SCI_EN is not set.=0D + **/=0D + PCH_ACPI_SMI_DISPATCH_REGISTER TmrOverflowRegister;=0D +};=0D +=0D +/**=0D + PCH ACPI SMI dispatch revision number=0D +=0D + Revision 1: Initial version=0D +**/=0D +#define PCH_ACPI_SMI_DISPATCH_REVISION 1=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspi= SmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchE= spiSmiDispatch.h new file mode 100644 index 0000000000..4ea48c3fcd --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchEspiSmiDisp= atch.h @@ -0,0 +1,144 @@ +/** @file=0D + SmmEspiDispatch Protocol=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_=0D +#define _PCH_ESPI_SMI_DISPATCH_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchEspiSmiDispatchProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL PCH_ESPI_SMI_DISPATCH_PROTO= COL;=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + Callback function for an PCH eSPI SMI handler dispatch.=0D +=0D + @param[in] DispatchHandle The unique handle assigned to this= handler by register function.=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *PCH_ESPI_SMI_DISPATCH_CALLBACK) (=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Generic function to register different types of eSPI SMI types=0D +=0D + @param[in] This Not used=0D + @param[in] DispatchFunction The callback to execute=0D + @param[out] DispatchHandle The handle for this callback registration= =0D +=0D + @retval EFI_SUCCESS Registration successful=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfDxe event= has been triggered=0D + @retval others Registration failed=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_ESPI_SMI_REGISTER) (=0D + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,=0D + IN PCH_ESPI_SMI_DISPATCH_CALLBACK DispatchFunction,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + eSPI SMI Dispatch Protocol instance to unregister a callback based on ha= ndle=0D +=0D + @param[in] This Not used=0D + @param[in] DispatchHandle Handle acquired during registration= =0D +=0D + @retval EFI_SUCCESS Unregister successful=0D + @retval EFI_INVALID_PARAMETER DispatchHandle is null=0D + @retval EFI_INVALID_PARAMETER DispatchHandle's forward link has ba= d pointer=0D + @retval EFI_INVALID_PARAMETER DispatchHandle does not exist in dat= abase=0D + @retval EFI_ACCESS_DENIED Unregistration is done after end of = DXE=0D +**/=0D +=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_ESPI_SMI_UNREGISTER) (=0D + IN PCH_ESPI_SMI_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for PCH eSPI SMIs Dispatch Protocol=0D + The PCH ESPI SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH eSPI related SMIs.=0D + It contains SMI types of BiosWr, EcAssertedVw, and eSPI Master asserted = SMIs=0D +**/=0D +struct _PCH_ESPI_SMI_DISPATCH_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + /**=0D + Unregister eSPI SMI events=0D + **/=0D + PCH_ESPI_SMI_UNREGISTER UnRegister;=0D + /**=0D + Register a BIOS Write Protect event=0D + **/=0D + PCH_ESPI_SMI_REGISTER BiosWrProtectRegister;=0D + /**=0D + Register a BIOS Write Report event=0D + **/=0D + PCH_ESPI_SMI_REGISTER BiosWrReportRegister;=0D + /**=0D + Register a Peripheral Channel Non Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER PcErrNonFatalRegister;=0D + /**=0D + Register a Peripheral Channel Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER PcErrFatalRegister;=0D + /**=0D + Register a Virtual Wire Non Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER VwErrNonFatalRegister;=0D + /**=0D + Register a Virtual Wire Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER VwErrFatalRegister;=0D + /**=0D + Register a Flash Channel Non Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER FlashErrNonFatalRegister;=0D + /**=0D + Register a Flash Channel Fatal Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER FlashErrFatalRegister;=0D + /**=0D + Register a Link Error event=0D + **/=0D + PCH_ESPI_SMI_REGISTER LnkErrType1Register;=0D + /**=0D + Register a SMI handler for Espi slaver=0D + This routine will also lock down ESPI_SMI_LOCK bit after registration = and prevent=0D + this handler from unregistration.=0D + On platform that supports more than 1 device through another chip sele= ct (SPT-H),=0D + the SMI handler itself needs to inspect both the eSPI devices' interru= pt status registers=0D + (implementation specific for each Slave) in order to identify and serv= ice the cause.=0D + After servicing it, it has to clear the Slaves' internal SMI# status r= egisters=0D + **/=0D + PCH_ESPI_SMI_REGISTER EspiSlaveSmiRegister;=0D +};=0D +=0D +/**=0D + PCH ESPI SMI dispatch revision number=0D +=0D + Revision 1: Initial version=0D +**/=0D +#define PCH_ESPI_SMI_DISPATCH_REVISION 1=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcie= SmiDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchP= cieSmiDispatch.h new file mode 100644 index 0000000000..b75b9ab45d --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPcieSmiDisp= atch.h @@ -0,0 +1,166 @@ +/** @file=0D + APIs of PCH PCIE SMI Dispatch Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_=0D +#define _PCH_PCIE_SMI_DISPATCH_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchPcieSmiDispatchProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL PCH_PCIE_SMI_DISPATCH_PR= OTOCOL;=0D +=0D +typedef enum {=0D + PchRpIndex0 =3D 0,=0D + PchRpIndex1 =3D 1,=0D + PchRpIndex2 =3D 2,=0D + PchRpIndex3 =3D 3,=0D + PchRpIndex4 =3D 4,=0D + PchRpIndex5 =3D 5,=0D + PchRpIndex6 =3D 6,=0D + PchRpIndex7 =3D 7,=0D + PchRpIndex8 =3D 8,=0D + PchRpIndex9 =3D 9,=0D + PchRpIndex10 =3D 10,=0D + PchRpIndex11 =3D 11,=0D + PchRpIndex12 =3D 12,=0D + PchRpIndex13 =3D 13,=0D + PchRpIndex14 =3D 14,=0D + PchRpIndex15 =3D 15,=0D + PchRpIndex16 =3D 16,=0D + PchRpIndex17 =3D 17,=0D + PchRpIndex18 =3D 18,=0D + PchRpIndex19 =3D 19,=0D + PchRpIndex20 =3D 20,=0D + PchRpIndex21 =3D 21,=0D + PchRpIndex22 =3D 22,=0D + PchRpIndex23 =3D 23,=0D + /**=0D + Quantity of PCH and CPU PCIe ports, as well as their encoding in this = enum, may change between=0D + silicon generations and series. Do not assume that PCH port 0 will be = always encoded by 0.=0D + Instead, it is recommended to use (PchRpIndex0 + PchPortIndex) style t= o be forward-compatible=0D + **/=0D + CpuRpIndex0 =3D 0x40,=0D + CpuRpIndex1 =3D 0x41,=0D + CpuRpIndex2 =3D 0x42,=0D + CpuRpIndex3 =3D 0x43=0D +} PCIE_COMBINED_RPINDEX;=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +typedef struct {=0D + UINT8 RpIndex; ///< Root port index (0-b= ased), 0: RP1, 1: RP2, n: RP(N+1)=0D + UINT8 BusNum; ///< Root port pci bus nu= mber=0D + UINT8 DevNum; ///< Root port pci device= number=0D + UINT8 FuncNum; ///< Root port pci functi= on number=0D +} PCH_PCIE_SMI_RP_CONTEXT;=0D +=0D +/**=0D + Callback function for an PCH PCIE RP SMI handler dispatch.=0D +=0D + @param[in] DispatchHandle The unique handle assigned to this= handler by register function.=0D + @param[in] RpContext Pointer of PCH PCIE Root Port cont= ext.=0D +=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_CALLBACK) (=0D + IN EFI_HANDLE DispatchHandle,=0D + IN PCH_PCIE_SMI_RP_CONTEXT *RpContext=0D + );=0D +=0D +/**=0D + Register a child SMI source dispatch function for PCH PCIERP SMI events.= =0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for=0D + this SMI source=0D + @param[in] RpIndex Refer PCIE_COMBINED_RPINDEX for PC= H RP index and CPU RP index.=0D + 0: RP1, 1: RP2, n: RP(N+1)=0D + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing=0D + with the parent SMM driver.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + registered and the SMI source has = been enabled.=0D + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source.=0D + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_PCIE_SMI_RP_DISPATCH_REGISTER) (=0D + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,=0D + IN PCH_PCIE_SMI_RP_DISPATCH_CALLBACK DispatchFunction,=0D + IN UINTN RpIndex,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + Unregister a child SMI source dispatch function with a parent PCIE SMM d= river=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchHandle Handle of dispatch function to der= egister.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + unregistered and the SMI source ha= s been disabled=0D + if there are no other registered c= hild dispatch=0D + functions for this SMI source.=0D + @retval EFI_INVALID_PARAMETER Handle is invalid.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_PCIE_SMI_DISPATCH_UNREGISTER) (=0D + IN PCH_PCIE_SMI_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for PCH PCIE SMIs Dispatch Protocol=0D + The PCH PCIE SMI DISPATCH PROTOCOL provides the ability to dispatch func= tion for PCH PCIE related SMIs.=0D + It contains SMI types of HotPlug, LinkActive, and Link EQ.=0D +**/=0D +struct _PCH_PCIE_SMI_DISPATCH_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + /**=0D + Smi unregister function for PCH PCIE SMI DISPATCH PROTOCOL.=0D + **/=0D + PCH_PCIE_SMI_DISPATCH_UNREGISTER UnRegister;=0D + /**=0D + PcieRpXHotPlug=0D + The event is triggered when PCIE root port Hot-Plug Presence Detect.=0D + **/=0D + PCH_PCIE_SMI_RP_DISPATCH_REGISTER HotPlugRegister;=0D + /**=0D + PcieRpXLinkActive=0D + The event is triggered when Hot-Plug Link Active State Changed.=0D + **/=0D + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkActiveRegister;=0D + /**=0D + PcieRpXLinkEq=0D + The event is triggered when Device Requests Software Link Equalization= .=0D + **/=0D + PCH_PCIE_SMI_RP_DISPATCH_REGISTER LinkEqRegister;=0D +};=0D +=0D +/**=0D + PCH PCIE SMI dispatch revision number=0D +=0D + Revision 1: Initial version=0D +**/=0D +#define PCH_PCIE_SMI_DISPATCH_REVISION 1=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPoli= cy.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h new file mode 100644 index 0000000000..ba7cbdb23e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchPolicy.h @@ -0,0 +1,40 @@ +/** @file=0D + Interface definition details between Pch and platform drivers during DXE= phase.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_POLICY_H_=0D +#define _PCH_POLICY_H_=0D +=0D +#include =0D +#include =0D +#include "../IncludePrivate/PchConfigHob.h" // To Be corrected=0D +#include =0D +=0D +extern EFI_GUID gPchPolicyProtocolGuid;=0D +=0D +#define PCH_POLICY_PROTOCOL_REVISION 1=0D +=0D +=0D +/**=0D + PCH DXE Policy=0D +=0D + The PCH_POLICY_PROTOCOL producer drvier is recommended to=0D + set all the PCH_POLICY_PROTOCOL size buffer zero before init any member = parameter,=0D + this clear step can make sure no random value for those unknown new vers= ion parameters.=0D +=0D + Make sure to update the Revision if any change to the protocol, includin= g the existing=0D + internal structure definations.\n=0D + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_TABLE_HEADER TableHeader;=0D +/*=0D + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock()=0D +*/=0D +} PCH_POLICY_PROTOCOL;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiD= ispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDi= spatch.h new file mode 100644 index 0000000000..12b5f8117b --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmiDispatch= .h @@ -0,0 +1,132 @@ +/** @file=0D + APIs of PCH SMI Dispatch Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_SMI_DISPATCH_PROTOCOL_H_=0D +#define _PCH_SMI_DISPATCH_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchSmiDispatchProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_SMI_DISPATCH_PROTOCOL PCH_SMI_DISPATCH_PROTOCO= L;=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + Callback function for an PCH SMI handler dispatch.=0D +=0D + @param[in] DispatchHandle The unique handle assigned to this= handler by register function.=0D +=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *PCH_SMI_DISPATCH_CALLBACK) (=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Register a child SMI source dispatch function for specific PCH SMI dispa= tch event.=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for=0D + this SMI source=0D + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing=0D + with the parent SMM driver.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + registered and the SMI source has = been enabled.=0D + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source.=0D + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SMI_DISPATCH_REGISTER) (=0D + IN PCH_SMI_DISPATCH_PROTOCOL *This,=0D + IN PCH_SMI_DISPATCH_CALLBACK DispatchFunction,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + Unregister a child SMI source dispatch function with a parent SMM driver= =0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchHandle Handle of dispatch function to der= egister.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + unregistered and the SMI source ha= s been disabled=0D + if there are no other registered c= hild dispatch=0D + functions for this SMI source.=0D + @retval EFI_INVALID_PARAMETER Handle is invalid.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SMI_DISPATCH_UNREGISTER) (=0D + IN PCH_SMI_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for PCH specific SMIs Dispatch Protocol=0D + The PCH SMI DISPATCH PROTOCOL provides the ability to dispatch function = for PCH misc SMIs.=0D + It contains legacy SMIs and new PCH SMI types like:=0D + SerialIrq, McSmi, Smbus, ...=0D +**/=0D +struct _PCH_SMI_DISPATCH_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + /**=0D + Smi unregister function for PCH SMI DISPATCH PROTOCOL.=0D + **/=0D + PCH_SMI_DISPATCH_UNREGISTER UnRegister;=0D + /**=0D + SerialIrq=0D + The event is triggered while the SMI# was caused by the SERIRQ decoder= .=0D + **/=0D + PCH_SMI_DISPATCH_REGISTER SerialIrqRegister;=0D + /**=0D + McSmi=0D + The event is triggered if there has been an access to the power manage= ment=0D + microcontroller range (62h or 66h) and the Microcontroller Decode Enab= le #1 bit=0D + in the LPC Bridge I/O Enables configuration register is 1 .=0D + **/=0D + PCH_SMI_DISPATCH_REGISTER McSmiRegister;=0D + /**=0D + SmBus=0D + The event is triggered while the SMI# was caused by:=0D + 1. The SMBus Slave receiving a message that an SMI# should be caused, = or=0D + 2. The SMBALERT# signal goes active and the SMB_SMI_EN bit is set and = the=0D + SMBALERT_DIS bit is cleared, or=0D + 3. The SMBus Slave receiving a Host Notify message and the HOST_NOTIFY= _INTREN and=0D + the SMB_SMI_EN bits are set, or=0D + 4. The PCH detecting the SMLINK_SLAVE_SMI command while in the S0 stat= e.=0D + **/=0D + PCH_SMI_DISPATCH_REGISTER SmbusRegister;=0D + /**=0D + SPI Asynchronous=0D + When registered, the flash controller will generate an SMI when it blo= cks a BIOS write or erase.=0D + **/=0D + PCH_SMI_DISPATCH_REGISTER SpiAsyncRegister;=0D +};=0D +=0D +/**=0D + PCH SMI dispatch revision number=0D +=0D + Revision 1: Initial version=0D +**/=0D +#define PCH_SMI_DISPATCH_REVISION 1=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmI= oTrapControl.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/Pch= SmmIoTrapControl.h new file mode 100644 index 0000000000..9f2793634e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmIoTrapCo= ntrol.h @@ -0,0 +1,65 @@ +/** @file=0D + PCH SMM IO Trap Control Protocol=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_SMM_IO_TRAP_CONTROL_H_=0D +#define _PCH_SMM_IO_TRAP_CONTROL_H_=0D +=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchSmmIoTrapControlGuid= ;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL PCH_SMM_IO_TRAP_CONTROL_= PROTOCOL;=0D +=0D +//=0D +// Related Definitions=0D +//=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + The Prototype of Pause and Resume IoTrap callback function.=0D +=0D + @param[in] This Pointer to the PCH_SMM_IO_TRAP_CONTROL_P= ROTOCOL instance.=0D + @param[in] DispatchHandle Handle of the child service to change st= ate.=0D +=0D + @retval EFI_SUCCESS This operation is complete.=0D + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.=0D + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RESUMED.= =0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SMM_IO_TRAP_CONTROL_FUNCTION) (=0D + IN PCH_SMM_IO_TRAP_CONTROL_PROTOCOL * This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for the SMM IO trap pause and resume protocol=0D + This protocol provides the functions to runtime control the IoTrap SMI e= nabled/disable.=0D + This applys the capability to the DispatchHandle which returned by IoTra= p callback=0D + registration, and the DispatchHandle which must be MergeDisable =3D TRUE= and Address !=3D 0.=0D + Besides, when S3 resuem, it only restores the state of IoTrap callback r= egistration.=0D + The Paused/Resume state won't be restored after S3 resume.=0D +**/=0D +struct _PCH_SMM_IO_TRAP_CONTROL_PROTOCOL {=0D + /**=0D + This runtime pauses a registered IoTrap handler.=0D + **/=0D + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Pause;=0D + /**=0D + This runtime resumes a registered IoTrap handler.=0D + **/=0D + PCH_SMM_IO_TRAP_CONTROL_FUNCTION Resume;=0D +};=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmP= eriodicTimerControl.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Proto= col/PchSmmPeriodicTimerControl.h new file mode 100644 index 0000000000..a7b44c5f7e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchSmmPeriodic= TimerControl.h @@ -0,0 +1,65 @@ +/** @file=0D + PCH SMM Periodic Timer Control Protocol=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_SMM_PERIODIC_TIMER_CONTROL_H_=0D +#define _PCH_SMM_PERIODIC_TIMER_CONTROL_H_=0D +=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchSmmPeriodi= cTimerControlGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL PCH_SMM_PERIOD= IC_TIMER_CONTROL_PROTOCOL;=0D +=0D +//=0D +// Related Definitions=0D +//=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + The Prototype of Pause and Resume SMM PERIODIC TIMER function.=0D +=0D + @param[in] This Pointer to the PCH_SMM_PERIODIC_TI= MER_CONTROL_PROTOCOL instance.=0D + @param[in] DispatchHandle Handle of the child service to cha= nge state.=0D +=0D + @retval EFI_SUCCESS This operation is complete.=0D + @retval EFI_INVALID_PARAMETER The DispatchHandle is invalid.=0D + @retval EFI_ACCESS_DENIED The SMI status is alrady PAUSED/RE= SUMED.=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION) (=0D + IN PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for the SMM PERIODIC TIMER pause and resume protocol= =0D + This protocol provides the functions to runtime control the SM periodic = timer enabled/disable.=0D + This applies the capability to the DispatchHandle which returned by SMM = periodic timer callback=0D + registration.=0D + Besides, when S3 resume, it only restores the state of callback registra= tion.=0D + The Paused/Resume state won't be restored after S3 resume.=0D +**/=0D +struct _PCH_SMM_PERIODIC_TIMER_CONTROL_PROTOCOL {=0D + /**=0D + This runtime pauses the registered periodic timer handler.=0D + **/=0D + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Pause;=0D + /**=0D + This runtime resumes the registered periodic timer handler.=0D + **/=0D + PCH_SMM_PERIODIC_TIMER_CONTROL_FUNCTION Resume;=0D +};=0D +=0D +#endif // _PCH_SMM_PERIODIC_TIMER_CONTROL_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoS= miDispatch.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTc= oSmiDispatch.h new file mode 100644 index 0000000000..b443484f39 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Protocol/PchTcoSmiDispa= tch.h @@ -0,0 +1,150 @@ +/** @file=0D + APIs of PCH TCO SMI Dispatch Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_=0D +#define _PCH_TCO_SMI_DISPATCH_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchTcoSmiDispatchProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_TCO_SMI_DISPATCH_PROTOCOL PCH_TCO_SMI_DISPATCH_PRO= TOCOL;=0D +=0D +//=0D +// Member functions=0D +//=0D +=0D +/**=0D + Callback function for an PCH TCO SMI handler dispatch.=0D +=0D + @param[in] DispatchHandle The unique handle assigned to this= handler by register function.=0D +=0D +**/=0D +typedef=0D +VOID=0D +(EFIAPI *PCH_TCO_SMI_DISPATCH_CALLBACK) (=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Register a child SMI source dispatch function for PCH TCO SMI events.=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchFunction Pointer to dispatch function to be= invoked for=0D + this SMI source=0D + @param[out] DispatchHandle Handle of dispatch function, for w= hen interfacing=0D + with the parent SMM driver.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + registered and the SMI source has = been enabled.=0D + @retval EFI_DEVICE_ERROR The driver was unable to enable th= e SMI source.=0D + @retval EFI_OUT_OF_RESOURCES Not enough memory (system or SMM) = to manage this child.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_TCO_SMI_DISPATCH_REGISTER) (=0D + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,=0D + IN PCH_TCO_SMI_DISPATCH_CALLBACK DispatchFunction,=0D + OUT EFI_HANDLE *DispatchHandle=0D + );=0D +=0D +/**=0D + Unregister a child SMI source dispatch function with a parent TCO SMM dr= iver=0D +=0D + @param[in] This Protocol instance pointer.=0D + @param[in] DispatchHandle Handle of dispatch function to der= egister.=0D +=0D + @retval EFI_SUCCESS The dispatch function has been suc= cessfully=0D + unregistered and the SMI source ha= s been disabled=0D + if there are no other registered c= hild dispatch=0D + functions for this SMI source.=0D + @retval EFI_INVALID_PARAMETER Handle is invalid.=0D + @retval EFI_ACCESS_DENIED Return access denied if the EndOfD= xe event has been triggered=0D +**/=0D +typedef=0D +EFI_STATUS=0D +(EFIAPI *PCH_TCO_SMI_DISPATCH_UNREGISTER) (=0D + IN PCH_TCO_SMI_DISPATCH_PROTOCOL *This,=0D + IN EFI_HANDLE DispatchHandle=0D + );=0D +=0D +/**=0D + Interface structure for PCH TCO SMIs Dispatch Protocol=0D + The PCH TCO SMI DISPATCH PROTOCOL provides the ability to dispatch funct= ion for PCH TCO related SMIs.=0D + It contains SMI types of Mch, TcoTimeout, OsTco, Nmi, IntruderDectect, a= nd BiowWp.=0D +**/=0D +struct _PCH_TCO_SMI_DISPATCH_PROTOCOL {=0D + /**=0D + This member specifies the revision of this structure. This field is us= ed to=0D + indicate backwards compatible changes to the protocol.=0D + **/=0D + UINT8 Revision;=0D + /**=0D + Smi unregister function for PCH TCO SMI DISPATCH PROTOCOL.=0D + **/=0D + PCH_TCO_SMI_DISPATCH_UNREGISTER UnRegister;=0D + /**=0D + Mch=0D + The event is triggered when PCH received a DMI special cycle message u= sing DMI indicating that=0D + it wants to cause an SMI.=0D + The software must read the processor to determine the reason for the S= MI.=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER MchRegister;=0D + /**=0D + TcoTimeout=0D + The event is triggered by PCH to indicate that the SMI was caused by t= he TCO timer reaching 0.=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER TcoTimeoutRegister;=0D + /**=0D + OsTco=0D + The event is triggered when software caused an SMI# by writing to the = TCO_DAT_IN register (TCOBASE + 02h).=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER OsTcoRegister;=0D + /**=0D + Nmi=0D + The event is triggered by the PCH when an SMI# occurs because an event= occurred that would otherwise have=0D + caused an NMI (because NMI2SMI_EN is set)=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER NmiRegister;=0D + /**=0D + IntruderDectect=0D + The event is triggered by PCH to indicate that an intrusion was detect= ed.=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER IntruderDetRegister;=0D + /**=0D + SpiBiosWp=0D + This event is triggered when SMI# was caused by the TCO logic and=0D + SPI flash controller asserted Synchronous SMI by BIOS lock enable set.= =0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER SpiBiosWpRegister;=0D + /**=0D + LpcBiosWp=0D + This event is triggered when SMI# was caused by the TCO logic and=0D + LPC/eSPI BIOS lock enable set.=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER LpcBiosWpRegister;=0D + /**=0D + NewCentury=0D + This event is triggered when SMI# was caused by the TCO logic and=0D + year of RTC date rolls over a century (99 to 00).=0D + **/=0D + PCH_TCO_SMI_DISPATCH_REGISTER NewCenturyRegister;=0D +};=0D +=0D +/**=0D + PCH TCO SMI dispatch revision number=0D +=0D + Revision 1: Initial version=0D + Revision 2: Add NEWCENTURY support=0D +**/=0D +#define PCH_TCO_SMI_DISPATCH_REVISION 2=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs= .h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h new file mode 100644 index 0000000000..679cb17f6c --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs.h @@ -0,0 +1,16 @@ +/** @file=0D + Generic register definitions for PCH.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_H_=0D +#define _PCH_REGS_H_=0D +=0D +///=0D +/// The default PCH PCI segment and bus number=0D +///=0D +#define DEFAULT_PCI_SEGMENT_NUMBER_PCH 0=0D +#define DEFAULT_PCI_BUS_NUMBER_PCH 0=0D +=0D +#endif //_PCH_REGS_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs= Lpc.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h new file mode 100644 index 0000000000..32dd88be0e --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsLpc.h @@ -0,0 +1,145 @@ +/** @file=0D + Register names for PCH LPC/eSPI device=0D +=0D +Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_LPC_H_=0D +#define _PCH_REGS_LPC_H_=0D +=0D +#define B_LPC_CFG_DID 0xFFE0=0D +=0D +//=0D +// PCI to LPC Bridge Registers=0D +//=0D +=0D +#define R_LPC_CFG_IOD 0x80=0D +#define V_LPC_CFG_IOD_COMB_2F8 1=0D +#define V_LPC_CFG_IOD_COMA_3F8 0=0D +#define V_LPC_CFG_IOD_COMA_2F8 1=0D +#define R_LPC_CFG_IOE 0x82=0D +#define B_LPC_CFG_IOE_SE BIT12 ///< Sup= er I/O Enable, Enables decoding of I/O locations 2Eh and 2Fh to LPC.=0D +#define B_LPC_CFG_IOE_KE BIT10 ///< Key= board Enable, Enables decoding of the keyboard I/O locations 60h and 64h to= LPC.=0D +#define B_LPC_CFG_IOE_PPE BIT2 ///< Par= allel Port Enable, Enables decoding of the LPT range to LPC. Range is selec= ted by LIOD.LPT.=0D +#define B_LPC_CFG_IOE_CBE BIT1 ///< Com= Port B Enable, Enables decoding of the COMB range to LPC. Range is selecte= d LIOD.CB.=0D +#define B_LPC_CFG_IOE_CAE BIT0 ///< Com= Port A Enable, Enables decoding of the COMA range to LPC. Range is selecte= d LIOD.CA.=0D +#define R_LPC_CFG_ULKMC 0x94=0D +#define B_LPC_CFG_ULKMC_A20PASSEN BIT5=0D +#define B_LPC_CFG_ULKMC_64WEN BIT3=0D +#define B_LPC_CFG_ULKMC_64REN BIT2=0D +#define B_LPC_CFG_ULKMC_60WEN BIT1=0D +#define B_LPC_CFG_ULKMC_60REN BIT0=0D +#define R_LPC_CFG_LGMR 0x98=0D +#define B_LPC_CFG_LGMR_MA 0xFFFF0000=0D +#define B_LPC_CFG_LGMR_LMRD_EN BIT0=0D +#define R_ESPI_CFG_CS1IORE 0xA0=0D +#define R_ESPI_CFG_CS1GMR1 0xA8=0D +=0D +#define R_LPC_CFG_BDE 0xD8 = ///< BIOS decode enable=0D +=0D +//=0D +// APM Registers=0D +//=0D +#define R_PCH_IO_APM_CNT 0xB2=0D +#define R_PCH_IO_APM_STS 0xB3=0D +=0D +#define R_LPC_CFG_BC 0xDC ///< Bio= s Control=0D +#define S_LPC_CFG_BC 1=0D +#define N_LPC_CFG_BC_LE 1=0D +#define B_LPC_CFG_BC_WPD BIT0 ///< Wri= te Protect Disable=0D +=0D +#define R_ESPI_CFG_PCBC 0xDC ///< Per= ipheral Channel BIOS Control=0D +#define S_ESPI_CFG_PCBC 4 ///< Per= ipheral Channel BIOS Control register size=0D +#define B_ESPI_CFG_PCBC_BWRE BIT11 ///< BIO= S Write Report Enable=0D +#define B_ESPI_CFG_PCBC_BWRS BIT10 ///< BIO= S Write Report Status=0D +#define B_ESPI_CFG_PCBC_BWPDS BIT8 ///< BIO= S Write Protect Disable Status=0D +#define N_ESPI_CFG_PCBC_BWPDS 8 ///< BIO= S Write Protect Disable Status bit position=0D +#define B_ESPI_CFG_PCBC_ESPI_EN BIT2 ///< eSP= I Enable Pin Strap=0D +#define B_ESPI_CFG_PCBC_LE BIT1 ///< Loc= k Enable=0D +#define N_ESPI_CFG_PCBC_LE 1=0D +=0D +//=0D +// eSPI slave registers=0D +//=0D +#define B_ESPI_SLAVE_BME BIT2 ///< Bus= Master Enable=0D +=0D +//=0D +// Reset Generator I/O Port=0D +//=0D +#define R_PCH_IO_RST_CNT 0xCF9=0D +#define V_PCH_IO_RST_CNT_FULLRESET 0x0E=0D +#define V_PCH_IO_RST_CNT_HARDRESET 0x06=0D +=0D +//=0D +// eSPI PCR Registers=0D +//=0D +#define R_ESPI_PCR_SLV_CFG_REG_CTL 0x4000 ///<= Slave Configuration Register and Link Control=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRE BIT31 ///<= Slave Configuration Register Access Enable=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRS (BIT30 | BIT29 | BIT28) ///<= Slave Configuration Register Access Status=0D +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRS 28 ///<= Slave Configuration Register Access Status bit position=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SBLCL BIT27 ///<= IOSF-SB eSPI Link Configuration Lock=0D +#define V_ESPI_PCR_SLV_CFG_REG_CTL_SCRS_NOERR 7 ///<= No errors (transaction completed successfully)=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SID (BIT20 | BIT19) ///<= Slave ID=0D +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SID 19 ///<= Slave ID bit position=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRT (BIT17 | BIT16) ///<= Slave Configuration Register Access Type=0D +#define N_ESPI_PCR_SLV_CFG_REG_CTL_SCRT 16 ///<= Slave Configuration Register Access Type bit position=0D +#define B_ESPI_PCR_SLV_CFG_REG_CTL_SCRA 0x00000FFF ///<= Slave Configuration Register Address=0D +#define R_ESPI_PCR_SLV_CFG_REG_DATA 0x4004 ///<= Slave Configuration Register Data=0D +=0D +#define R_ESPI_PCR_PCERR_SLV0 0x4020 ///< Periphe= ral Channel Error for Slave 0=0D +#define B_ESPI_PCR_PCERR_PCURD BIT24 ///< Periphe= ral Channel Unsupported Request Detected=0D +#define R_ESPI_PCR_VWERR_SLV0 0x4030 ///< Virtual= Wire Channel Error for Slave 0=0D +#define R_ESPI_PCR_FCERR_SLV0 0x4040 ///< Flash A= ccess Channel Error for Slave 0=0D +#define B_ESPI_PCR_FCERR_SAFBLK BIT17 ///< SAF Blo= cked (SAFBLK)=0D +#define B_ESPI_PCR_XERR_XNFEE (BIT14 | BIT13) ///< Non-Fat= al Error Reporting Enable bits=0D +#define N_ESPI_PCR_XERR_XNFEE 13 ///< Non-Fat= al Error Reporting Enable bit position=0D +#define V_ESPI_PCR_XERR_XNFEE_SMI 3 ///< Enable = Non-Fatal Error Reporting as SMI=0D +#define B_ESPI_PCR_XERR_XNFES BIT12 ///< Fatal E= rror Status=0D +#define B_ESPI_PCR_XERR_XFEE (BIT6 | BIT5) ///< Fatal E= rror Reporting Enable bits=0D +#define N_ESPI_PCR_XERR_XFEE 5 ///< Fatal E= rror Reporting Enable bit position=0D +#define V_ESPI_PCR_XERR_XFEE_SMI 3 ///< Enable = Fatal Error Reporting as SMI=0D +#define B_ESPI_PCR_XERR_XFES BIT4 ///< Fatal E= rror Status=0D +#define S_ESPI_PCR_XERR 4 ///< Channel= register sizes=0D +#define B_ESPI_PCR_PCERR_SLV0_PCURD BIT24 ///< Periphe= ral Channel Unsupported Request Detected=0D +#define R_ESPI_PCR_LNKERR_SLV0 0x4050 ///< Link Er= ror for Slave 0=0D +#define S_ESPI_PCR_LNKERR_SLV0 4 ///< Link Er= ror for Slave 0 register size=0D +#define B_ESPI_PCR_LNKERR_SLV0_SLCRR BIT31 ///< eSPI Li= nk and Slave Channel Recovery Required=0D +#define B_ESPI_PCR_LNKERR_SLV0_LFET1E (BIT22 | BIT21) ///< Fatal E= rror Type 1 Reporting Enable=0D +#define N_ESPI_PCR_LNKERR_SLV0_LFET1E 21 ///< Fatal E= rror Type 1 Reporting Enable bit position=0D +#define V_ESPI_PCR_LNKERR_SLV0_LFET1E_SMI 3 ///< Enable = Fatal Error Type 1 Reporting as SMI=0D +#define B_ESPI_PCR_LNKERR_SLV0_LFET1S BIT20 ///< Link Fa= tal Error Type 1 Status=0D +#define R_ESPI_PCR_LNKERR_SLV1 0x4054 ///< Link Er= ror for Slave 1=0D +#define R_ESPI_PCR_CFG_VAL 0xC00C ///< ESPI En= abled Strap=0D +#define B_ESPI_PCR_CFG_VAL_ESPI_EN BIT0 ///< ESPI En= abled Strap bit position=0D +#define R_ESPI_PCR_SOFTSTRAPS 0xC210 ///< eSPI So= fstraps Register 0=0D +#define B_ESPI_PCR_SOFTSTRAPS_CS1_EN BIT12 ///< CS1# En= able=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs= Psf.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h new file mode 100644 index 0000000000..dc32f1e5b3 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsf.h @@ -0,0 +1,50 @@ +/** @file=0D + Register definition for PSF component=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PSF_H_=0D +#define _PCH_REGS_PSF_H_=0D +//=0D +// PSFx segment registers=0D +//=0D +=0D +#define N_PCH_PSFX_PCR_MC_CONTROL_MCASTX_NUMMC 1=0D +#define B_PCH_PSFX_PCR_MC_CONTROL_MCASTX_MULTCEN BIT0=0D +=0D +//=0D +// PSFx PCRs definitions=0D +//=0D +#define B_PCH_PSFX_PCR_TARGET_PSFID 0xFF0000=0D +#define N_PCH_PSFX_PCR_TARGET_PSFID 16=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegs= Psth.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth= .h new file mode 100644 index 0000000000..2007eae44f --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/Include/Register/PchRegsPsth.h @@ -0,0 +1,66 @@ +/** @file=0D + Register definition for PSTH component=0D +=0D + Conventions:=0D +=0D + - Register definition format:=0D + Prefix_[GenerationName]_[ComponentName]_SubsystemName_RegisterSpace_Re= gisterName=0D + - Prefix:=0D + Definitions beginning with "R_" are registers=0D + Definitions beginning with "B_" are bits within registers=0D + Definitions beginning with "V_" are meaningful values within the bits= =0D + Definitions beginning with "S_" are register size=0D + Definitions beginning with "N_" are the bit position=0D + - [GenerationName]:=0D + Three letter acronym of the generation is used (e.g. SKL,KBL,CNL etc.)= .=0D + Register name without GenerationName applies to all generations.=0D + - [ComponentName]:=0D + This field indicates the component name that the register belongs to (= e.g. PCH, SA etc.)=0D + Register name without ComponentName applies to all components.=0D + Register that is specific to -LP denoted by "_PCH_LP_" in component na= me.=0D + - SubsystemName:=0D + This field indicates the subsystem name of the component that the regi= ster belongs to=0D + (e.g. PCIE, USB, SATA, GPIO, PMC etc.).=0D + - RegisterSpace:=0D + MEM - MMIO space register of subsystem.=0D + IO - IO space register of subsystem.=0D + PCR - Private configuration register of subsystem.=0D + CFG - PCI configuration space register of subsystem.=0D + - RegisterName:=0D + Full register name.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_REGS_PSTH_H_=0D +#define _PCH_REGS_PSTH_H_=0D +=0D +//=0D +// Private chipset regsiter (Memory space) offset definition=0D +// The PCR register defines is used for PCR MMIO programming and PCH SBI p= rogramming as well.=0D +//=0D +=0D +//=0D +// PSTH and IO Trap PCRs (PID:PSTH)=0D +//=0D +#define R_PSTH_PCR_PSTHCTL 0x1D00 ///< PSTH contro= l register=0D +#define B_PSTH_PCR_PSTHIOSFPTCGE BIT2 ///< PSTH IOSF p= rimary trunk clock gating enable=0D +#define R_PSTH_PCR_TRPST 0x1E00 ///< Trap status= regsiter=0D +#define R_PSTH_PCR_TRPC 0x1E10 ///< Trapped cyc= le=0D +#define B_PSTH_PCR_TRPC_RW BIT24 ///< Read/Write#= : 1=3DRead, 0=3DWrite=0D +#define B_PSTH_PCR_TRPC_AHBE 0x00000000000F0000 ///< Active high= byte enables=0D +#define B_PSTH_PCR_TRPC_IOA 0x000000000000FFFC ///< Trap cycle = I/O address=0D +#define R_PSTH_PCR_TRPD 0x1E18 ///< Trapped wri= te data=0D +#define R_PSTH_PCR_TRPREG0 0x1E80 ///< IO Tarp 0 r= egister=0D +#define R_PSTH_PCR_TRPREG1 0x1E88 ///< IO Tarp 1 r= egister=0D +#define R_PSTH_PCR_TRPREG2 0x1E90 ///< IO Tarp 2 r= egister=0D +#define R_PSTH_PCR_TRPREG3 0x1E98 ///< IO Tarp 3 r= egister=0D +#define B_PSTH_PCR_TRPREG_RWM BIT17 ///< 49 - 32 for= 32 bit access, Read/Write mask=0D +#define B_PSTH_PCR_TRPREG_RWIO BIT16 ///< 48 - 32 for= 32 bit access, Read/Write#, 1=3DRead, 0=3DWrite=0D +#define N_PSTH_PCR_TRPREG_RWIO 16 ///< 48 - 32 for= 32 bit access, 16bit shift for Read/Write field=0D +#define N_PSTH_PCR_TRPREG_BEM 36=0D +#define N_PSTH_PCR_TRPREG_BE 32=0D +#define B_PSTH_PCR_TRPREG_AD 0x000000000000FFFC ///< IO Address= =0D +#define B_PSTH_PCR_TRPREG_TSE BIT0 ///< Trap and SM= I# Enable=0D +=0D +#endif=0D --=20 2.24.0.windows.2