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From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [Patch V3 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers
Date: Fri,  5 Feb 2021 15:40:11 +0800	[thread overview]
Message-ID: <20210205074045.3916-6-heng.luo@intel.com> (raw)
In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3171

Adds the following header files:
  * Pch/IncludePrivate

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h |  47 +++++++++++++++++++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h   |  26 ++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h               | 269 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h        |  21 +++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h              | 319 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h                  |  58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h        |  30 ++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h        |  35 +++++++++++++++++++++++++++++++++++
 Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h         |  21 +++++++++++++++++++++
 9 files changed, 826 insertions(+)

diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h
new file mode 100644
index 0000000000..2ad80a0269
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleResetLib.h
@@ -0,0 +1,47 @@
+/** @file
+  Reset scheduling library services
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _SI_SCHEDULE_RESET_LIB_H_
+#define _SI_SCHEDULE_RESET_LIB_H_
+
+#include <Uefi/UefiMultiPhase.h>
+#include <PchResetPlatformSpecific.h>
+
+/**
+  This function updates the reset information in SiScheduleResetHob
+  @param[in] ResetType        UEFI defined reset type.
+  @param[in] ResetData        Optional element used to introduce a platform specific reset.
+                               The exact type of the reset is defined by the EFI_GUID that follows
+                               the Null-terminated Unicode string.
+**/
+VOID
+SiScheduleResetSetType (
+  IN EFI_RESET_TYPE     ResetType,
+  IN PCH_RESET_DATA     *ResetData OPTIONAL
+  );
+
+/**
+  This function returns TRUE or FALSE depending on whether a reset is required based on SiScheduleResetHob
+
+  @retval     BOOLEAN       The function returns FALSE if no reset is required
+**/
+BOOLEAN
+SiScheduleResetIsRequired (
+  VOID
+  );
+
+/**
+  This function performs reset based on SiScheduleResetHob
+
+  @retval     BOOLEAN       The function returns FALSE if no reset is required
+**/
+BOOLEAN
+SiScheduleResetPerformReset (
+  VOID
+  );
+
+#endif //_SI_SCHEDULE_RESET_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h
new file mode 100644
index 0000000000..955dac5a82
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivateLib.h
@@ -0,0 +1,26 @@
+/** @file
+  Header file for private PCH SMM Lib.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SMM_PCH_PRIVATE_LIB_H_
+#define _SMM_PCH_PRIVATE_LIB_H_
+
+/**
+  Set InSmm.Sts bit
+**/
+VOID
+PchSetInSmmSts (
+  VOID
+  );
+
+/**
+  Clear InSmm.Sts bit
+**/
+VOID
+PchClearInSmmSts (
+  VOID
+  );
+
+#endif // _SMM_PCH_PRIVATE_LIB_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h
new file mode 100644
index 0000000000..13a41f8d04
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h
@@ -0,0 +1,269 @@
+/** @file
+  The GUID definition for PchConfigHob
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_CONFIG_HOB_H_
+#define _PCH_CONFIG_HOB_H_
+
+#include <ConfigBlock.h>
+#include <SmbusConfig.h>
+#include <InterruptConfig.h>
+#include <PchPcieRpConfig.h>
+#include <SataConfig.h>
+#include <RstConfig.h>
+#include <ConfigBlock/FlashProtectionConfig.h>
+#include <FivrConfig.h>
+#include <ThcConfig.h>
+#include <SerialIoConfig.h>
+
+
+extern EFI_GUID gPchConfigHobGuid;
+
+#pragma pack (push,1)
+
+/**
+  This structure contains the HOB which are related to PCH general config.
+**/
+typedef struct {
+  /**
+    This member describes whether or not the Compatibility Revision ID (CRID) feature
+    of PCH should be enabled. <b>0: Disable</b>; 1: Enable
+  **/
+  UINT32 Crid      :  1;
+  UINT32 RsvdBits0 : 31; ///< Reserved bits
+} GENERAL_HOB;
+
+/**
+  The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable devices in the platform.
+**/
+typedef struct {
+  UINT8 RsvdBytes[3];          ///< Reserved bytes
+  UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbusAddressTable.
+  /**
+    Array of addresses reserved for non-ARP-capable SMBus devices.
+  **/
+  UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];
+} SMBUS_HOB;
+
+/**
+  The INTERRUPT_HOB describes interrupt settings for PCH.
+**/
+typedef struct {
+  UINT8                        NumOfDevIntConfig;                             ///< Number of entries in DevIntConfig table
+  UINT8                        GpioIrqRoute;                                  ///< Interrupt routing for GPIO. Default is <b>14</b>.
+  UINT8                        Rsvd0[2];                                      ///< Reserved bytes, align to multiple 4.
+  PCH_DEVICE_INTERRUPT_CONFIG  DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFIG]; ///< Array which stores PCH devices interrupts settings
+} INTERRUPT_HOB;
+
+/**
+  The SERIAL_IO block provides the configurations to set the Serial IO controllers
+**/
+typedef struct {
+  SERIAL_IO_SPI_CONFIG  SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS];   ///< SPI Configuration
+  SERIAL_IO_I2C_CONFIG  I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS];   ///< I2C Configuration
+  SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS]; ///< UART Configuration
+} SERIAL_IO_HOB;
+
+/**
+  The PCIERP_HOB block describes the expected configuration of the PCH PCI Express controllers
+**/
+typedef struct {
+  ///
+  /// These members describe the configuration of each PCH PCIe root port.
+  ///
+  PCH_PCIE_ROOT_PORT_CONFIG    RootPort[PCH_MAX_PCIE_ROOT_PORTS];
+  PCH_PCIE_CLOCK               PcieClock[PCH_MAX_PCIE_CLOCKS];
+  /**
+    This member allows BIOS to control ICC PLL Shutdown by determining PCIe devices are LTR capable
+    or leaving untouched.
+    - <b>0: Disable, ICC PLL Shutdown is determined by PCIe device LTR capablility.</b>
+      - To allow ICC PLL shutdown if all present PCIe devices are LTR capable or if no PCIe devices are
+        presented for maximum power savings where possible.
+      - To disable ICC PLL shutdown when BIOS detects any non-LTR capable PCIe device for ensuring device
+        functionality.
+    - 1: Enable, To allow ICC PLL shutdown even if some devices do not support LTR capability.
+  **/
+  UINT32  AllowNoLtrIccPllShutdown :  1;
+  UINT32  RsvdBits0                : 31; ///< Reserved bits
+} PCIERP_HOB;
+
+/**
+  The HDAUDIO_HOB block describes the configuration of the PCH cAVS controller
+**/
+typedef struct {
+  UINT32  DspEnable             :  1; ///< DSP enablement: 0: Disable; <b>1: Enable</b>
+  UINT32  DspUaaCompliance      :  1; ///< UAA-mode Select: <b>0: Non-Uaa</b>; 1: UAA
+  UINT32  CodecSxWakeCapability :  1; ///< Capability to detect wake initiated by a codec in Sx, <b>0: Disable</b>; 1: Enable
+  UINT32  AudioLinkSndw1        :  1; ///< SoundWire1 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with HDA
+  UINT32  AudioLinkSndw2        :  1; ///< SoundWire2 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with SSP1
+  UINT32  AudioLinkSndw3        :  1; ///< SoundWire3 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC1
+  UINT32  AudioLinkSndw4        :  1; ///< SoundWire4 link enablement: <b>0: Disable</b>; 1: Enable. Muxed with DMIC0
+  UINT32  Pme                   :  1; ///< Azalia wake-on-ring, <b>0: Disable</b>; 1: Enable
+  UINT32  RsvdBits0             : 24; ///< Reserved bits
+} HDAUDIO_HOB;
+
+/**
+  The SATA_HOB block describes the configuration of the PCH SATA controllers
+**/
+typedef struct {
+  /**
+    This member describes whether or not the SATA controllers should be enabled. 0: Disable; <b>1: Enable</b>.
+  **/
+  UINT32                        Enable          :  1;
+  UINT32                        TestMode        :  1; ///< <b>(Test)</b> <b>0: Disable</b>; 1: Allow entrance to the PCH SATA test modes
+  UINT32                        RsvdBits0       : 30; ///< Reserved bits
+  /**
+    This member configures the features, property, and capability for each SATA port.
+  **/
+  PCH_SATA_PORT_CONFIG          PortSettings[PCH_MAX_SATA_PORTS];
+} SATA_HOB;
+
+/**
+  The RST block describes the configuration of the RST PCIE Cycle Routers
+**/
+typedef struct {
+  /**
+    This member describes the details of implementation of Intel RST for PCIe Storage remapping (Intel RST Driver is required)
+  **/
+  RST_HARDWARE_REMAPPED_STORAGE_CONFIG   RstHardwareRemappedStorageConfig[PCH_MAX_RST_PCIE_STORAGE_CR];
+} RST_HOB;
+
+typedef struct {
+  UINT32  Enabled  : 1; ///< Indicates that SD card has been enabled
+  UINT32  Reserved : 31;
+} SD_CARD_HOB;
+
+/**
+  The EMMC_HOB block describes integrated eMMC settings for PCH.
+**/
+typedef struct {
+  UINT32  Enabled                      :  1;  ///< Determine if eMMC is enabled - 0: Disabled, <b>1: Enabled</b>.
+  UINT32  Hs400Enabled                 :  1;  ///< Determine eMMC HS400 Mode if EmmcEnabled - <b>0: Disabled</b>, 1: Enabled
+  /**
+    Determine if HS400 Training is required, set to FALSE if Hs400 Data is valid. <b>0: Disabled</b>, 1: Enabled.
+    First Boot or CMOS clear, system boot with Default settings, set tuning required.
+    Subsequent Boots, Get Variable 'Hs400TuningData'
+      - if failed to get variable, set tuning required
+      - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxDataDll from variable. Set tuning not required.
+  **/
+  UINT32  Hs400DllDataValid            :  1;  ///< Set if HS400 Tuning Data Valid
+  UINT32  RsvdBits                     : 29;
+} EMMC_HOB;
+
+/**
+  The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of the PCH
+  for security requirement.
+**/
+typedef struct {
+  UINT32  GlobalSmi      :  1;
+  /**
+    <b>(Test)</b> Enable BIOS Interface Lock Down bit to prevent writes to the Backup Control Register
+    Top Swap bit and the General Control and Status Registers Boot BIOS Straps. 0: Disable; <b>1: Enable</b>.
+  **/
+  UINT32  BiosInterface  :  1;
+  /**
+    Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:RegDCh[5])
+    for the BIOS region protection. When it is enabled, the BIOS Region can only be
+    modified from SMM after EndOfDxe protocol is installed.
+    Note: When BiosLock is enabled, platform code also needs to update to take care
+    of BIOS modification (including SetVariable) in DXE or runtime phase after
+    EndOfDxe protocol is installed.
+    Enable InSMM.STS (EISS) in SPI
+    If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be '1' also
+    in order to write to BIOS regions of SPI Flash. If this EISS bit is clear,
+    then the InSMM.STS is a don't care.
+    The BIOS must set the EISS bit while BIOS Guard support is enabled.
+    In recovery path, platform can temporary disable EISS for SPI programming in
+    PEI phase or early DXE phase.
+    0: Disable; <b>1: Enable.</b>
+  **/
+  UINT32  BiosLock        :  1;
+  UINT32  RsvdBits        : 29;
+} LOCK_DOWN_HOB;
+
+/**
+  The PM_HOB block describes expected miscellaneous power management settings.
+  The PowerResetStatusClear field would clear the Power/Reset status bits, please
+  set the bits if you want PCH Init driver to clear it, if you want to check the
+  status later then clear the bits.
+**/
+typedef struct {
+  UINT32 PsOnEnable             :  1; ///< Indicates if PS_ON support has been enabled, <b>0: Disable</b>; 1: Enable.
+  UINT32 EnableTimedGpio0       :  1; ///< Enable Bit for Timed GPIO 0 <b>0 = disable</b>; 1 = enable
+  UINT32 EnableTimedGpio1       :  1; ///< Enable Bit for Timed GPIO 1 <b>0 = disable</b>; 1 = enable
+  UINT32 RsvdBits1              : 29;
+} PM_HOB;
+
+/**
+  FIVR_HOB block
+**/
+typedef struct {
+  /**
+    Additional External Vnn VR rail configuration dedicated for Sx.
+    Required only if External Vnn VR needs different settings for Sx than
+    those specified in ExtVnnRail (refer to PCH_FIVR_CONFIG.ExtVnnRail)
+  **/
+  FIVR_EXT_RAIL_CONFIG     ExtVnnRailSx;
+} FIVR_HOB;
+
+/**
+  PCH Trace Hub HOB settings.
+**/
+typedef struct {
+  UINT32  PchTraceHubMode       :  2; ///< <b>0 = Disable</b>; 1 = Target Debugger mode; 2 = Host Debugger mode
+  UINT32  Rsvd1                 : 30; ///< Reserved bits
+  /**
+    Trace hub memory buffer region size policy.
+    The avaliable memory size options are: 0:0MB (none), 1:1MB, <b>2:8MB</b>, 3:64MB, 4:128MB, 5:256MB, 6:512MB.
+    Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt is enabled, the total size limits to 256 MB.
+    Refer to TRACE_BUFFER_SIZE
+  **/
+  UINT32  MemReg0Size;
+  UINT32  MemReg1Size;
+} PCH_TRACEHUB_HOB;
+
+/**
+  PCH eSPI HOB settings.
+**/
+typedef struct {
+  UINT32  BmeMasterSlaveEnabled :  1; ///< <b>0 = BME disable</b>; 1 = BME enable
+  UINT32  RsvdBits              : 31; ///< Reserved bits
+} PCH_ESPI_HOB;
+
+/**
+  THC HOB settings.
+**/
+typedef struct {
+  THC_PORT  ThcPort[2]; ///< Port Configuration
+} THC_HOB;
+
+
+/**
+  This structure contains the HOBs which are related to PCH controllers
+**/
+typedef struct {
+  EFI_HOB_GUID_TYPE  EfiHobGuidType;     ///< GUID HOB type structure for gPchConfigHobGuid
+  GENERAL_HOB        General;            ///< Pch general HOB definition
+  INTERRUPT_HOB      Interrupt;          ///< Interrupt HOB definition
+  SERIAL_IO_HOB      SerialIo;           ///< Serial io HOB definition
+  PCIERP_HOB         PcieRp;             ///< PCIE root port HOB definition
+  SD_CARD_HOB        SdCard;             ///< SD card HOB definition
+  EMMC_HOB           Emmc;               ///< eMMC HOB definition
+  LOCK_DOWN_HOB      LockDown;           ///< Lock down HOB definition
+  PM_HOB             Pm;                 ///< PM HOB definition
+  HDAUDIO_HOB        HdAudio;            ///< HD audio definition
+  SATA_HOB           Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA definition
+  RST_HOB            Rst;                ///< RST definition
+  PROTECTED_RANGE    ProtectRange[PCH_FLASH_PROTECTED_RANGES];
+  SMBUS_HOB          Smbus;
+  PCH_TRACEHUB_HOB   PchTraceHub;        ///< PCH Trace Hub definition
+  PCH_ESPI_HOB       Espi;               ///< PCH eSPI definition
+  THC_HOB            Thc;                ///< PCH Tocuh Host Controller definition
+  FIVR_HOB           Fivr;               ///< PCH FIVR HOB definition
+
+
+} PCH_CONFIG_HOB;
+#pragma pack (pop)
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h
new file mode 100644
index 0000000000..040bc270e6
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h
@@ -0,0 +1,21 @@
+/** @file
+
+  Definitions required to create HybridStorageHob
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_HYBRIDSTORAGE_HOB_
+#define _PCH_HYBRIDSTORAGE_HOB_
+
+extern EFI_GUID  gHybridStorageHobGuid;
+
+//
+//  Passes to DXE Hybrid Storage location
+//
+typedef struct {
+  UINT32 HybridStorageLocation;
+} PCH_HYBRIDSTORAGE_HOB;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h
new file mode 100644
index 0000000000..200f3ca8fa
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h
@@ -0,0 +1,319 @@
+//
+// Automatically generated by GenNvs ver 2.4.6
+// Please DO NOT modify !!!
+//
+
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+  //
+  // Define PCH NVS Area operatino region.
+  //
+#ifndef _PCH_NVS_AREA_DEF_H_
+#define _PCH_NVS_AREA_DEF_H_
+
+#pragma pack (push,1)
+typedef struct {
+  UINT16   PchSeries;                               ///< Offset 0       PCH Series
+  UINT16   PchGeneration;                           ///< Offset 2       PCH Generation
+  UINT16   PchStepping;                             ///< Offset 4       PCH Stepping
+  UINT32   RpAddress[28];                           ///< Offset 6       Root Port address 1
+                                                    ///< Offset 10      Root Port address 2
+                                                    ///< Offset 14      Root Port address 3
+                                                    ///< Offset 18      Root Port address 4
+                                                    ///< Offset 22      Root Port address 5
+                                                    ///< Offset 26      Root Port address 6
+                                                    ///< Offset 30      Root Port address 7
+                                                    ///< Offset 34      Root Port address 8
+                                                    ///< Offset 38      Root Port address 9
+                                                    ///< Offset 42      Root Port address 10
+                                                    ///< Offset 46      Root Port address 11
+                                                    ///< Offset 50      Root Port address 12
+                                                    ///< Offset 54      Root Port address 13
+                                                    ///< Offset 58      Root Port address 14
+                                                    ///< Offset 62      Root Port address 15
+                                                    ///< Offset 66      Root Port address 16
+                                                    ///< Offset 70      Root Port address 17
+                                                    ///< Offset 74      Root Port address 18
+                                                    ///< Offset 78      Root Port address 19
+                                                    ///< Offset 82      Root Port address 20
+                                                    ///< Offset 86      Root Port address 21
+                                                    ///< Offset 90      Root Port address 22
+                                                    ///< Offset 94      Root Port address 23
+                                                    ///< Offset 98      Root Port address 24
+                                                    ///< Offset 102     Root Port address 25
+                                                    ///< Offset 106     Root Port address 26
+                                                    ///< Offset 110     Root Port address 27
+                                                    ///< Offset 114     Root Port address 28
+  UINT64   NHLA;                                    ///< Offset 118     HD-Audio NHLT ACPI address
+  UINT32   NHLL;                                    ///< Offset 126     HD-Audio NHLT ACPI length
+  UINT32   ADFM;                                    ///< Offset 130     HD-Audio DSP Feature Mask
+  UINT8    SWQ0;                                    ///< Offset 134     HD-Audio SoundWire Link #1 quirk mask
+  UINT8    SWQ1;                                    ///< Offset 135     HD-Audio SoundWire Link #2 quirk mask
+  UINT8    SWQ2;                                    ///< Offset 136     HD-Audio SoundWire Link #3 quirk mask
+  UINT8    SWQ3;                                    ///< Offset 137     HD-Audio SoundWire Link #4 quirk mask
+  UINT8    ACS0;                                    ///< Offset 138     HD-Audio SoundWire Link #1 Autonomous Clock Stop
+  UINT8    ACS1;                                    ///< Offset 139     HD-Audio SoundWire Link #2 Autonomous Clock Stop
+  UINT8    ACS2;                                    ///< Offset 140     HD-Audio SoundWire Link #3 Autonomous Clock Stop
+  UINT8    ACS3;                                    ///< Offset 141     HD-Audio SoundWire Link #4 Autonomous Clock Stop
+  UINT8    DAI0;                                    ///< Offset 142     HD-Audio SoundWire Link #1 Data On Active Interval Select
+  UINT8    DAI1;                                    ///< Offset 143     HD-Audio SoundWire Link #2 Data On Active Interval Select
+  UINT8    DAI2;                                    ///< Offset 144     HD-Audio SoundWire Link #3 Data On Active Interval Select
+  UINT8    DAI3;                                    ///< Offset 145     HD-Audio SoundWire Link #4 Data On Active Interval Select
+  UINT8    DOD0;                                    ///< Offset 146     HD-Audio SoundWire Link #1 Data On Delay Select
+  UINT8    DOD1;                                    ///< Offset 147     HD-Audio SoundWire Link #2 Data On Delay Select
+  UINT8    DOD2;                                    ///< Offset 148     HD-Audio SoundWire Link #3 Data On Delay Select
+  UINT8    DOD3;                                    ///< Offset 149     HD-Audio SoundWire Link #4 Data On Delay Select
+  UINT8    SWMC;                                    ///< Offset 150     HD-Audio SoundWire Master Count
+  UINT8    XTAL;                                    ///< Offset 151     XTAL frequency: 0: 24MHz; 1: 38.4MHz; 2: Unsupported
+  UINT32   DSPM;                                    ///< Offset 152     HD-Audio DSP Stolen Memory Base Address (@todo: Remove after CNL-LP B0)
+  UINT32   SBRG;                                    ///< Offset 156     SBREG_BAR
+  UINT8    GEI0;                                    ///< Offset 160     GPIO GroupIndex mapped to GPE_DW0
+  UINT8    GEI1;                                    ///< Offset 161     GPIO GroupIndex mapped to GPE_DW1
+  UINT8    GEI2;                                    ///< Offset 162     GPIO GroupIndex mapped to GPE_DW2
+  UINT8    GED0;                                    ///< Offset 163     GPIO DW part of group mapped to GPE_DW0
+  UINT8    GED1;                                    ///< Offset 164     GPIO DW part of group mapped to GPE_DW1
+  UINT8    GED2;                                    ///< Offset 165     GPIO DW part of group mapped to GPE_DW2
+  UINT16   PcieLtrMaxSnoopLatency[28];              ///< Offset 166     PCIE LTR max snoop Latency 1
+                                                    ///< Offset 168     PCIE LTR max snoop Latency 2
+                                                    ///< Offset 170     PCIE LTR max snoop Latency 3
+                                                    ///< Offset 172     PCIE LTR max snoop Latency 4
+                                                    ///< Offset 174     PCIE LTR max snoop Latency 5
+                                                    ///< Offset 176     PCIE LTR max snoop Latency 6
+                                                    ///< Offset 178     PCIE LTR max snoop Latency 7
+                                                    ///< Offset 180     PCIE LTR max snoop Latency 8
+                                                    ///< Offset 182     PCIE LTR max snoop Latency 9
+                                                    ///< Offset 184     PCIE LTR max snoop Latency 10
+                                                    ///< Offset 186     PCIE LTR max snoop Latency 11
+                                                    ///< Offset 188     PCIE LTR max snoop Latency 12
+                                                    ///< Offset 190     PCIE LTR max snoop Latency 13
+                                                    ///< Offset 192     PCIE LTR max snoop Latency 14
+                                                    ///< Offset 194     PCIE LTR max snoop Latency 15
+                                                    ///< Offset 196     PCIE LTR max snoop Latency 16
+                                                    ///< Offset 198     PCIE LTR max snoop Latency 17
+                                                    ///< Offset 200     PCIE LTR max snoop Latency 18
+                                                    ///< Offset 202     PCIE LTR max snoop Latency 19
+                                                    ///< Offset 204     PCIE LTR max snoop Latency 20
+                                                    ///< Offset 206     PCIE LTR max snoop Latency 21
+                                                    ///< Offset 208     PCIE LTR max snoop Latency 22
+                                                    ///< Offset 210     PCIE LTR max snoop Latency 23
+                                                    ///< Offset 212     PCIE LTR max snoop Latency 24
+                                                    ///< Offset 214     PCIE LTR max snoop Latency 25
+                                                    ///< Offset 216     PCIE LTR max snoop Latency 26
+                                                    ///< Offset 218     PCIE LTR max snoop Latency 27
+                                                    ///< Offset 220     PCIE LTR max snoop Latency 28
+  UINT16   PcieLtrMaxNoSnoopLatency[28];            ///< Offset 222     PCIE LTR max no snoop Latency 1
+                                                    ///< Offset 224     PCIE LTR max no snoop Latency 2
+                                                    ///< Offset 226     PCIE LTR max no snoop Latency 3
+                                                    ///< Offset 228     PCIE LTR max no snoop Latency 4
+                                                    ///< Offset 230     PCIE LTR max no snoop Latency 5
+                                                    ///< Offset 232     PCIE LTR max no snoop Latency 6
+                                                    ///< Offset 234     PCIE LTR max no snoop Latency 7
+                                                    ///< Offset 236     PCIE LTR max no snoop Latency 8
+                                                    ///< Offset 238     PCIE LTR max no snoop Latency 9
+                                                    ///< Offset 240     PCIE LTR max no snoop Latency 10
+                                                    ///< Offset 242     PCIE LTR max no snoop Latency 11
+                                                    ///< Offset 244     PCIE LTR max no snoop Latency 12
+                                                    ///< Offset 246     PCIE LTR max no snoop Latency 13
+                                                    ///< Offset 248     PCIE LTR max no snoop Latency 14
+                                                    ///< Offset 250     PCIE LTR max no snoop Latency 15
+                                                    ///< Offset 252     PCIE LTR max no snoop Latency 16
+                                                    ///< Offset 254     PCIE LTR max no snoop Latency 17
+                                                    ///< Offset 256     PCIE LTR max no snoop Latency 18
+                                                    ///< Offset 258     PCIE LTR max no snoop Latency 19
+                                                    ///< Offset 260     PCIE LTR max no snoop Latency 20
+                                                    ///< Offset 262     PCIE LTR max no snoop Latency 21
+                                                    ///< Offset 264     PCIE LTR max no snoop Latency 22
+                                                    ///< Offset 266     PCIE LTR max no snoop Latency 23
+                                                    ///< Offset 268     PCIE LTR max no snoop Latency 24
+                                                    ///< Offset 270     PCIE LTR max no snoop Latency 25
+                                                    ///< Offset 272     PCIE LTR max no snoop Latency 26
+                                                    ///< Offset 274     PCIE LTR max no snoop Latency 27
+                                                    ///< Offset 276     PCIE LTR max no snoop Latency 28
+  UINT8    XHPC;                                    ///< Offset 278     Number of HighSpeed ports implemented in XHCI controller
+  UINT8    XRPC;                                    ///< Offset 279     Number of USBR ports implemented in XHCI controller
+  UINT8    XSPC;                                    ///< Offset 280     Number of SuperSpeed ports implemented in XHCI controller
+  UINT8    XSPA;                                    ///< Offset 281     Address of 1st SuperSpeed port
+  UINT32   HPTB;                                    ///< Offset 282     HPET base address
+  UINT8    HPTE;                                    ///< Offset 286     HPET enable
+  //SerialIo block
+  UINT8    SM0[7];                                  ///< Offset 287     SerialIo SPI Controller 0 Mode
+                                                    ///< Offset 288     SerialIo SPI Controller 1 Mode
+                                                    ///< Offset 289     SerialIo SPI Controller 2 Mode
+                                                    ///< Offset 290     SerialIo SPI Controller 3 Mode
+                                                    ///< Offset 291     SerialIo SPI Controller 4 Mode
+                                                    ///< Offset 292     SerialIo SPI Controller 5 Mode
+                                                    ///< Offset 293     SerialIo SPI Controller 6 Mode
+  UINT64   SC0[7];                                  ///< Offset 294     SerialIo SPI Controller 0 Pci Config
+                                                    ///< Offset 302     SerialIo SPI Controller 1 Pci Config
+                                                    ///< Offset 310     SerialIo SPI Controller 2 Pci Config
+                                                    ///< Offset 318     SerialIo SPI Controller 3 Pci Config
+                                                    ///< Offset 326     SerialIo SPI Controller 4 Pci Config
+                                                    ///< Offset 334     SerialIo SPI Controller 5 Pci Config
+                                                    ///< Offset 342     SerialIo SPI Controller 6 Pci Config
+  UINT8    IM0[8];                                  ///< Offset 350     SerialIo I2C Controller 0 Mode
+                                                    ///< Offset 351     SerialIo I2C Controller 1 Mode
+                                                    ///< Offset 352     SerialIo I2C Controller 2 Mode
+                                                    ///< Offset 353     SerialIo I2C Controller 3 Mode
+                                                    ///< Offset 354     SerialIo I2C Controller 4 Mode
+                                                    ///< Offset 355     SerialIo I2C Controller 5 Mode
+                                                    ///< Offset 356     SerialIo I2C Controller 6 Mode
+                                                    ///< Offset 357     SerialIo I2C Controller 7 Mode
+  UINT64   IC0[8];                                  ///< Offset 358     SerialIo I2C Controller 0 Pci Config
+                                                    ///< Offset 366     SerialIo I2C Controller 1 Pci Config
+                                                    ///< Offset 374     SerialIo I2C Controller 2 Pci Config
+                                                    ///< Offset 382     SerialIo I2C Controller 3 Pci Config
+                                                    ///< Offset 390     SerialIo I2C Controller 4 Pci Config
+                                                    ///< Offset 398     SerialIo I2C Controller 5 Pci Config
+                                                    ///< Offset 406     SerialIo I2C Controller 6 Pci Config
+                                                    ///< Offset 414     SerialIo I2C Controller 7 Pci Config
+  UINT8    UM0[7];                                  ///< Offset 422     SerialIo UART Controller 0 Mode
+                                                    ///< Offset 423     SerialIo UART Controller 1 Mode
+                                                    ///< Offset 424     SerialIo UART Controller 2 Mode
+                                                    ///< Offset 425     SerialIo UART Controller 3 Mode
+                                                    ///< Offset 426     SerialIo UART Controller 4 Mode
+                                                    ///< Offset 427     SerialIo UART Controller 5 Mode
+                                                    ///< Offset 428     SerialIo UART Controller 6 Mode
+  UINT64   UC0[7];                                  ///< Offset 429     SerialIo UART Controller 0 Pci Config
+                                                    ///< Offset 437     SerialIo UART Controller 1 Pci Config
+                                                    ///< Offset 445     SerialIo UART Controller 2 Pci Config
+                                                    ///< Offset 453     SerialIo UART Controller 3 Pci Config
+                                                    ///< Offset 461     SerialIo UART Controller 4 Pci Config
+                                                    ///< Offset 469     SerialIo UART Controller 5 Pci Config
+                                                    ///< Offset 477     SerialIo UART Controller 6 Pci Config
+  UINT8    UD0[7];                                  ///< Offset 485     SerialIo UART Controller 0 DmaEnable
+                                                    ///< Offset 486     SerialIo UART Controller 1 DmaEnable
+                                                    ///< Offset 487     SerialIo UART Controller 2 DmaEnable
+                                                    ///< Offset 488     SerialIo UART Controller 3 DmaEnable
+                                                    ///< Offset 489     SerialIo UART Controller 4 DmaEnable
+                                                    ///< Offset 490     SerialIo UART Controller 5 DmaEnable
+                                                    ///< Offset 491     SerialIo UART Controller 6 DmaEnable
+  UINT8    UP0[7];                                  ///< Offset 492     SerialIo UART Controller 0 Power Gating
+                                                    ///< Offset 493     SerialIo UART Controller 1 Power Gating
+                                                    ///< Offset 494     SerialIo UART Controller 2 Power Gating
+                                                    ///< Offset 495     SerialIo UART Controller 3 Power Gating
+                                                    ///< Offset 496     SerialIo UART Controller 4 Power Gating
+                                                    ///< Offset 497     SerialIo UART Controller 5 Power Gating
+                                                    ///< Offset 498     SerialIo UART Controller 6 Power Gating
+  UINT8    UI0[7];                                  ///< Offset 499     SerialIo UART Controller 0 Irq
+                                                    ///< Offset 500     SerialIo UART Controller 1 Irq
+                                                    ///< Offset 501     SerialIo UART Controller 2 Irq
+                                                    ///< Offset 502     SerialIo UART Controller 3 Irq
+                                                    ///< Offset 503     SerialIo UART Controller 4 Irq
+                                                    ///< Offset 504     SerialIo UART Controller 5 Irq
+                                                    ///< Offset 505     SerialIo UART Controller 6 Irq
+  //end of SerialIo block
+  UINT8    SGIR;                                    ///< Offset 506     GPIO IRQ
+  UINT8    GPHD;                                    ///< Offset 507     Hide GPIO ACPI device
+  UINT8    RstPcieStorageInterfaceType[3];          ///< Offset 508     RST PCIe Storage Cycle Router#1 Interface Type
+                                                    ///< Offset 509     RST PCIe Storage Cycle Router#2 Interface Type
+                                                    ///< Offset 510     RST PCIe Storage Cycle Router#3 Interface Type
+  UINT8    RstPcieStoragePmCapPtr[3];               ///< Offset 511     RST PCIe Storage Cycle Router#1 Power Management Capability Pointer
+                                                    ///< Offset 512     RST PCIe Storage Cycle Router#2 Power Management Capability Pointer
+                                                    ///< Offset 513     RST PCIe Storage Cycle Router#3 Power Management Capability Pointer
+  UINT8    RstPcieStoragePcieCapPtr[3];             ///< Offset 514     RST PCIe Storage Cycle Router#1 PCIe Capabilities Pointer
+                                                    ///< Offset 515     RST PCIe Storage Cycle Router#2 PCIe Capabilities Pointer
+                                                    ///< Offset 516     RST PCIe Storage Cycle Router#3 PCIe Capabilities Pointer
+  UINT16   RstPcieStorageL1ssCapPtr[3];             ///< Offset 517     RST PCIe Storage Cycle Router#1 L1SS Capability Pointer
+                                                    ///< Offset 519     RST PCIe Storage Cycle Router#2 L1SS Capability Pointer
+                                                    ///< Offset 521     RST PCIe Storage Cycle Router#3 L1SS Capability Pointer
+  UINT8    RstPcieStorageEpL1ssControl2[3];         ///< Offset 523     RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2
+                                                    ///< Offset 524     RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2
+                                                    ///< Offset 525     RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2
+  UINT32   RstPcieStorageEpL1ssControl1[3];         ///< Offset 526     RST PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1
+                                                    ///< Offset 530     RST PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1
+                                                    ///< Offset 534     RST PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1
+  UINT16   RstPcieStorageLtrCapPtr[3];              ///< Offset 538     RST PCIe Storage Cycle Router#1 LTR Capability Pointer
+                                                    ///< Offset 540     RST PCIe Storage Cycle Router#2 LTR Capability Pointer
+                                                    ///< Offset 542     RST PCIe Storage Cycle Router#3 LTR Capability Pointer
+  UINT32   RstPcieStorageEpLtrData[3];              ///< Offset 544     RST PCIe Storage Cycle Router#1 Endpoint LTR Data
+                                                    ///< Offset 548     RST PCIe Storage Cycle Router#2 Endpoint LTR Data
+                                                    ///< Offset 552     RST PCIe Storage Cycle Router#3 Endpoint LTR Data
+  UINT16   RstPcieStorageEpLctlData16[3];           ///< Offset 556     RST PCIe Storage Cycle Router#1 Endpoint LCTL Data
+                                                    ///< Offset 558     RST PCIe Storage Cycle Router#2 Endpoint LCTL Data
+                                                    ///< Offset 560     RST PCIe Storage Cycle Router#3 Endpoint LCTL Data
+  UINT16   RstPcieStorageEpDctlData16[3];           ///< Offset 562     RST PCIe Storage Cycle Router#1 Endpoint DCTL Data
+                                                    ///< Offset 564     RST PCIe Storage Cycle Router#2 Endpoint DCTL Data
+                                                    ///< Offset 566     RST PCIe Storage Cycle Router#3 Endpoint DCTL Data
+  UINT16   RstPcieStorageEpDctl2Data16[3];          ///< Offset 568     RST PCIe Storage Cycle Router#1 Endpoint DCTL2 Data
+                                                    ///< Offset 570     RST PCIe Storage Cycle Router#2 Endpoint DCTL2 Data
+                                                    ///< Offset 572     RST PCIe Storage Cycle Router#3 Endpoint DCTL2 Data
+  UINT16   RstPcieStorageRpDctl2Data16[3];          ///< Offset 574     RST PCIe Storage Cycle Router#1 RootPort DCTL2 Data
+                                                    ///< Offset 576     RST PCIe Storage Cycle Router#2 RootPort DCTL2 Data
+                                                    ///< Offset 578     RST PCIe Storage Cycle Router#3 RootPort DCTL2 Data
+  UINT32   RstPcieStorageUniqueTableBar[3];         ///< Offset 580     RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR
+                                                    ///< Offset 584     RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR
+                                                    ///< Offset 588     RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR
+  UINT32   RstPcieStorageUniqueTableBarValue[3];    ///< Offset 592     RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value
+                                                    ///< Offset 596     RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value
+                                                    ///< Offset 600     RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value
+  UINT32   RstPcieStorageUniquePbaBar[3];           ///< Offset 604     RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR
+                                                    ///< Offset 608     RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR
+                                                    ///< Offset 612     RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR
+  UINT32   RstPcieStorageUniquePbaBarValue[3];      ///< Offset 616     RST PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value
+                                                    ///< Offset 620     RST PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value
+                                                    ///< Offset 624     RST PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value
+  UINT32   RstPcieStorageRootPortNum[3];            ///< Offset 628     RST PCIe Storage Cycle Router#1 Root Port number
+                                                    ///< Offset 632     RST PCIe Storage Cycle Router#2 Root Port number
+                                                    ///< Offset 636     RST PCIe Storage Cycle Router#3 Root Port number
+  UINT8    EMH4;                                    ///< Offset 640     eMMC HS400 mode enabled
+  UINT8    EMDS;                                    ///< Offset 641     eMMC Driver Strength
+  UINT8    CpuSku;                                  ///< Offset 642     CPU SKU
+  UINT16   IoTrapAddress[4];                        ///< Offset 643
+  UINT8    IoTrapStatus[4];                         ///< Offset 651
+  UINT16   PMBS;                                    ///< Offset 655     ACPI IO BASE address
+  UINT32   PWRM;                                    ///< Offset 657     PWRM MEM BASE address
+  // CNVi specific
+  UINT8    CnviMode;                                ///< Offset 661     CNVi mode
+  UINT8    CnviBtCore;                              ///< Offset 662     CNVi BT Core
+  UINT8    CnviBtAudioOffload;                      ///< Offset 663     CNVi BT Audio Offload
+  // PCH Trace Hub
+  UINT8    PchTraceHubMode;                         ///< Offset 664     PCH Trace Hub Mode
+  // PCH PS_ON support
+  UINT8    PsOnEnable;                              ///< Offset 665     PCH PS_ON enable
+  //
+  // These are for PchApciTablesSelfTest use
+  //
+  UINT8    LtrEnable[24];                           ///< Offset 666     Latency Tolerance Reporting Enable
+                                                    ///< Offset 667     Latency Tolerance Reporting Enable
+                                                    ///< Offset 668     Latency Tolerance Reporting Enable
+                                                    ///< Offset 669     Latency Tolerance Reporting Enable
+                                                    ///< Offset 670     Latency Tolerance Reporting Enable
+                                                    ///< Offset 671     Latency Tolerance Reporting Enable
+                                                    ///< Offset 672     Latency Tolerance Reporting Enable
+                                                    ///< Offset 673     Latency Tolerance Reporting Enable
+                                                    ///< Offset 674     Latency Tolerance Reporting Enable
+                                                    ///< Offset 675     Latency Tolerance Reporting Enable
+                                                    ///< Offset 676     Latency Tolerance Reporting Enable
+                                                    ///< Offset 677     Latency Tolerance Reporting Enable
+                                                    ///< Offset 678     Latency Tolerance Reporting Enable
+                                                    ///< Offset 679     Latency Tolerance Reporting Enable
+                                                    ///< Offset 680     Latency Tolerance Reporting Enable
+                                                    ///< Offset 681     Latency Tolerance Reporting Enable
+                                                    ///< Offset 682     Latency Tolerance Reporting Enable
+                                                    ///< Offset 683     Latency Tolerance Reporting Enable
+                                                    ///< Offset 684     Latency Tolerance Reporting Enable
+                                                    ///< Offset 685     Latency Tolerance Reporting Enable
+                                                    ///< Offset 686     Latency Tolerance Reporting Enable
+                                                    ///< Offset 687     Latency Tolerance Reporting Enable
+                                                    ///< Offset 688     Latency Tolerance Reporting Enable
+                                                    ///< Offset 689     Latency Tolerance Reporting Enable
+  UINT8    GBES;                                    ///< Offset 690     GbE Support
+  UINT32   PchxDCIPwrDnScale;                       ///< Offset 691     PCH xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19]
+  UINT8    EmmcEnabled;                             ///< Offset 695     Set to indicate that eMMC is enabled
+  UINT8    SdCardEnabled;                           ///< Offset 696     Set to indicate that SD card is enabled
+  UINT8    EnableTimedGpio0;                        ///< Offset 697     Set to indicate that Timed GPIO 0 is enabled
+  UINT8    EnableTimedGpio1;                        ///< Offset 698     Set to indicate that Timed GPIO 1 is enabled
+  UINT8    ClockToRootPortMap[18];                  ///< Offset 699     CLOCK index to root port index map. Used during PCIe D3Cold flows
+  UINT16   TcoBase;                                 ///< Offset 717     TCO base address
+  UINT16   IclkPid;                                 ///< Offset 719     Iclk PID number
+  UINT16   CnviPortId;                              ///< Offset 721     CNVi sideband port id
+  UINT32   HybridStorageLocation;                   ///< Offset 723
+  UINT8    SataPortPresence;                        ///< Offset 727     Holds information from SATA PCS register about SATA ports which recieved COMINIT from connected devices.
+} PCH_NVS_AREA;
+
+#pragma pack(pop)
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h
new file mode 100644
index 0000000000..428858afcf
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h
@@ -0,0 +1,58 @@
+/** @file
+
+  Definitions required to create RstHob
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_RST_HOB_
+#define _PCH_RST_HOB_
+
+extern EFI_GUID  gPchRstHobGuid;
+
+//
+// This struct is used to record the fields that should be restored during device wake up
+//
+typedef struct {
+  UINT8     PmCapPtr;
+  UINT8     PcieCapPtr;
+  UINT16    L1ssCapPtr;
+  UINT8     EndpointL1ssControl2;
+  UINT32    EndpointL1ssControl1;
+  UINT16    LtrCapPtr;
+  UINT32    EndpointLtrData;
+  UINT16    EndpointLctlData16;
+  UINT16    EndpointDctlData16;
+  UINT16    EndpointDctl2Data16;
+  UINT16    RootPortDctl2Data16;
+} SAVED_DEVICE_CONFIG_SPACE;
+
+//
+// This structure is used to record the result of PCIe storageremapping for each cycle router
+//
+typedef struct {
+  UINT8                                 RootPortNum;                      // Indicates the root port number with RST PCIe Storage Remapping remapping supported and PCIe storage device plugged on, numbering is 0-based
+  UINT8                                 DeviceInterface;                  // Indicates the interface of the PCIe storage device (AHCI or NVMe)
+  UINT32                                EndPointUniqueMsixTableBar;       // Records the PCIe storage device's MSI-X Table BAR if it supports unique MSI-X Table BAR
+  UINT32                                EndPointUniqueMsixTableBarValue;  // Records the PCIe storage device's MSI-X Table BAR value if it supports unique MSI-X Table BAR
+  UINT32                                EndPointUniqueMsixPbaBar;         // Records the PCIe storage device's MSI-X PBA BAR if it supports unique MSI-X PBA BAR
+  UINT32                                EndPointUniqueMsixPbaBarValue;    // Records the PCIe storage device's MSI-X PBA BAR value if it supports unique MSI-X PBA BAR
+} RST_CR_CONFIGURATION;
+
+//
+//  Passes to DXE results of PCIe storage remapping
+//
+typedef struct {
+  //
+  // Stores configuration information about cycle router
+  //
+  RST_CR_CONFIGURATION  RstCrConfiguration[PCH_MAX_RST_PCIE_STORAGE_CR];
+
+  //
+  // Saved fields from hidden device config space to be used later by RST driver
+  //
+  SAVED_DEVICE_CONFIG_SPACE  SavedRemapedDeviceConfigSpace[PCH_MAX_RST_PCIE_STORAGE_CR];
+} PCH_RST_HOB;
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h
new file mode 100644
index 0000000000..1c45d89225
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h
@@ -0,0 +1,30 @@
+/** @file
+  This file defines the PCH NVS Area Protocol.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PCH_NVS_AREA_H_
+#define _PCH_NVS_AREA_H_
+
+//
+// PCH NVS Area definition
+//
+#include <Pch/IncludePrivate/PchNvsAreaDef.h>
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID                         gPchNvsAreaProtocolGuid;
+
+/**
+  This protocol is used to sync PCH information from POST to runtime ASL.
+  This protocol exposes the pointer of PCH NVS Area only. Please refer to
+  ASL definition for PCH NVS AREA.
+**/
+typedef struct {
+  PCH_NVS_AREA                          *Area;
+} PCH_NVS_AREA_PROTOCOL;
+
+#endif // _PCH_NVS_AREA_H_
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h
new file mode 100644
index 0000000000..ecea5db4fc
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h
@@ -0,0 +1,35 @@
+/** @file
+  This file defines the PCH PCIE IoTrap Protocol.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _PCH_PCIE_IOTRAP_H_
+#define _PCH_PCIE_IOTRAP_H_
+
+//
+// Extern the GUID for protocol users.
+//
+extern EFI_GUID                       gPchPcieIoTrapProtocolGuid;
+
+//
+// Forward reference for ANSI C compatibility
+//
+typedef struct _PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL;
+
+///
+/// Pcie Trap valid types
+///
+typedef enum {
+  PchPciePmTrap,
+  PcieTrapTypeMaximum
+} PCH_PCIE_TRAP_TYPE;
+
+/**
+ This protocol is used to provide the IoTrap address to trigger PCH PCIE call back events
+**/
+struct _PCH_PCIE_IOTRAP_PROTOCOL {
+  UINT16      PcieTrapAddress;
+};
+
+#endif
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h
new file mode 100644
index 0000000000..0d9b167588
--- /dev/null
+++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h
@@ -0,0 +1,21 @@
+/** @file
+  This file contains definitions of Si Schedule Reset HOB.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#ifndef _SI_SCHEDULE_RESET_HOB_H_
+#define _SI_SCHEDULE_RESET_HOB_H_
+
+/**
+  This structure is used to provide information about PCH Resets
+**/
+typedef struct {
+  EFI_RESET_TYPE             ResetType;
+  PCH_RESET_DATA             ResetData;
+} SI_SCHEDULE_RESET_HOB;
+
+extern EFI_GUID gSiScheduleResetHobGuid;
+
+#endif // _SI_SCHEDULE_RESET_HOB_H_
+
-- 
2.24.0.windows.2


  parent reply	other threads:[~2021-02-05  7:41 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-05  7:40 [Patch V3 01/40] TigerlakeSiliconPkg: Add package and Include/ConfigBlock headers Heng Luo
2021-02-05  7:40 ` [Patch V3 02/40] TigerlakeSiliconPkg/Include: Add Library, PPI and Protocol include headers Heng Luo
2021-02-05  7:40 ` [Patch V3 03/40] TigerlakeSiliconPkg/Include: Add Pins, Register and other " Heng Luo
2021-02-05  7:40 ` [Patch V3 04/40] TigerlakeSiliconPkg/Cpu: Add Include headers Heng Luo
2021-02-05  7:40 ` [Patch V3 05/40] TigerlakeSiliconPkg/Pch: Add include headers Heng Luo
2021-02-05  7:40 ` Heng Luo [this message]
2021-02-05  7:40 ` [Patch V3 07/40] TigerlakeSiliconPkg/SystemAgent: " Heng Luo
2021-02-05  7:40 ` [Patch V3 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Heng Luo
2021-02-05  7:40 ` [Patch V3 09/40] TigerlakeSiliconPkg/Fru: Add TglCpu/Include headers Heng Luo
2021-02-05  7:40 ` [Patch V3 10/40] TigerlakeSiliconPkg/Fru: Add TglCpu/IncludePrivate headers Heng Luo
2021-02-05  7:40 ` [Patch V3 11/40] TigerlakeSiliconPkg/Fru: Add TglPch/Include headers Heng Luo
2021-02-05  7:40 ` [Patch V3 12/40] TigerlakeSiliconPkg/Fru: Add TglPch/IncludePrivate headers Heng Luo
2021-02-05  7:40 ` [Patch V3 13/40] TigerlakeSiliconPkg/IpBlock: Add Cnvi component Heng Luo
2021-02-05  7:40 ` [Patch V3 14/40] TigerlakeSiliconPkg/IpBlock: Add CpuPcieRp component Heng Luo
2021-02-05  7:40 ` [Patch V3 15/40] TigerlakeSiliconPkg/IpBlock: Add Espi component Heng Luo
2021-02-05  7:40 ` [Patch V3 16/40] TigerlakeSiliconPkg/IpBlock: Add Gbe component Heng Luo
2021-02-05  7:40 ` [Patch V3 17/40] TigerlakeSiliconPkg/IpBlock: Add Gpio component Heng Luo
2021-02-05  7:40 ` [Patch V3 18/40] TigerlakeSiliconPkg/IpBlock: Add Graphics component Heng Luo
2021-02-05  7:40 ` [Patch V3 19/40] TigerlakeSiliconPkg/IpBlock: Add Hda component Heng Luo
2021-02-05  7:40 ` [Patch V3 20/40] TigerlakeSiliconPkg/IpBlock: Add HostBridge component Heng Luo
2021-02-05  7:40 ` [Patch V3 21/40] TigerlakeSiliconPkg/IpBlock: Add P2sb component Heng Luo
2021-02-05  7:40 ` [Patch V3 22/40] TigerlakeSiliconPkg/IpBlock: Add PchDmi component Heng Luo
2021-02-05  7:40 ` [Patch V3 23/40] TigerlakeSiliconPkg/IpBlock: Add PcieRp component Heng Luo
2021-02-05  7:40 ` [Patch V3 24/40] TigerlakeSiliconPkg/IpBlock: Add Pmc component Heng Luo
2021-02-05  7:40 ` [Patch V3 25/40] TigerlakeSiliconPkg/IpBlock: Add Psf component Heng Luo
2021-02-05  7:40 ` [Patch V3 26/40] TigerlakeSiliconPkg/IpBlock: Add Sata component Heng Luo
2021-02-05  7:40 ` [Patch V3 27/40] TigerlakeSiliconPkg/IpBlock: Add SerialIo component Heng Luo
2021-02-05  7:40 ` [Patch V3 28/40] TigerlakeSiliconPkg/IpBlock: Add Smbus component Heng Luo
2021-02-05  7:40 ` [Patch V3 29/40] TigerlakeSiliconPkg/IpBlock: Add Spi component Heng Luo
2021-02-05  7:40 ` [Patch V3 30/40] TigerlakeSiliconPkg/IpBlock: Add Vtd component Heng Luo
2021-02-05  7:40 ` [Patch V3 31/40] TigerlakeSiliconPkg/Library: Add package common library instances Heng Luo
2021-02-05  7:40 ` [Patch V3 32/40] TigerlakeSiliconPkg/Pch: Add Pch " Heng Luo
2021-02-05  7:40 ` [Patch V3 33/40] TigerlakeSiliconPkg/Pch: Add Pch private " Heng Luo
2021-02-05  7:40 ` [Patch V3 34/40] TigerlakeSiliconPkg/SystemAgent: Add Acpi Tables and " Heng Luo
2021-02-05  7:40 ` [Patch V3 35/40] TigerlakeSiliconPkg/Fru/TglCpu: Add CpuPcieRp and Vtd " Heng Luo
2021-02-05  7:40 ` [Patch V3 36/40] TigerlakeSiliconPkg/Pch: Add Pch modules Heng Luo
2021-02-05  7:40 ` [Patch V3 37/40] TigerlakeSiliconPkg/SystemAgent: Add SystemAgent modules Heng Luo
2021-02-05  7:40 ` [Patch V3 38/40] TigerlakeSiliconPkg/Fru: Add Fru DSC files Heng Luo
2021-02-05  7:40 ` [Patch V3 39/40] TigerlakeSiliconPkg: Add package " Heng Luo
2021-02-05  7:40 ` [Patch V3 40/40] Maintainers.txt: Add TigerlakeSiliconPkg maintainers Heng Luo
2021-02-05 18:36   ` Nate DeSimone
2021-02-05 18:57     ` Chaganty, Rangasai V

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