From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web10.5193.1612510886959585337 for ; Thu, 04 Feb 2021 23:41:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: heng.luo@intel.com) IronPort-SDR: sRaDmEmwE630odV2qzyG0UGSFvZKAzPtTFX4/7Tpf2CtbdgX7sPpfNHQKgJShz+DEWK8WwJEbO 6RdNENq5uCaA== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543620" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543620" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:25 -0800 IronPort-SDR: v7EhsU6mu6i1Y4FV1CyjvVxJ7TFCZeLLlkEAHKUTVRDyM6Q4iPgnLAI092LBgJu53m2bznrToB YuCOH8AKkUEg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260243" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:24 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 06/40] TigerlakeSiliconPkg/Pch: Add IncludePrivate headers Date: Fri, 5 Feb 2021 15:40:11 +0800 Message-Id: <20210205074045.3916-6-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * Pch/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiScheduleRes= etLib.h | 47 +++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPrivate= Lib.h | 26 ++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h = | 269 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorageHob.h= | 21 +++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h = | 319 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h = | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsArea.h= | 30 ++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoTrap.h= | 35 +++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetHob.h = | 21 +++++++++++++++++++++ 9 files changed, 826 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/S= iScheduleResetLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/= Library/SiScheduleResetLib.h new file mode 100644 index 0000000000..2ad80a0269 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SiSchedu= leResetLib.h @@ -0,0 +1,47 @@ +/** @file=0D + Reset scheduling library services=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SI_SCHEDULE_RESET_LIB_H_=0D +#define _SI_SCHEDULE_RESET_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +/**=0D + This function updates the reset information in SiScheduleResetHob=0D + @param[in] ResetType UEFI defined reset type.=0D + @param[in] ResetData Optional element used to introduce a platfor= m specific reset.=0D + The exact type of the reset is defined by t= he EFI_GUID that follows=0D + the Null-terminated Unicode string.=0D +**/=0D +VOID=0D +SiScheduleResetSetType (=0D + IN EFI_RESET_TYPE ResetType,=0D + IN PCH_RESET_DATA *ResetData OPTIONAL=0D + );=0D +=0D +/**=0D + This function returns TRUE or FALSE depending on whether a reset is requ= ired based on SiScheduleResetHob=0D +=0D + @retval BOOLEAN The function returns FALSE if no reset is requ= ired=0D +**/=0D +BOOLEAN=0D +SiScheduleResetIsRequired (=0D + VOID=0D + );=0D +=0D +/**=0D + This function performs reset based on SiScheduleResetHob=0D +=0D + @retval BOOLEAN The function returns FALSE if no reset is requ= ired=0D +**/=0D +BOOLEAN=0D +SiScheduleResetPerformReset (=0D + VOID=0D + );=0D +=0D +#endif //_SI_SCHEDULE_RESET_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/S= mmPchPrivateLib.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Li= brary/SmmPchPrivateLib.h new file mode 100644 index 0000000000..955dac5a82 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Library/SmmPchPr= ivateLib.h @@ -0,0 +1,26 @@ +/** @file=0D + Header file for private PCH SMM Lib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SMM_PCH_PRIVATE_LIB_H_=0D +#define _SMM_PCH_PRIVATE_LIB_H_=0D +=0D +/**=0D + Set InSmm.Sts bit=0D +**/=0D +VOID=0D +PchSetInSmmSts (=0D + VOID=0D + );=0D +=0D +/**=0D + Clear InSmm.Sts bit=0D +**/=0D +VOID=0D +PchClearInSmmSts (=0D + VOID=0D + );=0D +=0D +#endif // _SMM_PCH_PRIVATE_LIB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfig= Hob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h new file mode 100644 index 0000000000..13a41f8d04 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchConfigHob.h @@ -0,0 +1,269 @@ +/** @file=0D + The GUID definition for PchConfigHob=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_CONFIG_HOB_H_=0D +#define _PCH_CONFIG_HOB_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +=0D +extern EFI_GUID gPchConfigHobGuid;=0D +=0D +#pragma pack (push,1)=0D +=0D +/**=0D + This structure contains the HOB which are related to PCH general config.= =0D +**/=0D +typedef struct {=0D + /**=0D + This member describes whether or not the Compatibility Revision ID (CR= ID) feature=0D + of PCH should be enabled. 0: Disable; 1: Enable=0D + **/=0D + UINT32 Crid : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} GENERAL_HOB;=0D +=0D +/**=0D + The SMBUS_CONFIG block lists the reserved addresses for non-ARP capable = devices in the platform.=0D +**/=0D +typedef struct {=0D + UINT8 RsvdBytes[3]; ///< Reserved bytes=0D + UINT8 NumRsvdSmbusAddresses; ///< The number of elements in the RsvdSmbu= sAddressTable.=0D + /**=0D + Array of addresses reserved for non-ARP-capable SMBus devices.=0D + **/=0D + UINT8 RsvdSmbusAddressTable[PCH_MAX_SMBUS_RESERVED_ADDRESS];=0D +} SMBUS_HOB;=0D +=0D +/**=0D + The INTERRUPT_HOB describes interrupt settings for PCH.=0D +**/=0D +typedef struct {=0D + UINT8 NumOfDevIntConfig; = ///< Number of entries in DevIntConfig table=0D + UINT8 GpioIrqRoute; = ///< Interrupt routing for GPIO. Default is 14.=0D + UINT8 Rsvd0[2]; = ///< Reserved bytes, align to multiple 4.=0D + PCH_DEVICE_INTERRUPT_CONFIG DevIntConfig[PCH_MAX_DEVICE_INTERRUPT_CONFI= G]; ///< Array which stores PCH devices interrupts settings=0D +} INTERRUPT_HOB;=0D +=0D +/**=0D + The SERIAL_IO block provides the configurations to set the Serial IO con= trollers=0D +**/=0D +typedef struct {=0D + SERIAL_IO_SPI_CONFIG SpiDeviceConfig[PCH_MAX_SERIALIO_SPI_CONTROLLERS];= ///< SPI Configuration=0D + SERIAL_IO_I2C_CONFIG I2cDeviceConfig[PCH_MAX_SERIALIO_I2C_CONTROLLERS];= ///< I2C Configuration=0D + SERIAL_IO_UART_CONFIG UartDeviceConfig[PCH_MAX_SERIALIO_UART_CONTROLLERS= ]; ///< UART Configuration=0D +} SERIAL_IO_HOB;=0D +=0D +/**=0D + The PCIERP_HOB block describes the expected configuration of the PCH PCI= Express controllers=0D +**/=0D +typedef struct {=0D + ///=0D + /// These members describe the configuration of each PCH PCIe root port.= =0D + ///=0D + PCH_PCIE_ROOT_PORT_CONFIG RootPort[PCH_MAX_PCIE_ROOT_PORTS];=0D + PCH_PCIE_CLOCK PcieClock[PCH_MAX_PCIE_CLOCKS];=0D + /**=0D + This member allows BIOS to control ICC PLL Shutdown by determining PCI= e devices are LTR capable=0D + or leaving untouched.=0D + - 0: Disable, ICC PLL Shutdown is determined by PCIe device LTR cap= ablility.=0D + - To allow ICC PLL shutdown if all present PCIe devices are LTR capa= ble or if no PCIe devices are=0D + presented for maximum power savings where possible.=0D + - To disable ICC PLL shutdown when BIOS detects any non-LTR capable = PCIe device for ensuring device=0D + functionality.=0D + - 1: Enable, To allow ICC PLL shutdown even if some devices do not sup= port LTR capability.=0D + **/=0D + UINT32 AllowNoLtrIccPllShutdown : 1;=0D + UINT32 RsvdBits0 : 31; ///< Reserved bits=0D +} PCIERP_HOB;=0D +=0D +/**=0D + The HDAUDIO_HOB block describes the configuration of the PCH cAVS contro= ller=0D +**/=0D +typedef struct {=0D + UINT32 DspEnable : 1; ///< DSP enablement: 0: Disable; = 1: Enable=0D + UINT32 DspUaaCompliance : 1; ///< UAA-mode Select: 0: Non-Uaa<= /b>; 1: UAA=0D + UINT32 CodecSxWakeCapability : 1; ///< Capability to detect wake initi= ated by a codec in Sx, 0: Disable; 1: Enable=0D + UINT32 AudioLinkSndw1 : 1; ///< SoundWire1 link enablement: = 0: Disable; 1: Enable. Muxed with HDA=0D + UINT32 AudioLinkSndw2 : 1; ///< SoundWire2 link enablement: = 0: Disable; 1: Enable. Muxed with SSP1=0D + UINT32 AudioLinkSndw3 : 1; ///< SoundWire3 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC1=0D + UINT32 AudioLinkSndw4 : 1; ///< SoundWire4 link enablement: = 0: Disable; 1: Enable. Muxed with DMIC0=0D + UINT32 Pme : 1; ///< Azalia wake-on-ring, 0: Disa= ble; 1: Enable=0D + UINT32 RsvdBits0 : 24; ///< Reserved bits=0D +} HDAUDIO_HOB;=0D +=0D +/**=0D + The SATA_HOB block describes the configuration of the PCH SATA controlle= rs=0D +**/=0D +typedef struct {=0D + /**=0D + This member describes whether or not the SATA controllers should be en= abled. 0: Disable; 1: Enable.=0D + **/=0D + UINT32 Enable : 1;=0D + UINT32 TestMode : 1; ///< (Test) <= b>0: Disable; 1: Allow entrance to the PCH SATA test modes=0D + UINT32 RsvdBits0 : 30; ///< Reserved bits=0D + /**=0D + This member configures the features, property, and capability for each= SATA port.=0D + **/=0D + PCH_SATA_PORT_CONFIG PortSettings[PCH_MAX_SATA_PORTS];=0D +} SATA_HOB;=0D +=0D +/**=0D + The RST block describes the configuration of the RST PCIE Cycle Routers= =0D +**/=0D +typedef struct {=0D + /**=0D + This member describes the details of implementation of Intel RST for P= CIe Storage remapping (Intel RST Driver is required)=0D + **/=0D + RST_HARDWARE_REMAPPED_STORAGE_CONFIG RstHardwareRemappedStorageConfig[= PCH_MAX_RST_PCIE_STORAGE_CR];=0D +} RST_HOB;=0D +=0D +typedef struct {=0D + UINT32 Enabled : 1; ///< Indicates that SD card has been enabled=0D + UINT32 Reserved : 31;=0D +} SD_CARD_HOB;=0D +=0D +/**=0D + The EMMC_HOB block describes integrated eMMC settings for PCH.=0D +**/=0D +typedef struct {=0D + UINT32 Enabled : 1; ///< Determine if eMMC is en= abled - 0: Disabled, 1: Enabled.=0D + UINT32 Hs400Enabled : 1; ///< Determine eMMC HS400 Mo= de if EmmcEnabled - 0: Disabled, 1: Enabled=0D + /**=0D + Determine if HS400 Training is required, set to FALSE if Hs400 Data is= valid. 0: Disabled, 1: Enabled.=0D + First Boot or CMOS clear, system boot with Default settings, set tunin= g required.=0D + Subsequent Boots, Get Variable 'Hs400TuningData'=0D + - if failed to get variable, set tuning required=0D + - if passed, retrieve Hs400DataValid, Hs400RxStrobe1Dll and Hs400TxD= ataDll from variable. Set tuning not required.=0D + **/=0D + UINT32 Hs400DllDataValid : 1; ///< Set if HS400 Tuning Dat= a Valid=0D + UINT32 RsvdBits : 29;=0D +} EMMC_HOB;=0D +=0D +/**=0D + The PCH_LOCK_DOWN_CONFIG block describes the expected configuration of t= he PCH=0D + for security requirement.=0D +**/=0D +typedef struct {=0D + UINT32 GlobalSmi : 1;=0D + /**=0D + (Test) Enable BIOS Interface Lock Down bit to prevent writes to= the Backup Control Register=0D + Top Swap bit and the General Control and Status Registers Boot BIOS St= raps. 0: Disable; 1: Enable.=0D + **/=0D + UINT32 BiosInterface : 1;=0D + /**=0D + Enable the BIOS Lock Enable (BLE) feature and set EISS bit (D31:F5:Reg= DCh[5])=0D + for the BIOS region protection. When it is enabled, the BIOS Region ca= n only be=0D + modified from SMM after EndOfDxe protocol is installed.=0D + Note: When BiosLock is enabled, platform code also needs to update to = take care=0D + of BIOS modification (including SetVariable) in DXE or runtime phase a= fter=0D + EndOfDxe protocol is installed.=0D + Enable InSMM.STS (EISS) in SPI=0D + If this EISS bit is set, then WPD must be a '1' and InSMM.STS must be = '1' also=0D + in order to write to BIOS regions of SPI Flash. If this EISS bit is cl= ear,=0D + then the InSMM.STS is a don't care.=0D + The BIOS must set the EISS bit while BIOS Guard support is enabled.=0D + In recovery path, platform can temporary disable EISS for SPI programm= ing in=0D + PEI phase or early DXE phase.=0D + 0: Disable; 1: Enable.=0D + **/=0D + UINT32 BiosLock : 1;=0D + UINT32 RsvdBits : 29;=0D +} LOCK_DOWN_HOB;=0D +=0D +/**=0D + The PM_HOB block describes expected miscellaneous power management setti= ngs.=0D + The PowerResetStatusClear field would clear the Power/Reset status bits,= please=0D + set the bits if you want PCH Init driver to clear it, if you want to che= ck the=0D + status later then clear the bits.=0D +**/=0D +typedef struct {=0D + UINT32 PsOnEnable : 1; ///< Indicates if PS_ON support has = been enabled, 0: Disable; 1: Enable.=0D + UINT32 EnableTimedGpio0 : 1; ///< Enable Bit for Timed GPIO 0 = 0 =3D disable; 1 =3D enable=0D + UINT32 EnableTimedGpio1 : 1; ///< Enable Bit for Timed GPIO 1 = 0 =3D disable; 1 =3D enable=0D + UINT32 RsvdBits1 : 29;=0D +} PM_HOB;=0D +=0D +/**=0D + FIVR_HOB block=0D +**/=0D +typedef struct {=0D + /**=0D + Additional External Vnn VR rail configuration dedicated for Sx.=0D + Required only if External Vnn VR needs different settings for Sx than= =0D + those specified in ExtVnnRail (refer to PCH_FIVR_CONFIG.ExtVnnRail)=0D + **/=0D + FIVR_EXT_RAIL_CONFIG ExtVnnRailSx;=0D +} FIVR_HOB;=0D +=0D +/**=0D + PCH Trace Hub HOB settings.=0D +**/=0D +typedef struct {=0D + UINT32 PchTraceHubMode : 2; ///< 0 =3D Disable; 1 =3D Tar= get Debugger mode; 2 =3D Host Debugger mode=0D + UINT32 Rsvd1 : 30; ///< Reserved bits=0D + /**=0D + Trace hub memory buffer region size policy.=0D + The avaliable memory size options are: 0:0MB (none), 1:1MB, 2:8MB, 3:64MB, 4:128MB, 5:256MB, 6:512MB.=0D + Note : Limitation of total buffer size (CPU + PCH) is 512MB. If iTbt i= s enabled, the total size limits to 256 MB.=0D + Refer to TRACE_BUFFER_SIZE=0D + **/=0D + UINT32 MemReg0Size;=0D + UINT32 MemReg1Size;=0D +} PCH_TRACEHUB_HOB;=0D +=0D +/**=0D + PCH eSPI HOB settings.=0D +**/=0D +typedef struct {=0D + UINT32 BmeMasterSlaveEnabled : 1; ///< 0 =3D BME disable; 1 =3D= BME enable=0D + UINT32 RsvdBits : 31; ///< Reserved bits=0D +} PCH_ESPI_HOB;=0D +=0D +/**=0D + THC HOB settings.=0D +**/=0D +typedef struct {=0D + THC_PORT ThcPort[2]; ///< Port Configuration=0D +} THC_HOB;=0D +=0D +=0D +/**=0D + This structure contains the HOBs which are related to PCH controllers=0D +**/=0D +typedef struct {=0D + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< GUID HOB type structure for = gPchConfigHobGuid=0D + GENERAL_HOB General; ///< Pch general HOB definition=0D + INTERRUPT_HOB Interrupt; ///< Interrupt HOB definition=0D + SERIAL_IO_HOB SerialIo; ///< Serial io HOB definition=0D + PCIERP_HOB PcieRp; ///< PCIE root port HOB definitio= n=0D + SD_CARD_HOB SdCard; ///< SD card HOB definition=0D + EMMC_HOB Emmc; ///< eMMC HOB definition=0D + LOCK_DOWN_HOB LockDown; ///< Lock down HOB definition=0D + PM_HOB Pm; ///< PM HOB definition=0D + HDAUDIO_HOB HdAudio; ///< HD audio definition=0D + SATA_HOB Sata[PCH_MAX_SATA_CONTROLLERS]; ///< SATA definition= =0D + RST_HOB Rst; ///< RST definition=0D + PROTECTED_RANGE ProtectRange[PCH_FLASH_PROTECTED_RANGES];=0D + SMBUS_HOB Smbus;=0D + PCH_TRACEHUB_HOB PchTraceHub; ///< PCH Trace Hub definition=0D + PCH_ESPI_HOB Espi; ///< PCH eSPI definition=0D + THC_HOB Thc; ///< PCH Tocuh Host Controller de= finition=0D + FIVR_HOB Fivr; ///< PCH FIVR HOB definition=0D +=0D +=0D +} PCH_CONFIG_HOB;=0D +#pragma pack (pop)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybrid= StorageHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybr= idStorageHob.h new file mode 100644 index 0000000000..040bc270e6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchHybridStorage= Hob.h @@ -0,0 +1,21 @@ +/** @file=0D +=0D + Definitions required to create HybridStorageHob=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PCH_HYBRIDSTORAGE_HOB_=0D +#define _PCH_HYBRIDSTORAGE_HOB_=0D +=0D +extern EFI_GUID gHybridStorageHobGuid;=0D +=0D +//=0D +// Passes to DXE Hybrid Storage location=0D +//=0D +typedef struct {=0D + UINT32 HybridStorageLocation;=0D +} PCH_HYBRIDSTORAGE_HOB;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAre= aDef.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef= .h new file mode 100644 index 0000000000..200f3ca8fa --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchNvsAreaDef.h @@ -0,0 +1,319 @@ +//=0D +// Automatically generated by GenNvs ver 2.4.6=0D +// Please DO NOT modify !!!=0D +//=0D +=0D +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D + //=0D + // Define PCH NVS Area operatino region.=0D + //=0D +#ifndef _PCH_NVS_AREA_DEF_H_=0D +#define _PCH_NVS_AREA_DEF_H_=0D +=0D +#pragma pack (push,1)=0D +typedef struct {=0D + UINT16 PchSeries; ///< Offset 0 PC= H Series=0D + UINT16 PchGeneration; ///< Offset 2 PC= H Generation=0D + UINT16 PchStepping; ///< Offset 4 PC= H Stepping=0D + UINT32 RpAddress[28]; ///< Offset 6 Ro= ot Port address 1=0D + ///< Offset 10 Ro= ot Port address 2=0D + ///< Offset 14 Ro= ot Port address 3=0D + ///< Offset 18 Ro= ot Port address 4=0D + ///< Offset 22 Ro= ot Port address 5=0D + ///< Offset 26 Ro= ot Port address 6=0D + ///< Offset 30 Ro= ot Port address 7=0D + ///< Offset 34 Ro= ot Port address 8=0D + ///< Offset 38 Ro= ot Port address 9=0D + ///< Offset 42 Ro= ot Port address 10=0D + ///< Offset 46 Ro= ot Port address 11=0D + ///< Offset 50 Ro= ot Port address 12=0D + ///< Offset 54 Ro= ot Port address 13=0D + ///< Offset 58 Ro= ot Port address 14=0D + ///< Offset 62 Ro= ot Port address 15=0D + ///< Offset 66 Ro= ot Port address 16=0D + ///< Offset 70 Ro= ot Port address 17=0D + ///< Offset 74 Ro= ot Port address 18=0D + ///< Offset 78 Ro= ot Port address 19=0D + ///< Offset 82 Ro= ot Port address 20=0D + ///< Offset 86 Ro= ot Port address 21=0D + ///< Offset 90 Ro= ot Port address 22=0D + ///< Offset 94 Ro= ot Port address 23=0D + ///< Offset 98 Ro= ot Port address 24=0D + ///< Offset 102 Ro= ot Port address 25=0D + ///< Offset 106 Ro= ot Port address 26=0D + ///< Offset 110 Ro= ot Port address 27=0D + ///< Offset 114 Ro= ot Port address 28=0D + UINT64 NHLA; ///< Offset 118 HD= -Audio NHLT ACPI address=0D + UINT32 NHLL; ///< Offset 126 HD= -Audio NHLT ACPI length=0D + UINT32 ADFM; ///< Offset 130 HD= -Audio DSP Feature Mask=0D + UINT8 SWQ0; ///< Offset 134 HD= -Audio SoundWire Link #1 quirk mask=0D + UINT8 SWQ1; ///< Offset 135 HD= -Audio SoundWire Link #2 quirk mask=0D + UINT8 SWQ2; ///< Offset 136 HD= -Audio SoundWire Link #3 quirk mask=0D + UINT8 SWQ3; ///< Offset 137 HD= -Audio SoundWire Link #4 quirk mask=0D + UINT8 ACS0; ///< Offset 138 HD= -Audio SoundWire Link #1 Autonomous Clock Stop=0D + UINT8 ACS1; ///< Offset 139 HD= -Audio SoundWire Link #2 Autonomous Clock Stop=0D + UINT8 ACS2; ///< Offset 140 HD= -Audio SoundWire Link #3 Autonomous Clock Stop=0D + UINT8 ACS3; ///< Offset 141 HD= -Audio SoundWire Link #4 Autonomous Clock Stop=0D + UINT8 DAI0; ///< Offset 142 HD= -Audio SoundWire Link #1 Data On Active Interval Select=0D + UINT8 DAI1; ///< Offset 143 HD= -Audio SoundWire Link #2 Data On Active Interval Select=0D + UINT8 DAI2; ///< Offset 144 HD= -Audio SoundWire Link #3 Data On Active Interval Select=0D + UINT8 DAI3; ///< Offset 145 HD= -Audio SoundWire Link #4 Data On Active Interval Select=0D + UINT8 DOD0; ///< Offset 146 HD= -Audio SoundWire Link #1 Data On Delay Select=0D + UINT8 DOD1; ///< Offset 147 HD= -Audio SoundWire Link #2 Data On Delay Select=0D + UINT8 DOD2; ///< Offset 148 HD= -Audio SoundWire Link #3 Data On Delay Select=0D + UINT8 DOD3; ///< Offset 149 HD= -Audio SoundWire Link #4 Data On Delay Select=0D + UINT8 SWMC; ///< Offset 150 HD= -Audio SoundWire Master Count=0D + UINT8 XTAL; ///< Offset 151 XT= AL frequency: 0: 24MHz; 1: 38.4MHz; 2: Unsupported=0D + UINT32 DSPM; ///< Offset 152 HD= -Audio DSP Stolen Memory Base Address (@todo: Remove after CNL-LP B0)=0D + UINT32 SBRG; ///< Offset 156 SB= REG_BAR=0D + UINT8 GEI0; ///< Offset 160 GP= IO GroupIndex mapped to GPE_DW0=0D + UINT8 GEI1; ///< Offset 161 GP= IO GroupIndex mapped to GPE_DW1=0D + UINT8 GEI2; ///< Offset 162 GP= IO GroupIndex mapped to GPE_DW2=0D + UINT8 GED0; ///< Offset 163 GP= IO DW part of group mapped to GPE_DW0=0D + UINT8 GED1; ///< Offset 164 GP= IO DW part of group mapped to GPE_DW1=0D + UINT8 GED2; ///< Offset 165 GP= IO DW part of group mapped to GPE_DW2=0D + UINT16 PcieLtrMaxSnoopLatency[28]; ///< Offset 166 PC= IE LTR max snoop Latency 1=0D + ///< Offset 168 PC= IE LTR max snoop Latency 2=0D + ///< Offset 170 PC= IE LTR max snoop Latency 3=0D + ///< Offset 172 PC= IE LTR max snoop Latency 4=0D + ///< Offset 174 PC= IE LTR max snoop Latency 5=0D + ///< Offset 176 PC= IE LTR max snoop Latency 6=0D + ///< Offset 178 PC= IE LTR max snoop Latency 7=0D + ///< Offset 180 PC= IE LTR max snoop Latency 8=0D + ///< Offset 182 PC= IE LTR max snoop Latency 9=0D + ///< Offset 184 PC= IE LTR max snoop Latency 10=0D + ///< Offset 186 PC= IE LTR max snoop Latency 11=0D + ///< Offset 188 PC= IE LTR max snoop Latency 12=0D + ///< Offset 190 PC= IE LTR max snoop Latency 13=0D + ///< Offset 192 PC= IE LTR max snoop Latency 14=0D + ///< Offset 194 PC= IE LTR max snoop Latency 15=0D + ///< Offset 196 PC= IE LTR max snoop Latency 16=0D + ///< Offset 198 PC= IE LTR max snoop Latency 17=0D + ///< Offset 200 PC= IE LTR max snoop Latency 18=0D + ///< Offset 202 PC= IE LTR max snoop Latency 19=0D + ///< Offset 204 PC= IE LTR max snoop Latency 20=0D + ///< Offset 206 PC= IE LTR max snoop Latency 21=0D + ///< Offset 208 PC= IE LTR max snoop Latency 22=0D + ///< Offset 210 PC= IE LTR max snoop Latency 23=0D + ///< Offset 212 PC= IE LTR max snoop Latency 24=0D + ///< Offset 214 PC= IE LTR max snoop Latency 25=0D + ///< Offset 216 PC= IE LTR max snoop Latency 26=0D + ///< Offset 218 PC= IE LTR max snoop Latency 27=0D + ///< Offset 220 PC= IE LTR max snoop Latency 28=0D + UINT16 PcieLtrMaxNoSnoopLatency[28]; ///< Offset 222 PC= IE LTR max no snoop Latency 1=0D + ///< Offset 224 PC= IE LTR max no snoop Latency 2=0D + ///< Offset 226 PC= IE LTR max no snoop Latency 3=0D + ///< Offset 228 PC= IE LTR max no snoop Latency 4=0D + ///< Offset 230 PC= IE LTR max no snoop Latency 5=0D + ///< Offset 232 PC= IE LTR max no snoop Latency 6=0D + ///< Offset 234 PC= IE LTR max no snoop Latency 7=0D + ///< Offset 236 PC= IE LTR max no snoop Latency 8=0D + ///< Offset 238 PC= IE LTR max no snoop Latency 9=0D + ///< Offset 240 PC= IE LTR max no snoop Latency 10=0D + ///< Offset 242 PC= IE LTR max no snoop Latency 11=0D + ///< Offset 244 PC= IE LTR max no snoop Latency 12=0D + ///< Offset 246 PC= IE LTR max no snoop Latency 13=0D + ///< Offset 248 PC= IE LTR max no snoop Latency 14=0D + ///< Offset 250 PC= IE LTR max no snoop Latency 15=0D + ///< Offset 252 PC= IE LTR max no snoop Latency 16=0D + ///< Offset 254 PC= IE LTR max no snoop Latency 17=0D + ///< Offset 256 PC= IE LTR max no snoop Latency 18=0D + ///< Offset 258 PC= IE LTR max no snoop Latency 19=0D + ///< Offset 260 PC= IE LTR max no snoop Latency 20=0D + ///< Offset 262 PC= IE LTR max no snoop Latency 21=0D + ///< Offset 264 PC= IE LTR max no snoop Latency 22=0D + ///< Offset 266 PC= IE LTR max no snoop Latency 23=0D + ///< Offset 268 PC= IE LTR max no snoop Latency 24=0D + ///< Offset 270 PC= IE LTR max no snoop Latency 25=0D + ///< Offset 272 PC= IE LTR max no snoop Latency 26=0D + ///< Offset 274 PC= IE LTR max no snoop Latency 27=0D + ///< Offset 276 PC= IE LTR max no snoop Latency 28=0D + UINT8 XHPC; ///< Offset 278 Nu= mber of HighSpeed ports implemented in XHCI controller=0D + UINT8 XRPC; ///< Offset 279 Nu= mber of USBR ports implemented in XHCI controller=0D + UINT8 XSPC; ///< Offset 280 Nu= mber of SuperSpeed ports implemented in XHCI controller=0D + UINT8 XSPA; ///< Offset 281 Ad= dress of 1st SuperSpeed port=0D + UINT32 HPTB; ///< Offset 282 HP= ET base address=0D + UINT8 HPTE; ///< Offset 286 HP= ET enable=0D + //SerialIo block=0D + UINT8 SM0[7]; ///< Offset 287 Se= rialIo SPI Controller 0 Mode=0D + ///< Offset 288 Se= rialIo SPI Controller 1 Mode=0D + ///< Offset 289 Se= rialIo SPI Controller 2 Mode=0D + ///< Offset 290 Se= rialIo SPI Controller 3 Mode=0D + ///< Offset 291 Se= rialIo SPI Controller 4 Mode=0D + ///< Offset 292 Se= rialIo SPI Controller 5 Mode=0D + ///< Offset 293 Se= rialIo SPI Controller 6 Mode=0D + UINT64 SC0[7]; ///< Offset 294 Se= rialIo SPI Controller 0 Pci Config=0D + ///< Offset 302 Se= rialIo SPI Controller 1 Pci Config=0D + ///< Offset 310 Se= rialIo SPI Controller 2 Pci Config=0D + ///< Offset 318 Se= rialIo SPI Controller 3 Pci Config=0D + ///< Offset 326 Se= rialIo SPI Controller 4 Pci Config=0D + ///< Offset 334 Se= rialIo SPI Controller 5 Pci Config=0D + ///< Offset 342 Se= rialIo SPI Controller 6 Pci Config=0D + UINT8 IM0[8]; ///< Offset 350 Se= rialIo I2C Controller 0 Mode=0D + ///< Offset 351 Se= rialIo I2C Controller 1 Mode=0D + ///< Offset 352 Se= rialIo I2C Controller 2 Mode=0D + ///< Offset 353 Se= rialIo I2C Controller 3 Mode=0D + ///< Offset 354 Se= rialIo I2C Controller 4 Mode=0D + ///< Offset 355 Se= rialIo I2C Controller 5 Mode=0D + ///< Offset 356 Se= rialIo I2C Controller 6 Mode=0D + ///< Offset 357 Se= rialIo I2C Controller 7 Mode=0D + UINT64 IC0[8]; ///< Offset 358 Se= rialIo I2C Controller 0 Pci Config=0D + ///< Offset 366 Se= rialIo I2C Controller 1 Pci Config=0D + ///< Offset 374 Se= rialIo I2C Controller 2 Pci Config=0D + ///< Offset 382 Se= rialIo I2C Controller 3 Pci Config=0D + ///< Offset 390 Se= rialIo I2C Controller 4 Pci Config=0D + ///< Offset 398 Se= rialIo I2C Controller 5 Pci Config=0D + ///< Offset 406 Se= rialIo I2C Controller 6 Pci Config=0D + ///< Offset 414 Se= rialIo I2C Controller 7 Pci Config=0D + UINT8 UM0[7]; ///< Offset 422 Se= rialIo UART Controller 0 Mode=0D + ///< Offset 423 Se= rialIo UART Controller 1 Mode=0D + ///< Offset 424 Se= rialIo UART Controller 2 Mode=0D + ///< Offset 425 Se= rialIo UART Controller 3 Mode=0D + ///< Offset 426 Se= rialIo UART Controller 4 Mode=0D + ///< Offset 427 Se= rialIo UART Controller 5 Mode=0D + ///< Offset 428 Se= rialIo UART Controller 6 Mode=0D + UINT64 UC0[7]; ///< Offset 429 Se= rialIo UART Controller 0 Pci Config=0D + ///< Offset 437 Se= rialIo UART Controller 1 Pci Config=0D + ///< Offset 445 Se= rialIo UART Controller 2 Pci Config=0D + ///< Offset 453 Se= rialIo UART Controller 3 Pci Config=0D + ///< Offset 461 Se= rialIo UART Controller 4 Pci Config=0D + ///< Offset 469 Se= rialIo UART Controller 5 Pci Config=0D + ///< Offset 477 Se= rialIo UART Controller 6 Pci Config=0D + UINT8 UD0[7]; ///< Offset 485 Se= rialIo UART Controller 0 DmaEnable=0D + ///< Offset 486 Se= rialIo UART Controller 1 DmaEnable=0D + ///< Offset 487 Se= rialIo UART Controller 2 DmaEnable=0D + ///< Offset 488 Se= rialIo UART Controller 3 DmaEnable=0D + ///< Offset 489 Se= rialIo UART Controller 4 DmaEnable=0D + ///< Offset 490 Se= rialIo UART Controller 5 DmaEnable=0D + ///< Offset 491 Se= rialIo UART Controller 6 DmaEnable=0D + UINT8 UP0[7]; ///< Offset 492 Se= rialIo UART Controller 0 Power Gating=0D + ///< Offset 493 Se= rialIo UART Controller 1 Power Gating=0D + ///< Offset 494 Se= rialIo UART Controller 2 Power Gating=0D + ///< Offset 495 Se= rialIo UART Controller 3 Power Gating=0D + ///< Offset 496 Se= rialIo UART Controller 4 Power Gating=0D + ///< Offset 497 Se= rialIo UART Controller 5 Power Gating=0D + ///< Offset 498 Se= rialIo UART Controller 6 Power Gating=0D + UINT8 UI0[7]; ///< Offset 499 Se= rialIo UART Controller 0 Irq=0D + ///< Offset 500 Se= rialIo UART Controller 1 Irq=0D + ///< Offset 501 Se= rialIo UART Controller 2 Irq=0D + ///< Offset 502 Se= rialIo UART Controller 3 Irq=0D + ///< Offset 503 Se= rialIo UART Controller 4 Irq=0D + ///< Offset 504 Se= rialIo UART Controller 5 Irq=0D + ///< Offset 505 Se= rialIo UART Controller 6 Irq=0D + //end of SerialIo block=0D + UINT8 SGIR; ///< Offset 506 GP= IO IRQ=0D + UINT8 GPHD; ///< Offset 507 Hi= de GPIO ACPI device=0D + UINT8 RstPcieStorageInterfaceType[3]; ///< Offset 508 RS= T PCIe Storage Cycle Router#1 Interface Type=0D + ///< Offset 509 RS= T PCIe Storage Cycle Router#2 Interface Type=0D + ///< Offset 510 RS= T PCIe Storage Cycle Router#3 Interface Type=0D + UINT8 RstPcieStoragePmCapPtr[3]; ///< Offset 511 RS= T PCIe Storage Cycle Router#1 Power Management Capability Pointer=0D + ///< Offset 512 RS= T PCIe Storage Cycle Router#2 Power Management Capability Pointer=0D + ///< Offset 513 RS= T PCIe Storage Cycle Router#3 Power Management Capability Pointer=0D + UINT8 RstPcieStoragePcieCapPtr[3]; ///< Offset 514 RS= T PCIe Storage Cycle Router#1 PCIe Capabilities Pointer=0D + ///< Offset 515 RS= T PCIe Storage Cycle Router#2 PCIe Capabilities Pointer=0D + ///< Offset 516 RS= T PCIe Storage Cycle Router#3 PCIe Capabilities Pointer=0D + UINT16 RstPcieStorageL1ssCapPtr[3]; ///< Offset 517 RS= T PCIe Storage Cycle Router#1 L1SS Capability Pointer=0D + ///< Offset 519 RS= T PCIe Storage Cycle Router#2 L1SS Capability Pointer=0D + ///< Offset 521 RS= T PCIe Storage Cycle Router#3 L1SS Capability Pointer=0D + UINT8 RstPcieStorageEpL1ssControl2[3]; ///< Offset 523 RS= T PCIe Storage Cycle Router#1 Endpoint L1SS Control Data2=0D + ///< Offset 524 RS= T PCIe Storage Cycle Router#2 Endpoint L1SS Control Data2=0D + ///< Offset 525 RS= T PCIe Storage Cycle Router#3 Endpoint L1SS Control Data2=0D + UINT32 RstPcieStorageEpL1ssControl1[3]; ///< Offset 526 RS= T PCIe Storage Cycle Router#1 Endpoint L1SS Control Data1=0D + ///< Offset 530 RS= T PCIe Storage Cycle Router#2 Endpoint L1SS Control Data1=0D + ///< Offset 534 RS= T PCIe Storage Cycle Router#3 Endpoint L1SS Control Data1=0D + UINT16 RstPcieStorageLtrCapPtr[3]; ///< Offset 538 RS= T PCIe Storage Cycle Router#1 LTR Capability Pointer=0D + ///< Offset 540 RS= T PCIe Storage Cycle Router#2 LTR Capability Pointer=0D + ///< Offset 542 RS= T PCIe Storage Cycle Router#3 LTR Capability Pointer=0D + UINT32 RstPcieStorageEpLtrData[3]; ///< Offset 544 RS= T PCIe Storage Cycle Router#1 Endpoint LTR Data=0D + ///< Offset 548 RS= T PCIe Storage Cycle Router#2 Endpoint LTR Data=0D + ///< Offset 552 RS= T PCIe Storage Cycle Router#3 Endpoint LTR Data=0D + UINT16 RstPcieStorageEpLctlData16[3]; ///< Offset 556 RS= T PCIe Storage Cycle Router#1 Endpoint LCTL Data=0D + ///< Offset 558 RS= T PCIe Storage Cycle Router#2 Endpoint LCTL Data=0D + ///< Offset 560 RS= T PCIe Storage Cycle Router#3 Endpoint LCTL Data=0D + UINT16 RstPcieStorageEpDctlData16[3]; ///< Offset 562 RS= T PCIe Storage Cycle Router#1 Endpoint DCTL Data=0D + ///< Offset 564 RS= T PCIe Storage Cycle Router#2 Endpoint DCTL Data=0D + ///< Offset 566 RS= T PCIe Storage Cycle Router#3 Endpoint DCTL Data=0D + UINT16 RstPcieStorageEpDctl2Data16[3]; ///< Offset 568 RS= T PCIe Storage Cycle Router#1 Endpoint DCTL2 Data=0D + ///< Offset 570 RS= T PCIe Storage Cycle Router#2 Endpoint DCTL2 Data=0D + ///< Offset 572 RS= T PCIe Storage Cycle Router#3 Endpoint DCTL2 Data=0D + UINT16 RstPcieStorageRpDctl2Data16[3]; ///< Offset 574 RS= T PCIe Storage Cycle Router#1 RootPort DCTL2 Data=0D + ///< Offset 576 RS= T PCIe Storage Cycle Router#2 RootPort DCTL2 Data=0D + ///< Offset 578 RS= T PCIe Storage Cycle Router#3 RootPort DCTL2 Data=0D + UINT32 RstPcieStorageUniqueTableBar[3]; ///< Offset 580 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR=0D + ///< Offset 584 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR=0D + ///< Offset 588 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR=0D + UINT32 RstPcieStorageUniqueTableBarValue[3]; ///< Offset 592 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X Table BAR value=0D + ///< Offset 596 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X Table BAR value=0D + ///< Offset 600 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X Table BAR value=0D + UINT32 RstPcieStorageUniquePbaBar[3]; ///< Offset 604 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR=0D + ///< Offset 608 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR=0D + ///< Offset 612 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR=0D + UINT32 RstPcieStorageUniquePbaBarValue[3]; ///< Offset 616 RS= T PCIe Storage Cycle Router#1 Endpoint unique MSI-X PBA BAR value=0D + ///< Offset 620 RS= T PCIe Storage Cycle Router#2 Endpoint unique MSI-X PBA BAR value=0D + ///< Offset 624 RS= T PCIe Storage Cycle Router#3 Endpoint unique MSI-X PBA BAR value=0D + UINT32 RstPcieStorageRootPortNum[3]; ///< Offset 628 RS= T PCIe Storage Cycle Router#1 Root Port number=0D + ///< Offset 632 RS= T PCIe Storage Cycle Router#2 Root Port number=0D + ///< Offset 636 RS= T PCIe Storage Cycle Router#3 Root Port number=0D + UINT8 EMH4; ///< Offset 640 eM= MC HS400 mode enabled=0D + UINT8 EMDS; ///< Offset 641 eM= MC Driver Strength=0D + UINT8 CpuSku; ///< Offset 642 CP= U SKU=0D + UINT16 IoTrapAddress[4]; ///< Offset 643=0D + UINT8 IoTrapStatus[4]; ///< Offset 651=0D + UINT16 PMBS; ///< Offset 655 AC= PI IO BASE address=0D + UINT32 PWRM; ///< Offset 657 PW= RM MEM BASE address=0D + // CNVi specific=0D + UINT8 CnviMode; ///< Offset 661 CN= Vi mode=0D + UINT8 CnviBtCore; ///< Offset 662 CN= Vi BT Core=0D + UINT8 CnviBtAudioOffload; ///< Offset 663 CN= Vi BT Audio Offload=0D + // PCH Trace Hub=0D + UINT8 PchTraceHubMode; ///< Offset 664 PC= H Trace Hub Mode=0D + // PCH PS_ON support=0D + UINT8 PsOnEnable; ///< Offset 665 PC= H PS_ON enable=0D + //=0D + // These are for PchApciTablesSelfTest use=0D + //=0D + UINT8 LtrEnable[24]; ///< Offset 666 La= tency Tolerance Reporting Enable=0D + ///< Offset 667 La= tency Tolerance Reporting Enable=0D + ///< Offset 668 La= tency Tolerance Reporting Enable=0D + ///< Offset 669 La= tency Tolerance Reporting Enable=0D + ///< Offset 670 La= tency Tolerance Reporting Enable=0D + ///< Offset 671 La= tency Tolerance Reporting Enable=0D + ///< Offset 672 La= tency Tolerance Reporting Enable=0D + ///< Offset 673 La= tency Tolerance Reporting Enable=0D + ///< Offset 674 La= tency Tolerance Reporting Enable=0D + ///< Offset 675 La= tency Tolerance Reporting Enable=0D + ///< Offset 676 La= tency Tolerance Reporting Enable=0D + ///< Offset 677 La= tency Tolerance Reporting Enable=0D + ///< Offset 678 La= tency Tolerance Reporting Enable=0D + ///< Offset 679 La= tency Tolerance Reporting Enable=0D + ///< Offset 680 La= tency Tolerance Reporting Enable=0D + ///< Offset 681 La= tency Tolerance Reporting Enable=0D + ///< Offset 682 La= tency Tolerance Reporting Enable=0D + ///< Offset 683 La= tency Tolerance Reporting Enable=0D + ///< Offset 684 La= tency Tolerance Reporting Enable=0D + ///< Offset 685 La= tency Tolerance Reporting Enable=0D + ///< Offset 686 La= tency Tolerance Reporting Enable=0D + ///< Offset 687 La= tency Tolerance Reporting Enable=0D + ///< Offset 688 La= tency Tolerance Reporting Enable=0D + ///< Offset 689 La= tency Tolerance Reporting Enable=0D + UINT8 GBES; ///< Offset 690 Gb= E Support=0D + UINT32 PchxDCIPwrDnScale; ///< Offset 691 PC= H xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19]=0D + UINT8 EmmcEnabled; ///< Offset 695 Se= t to indicate that eMMC is enabled=0D + UINT8 SdCardEnabled; ///< Offset 696 Se= t to indicate that SD card is enabled=0D + UINT8 EnableTimedGpio0; ///< Offset 697 Se= t to indicate that Timed GPIO 0 is enabled=0D + UINT8 EnableTimedGpio1; ///< Offset 698 Se= t to indicate that Timed GPIO 1 is enabled=0D + UINT8 ClockToRootPortMap[18]; ///< Offset 699 CL= OCK index to root port index map. Used during PCIe D3Cold flows=0D + UINT16 TcoBase; ///< Offset 717 TC= O base address=0D + UINT16 IclkPid; ///< Offset 719 Ic= lk PID number=0D + UINT16 CnviPortId; ///< Offset 721 CN= Vi sideband port id=0D + UINT32 HybridStorageLocation; ///< Offset 723=0D + UINT8 SataPortPresence; ///< Offset 727 Ho= lds information from SATA PCS register about SATA ports which recieved COMI= NIT from connected devices.=0D +} PCH_NVS_AREA;=0D +=0D +#pragma pack(pop)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob= .h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h new file mode 100644 index 0000000000..428858afcf --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/PchRstHob.h @@ -0,0 +1,58 @@ +/** @file=0D +=0D + Definitions required to create RstHob=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PCH_RST_HOB_=0D +#define _PCH_RST_HOB_=0D +=0D +extern EFI_GUID gPchRstHobGuid;=0D +=0D +//=0D +// This struct is used to record the fields that should be restored during= device wake up=0D +//=0D +typedef struct {=0D + UINT8 PmCapPtr;=0D + UINT8 PcieCapPtr;=0D + UINT16 L1ssCapPtr;=0D + UINT8 EndpointL1ssControl2;=0D + UINT32 EndpointL1ssControl1;=0D + UINT16 LtrCapPtr;=0D + UINT32 EndpointLtrData;=0D + UINT16 EndpointLctlData16;=0D + UINT16 EndpointDctlData16;=0D + UINT16 EndpointDctl2Data16;=0D + UINT16 RootPortDctl2Data16;=0D +} SAVED_DEVICE_CONFIG_SPACE;=0D +=0D +//=0D +// This structure is used to record the result of PCIe storageremapping fo= r each cycle router=0D +//=0D +typedef struct {=0D + UINT8 RootPortNum; = // Indicates the root port number with RST PCIe Storage Remapping remapping= supported and PCIe storage device plugged on, numbering is 0-based=0D + UINT8 DeviceInterface; = // Indicates the interface of the PCIe storage device (AHCI or NVMe)=0D + UINT32 EndPointUniqueMsixTableBar; = // Records the PCIe storage device's MSI-X Table BAR if it supports unique = MSI-X Table BAR=0D + UINT32 EndPointUniqueMsixTableBarValue; = // Records the PCIe storage device's MSI-X Table BAR value if it supports u= nique MSI-X Table BAR=0D + UINT32 EndPointUniqueMsixPbaBar; = // Records the PCIe storage device's MSI-X PBA BAR if it supports unique MS= I-X PBA BAR=0D + UINT32 EndPointUniqueMsixPbaBarValue; = // Records the PCIe storage device's MSI-X PBA BAR value if it supports uni= que MSI-X PBA BAR=0D +} RST_CR_CONFIGURATION;=0D +=0D +//=0D +// Passes to DXE results of PCIe storage remapping=0D +//=0D +typedef struct {=0D + //=0D + // Stores configuration information about cycle router=0D + //=0D + RST_CR_CONFIGURATION RstCrConfiguration[PCH_MAX_RST_PCIE_STORAGE_CR];=0D +=0D + //=0D + // Saved fields from hidden device config space to be used later by RST = driver=0D + //=0D + SAVED_DEVICE_CONFIG_SPACE SavedRemapedDeviceConfigSpace[PCH_MAX_RST_PCI= E_STORAGE_CR];=0D +} PCH_RST_HOB;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/= PchNvsArea.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protoco= l/PchNvsArea.h new file mode 100644 index 0000000000..1c45d89225 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PchNvsA= rea.h @@ -0,0 +1,30 @@ +/** @file=0D + This file defines the PCH NVS Area Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PCH_NVS_AREA_H_=0D +#define _PCH_NVS_AREA_H_=0D +=0D +//=0D +// PCH NVS Area definition=0D +//=0D +#include =0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchNvsAreaProtocolGuid;=0D +=0D +/**=0D + This protocol is used to sync PCH information from POST to runtime ASL.= =0D + This protocol exposes the pointer of PCH NVS Area only. Please refer to= =0D + ASL definition for PCH NVS AREA.=0D +**/=0D +typedef struct {=0D + PCH_NVS_AREA *Area;=0D +} PCH_NVS_AREA_PROTOCOL;=0D +=0D +#endif // _PCH_NVS_AREA_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/= PcieIoTrap.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protoco= l/PcieIoTrap.h new file mode 100644 index 0000000000..ecea5db4fc --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/Protocol/PcieIoT= rap.h @@ -0,0 +1,35 @@ +/** @file=0D + This file defines the PCH PCIE IoTrap Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCH_PCIE_IOTRAP_H_=0D +#define _PCH_PCIE_IOTRAP_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gPchPcieIoTrapProtocolGuid;=0D +=0D +//=0D +// Forward reference for ANSI C compatibility=0D +//=0D +typedef struct _PCH_PCIE_IOTRAP_PROTOCOL PCH_PCIE_IOTRAP_PROTOCOL;=0D +=0D +///=0D +/// Pcie Trap valid types=0D +///=0D +typedef enum {=0D + PchPciePmTrap,=0D + PcieTrapTypeMaximum=0D +} PCH_PCIE_TRAP_TYPE;=0D +=0D +/**=0D + This protocol is used to provide the IoTrap address to trigger PCH PCIE c= all back events=0D +**/=0D +struct _PCH_PCIE_IOTRAP_PROTOCOL {=0D + UINT16 PcieTrapAddress;=0D +};=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiSchedul= eResetHob.h b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiSchedu= leResetHob.h new file mode 100644 index 0000000000..0d9b167588 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/Pch/IncludePrivate/SiScheduleResetH= ob.h @@ -0,0 +1,21 @@ +/** @file=0D + This file contains definitions of Si Schedule Reset HOB.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SI_SCHEDULE_RESET_HOB_H_=0D +#define _SI_SCHEDULE_RESET_HOB_H_=0D +=0D +/**=0D + This structure is used to provide information about PCH Resets=0D +**/=0D +typedef struct {=0D + EFI_RESET_TYPE ResetType;=0D + PCH_RESET_DATA ResetData;=0D +} SI_SCHEDULE_RESET_HOB;=0D +=0D +extern EFI_GUID gSiScheduleResetHobGuid;=0D +=0D +#endif // _SI_SCHEDULE_RESET_HOB_H_=0D +=0D --=20 2.24.0.windows.2