From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com []) by mx.groups.io with SMTP id smtpd.web12.5213.1612510882795645881 for ; Thu, 04 Feb 2021 23:41:27 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: ULPJneo0OlETPf7KLzp7d5NyeJZ4jAx9D/4plVl9dur+o5Sdc08bFR8Qvks5FWuej4rPim9lmB EQJQDWmcZ/5Q== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543631" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543631" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:26 -0800 IronPort-SDR: fxVlIp3VT0eQh6mydk4G+CZQ3X8aX9sMw0wbtju3FiDpVfpelu+wrw5gOLe0f4gmjf05rVshgX uK/ekZxyabSA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260253" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:25 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 07/40] TigerlakeSiliconPkg/SystemAgent: Add include headers Date: Fri, 5 Feb 2021 15:40:12 +0800 Message-Id: <20210205074045.3916-7-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * SystemAgent/Include Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/MemoryDx= eConfig.h | 123 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PcieDxeC= onfig.h | 114 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/PramPreM= emConfig.h | 34 ++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPe= iConfig.h | 24 ++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaMiscPe= iPreMemConfig.h | 104 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatformLi= b.h | 48 ++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h = | 245 +++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPolicy.h = | 61 +++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++ 8 files changed, 753 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/MemoryDxeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/MemoryDxeConfig.h new file mode 100644 index 0000000000..451e295b49 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Mem= oryDxeConfig.h @@ -0,0 +1,123 @@ +/** @file=0D + Memory DXE Policy definitions=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _MEMORY_DXE_CONFIG_H_=0D +#define _MEMORY_DXE_CONFIG_H_=0D +=0D +#pragma pack(push, 1)=0D +=0D +#define MEMORY_DXE_CONFIG_REVISION 1=0D +=0D +typedef struct _MEMORY_DXE_CONFIG MEMORY_DXE_CONFIG;=0D +=0D +/**=0D + Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocat= or field.=0D + Implementation of this function is optional, if this function pointer is= NULL then=0D + the reference implementation of DeviceLocator will be used.=0D +=0D + @param[in] This A pointer to this instance of = MEMORY_DXE_CONFIG.=0D + @param[in] Controller Desired Controller to get a De= viceLocator string for.=0D + @param[in] Dimm Desired DIMM to get a DeviceLo= cator string for.=0D + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Socke= ted.=0D +=0D + @retval The DeviceLocator string=0D + @retval NULL If the return value is NULL, t= he default value will be used.=0D +**/=0D +typedef=0D +CHAR8*=0D +(EFIAPI *MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING)(=0D + IN CONST MEMORY_DXE_CONFIG *This,=0D + IN UINT8 Controller,=0D + IN UINT8 Dimm,=0D + IN UINT8 MdSocket=0D + );=0D +=0D +/**=0D + Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator= field.=0D + Implementation of this function is optional, if this function pointer is= NULL then=0D + the reference implementation of DeviceLocator will be used.=0D +=0D + @param[in] This A pointer to this instance of = MEMORY_DXE_CONFIG.=0D + @param[in] Controller Desired Controller to get a Ba= nkLocator string for.=0D + @param[in] Dimm Desired DIMM to get a BankLoca= tor string for.=0D + @param[in] MdSocket 0 =3D Memory Down, 1 =3D Socke= ted.=0D +=0D + @retval The BankLocator string=0D + @retval NULL If the return value is NULL, t= he default value will be used.=0D +**/=0D +typedef=0D +CHAR8*=0D +(EFIAPI *MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING)(=0D + IN CONST MEMORY_DXE_CONFIG *This,=0D + IN UINT8 Controller,=0D + IN UINT8 Dimm,=0D + IN UINT8 MdSocket=0D + );=0D +=0D +/**=0D + The Memory Configuration includes DIMM SPD address Map and DIMM Slot Mec= hanical present bit map.=0D + The data elements should be initialized by a Platform Module.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +struct _MEMORY_DXE_CONFIG {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27: Config= Block Header=0D +/**=0D + Offset 28:=0D + Dimm SPD address=0D + Only Server support 2 channels * 3 slots per channel =3D 6 sockets total= ly=0D + The Desktop and mobile only support 2 channels * 2 slots per channel =3D= 4 sockets totally=0D + So there is mapping rule here for Desktop and mobile that there are no m= ore 4 DIMMS totally in a system:=0D + Channel A/ Slot 0 --> Dimm 0 --> SpdAddressTable[0]=0D + Channel A/ Slot 1 --> Dimm 1 --> SpdAddressTable[1]=0D + Channel B/ Slot 0 --> Dimm 2 --> SpdAddressTable[2]=0D + Channel B/ Slot 1 --> Dimm 3 --> SpdAddressTable[3]=0D + Refer to SmbiosMemory.c for use=0D + If change the mapping rule, please update the Revision number.=0D +**/=0D + UINT8 *SpdAddressTable;=0D +/**=0D + Offset 36:=0D + Channel A DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ...=0D + if the bit is 1, the related DIMM slot is present.=0D + E.g. if channel A has 2 DIMMs, ChannelASlotMap =3D 0x03;=0D + E.g. if channel A has only 1 DIMMs, ChannelASlotMap =3D 0x01;=0D + Refer to SmbiosMemory.c=0D +**/=0D + UINT8 ChannelASlotMap;=0D +/**=0D + Offset 37:=0D + Channel B DIMM Slot Mechanical present bit map, bit 0 -> DIMM 0, bit 1 -= > DIMM1, ...=0D + if the bit is 1, the related DIMM slot is present.=0D + E.g. if channel B has 2 DIMMs, ChannelBSlotMap =3D 0x03;=0D + E.g. if channel B has only 1 DIMMs, ChannelBSlotMap =3D 0x01;=0D + Refer to SmbiosMemory.c=0D +**/=0D + UINT8 ChannelBSlotMap;=0D +/**=0D + Offset 38:=0D + MRC execution time measurement: 0=3DDisable, 1=3DEnable=0D +**/=0D + UINT8 MrcTimeMeasure;=0D +/**=0D + Offset 39:=0D + Fast boot: 0=3DDisable, 1=3DEnable=0D +**/=0D + UINT8 MrcFastBoot;=0D +/**=0D + Offset 40:=0D + Retrieves the OEM custom string for the SMBIOS Type 17 Table DeviceLocat= or field.=0D +**/=0D + MEMORY_DXE_CONFIG_GET_DEVICE_LOCATOR_STRING GetDeviceLocatorString;= =0D +/**=0D + Offset 48:=0D + Retrieves the OEM custom string for the SMBIOS Type 17 Table BankLocator= field.=0D +**/=0D + MEMORY_DXE_CONFIG_GET_BANK_LOCATOR_STRING GetBankLocatorString;=0D +};=0D +#pragma pack(pop)=0D +=0D +#endif // _MEMORY_DXE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/PcieDxeConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include= /ConfigBlock/PcieDxeConfig.h new file mode 100644 index 0000000000..799121f1ab --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pci= eDxeConfig.h @@ -0,0 +1,114 @@ +/** @file=0D + PCIE DXE policy definitions=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PCIE_DXE_CONFIG_H_=0D +#define _PCIE_DXE_CONFIG_H_=0D +=0D +#include "CpuPcieInfo.h"=0D +=0D +#pragma pack(push, 1)=0D +=0D +#define PCIE_DXE_CONFIG_REVISION 2=0D +=0D +typedef struct {=0D + UINT16 VendorId; ///< Offset 0 PCI Config space offset 0=0D + UINT16 DeviceId; ///< Offset 2 PCI Config space offset 2=0D +/**=0D + Offset 4:=0D + SnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid=0D + When clear values in bits 9:0 will be ignored=0D + BIT[14] - Should be set to 0b=0D + BIT[13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Snoop Latency Value. The value in these bits will be multi= plied with=0D + the scale in bits 12:10=0D +**/=0D + UINT16 SnoopLatency;=0D +/**=0D + Offset 6:=0D + NonSnoopLatency bit definition=0D + Note: All Reserved bits must be set to 0=0D +=0D + BIT[15] - When set to 1b, indicates that the values in bits 9:0 are = valid=0D + When clear values in bits 9:0 will be ignored=0D + BIT[14] - Should be set to 0b=0D + BIT[13] - Reserved=0D + BITS[12:10] - Value in bits 9:0 will be multiplied with the scale in the= se bits=0D + 000b - 1 ns=0D + 001b - 32 ns=0D + 010b - 1024 ns=0D + 011b - 32,768 ns=0D + 100b - 1,048,576 ns=0D + 101b - 33,554,432 ns=0D + 110b - Reserved=0D + 111b - Reserved=0D + BITS[9:0] - Non Snoop Latency Value. The value in these bits will be m= ultiplied with=0D + the scale in bits 12:10=0D +**/=0D + UINT16 NonSnoopLatency;=0D + UINT8 RevId; ///< Offset 8 PCI Config space offset 8; 0xFF means = all steppings=0D + UINT8 Rsvd0[3]; ///< Offset 9=0D +} PCIE_LTR_DEV_INFO;=0D +=0D +///=0D +/// PCIE Power Optimizer config=0D +///=0D +typedef struct {=0D + UINT16 LtrMaxSnoopLatency; ///< Offset 0 LTR Maximum Snoop Latency: <= b>0x0846=3D70us=0D + UINT16 LtrMaxNoSnoopLatency; ///< Offset 2 LTR Maximum Non-Snoop Latenc= y: 0x0846=3D70us=0D + UINT8 ObffEnable; ///< Offset 4 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable=0D + UINT8 LtrEnable; ///< Offset 5 LTR enable/disable: 0=3DDisa= ble, 1=3DEnable=0D + UINT8 Rsvd0[2]; ///< Offset 6 Reserved=0D +} CPU_PCIE_PWR_OPT;=0D +=0D +=0D +/**=0D + The PCI Express Configuration info includes PCI Resources Range Base and= Limits and the control=0D + for PEG ASPM.=0D + The data elements should be initialized by a Platform Module.\n=0D + @note Optional. These policies will be ignored if there is no PEG= port present on board.=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Adding PEG RTD3 Support Setup Variable=0D + Revision 3:=0D + - Adding CPU PCIE RTD3 Support Setup Variable=0D + - Deprecating PEG RTD3 Support Setup Variable=0D + Revision 4:=0D + - Deprecating CPU PCIE RTD3 Support Setup Variable=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-2= 7 Config Block Header=0D +/**=0D + Offset 28: This field is used to describe the ASPM control for PEG Ports= \n=0D + 0=3DASPM Disabled, 1=3DASPM L0s Enabled, 2=3DASPM L1 Enabled, 3=3DASPM L= 0sL1 Enabled, 4=3DASPM AUTO=0D +**/=0D + UINT8 PegAspm[SA_PEG_MAX_FUN];=0D +/**=0D + Offset 32: PCIe Hot Plug Enable/Disable. It has 2 policies.=0D + - Disabled (0x0) : No hotplug.=0D + - Enabled (0x1) : Bios assist hotplug.=0D +**/=0D + UINT8 PegRootPortHPE[SA_PEG_MAX_FUN];=0D + CPU_PCIE_PWR_OPT PegPwrOpt[SA_PEG_MAX_FUN]; ///< Offset 36:= This field is used to describe the PCIe LTR/OBFF relevant settings=0D + UINT32 PegRtd3; /// Deprecated = Policy=0D + UINT8 CpuPcieRtd3; ///< Enable/Disa= ble RTD3 Support for CPU PCIE. 0=3DDisable and 1=3DEnable (default) // Dep= recated Policy=0D + UINT8 Rsvd3[3];=0D +} PCIE_DXE_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _PCIE_DXE_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/PramPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Incl= ude/ConfigBlock/PramPreMemConfig.h new file mode 100644 index 0000000000..8947e80b22 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/Pra= mPreMemConfig.h @@ -0,0 +1,34 @@ +/** @file=0D + Policy definition for Persisted Ram (Pram) Config Block=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _PRAM_PREMEM_CONFIG__H_=0D +#define _PRAM_PREMEM_CONFIG__H_=0D +#pragma pack(push, 1)=0D +=0D +#define PRAM_PREMEM_CONFIG_REVISION 1=0D +=0D +/**=0D + Defines Pram configuration parameters.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block Header=0D + /**=0D + Offset 28:=0D + Size of Pram=0D + If disabled, or if PcdSaOcEnable is disabled, all other policies in this= config block are ignored.=0D + 0=3DDisable,=0D + 1=3D4MB,=0D + 2=3D16MB,=0D + 3=3D64MB=0D + **/=0D + UINT8 Pram;=0D + UINT8 Rsvd[3]; ///< Offset 29 Reserved for DWORD alignm= ent=0D +} PRAM_PREMEM_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _PRAM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/SaMiscPeiConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Inclu= de/ConfigBlock/SaMiscPeiConfig.h new file mode 100644 index 0000000000..203d894df9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaM= iscPeiConfig.h @@ -0,0 +1,24 @@ +/** @file=0D + Policy details for miscellaneous configuration in System Agent=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_MISC_PEI_CONFIG_H_=0D +#define _SA_MISC_PEI_CONFIG_H_=0D +=0D +#pragma pack(push, 1)=0D +=0D +#define SA_MISC_PEI_CONFIG_REVISION 1=0D +=0D +/**=0D + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Post-Mem.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D +} SA_MISC_PEI_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _SA_MISC_PEI_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBl= ock/SaMiscPeiPreMemConfig.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent= /Include/ConfigBlock/SaMiscPeiPreMemConfig.h new file mode 100644 index 0000000000..8c660b31a9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/ConfigBlock/SaM= iscPeiPreMemConfig.h @@ -0,0 +1,104 @@ +/** @file=0D + Policy details for miscellaneous configuration in System Agent=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_MISC_PEI_PREMEM_CONFIG_H_=0D +#define _SA_MISC_PEI_PREMEM_CONFIG_H_=0D +=0D +#pragma pack(push, 1)=0D +=0D +#ifndef MEM_CFG_MAX_SOCKETS=0D +#define MEM_CFG_MAX_SOCKETS 16=0D +#endif=0D +=0D +#define SA_MISC_PEI_PREMEM_CONFIG_REVISION 2=0D +=0D +/**=0D + This configuration block is to configure SA Miscellaneous variables duri= ng PEI Pre-Mem phase like programming=0D + different System Agent BARs, TsegSize, MmioSize required etc.=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Deprecate IedSize.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_HEADER Header; ///< Offset 0-27 Config Block= Header=0D + /**=0D + Offset 28 Memory DIMMs' SPD address for reading SPD data.=0D + TGL Mapping=0D + 0 - Controller 0 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5=0D + 1 - Controller 0 Channel 0 Dimm 1 - DDR4=0D + 2 - Controller 0 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5=0D + 3 - Controller 0 Channel 1 Dimm 1 -------- DDR5 2DPC=0D + 4 - Controller 0 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5=0D + 6 - Controller 0 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5=0D + 8 - Controller 1 Channel 0 Dimm 0 - DDR4 - DDR5 - LPDDR4 - LPDDR5=0D + 9 - Controller 1 Channel 0 Dimm 1 - DDR4=0D + 10 - Controller 1 Channel 1 Dimm 0 -------- DDR5 - LPDDR4 - LPDDR5=0D + 11 - Controller 1 Channel 1 Dimm 1 -------- DDR5 2DPC=0D + 12 - Controller 1 Channel 2 Dimm 0 --------------- LPDDR4 - LPDDR5=0D + 14 - Controller 1 Channel 3 Dimm 0 --------------- LPDDR4 - LPDDR5=0D + **/=0D + UINT8 SpdAddressTable[MEM_CFG_MAX_SOCKETS];=0D + VOID *S3DataPtr; ///< Offset 44 Memory data sa= ve pointer for S3 resume. The memory space should be allocated and filled w= ith proper S3 resume data on a resume path=0D + UINT32 SmbusBar; ///< Offset 48 Address of Sys= tem Agent SMBUS BAR: 0xEFA0=0D + /**=0D + Offset 52 Size of TSEG in bytes. (Must be power of 2)=0D + 0x400000: 4MB for Release build (When IED enabled, it will be 8= MB)=0D + 0x1000000 : 16MB for Debug build (Regardless IED enabled or disab= led)=0D + **/=0D + UINT32 TsegSize;=0D + /**=0D + Offset 56=0D + (Test) Size of IED region in bytes.=0D + 0 : IED Disabled (no memory occupied)=0D + 0x400000 : 4MB SMM memory occupied by IED (Part of TSEG)=0D + Note: Enabling IED may also enlarge TsegSize together.=0D + @deprecated=0D + **/=0D + UINT32 IedSize;=0D + UINT32 SkipExtGfxScan:1; ///< (Test) OFfset 60:= 0 :1=3DSkip External Gfx Device Scan; 0=3DScan for external graphics dev= ices. Set this policy to skip External Graphics card scanning if the pl= atform uses Internal Graphics only.=0D + UINT32 BdatEnable:1; ///< Offset 60:1 :This field = enables the generation of the BIOS DATA ACPI Tables: 0=3DFALSE, 1=3D= TRUE.=0D + UINT32 TxtImplemented:1; ///< OFfset 60:2 :This field = currently is used to tell MRC if it should run after TXT initializatoin com= pleted: 0=3DRun without waiting for TXT, 1=3DRun after TXT initializ= ation by callback=0D + /**=0D + Offset 60:3 :=0D + (Test) Scan External Discrete Graphics Devices for Legacy Only V= GA OpROMs=0D +=0D + When enabled, if the primary graphics device is an external discrete gr= aphics device, Si will scan the=0D + graphics device for legacy only VGA OpROMs.=0D +=0D + This is intended to ease the implementation of a BIOS feature to automa= tically enable CSM if the Primary Gfx device=0D + only supports Legacy VBIOS (No UEFI GOP Present). Otherwise disabling = CSM won't result in no video being displayed.=0D + This is useful for platforms that implement PCIe slots that allow the e= nd user to install an arbitrary Gfx device.=0D +=0D + This setting will only take effect if SkipExtGfxScan =3D=3D 0. It is i= gnored otherwise.=0D +=0D + - Disabled (0x0) : Don't Scan for Legacy Only VGA OpROMs (Defaul= t)=0D + - Enabled (0x1) : Scan External Gfx for Legacy Only VGA OpROM=0D + **/=0D + UINT32 ScanExtGfxForLegacyOpRom:1;=0D + UINT32 RsvdBits0 :28; ///< Offset 60:4 :Reserved fo= r future use=0D + UINT8 UserBd; ///< Offset 64 0=3DMobile/= Mobile Halo, 1=3DDesktop/DT Halo, 5=3DULT/ULX/Mobile Halo, 7=3DUP Serve= r=0D + UINT8 LockPTMregs; ///< (Test) Offset 65 = Lock PCU Thermal Management registers: 0=3DFALSE, 1=3DTRUE=0D + UINT8 BdatTestType; ///< Offset 66 When BdatEnabl= e is set to TRUE, this option selects the type of data which will be popula= ted in the BIOS Data ACPI Tables: 0=3DRMT, 1=3DRMT Per Bit, 2=3DMarg= in 2D.=0D + UINT8 CridEnable; ///< Offset 67 For Platforms = supporting Intel(R) SIPP, this policy is use control enable/disable Compati= bility Revision ID (CRID) feature: 0=3DFALSE, 1=3DTRUE=0D + UINT32 AcpiReservedMemorySize; ///< Offset 68 The Size of a = Reserved memory buffer allocated in previous boot for S3 resume used. Origi= nally it is retrieved from AcpiVariableCompatibility variable.=0D + UINT32 OpRomScanTempMmioBar; ///< (Test) Offset 72 = Temporary address to MMIO map OpROMs during VGA scanning. Used for ScanExt= GfxForLegacyOpRom feature. MUST BE 16MB ALIGNED!=0D + UINT32 OpRomScanTempMmioLimit; ///< (Test) Offset 76 = Limit address for OpROM MMIO range. Used for ScanExtGfxForLegacyOpRom feat= ure. (OpROMScanTempMmioLimit - OpRomScanTempMmioBar) MUST BE >=3D 16MB!=0D + UINT64 AcpiReservedMemoryBase; ///< Offset 80 The Base addre= ss of a Reserved memory buffer allocated in previous boot for S3 resume use= d. Originally it is retrieved from AcpiVariableCompatibility variable.=0D + UINT64 SystemMemoryLength; ///< Offset 88 Total system m= emory length from previous boot, this is required for S3 resume. Originally= it is retrieved from AcpiVariableCompatibility variable.=0D +=0D + UINT8 WrcFeatureEnable; ///< Offset 96: Enable/Disab= le WRC (Write Cache) feature of IOP. When enabled, supports IO devices allo= cating onto the ring and into LLC.=0D + UINT8 Reserved1[3]; ///< Reserved for config blo= ck alignment.=0D +=0D +=0D + // Since the biggest element is UINT64, this structure should be aligned= with 64 bits.=0D + UINT8 Rsvd[4]; ///< Reserved for config bloc= k alignment.=0D +=0D +=0D +} SA_MISC_PEI_PREMEM_CONFIG;=0D +#pragma pack(pop)=0D +=0D +#endif // _SA_MISC_PEI_PREMEM_CONFIG_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/= SaPlatformLib.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Lib= rary/SaPlatformLib.h new file mode 100644 index 0000000000..daf3746605 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Library/SaPlatf= ormLib.h @@ -0,0 +1,48 @@ +/** @file=0D + Header file for SaPlatformLib.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SA_PLATFORM_LIB_H_=0D +#define _SA_PLATFORM_LIB_H_=0D +=0D +=0D +/**=0D + Checks if SKU is Mobile=0D +=0D + @retval FALSE SKU is not Mobile=0D + @retval TRUE SKU is Mobile=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsMobileSku (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if SKU is Desktop=0D +=0D + @retval FALSE SKU is not Desktop=0D + @retval TRUE SKU is Desktop=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsDesktopSku (=0D + VOID=0D + );=0D +=0D +/**=0D + Checks if SKU is Server=0D +=0D + @retval FALSE SKU is not Server=0D + @retval TRUE SKU is Server=0D +**/=0D +BOOLEAN=0D +EFIAPI=0D +IsServerSku (=0D + VOID=0D + );=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoH= ob.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h new file mode 100644 index 0000000000..f280a3d379 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/MemInfoHob.h @@ -0,0 +1,245 @@ +/** @file=0D + This file contains definitions required for creation of=0D + Memory S3 Save data, Memory Info data and Memory Platform=0D + data hobs.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _MEM_INFO_HOB_H_=0D +#define _MEM_INFO_HOB_H_=0D +=0D +#pragma pack (push, 1)=0D +=0D +extern EFI_GUID gSiMemoryS3DataGuid;=0D +extern EFI_GUID gSiMemoryInfoDataGuid;=0D +extern EFI_GUID gSiMemoryPlatformDataGuid;=0D +=0D +#define MAX_TRACE_CACHE_TYPE 3=0D +=0D +#define MAX_NODE 2=0D +#define MAX_CH 4=0D +#define MAX_DIMM 2=0D +=0D +///=0D +/// Host reset states from MRC.=0D +///=0D +#define WARM_BOOT 2=0D +=0D +#define R_MC_CHNL_RANK_PRESENT 0x7C=0D +#define B_RANK0_PRS BIT0=0D +#define B_RANK1_PRS BIT1=0D +#define B_RANK2_PRS BIT4=0D +#define B_RANK3_PRS BIT5=0D +=0D +///=0D +/// Defines taken from MRC so avoid having to include MrcInterface.h=0D +///=0D +=0D +//=0D +// Matches MAX_SPD_SAVE define in MRC=0D +//=0D +#ifndef MAX_SPD_SAVE=0D +#define MAX_SPD_SAVE 29=0D +#endif=0D +=0D +//=0D +// MRC version description.=0D +//=0D +typedef struct {=0D + UINT8 Major; ///< Major version number=0D + UINT8 Minor; ///< Minor version number=0D + UINT8 Rev; ///< Revision number=0D + UINT8 Build; ///< Build number=0D +} SiMrcVersion;=0D +=0D +//=0D +// Matches MrcDimmSts enum in MRC=0D +//=0D +#ifndef DIMM_ENABLED=0D +#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be= detected.=0D +#endif=0D +#ifndef DIMM_DISABLED=0D +#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of p= resence.=0D +#endif=0D +#ifndef DIMM_PRESENT=0D +#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pa= ir and it will be used.=0D +#endif=0D +#ifndef DIMM_NOT_PRESENT=0D +#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank p= air.=0D +#endif=0D +=0D +//=0D +// Matches MrcBootMode enum in MRC=0D +//=0D +#ifndef __MRC_BOOT_MODE__=0D +#define __MRC_BOOT_MODE__ //The below values are originate= d from MrcCommonTypes.h=0D + #ifndef INT32_MAX=0D + #define INT32_MAX (0x7FFFFFFF)=0D + #endif //INT32_MAX=0D +typedef enum {=0D + bmCold, ///< Cold boot=0D + bmWarm, ///< Warm boot=0D + bmS3, ///< S3 resume=0D + bmFast, ///< Fast boot=0D + MrcBootModeMax, ///< MRC_BOOT_MODE enumeration m= aximum value.=0D + MrcBootModeDelim =3D INT32_MAX ///< This value ensures the en= um size is consistent on both sides of the PPI.=0D +} MRC_BOOT_MODE;=0D +#endif //__MRC_BOOT_MODE__=0D +=0D +//=0D +// Matches MrcDdrType enum in MRC=0D +//=0D +#ifndef MRC_DDR_TYPE_DDR4=0D +#define MRC_DDR_TYPE_DDR4 0=0D +#endif=0D +#ifndef MRC_DDR_TYPE_DDR3=0D +#define MRC_DDR_TYPE_DDR3 1=0D +#endif=0D +#ifndef MRC_DDR_TYPE_LPDDR3=0D +#define MRC_DDR_TYPE_LPDDR3 2=0D +#endif=0D +#ifndef MRC_DDR_TYPE_LPDDR4=0D +#define MRC_DDR_TYPE_LPDDR4 3=0D +#endif=0D +#ifndef MRC_DDR_TYPE_WIO2=0D +#define MRC_DDR_TYPE_WIO2 4=0D +#endif=0D +#ifndef MRC_DDR_TYPE_UNKNOWN=0D +#define MRC_DDR_TYPE_UNKNOWN 5=0D +#endif=0D +=0D +#define MAX_PROFILE_NUM 4 // number of memory profiles supported=0D +#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported=0D +=0D +//=0D +// DIMM timings=0D +//=0D +typedef struct {=0D + UINT32 tCK; ///< Memory cycle time, in femtoseconds.=0D + UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's comma= nd rate mode.=0D + UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS l= atency.=0D + UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minim= um CAS write latency time.=0D + UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minim= um four activate window delay time.=0D + UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minim= um active to precharge delay time.=0D + UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minim= um RAS# to CAS# delay time and Row Precharge delay time.=0D + UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minim= um Average Periodic Refresh Interval.=0D + UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time.=0D + UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minim= um per bank refresh recovery delay time.=0D + UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time.=0D + UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minim= um refresh recovery delay time.=0D + UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minim= um row precharge delay time for all banks.=0D + UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time.=0D + UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for same bank groups.=0D + UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minim= um row active to row active delay time for different bank groups.=0D + UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minim= um internal read to precharge command delay time.=0D + UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minim= um write recovery time.=0D + UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time.=0D + UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for same bank groups.=0D + UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minim= um internal write to read command delay time for different bank groups.=0D + UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum= CAS-to-CAS delay for same bank group.=0D +} MRC_CH_TIMING;=0D +=0D +///=0D +/// Memory SMBIOS & OC Memory Data Hob=0D +///=0D +typedef struct {=0D + UINT8 Status; ///< See MrcDimmStatus for the= definition of this field.=0D + UINT8 DimmId;=0D + UINT32 DimmCapacity; ///< DIMM size in MBytes.=0D + UINT16 MfgId;=0D + UINT8 ModulePartNum[20]; ///< Module part number for DD= R3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20= bytes=0D + UINT8 RankInDimm; ///< The number of ranks in th= is DIMM.=0D + UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType i= nformation needed for SMBIOS structure creation.=0D + UINT8 SpdModuleType; ///< Save SPD ModuleType infor= mation needed for SMBIOS structure creation.=0D + UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusW= idth information needed for SMBIOS structure creation.=0D + UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing in= formation needed for SMBIOS structure creation.=0D + UINT16 Speed; ///< The maximum capable speed= of the device, in MHz=0D + UINT8 MdSocket; ///< MdSocket: 0 =3D Memory Do= wn, 1 =3D Socketed. Needed for SMBIOS structure creation.=0D +} DIMM_INFO;=0D +=0D +typedef struct {=0D + UINT8 Status; ///< Indicates whether this ch= annel should be used.=0D + UINT8 ChannelId;=0D + UINT8 DimmCount; ///< Number of valid DIMMs tha= t exist in the channel.=0D + MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values= .=0D + DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output char= acteristics.=0D +} CHANNEL_INFO;=0D +=0D +typedef struct {=0D + UINT8 Status; ///< Indicates whether this co= ntroller should be used.=0D + UINT16 DeviceId; ///< The PCI device id of this= memory controller.=0D + UINT8 RevisionId; ///< The PCI revision id of th= is memory controller.=0D + UINT8 ChannelCount; ///< Number of valid channels = that exist on the controller.=0D + CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel= level definitions.=0D +} CONTROLLER_INFO;=0D +=0D +typedef struct {=0D + UINT64 BaseAddress; ///< Trace Base Address=0D + UINT64 TotalSize; ///< Total Trace Region of Same Cache type=0D + UINT8 CacheType; ///< Trace Cache Type=0D + UINT8 ErrorCode; ///< Trace Region Allocation Fail Error code=0D + UINT8 Rsvd[2];=0D +} PSMI_MEM_INFO;=0D +=0D +typedef struct {=0D + UINT8 Revision;=0D + UINT16 DataWidth; ///< Data width, in bits, of t= his memory device=0D + /** As defined in SMBIOS 3.0 spec=0D + Section 7.18.2 and Table 75=0D + **/=0D + UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or = LPDDR3=0D + UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed= of the device, in megahertz (MHz)=0D + UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock = speed to the memory device, in megahertz (MHz)=0D + /** As defined in SMBIOS 3.0 spec=0D + Section 7.17.3 and Table 72=0D + **/=0D + UINT8 ErrorCorrectionType;=0D +=0D + SiMrcVersion Version;=0D + BOOLEAN EccSupport;=0D + UINT8 MemoryProfile;=0D + UINT32 TotalPhysicalMemorySize;=0D + UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK= value read from SPD XMP profiles if they exist.=0D + UINT8 XmpProfileEnable; ///< If XMP capable= DIMMs are detected, this will indicate which XMP Profiles are common among= all DIMMs.=0D + UINT8 Ratio;=0D + UINT8 RefClk;=0D + UINT32 VddVoltage[MAX_PROFILE_NUM];=0D + CONTROLLER_INFO Controller[MAX_NODE];=0D +} MEMORY_INFO_DATA_HOB;=0D +=0D +/**=0D + Memory Platform Data Hob=0D +=0D + Revision 1:=0D + - Initial version.=0D + Revision 2:=0D + - Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddre= ss fields=0D +**/=0D +typedef struct {=0D + UINT8 Revision;=0D + UINT8 Reserved[3];=0D + UINT32 BootMode;=0D + UINT32 TsegSize;=0D + UINT32 TsegBase;=0D + UINT32 PrmrrSize;=0D + UINT64 PrmrrBase;=0D + UINT32 PramSize;=0D + UINT64 PramBase;=0D + UINT64 DismLimit;=0D + UINT64 DismBase;=0D + UINT32 GttBase;=0D + UINT32 MmioSize;=0D + UINT32 PciEBaseAddress;=0D + PSMI_MEM_INFO PsmiInfo[MAX_TRACE_CACHE_TYPE];=0D +} MEMORY_PLATFORM_DATA;=0D +=0D +typedef struct {=0D + EFI_HOB_GUID_TYPE EfiHobGuidType;=0D + MEMORY_PLATFORM_DATA Data;=0D + UINT8 *Buffer;=0D +} MEMORY_PLATFORM_DATA_HOB;=0D +=0D +#pragma pack (pop)=0D +=0D +#endif // _MEM_INFO_HOB_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol= /SaPolicy.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protoco= l/SaPolicy.h new file mode 100644 index 0000000000..4ff2578038 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include/Protocol/SaPoli= cy.h @@ -0,0 +1,61 @@ +/** @file=0D + Interface definition details between System Agent and platform drivers d= uring DXE phase.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_POLICY_H_=0D +#define _SA_POLICY_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +///=0D +/// Extern the GUID for protocol users.=0D +///=0D +extern EFI_GUID gSaPolicyProtocolGuid;=0D +extern EFI_GUID gGraphicsDxeConfigGuid;=0D +extern EFI_GUID gPcieDxeConfigGuid;=0D +extern EFI_GUID gMemoryDxeConfigGuid;=0D +extern EFI_GUID gVtdDxeConfigGuid;=0D +=0D +/**=0D + Don't change the original SA_POLICY_PROTOCOL_REVISION macro, external=0D + modules maybe have consumed this macro in their source code. Directly=0D + update the SA_POLICY_PROTOCOL_REVISION version number may cause those=0D + external modules to auto mark themselves wrong version info.=0D + Always create new version macro for new Policy protocol interface.=0D +**/=0D +#define SA_POLICY_PROTOCOL_REVISION 1=0D +=0D +#define CPU_PCIE_DEV_END_OF_TABLE 0xFFFF=0D +=0D +#define LTR_MAX_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Snoop Latency=0D +#define LTR_MAX_NON_SNOOP_LATENCY_VALUE 0x0846 ///< Intel recom= mended maximum value for Non-Snoop Latency=0D +=0D +=0D +/**=0D + SA DXE Policy=0D +=0D + The SA_POLICY_PROTOCOL producer drvier is recommended to=0D + set all the SA_POLICY_PROTOCOL size buffer zero before init any member pa= rameter,=0D + this clear step can make sure no random value for those unknow new versio= n parameters.=0D +=0D + Make sure to update the Revision if any change to the protocol, including= the existing=0D + internal structure definations.\n=0D + Note: Here revision will be bumped up when adding/removing any config bl= ock under this structure.\n=0D + Revision 1:=0D + - Initial version.=0D +**/=0D +typedef struct {=0D + CONFIG_BLOCK_TABLE_HEADER TableHeader; ///< Offset 0-31=0D +/*=0D + Individual Config Block Structures are added here in memory as part of A= ddConfigBlock()=0D +*/=0D +} SA_POLICY_PROTOCOL;=0D +=0D +#endif=0D --=20 2.24.0.windows.2