From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by mx.groups.io with SMTP id smtpd.web11.5275.1612510889619185483 for ; Thu, 04 Feb 2021 23:41:29 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.24, mailfrom: heng.luo@intel.com) IronPort-SDR: njuEcKAaJ0YfVnOXXAfOyeXbwHU3nycxN46PX92dGTeZPpBwNh5+v41kTfepCPOIO9gGV24na1 zb9TyVHeVlbg== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="181543639" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="181543639" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:41:27 -0800 IronPort-SDR: CszPYrLVb1ZYZiJDRwP5HXGGOgZBN1ug9sOPHqN1KyRW9/8L2kRLVcU1Bi8ZVBQ1Y4lyoJJ6bI PrbV9JggAezg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="373260258" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 04 Feb 2021 23:41:26 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 08/40] TigerlakeSiliconPkg/SystemAgent: Add IncludePrivate headers Date: Fri, 5 Feb 2021 15:40:13 +0800 Message-Id: <20210205074045.3916-8-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210205074045.3916-1-heng.luo@intel.com> References: <20210205074045.3916-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3171 Adds the following header files: * SystemAgent/IncludePrivate Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaIo= trapSmi.h | 42 ++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol/SaNv= sArea.h | 30 ++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfigHob.h= | 50 ++++++++++++++++++++++++++++++++++++++++++++++++++ Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAreaDef.= h | 222 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++ 4 files changed, 344 insertions(+) diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/P= rotocol/SaIotrapSmi.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Inclu= dePrivate/Protocol/SaIotrapSmi.h new file mode 100644 index 0000000000..2e86d497f9 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol= /SaIotrapSmi.h @@ -0,0 +1,42 @@ +/** @file=0D + This file defines the SA Iotrap SMI Protocol to provide the=0D + I/O address for registered Iotrap SMI.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_IOTRAP_SMI_PROTOCOL_H_=0D +#define _SA_IOTRAP_SMI_PROTOCOL_H_=0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gSaIotrapSmiProtocolGuid;=0D +=0D +#define SA_IOTRAP_SMI_PROTOCOL_REVISION_1 1=0D +=0D +//=0D +// SA IO Trap SMI Protocol definition (Private protocol for RC internal us= e only)=0D +//=0D +typedef struct {=0D +/*=0D + Protocol revision number=0D + Any backwards compatible changes to this protocol will result in an updat= e in the revision number=0D + Major changes will require publication of a new protocol=0D +=0D + Revision 1:=0D + - First version=0D +*/=0D + UINT8 Revision;=0D + UINT16 SaIotrapSmiAddress;=0D +} SA_IOTRAP_SMI_PROTOCOL;=0D +=0D +///=0D +/// Pcie Trap valid types=0D +///=0D +typedef enum {=0D + CpuPciePmTrap,=0D + CpuPcieTrapTypeMaximum=0D +} CPU_PCIE_TRAP_TYPE;=0D +=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/P= rotocol/SaNvsArea.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/Include= Private/Protocol/SaNvsArea.h new file mode 100644 index 0000000000..785a808cf4 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/Protocol= /SaNvsArea.h @@ -0,0 +1,30 @@ +/** @file=0D + Definition of the System Agent global NVS area protocol.=0D + This protocol publishes the address and format of a global ACPI NVS buff= er=0D + used as a communications buffer between SMM/DXE/PEI code and ASL code.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _SYSTEM_AGENT_NVS_AREA_H_=0D +#define _SYSTEM_AGENT_NVS_AREA_H_=0D +=0D +//=0D +// SA NVS Area definition=0D +//=0D +#include =0D +=0D +//=0D +// Extern the GUID for protocol users.=0D +//=0D +extern EFI_GUID gSaNvsAreaProtocolGuid;=0D +=0D +///=0D +/// System Agent Global NVS Area Protocol=0D +///=0D +typedef struct {=0D + SYSTEM_AGENT_NVS_AREA *Area; ///< System Agent Global NVS Area St= ructure=0D +} SYSTEM_AGENT_NVS_AREA_PROTOCOL;=0D +=0D +#endif // _SYSTEM_AGENT_NVS_AREA_H_=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/S= aConfigHob.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate= /SaConfigHob.h new file mode 100644 index 0000000000..65622069e6 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaConfig= Hob.h @@ -0,0 +1,50 @@ +/** @file=0D + The GUID definition for SaConfigHob=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +#ifndef _SA_CONFIG_HOB_H_=0D +#define _SA_CONFIG_HOB_H_=0D +=0D +#include =0D +#include =0D +#include "CpuPcieInfo.h"=0D +#include =0D +=0D +extern EFI_GUID gSaConfigHobGuid;=0D +#define SA_VTD_ENGINE_NUMBER 3=0D +=0D +#pragma pack (push,1)=0D +///=0D +/// DPR Directory Types=0D +///=0D +typedef enum {=0D + EnumDprDirectoryTxt =3D 0,=0D +} DPR_DIRECTORY_ELEMENT;=0D +=0D +#define DPR_DIRECTORY_TYPE_TXT 0x01 ///< DPR directory type = - TXT=0D +#define DPR_DIRECTORY_TYPE_BIOSGUARD 0x02 ///< DPR directory type = - BIOS Guard=0D +#define DPR_DIRECTORY_MAX 1 ///< DPR Maximum Size=0D +=0D +///=0D +/// DPR directory entry definition=0D +///=0D +typedef struct {=0D + UINT8 Type; ///< DPR Directory Type=0D + UINT8 Size; ///< DPR Size in MB=0D + UINT32 PhysBase; ///< Must be 4K aligned (bits 11..0 must be clear= )=0D + UINT16 Reserved; ///< Must be 0=0D +} DPR_DIRECTORY_ENTRY;=0D +=0D +///=0D +/// System Agent Config Hob=0D +///=0D +typedef struct {=0D + EFI_HOB_GUID_TYPE EfiHobGuidType; ///< = GUID Hob type structure for gSaConfigHobGuid=0D + DPR_DIRECTORY_ENTRY DprDirectory[DPR_DIRECTORY_MAX]; ///< = DPR directory entry definition=0D + UINT8 ApertureSize; ///< = Aperture size value=0D + BOOLEAN CridEnable; ///< = This field inidicates if CRID is enabled or disabled (to support Intel(R) S= IPP)=0D +} SA_CONFIG_HOB;=0D +#pragma pack (pop)=0D +#endif=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/S= aNvsAreaDef.h b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivat= e/SaNvsAreaDef.h new file mode 100644 index 0000000000..6ee2343363 --- /dev/null +++ b/Silicon/Intel/TigerlakeSiliconPkg/SystemAgent/IncludePrivate/SaNvsAre= aDef.h @@ -0,0 +1,222 @@ +//=0D +// Automatically generated by GenNvs ver 2.4.6=0D +// Please DO NOT modify !!!=0D +//=0D +=0D +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D + //=0D + // Define SA NVS Area operation region.=0D + //=0D +#ifndef _SA_NVS_AREA_DEF_H_=0D +#define _SA_NVS_AREA_DEF_H_=0D +=0D +#pragma pack (push,1)=0D +typedef struct {=0D + UINT32 IgdOpRegionAddress; ///< Offset 0 IG= D OpRegion base address=0D + UINT8 GfxTurboIMON; ///< Offset 4 IM= ON Current Value=0D + UINT8 IgdState; ///< Offset 5 IG= D State (Primary Display =3D 1)=0D + UINT8 IgdBootType; ///< Offset 6 IG= D Boot Display Device=0D + UINT8 IgdPanelType; ///< Offset 7 IG= D Panel Type CMOS option=0D + UINT8 IgdPanelScaling; ///< Offset 8 IG= D Panel Scaling=0D + UINT8 IgdBiaConfig; ///< Offset 9 IG= D BIA Configuration=0D + UINT8 IgdSscConfig; ///< Offset 10 IG= D SSC Configuration=0D + UINT8 IgdDvmtMemSize; ///< Offset 11 IG= D DVMT Memory Size=0D + UINT8 IgdFunc1Enable; ///< Offset 12 IG= D Function 1 Enable=0D + UINT8 IgdHpllVco; ///< Offset 13 HP= LL VCO=0D + UINT8 IgdSciSmiMode; ///< Offset 14 GM= CH SMI/SCI mode (0=3DSCI)=0D + UINT8 IgdPAVP; ///< Offset 15 IG= D PAVP data=0D + UINT8 CurrentDeviceList; ///< Offset 16 Cu= rrent Attached Device List=0D + UINT16 CurrentDisplayState; ///< Offset 17 Cu= rrent Display State=0D + UINT16 NextDisplayState; ///< Offset 19 Ne= xt Display State=0D + UINT8 NumberOfValidDeviceId; ///< Offset 21 Nu= mber of Valid Device IDs=0D + UINT32 DeviceId1; ///< Offset 22 De= vice ID 1=0D + UINT32 DeviceId2; ///< Offset 26 De= vice ID 2=0D + UINT32 DeviceId3; ///< Offset 30 De= vice ID 3=0D + UINT32 DeviceId4; ///< Offset 34 De= vice ID 4=0D + UINT32 DeviceId5; ///< Offset 38 De= vice ID 5=0D + UINT32 DeviceId6; ///< Offset 42 De= vice ID 6=0D + UINT32 DeviceId7; ///< Offset 46 De= vice ID 7=0D + UINT32 DeviceId8; ///< Offset 50 De= vice ID 8=0D + UINT32 DeviceId9; ///< Offset 54 De= vice ID 9=0D + UINT32 DeviceId10; ///< Offset 58 De= vice ID 10=0D + UINT32 DeviceId11; ///< Offset 62 De= vice ID 11=0D + UINT32 DeviceId12; ///< Offset 66 De= vice ID 12=0D + UINT32 DeviceId13; ///< Offset 70 De= vice ID 13=0D + UINT32 DeviceId14; ///< Offset 74 De= vice ID 14=0D + UINT32 DeviceId15; ///< Offset 78 De= vice ID 15=0D + UINT32 DeviceIdX; ///< Offset 82 De= vice ID for eDP device=0D + UINT32 NextStateDid1; ///< Offset 86 Ne= xt state DID1 for _DGS=0D + UINT32 NextStateDid2; ///< Offset 90 Ne= xt state DID2 for _DGS=0D + UINT32 NextStateDid3; ///< Offset 94 Ne= xt state DID3 for _DGS=0D + UINT32 NextStateDid4; ///< Offset 98 Ne= xt state DID4 for _DGS=0D + UINT32 NextStateDid5; ///< Offset 102 Ne= xt state DID5 for _DGS=0D + UINT32 NextStateDid6; ///< Offset 106 Ne= xt state DID6 for _DGS=0D + UINT32 NextStateDid7; ///< Offset 110 Ne= xt state DID7 for _DGS=0D + UINT32 NextStateDid8; ///< Offset 114 Ne= xt state DID8 for _DGS=0D + UINT32 NextStateDidEdp; ///< Offset 118 Ne= xt state DID for eDP=0D + UINT8 LidState; ///< Offset 122 Li= d State (Lid Open =3D 1)=0D + UINT32 AKsv0; ///< Offset 123 Fi= rst four bytes of AKSV (manufacturing mode)=0D + UINT8 AKsv1; ///< Offset 127 Fi= fth byte of AKSV (manufacturing mode)=0D + UINT8 BrightnessPercentage; ///< Offset 128 Br= ightness Level Percentage=0D + UINT8 AlsEnable; ///< Offset 129 Am= bient Light Sensor Enable=0D + UINT8 AlsAdjustmentFactor; ///< Offset 130 Am= bient Light Adjusment Factor=0D + UINT8 LuxLowValue; ///< Offset 131 LU= X Low Value=0D + UINT8 LuxHighValue; ///< Offset 132 LU= X High Value=0D + UINT8 ActiveLFP; ///< Offset 133 Ac= tive LFP=0D + UINT8 IpuAcpiMode; ///< Offset 134 IP= U ACPI device type (0=3DDisabled, 1=3DAVStream virtual device as child of G= FX)=0D + UINT8 EdpValid; ///< Offset 135 Ch= eck for eDP display device=0D + UINT8 HgMode; ///< Offset 136 SG= Mode (0=3DDisabled, 1=3DHG Muxed, 2=3DHG Muxless, 3=3DDGPU Only)=0D + UINT8 HgFeatureList; ///< Offset 137 HG= Feature List=0D + UINT8 Pcie0GpioSupport; ///< Offset 138 PC= Ie0 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based)=0D + UINT8 Pcie0HoldRstExpanderNo; ///< Offset 139 PC= Ie0 HLD RST IO Expander Number=0D + UINT32 Pcie0HoldRstGpioNo; ///< Offset 140 PC= Ie0 HLD RST GPIO Number=0D + UINT8 Pcie0HoldRstActiveInfo; ///< Offset 144 PC= Ie0 HLD RST GPIO Active Information=0D + UINT8 Pcie0PwrEnExpanderNo; ///< Offset 145 PC= Ie0 PWR Enable IO Expander Number=0D + UINT32 Pcie0PwrEnGpioNo; ///< Offset 146 PC= Ie0 PWR Enable GPIO Number=0D + UINT8 Pcie0PwrEnActiveInfo; ///< Offset 150 PC= Ie0 PWR Enable GPIO Active Information=0D + UINT8 Pcie1GpioSupport; ///< Offset 151 PC= Ie1 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based)=0D + UINT8 Pcie1HoldRstExpanderNo; ///< Offset 152 PC= Ie1 HLD RST IO Expander Number=0D + UINT32 Pcie1HoldRstGpioNo; ///< Offset 153 PC= Ie1 HLD RST GPIO Number=0D + UINT8 Pcie1HoldRstActiveInfo; ///< Offset 157 PC= Ie1 HLD RST GPIO Active Information=0D + UINT8 Pcie1PwrEnExpanderNo; ///< Offset 158 PC= Ie1 PWR Enable IO Expander Number=0D + UINT32 Pcie1PwrEnGpioNo; ///< Offset 159 PC= Ie1 PWR Enable GPIO Number=0D + UINT8 Pcie1PwrEnActiveInfo; ///< Offset 163 PC= Ie1 PWR Enable GPIO Active Information=0D + UINT8 Pcie2GpioSupport; ///< Offset 164 PC= Ie2 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based)=0D + UINT8 Pcie2HoldRstExpanderNo; ///< Offset 165 PC= Ie2 HLD RST IO Expander Number=0D + UINT32 Pcie2HoldRstGpioNo; ///< Offset 166 PC= Ie2 HLD RST GPIO Number=0D + UINT8 Pcie2HoldRstActiveInfo; ///< Offset 170 PC= Ie2 HLD RST GPIO Active Information=0D + UINT8 Pcie2PwrEnExpanderNo; ///< Offset 171 PC= Ie2 PWR Enable IO Expander Number=0D + UINT32 Pcie2PwrEnGpioNo; ///< Offset 172 PC= Ie2 PWR Enable GPIO Number=0D + UINT8 Pcie2PwrEnActiveInfo; ///< Offset 176 PC= Ie2 PWR Enable GPIO Active Information=0D + UINT8 Pcie3GpioSupport; ///< Offset 177 PC= Ie3 GPIO Support (0=3DDisabled, 1=3DPCH Based, 2=3DI2C Based)=0D + UINT8 Pcie3HoldRstExpanderNo; ///< Offset 178 PC= Ie3 HLD RST IO Expander Number=0D + UINT32 Pcie3HoldRstGpioNo; ///< Offset 179 PC= Ie3 HLD RST GPIO Number=0D + UINT8 Pcie3HoldRstActiveInfo; ///< Offset 183 PC= Ie3 HLD RST GPIO Active Information=0D + UINT8 Pcie3PwrEnExpanderNo; ///< Offset 184 PC= Ie3 PWR Enable IO Expander Number=0D + UINT32 Pcie3PwrEnGpioNo; ///< Offset 185 PC= Ie3 PWR Enable GPIO Number=0D + UINT8 Pcie3PwrEnActiveInfo; ///< Offset 189 PC= Ie3 PWR Enable GPIO Active Information=0D + UINT32 Pcie3WakeGpioNo; ///< Offset 190 PC= Ie3 RTD3 Device Wake GPIO Number=0D + UINT16 DelayAfterPwrEn; ///< Offset 194 De= lay after power enable for PCIe=0D + UINT16 DelayAfterHoldReset; ///< Offset 196 De= lay after Hold Reset for PCIe=0D + UINT8 Pcie0EpCapOffset; ///< Offset 198 PC= Ie0 Endpoint Capability Structure Offset=0D + UINT32 XPcieCfgBaseAddress; ///< Offset 199 An= y Device's PCIe Config Space Base Address=0D + UINT16 GpioBaseAddress; ///< Offset 203 GP= IO Base Address=0D + UINT32 NvIgOpRegionAddress; ///< Offset 205 NV= IG opregion address=0D + UINT32 NvHmOpRegionAddress; ///< Offset 209 NV= HM opregion address=0D + UINT32 ApXmOpRegionAddress; ///< Offset 213 AM= DA opregion address=0D + UINT8 Peg0LtrEnable; ///< Offset 217 La= tency Tolerance Reporting Enable=0D + UINT8 Peg0ObffEnable; ///< Offset 218 Op= timized Buffer Flush and Fill=0D + UINT8 Peg1LtrEnable; ///< Offset 219 La= tency Tolerance Reporting Enable=0D + UINT8 Peg1ObffEnable; ///< Offset 220 Op= timized Buffer Flush and Fill=0D + UINT8 Peg2LtrEnable; ///< Offset 221 La= tency Tolerance Reporting Enable=0D + UINT8 Peg2ObffEnable; ///< Offset 222 Op= timized Buffer Flush and Fill=0D + UINT8 Peg3LtrEnable; ///< Offset 223 La= tency Tolerance Reporting Enable=0D + UINT8 Peg3ObffEnable; ///< Offset 224 Op= timized Buffer Flush and Fill=0D + UINT16 PegLtrMaxSnoopLatency; ///< Offset 225 SA= Peg Latency Tolerance Reporting Max Snoop Latency=0D + UINT16 PegLtrMaxNoSnoopLatency; ///< Offset 227 SA= Peg Latency Tolerance Reporting Max No Snoop Latency=0D + UINT64 Mmio64Base; ///< Offset 229 Ba= se of above 4GB MMIO resource=0D + UINT64 Mmio64Length; ///< Offset 237 Le= ngth of above 4GB MMIO resource=0D + UINT32 CpuIdInfo; ///< Offset 245 CP= U ID info to get Family Id or Stepping=0D + UINT32 Mmio32Base; ///< Offset 249 Ba= se of below 4GB MMIO resource=0D + UINT32 Mmio32Length; ///< Offset 253 Le= ngth of below 4GB MMIO resource=0D + UINT32 Pcie0WakeGpioNo; ///< Offset 257 PC= Ie0 RTD3 Device Wake GPIO Number=0D + UINT32 Pcie1WakeGpioNo; ///< Offset 261 PC= Ie1 RTD3 Device Wake GPIO Number=0D + UINT32 Pcie2WakeGpioNo; ///< Offset 265 PC= Ie2 RTD3 Device Wake GPIO Number=0D + UINT8 VtdDisable; ///< Offset 269 VT= -d Enable/Disable=0D + UINT32 VtdBaseAddress[7]; ///< Offset 270 VT= -d Base Address 1=0D + ///< Offset 274 VT= -d Base Address 2=0D + ///< Offset 278 VT= -d Base Address 3=0D + ///< Offset 282 VT= -d Base Address 4 (iTBT PCIE0)=0D + ///< Offset 286 VT= -d Base Address 5 (iTBT PCIE1)=0D + ///< Offset 290 VT= -d Base Address 6 (iTBT PCIE2)=0D + ///< Offset 294 VT= -d Base Address 7 (iTBT PCIE3)=0D + UINT16 VtdEngine1Vid; ///< Offset 298 VT= -d Engine#1 Vendor ID=0D + UINT16 VtdEngine2Vid; ///< Offset 300 VT= -d Engine#2 Vendor ID=0D + UINT8 RootPortIndex; ///< Offset 302 Ro= otPort Number=0D + UINT32 RootPortAddress; ///< Offset 303 Ro= otPortAddress=0D + UINT8 CpuTraceHubMode; ///< Offset 307 CP= U Trace Hub Mode=0D + UINT8 SimicsEnvironment; ///< Offset 308 Si= mics Environment information=0D + UINT8 ItbtXhciEn; ///< Offset 309 TC= SS XHCI Device Enable=0D + UINT8 ItbtXdciEn; ///< Offset 310 TC= SS XDCI Device Enable=0D + UINT8 ItbtDmaEn[2]; ///< Offset 311 TC= SS DMA 0 Device Enable=0D + ///< Offset 312 TC= SS DMA 1 Device Enable=0D + UINT8 ItbtPcieRpEn[4]; ///< Offset 313 TC= SS ItbtPcieRp PCIE RP 0 Device Enable=0D + ///< Offset 314 TC= SS ItbtPcieRp PCIE RP 1 Device Enable=0D + ///< Offset 315 TC= SS ItbtPcieRp PCIE RP 2 Device Enable=0D + ///< Offset 316 TC= SS ItbtPcieRp PCIE RP 3 Device Enable=0D + UINT32 ItbtPcieRpAddress[4]; ///< Offset 317 TC= SS ItbtPcie Root Port address 0=0D + ///< Offset 321 TC= SS ItbtPcie Root Port address 1=0D + ///< Offset 325 TC= SS ItbtPcie Root Port address 2=0D + ///< Offset 329 TC= SS ItbtPcie Root Port address 3=0D + UINT32 TcssxDCIPwrDnScale; ///< Offset 333 TC= SS xDCI Power Down Scale Value, DWC_USB3_GCTL_INIT[31:19]=0D + UINT8 TcssxDCIInt; ///< Offset 337 TC= SS xDCI Int Pin=0D + UINT8 TcssxDCIIrq; ///< Offset 338 TC= SS xDCI Irq Number=0D + UINT8 TcssRtd3; ///< Offset 339 TC= SS RTD3=0D + UINT32 TcssDma0RmrrAddr; ///< Offset 340 TC= SS DMA0 RMRR address=0D + UINT32 TcssDma1RmrrAddr; ///< Offset 344 TC= SS DMA1 RMRR address=0D + UINT8 LtrEnable[4]; ///< Offset 348 La= tency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.=0D + ///< Offset 349 La= tency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.=0D + ///< Offset 350 La= tency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.=0D + ///< Offset 351 La= tency Tolerance Reporting Mechanism. 0: Disable; 1: Enable.=0D + UINT16 PcieLtrMaxSnoopLatency[4]; ///< Offset 352 PC= IE LTR max snoop Latency 0=0D + ///< Offset 354 PC= IE LTR max snoop Latency 1=0D + ///< Offset 356 PC= IE LTR max snoop Latency 2=0D + ///< Offset 358 PC= IE LTR max snoop Latency 3=0D + UINT16 PcieLtrMaxNoSnoopLatency[4]; ///< Offset 360 PC= IE LTR max no snoop Latency 0=0D + ///< Offset 362 PC= IE LTR max no snoop Latency 1=0D + ///< Offset 364 PC= IE LTR max no snoop Latency 2=0D + ///< Offset 366 PC= IE LTR max no snoop Latency 3=0D + UINT8 IomReady; ///< Offset 368 IO= M Ready=0D + UINT8 TcssIomVccSt; ///< Offset 369 TC= SS IOM VccSt=0D + UINT8 CpuPcieRp0Enable; ///< Offset 370 <0= :Disabled, 1:Enabled>=0D + UINT8 CpuPcieRp1Enable; ///< Offset 371 <0= :Disabled, 1:Enabled>=0D + UINT8 CpuPcieRp2Enable; ///< Offset 372 <0= :Disabled, 1:Enabled>=0D + UINT8 CpuPcieRp3Enable; ///< Offset 373 <0= :Disabled, 1:Enabled>=0D + UINT8 VmdEnable; ///< Offset 374 VM= D Device Enable=0D + UINT32 DeviceIdY; ///< Offset 375 De= vice ID for second LFP device=0D + UINT32 NextStateDidEdp2; ///< Offset 379 Ne= xt state DID for Second Display=0D + UINT8 SlotSelection; ///< Offset 383 PC= Ie slot selection=0D + UINT8 VmdRp1to8; ///< Offset 384 VM= D PCH RP 1 to 8 <0:Disabled, 1:Enabled>=0D + UINT8 VmdRp9to16; ///< Offset 385 VM= D PCH RP 9 to 16 <0:Disabled, 1:Enabled>=0D + UINT8 VmdRp17to24; ///< Offset 386 VM= D PCH RP 17 to 24 <0:Disabled, 1:Enabled>=0D + UINT8 VmdSataPort[8]; ///< Offset 387 VM= D SATA PORT 0 <0:Disabled, 1:Enabled>=0D + ///< Offset 388 VM= D SATA PORT 1 <0:Disabled, 1:Enabled>=0D + ///< Offset 389 VM= D SATA PORT 2 <0:Disabled, 1:Enabled>=0D + ///< Offset 390 VM= D SATA PORT 3 <0:Disabled, 1:Enabled>=0D + ///< Offset 391 VM= D SATA PORT 4 <0:Disabled, 1:Enabled>=0D + ///< Offset 392 VM= D SATA PORT 5 <0:Disabled, 1:Enabled>=0D + ///< Offset 393 VM= D SATA PORT 6 <0:Disabled, 1:Enabled>=0D + ///< Offset 394 VM= D SATA PORT 7 <0:Disabled, 1:Enabled>=0D + UINT8 VmdCpuRp; ///< Offset 395 VM= D CPU RP <0:Disabled, 1:Enabled>=0D + UINT8 CpuPcieRtd3; ///< Offset 396 RT= D3 Support for CPU PCIE.=0D + UINT32 LaneUsed; ///< Offset 397 La= ne Used of each CSI Port <0:Not Configured, 1:x1, 2:x2, 3:x3 4:x4>=0D + UINT32 CsiSpeed; ///< Offset 401 Sp= eed of each CSI Port <0:Not configured, 1:<416GMbps, 2:<1.5Gbps, 3:<2.0Gbps= , 4:<2.5Gbps, 5:<4Gbps, 6:>4Gbps>=0D + UINT8 MaxPegPortNumber; ///< Offset 405 Ma= x PEG port number=0D + UINT8 MemBootMode; ///< Offset 406 Cu= rrent Memory Boot Mode <0: BOOT_MODE_1LM(Default), 1: BOOT_MODE_2LM, 2: BOO= T_MODE_PROVISION>=0D + UINT8 DpmemSupport; ///< Offset 407 Dy= namic PMem Support <0: Disabled, 1:Enabled>=0D + UINT64 PmemStartingAddress; ///< Offset 408 Pr= ivate Pmem Starting address=0D + UINT64 PmemRangeLength; ///< Offset 416 Pr= ivate Pmem Range Length=0D + UINT8 Pcie3EpCapOffset; ///< Offset 424 PC= Ie3 Endpoint Capability Structure Offset=0D + UINT8 Pcie0SrcClkNo; ///< Offset 425 PC= Ie0 RTD3 Device Source Clock Number=0D + UINT8 Pcie1SrcClkNo; ///< Offset 426 PC= Ie1 RTD3 Device Source Clock Number=0D + UINT8 Pcie2SrcClkNo; ///< Offset 427 PC= Ie2 RTD3 Device Source Clock Number=0D + UINT8 Pcie3SrcClkNo; ///< Offset 428 PC= Ie2 RTD3 Device Source Clock Number=0D + UINT8 Pcie0SecBusNum; ///< Offset 429 PC= Ie0 Secondary Bus Number (PCIe0 Endpoint Bus Number)=0D + UINT8 Pcie1SecBusNum; ///< Offset 430 PC= Ie1 Secondary Bus Number (PCIe0 Endpoint Bus Number)=0D + UINT8 Pcie2SecBusNum; ///< Offset 431 PC= Ie2 Secondary Bus Number (PCIe0 Endpoint Bus Number)=0D + UINT8 Pcie3SecBusNum; ///< Offset 432 PC= Ie2 Secondary Bus Number (PCIe0 Endpoint Bus Number)=0D + UINT8 Pcie1EpCapOffset; ///< Offset 433 PC= Ie1 Endpoint Capability Structure Offset=0D + UINT8 Pcie2EpCapOffset; ///< Offset 434 PC= Ie2 Endpoint Capability Structure Offset=0D + UINT8 IsBridgeDeviceBehindPeg1; ///< Offset 435 Is= bridge device behind PEG1=0D + UINT8 IsBridgeDeviceBehindPeg2; ///< Offset 436 Is= bridge device behind PEG2=0D + UINT8 IsBridgeDeviceBehindPeg3; ///< Offset 437 Is= bridge device behind PEG3=0D + UINT8 HgSlot; ///< Offset 438 Sl= ot selection between PCH/PEG=0D +} SYSTEM_AGENT_NVS_AREA;=0D +=0D +#pragma pack(pop)=0D +#endif=0D --=20 2.24.0.windows.2