From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga06.intel.com (mga06.intel.com []) by mx.groups.io with SMTP id smtpd.web09.5115.1612511895936364606 for ; Thu, 04 Feb 2021 23:58:18 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: ray.ni@intel.com) IronPort-SDR: ytJLzc7Ay7vzqoUEsDiT+0GW2ZnYQ3tigG6JHQLN3wLJBSuUJIQMSDPQv2NU1jNAzpafprnVmF Q8PeIkV3VDhw== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="242902251" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="242902251" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 04 Feb 2021 23:58:17 -0800 IronPort-SDR: JATrtR28z038XSdFyw+mtv1rWl8QN5zx3CDnv6fQIAliWa72MzNPUnWNb9xVFHnPpPncH3Chqz Apv8ypwUjAqg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="434322781" Received: from ray-dev.ccr.corp.intel.com ([10.239.158.87]) by orsmga001.jf.intel.com with ESMTP; 04 Feb 2021 23:58:15 -0800 From: "Ni, Ray" To: devel@edk2.groups.io Cc: Eric Dong , Laszlo Ersek , Rahul Kumar Subject: [PATCH v2 2/3] UefiCpuPkg/MpInitLib: Use NASM struc to avoid hardcode offset Date: Fri, 5 Feb 2021 15:58:09 +0800 Message-Id: <20210205075810.981-3-ray.ni@intel.com> X-Mailer: git-send-email 2.27.0.windows.1 In-Reply-To: <20210205075810.981-1-ray.ni@intel.com> References: <20210205075810.981-1-ray.ni@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable In Windows environment, "dumpbin /disasm" is used to verify the disassembly before and after using NASM struc doesn't change. Signed-off-by: Ray Ni Cc: Eric Dong Cc: Laszlo Ersek Cc: Rahul Kumar --- UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf | 5 +- UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc | 43 -------- .../Library/MpInitLib/Ia32/MpFuncs.nasm | 82 +++++++------- UefiCpuPkg/Library/MpInitLib/MpEqu.inc | 103 ++++++++++++++++++ UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf | 5 +- UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc | 45 -------- UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm | 94 ++++++++-------- 7 files changed, 195 insertions(+), 182 deletions(-) delete mode 100644 UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc create mode 100644 UefiCpuPkg/Library/MpInitLib/MpEqu.inc delete mode 100644 UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc diff --git a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/DxeMpInitLib.inf index 1771575c69..860a9750e2 100644 --- a/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/DxeMpInitLib.inf @@ -1,7 +1,7 @@ ## @file=0D # MP Initialize Library instance for DXE driver.=0D #=0D -# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
= =0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -22,14 +22,13 @@ [Defines] #=0D =0D [Sources.IA32]=0D - Ia32/MpEqu.inc=0D Ia32/MpFuncs.nasm=0D =0D [Sources.X64]=0D - X64/MpEqu.inc=0D X64/MpFuncs.nasm=0D =0D [Sources.common]=0D + MpEqu.inc=0D DxeMpLib.c=0D MpLib.c=0D MpLib.h=0D diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc b/UefiCpuPkg/Libra= ry/MpInitLib/Ia32/MpEqu.inc deleted file mode 100644 index 4f5a7c859a..0000000000 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpEqu.inc +++ /dev/null @@ -1,43 +0,0 @@ -;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2016, Intel Corporation. All rights reserved.
=0D -; SPDX-License-Identifier: BSD-2-Clause-Patent=0D -;=0D -; Module Name:=0D -;=0D -; MpEqu.inc=0D -;=0D -; Abstract:=0D -;=0D -; This is the equates file for Multiple Processor support=0D -;=0D -;-------------------------------------------------------------------------= ------=0D -=0D -VacantFlag equ 00h=0D -NotVacantFlag equ 0ffh=0D -=0D -CPU_SWITCH_STATE_IDLE equ 0=0D -CPU_SWITCH_STATE_STORED equ 1=0D -CPU_SWITCH_STATE_LOADED equ 2=0D -=0D -LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart)=0D -StackStartAddressLocation equ LockLocation + 04h=0D -StackSizeLocation equ LockLocation + 08h=0D -ApProcedureLocation equ LockLocation + 0Ch=0D -GdtrLocation equ LockLocation + 10h=0D -IdtrLocation equ LockLocation + 16h=0D -BufferStartLocation equ LockLocation + 1Ch=0D -ModeOffsetLocation equ LockLocation + 20h=0D -ApIndexLocation equ LockLocation + 24h=0D -CodeSegmentLocation equ LockLocation + 28h=0D -DataSegmentLocation equ LockLocation + 2Ch=0D -EnableExecuteDisableLocation equ LockLocation + 30h=0D -Cr3Location equ LockLocation + 34h=0D -InitFlagLocation equ LockLocation + 38h=0D -CpuInfoLocation equ LockLocation + 3Ch=0D -NumApsExecutingLocation equ LockLocation + 40h=0D -InitializeFloatingPointUnitsAddress equ LockLocation + 48h=0D -ModeTransitionMemoryLocation equ LockLocation + 4Ch=0D -ModeTransitionSegmentLocation equ LockLocation + 50h=0D -ModeHighMemoryLocation equ LockLocation + 52h=0D -ModeHighSegmentLocation equ LockLocation + 56h=0D -=0D diff --git a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm b/UefiCpuPkg/Li= brary/MpInitLib/Ia32/MpFuncs.nasm index 7e81d24aa6..2f1b102717 100644 --- a/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/Ia32/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -39,21 +39,21 @@ BITS 16 mov fs, ax=0D mov gs, ax=0D =0D - mov si, BufferStartLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart)=0D mov ebx, [si]=0D =0D - mov si, DataSegmentLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment)=0D mov edx, [si]=0D =0D ;=0D ; Get start address of 32-bit code in low memory (<1MB)=0D ;=0D - mov edi, ModeTransitionMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeTransitionMemory)=0D =0D - mov si, GdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)=0D o32 lgdt [cs:si]=0D =0D - mov si, IdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)=0D o32 lidt [cs:si]=0D =0D ;=0D @@ -82,7 +82,7 @@ Flat32Start: ; protecte= d mode entry point mov esi, ebx=0D =0D mov edi, esi=0D - add edi, EnableExecuteDisableLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (EnableExecuteDisable)=0D cmp byte [edi], 0=0D jz SkipEnableExecuteDisable=0D =0D @@ -96,7 +96,7 @@ Flat32Start: ; protecte= d mode entry point wrmsr=0D =0D mov edi, esi=0D - add edi, Cr3Location=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3)=0D mov eax, dword [edi]=0D mov cr3, eax=0D =0D @@ -110,19 +110,19 @@ Flat32Start: ; prot= ected mode entry point =0D SkipEnableExecuteDisable:=0D mov edi, esi=0D - add edi, InitFlagLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)=0D cmp dword [edi], 1 ; 1 =3D=3D ApInitConfig=0D jnz GetApicId=0D =0D ; Increment the number of APs executing here as early as possible=0D ; This is decremented in C code when AP is finished executing=0D mov edi, esi=0D - add edi, NumApsExecutingLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting)=0D lock inc dword [edi]=0D =0D ; AP init=0D mov edi, esi=0D - add edi, LockLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (Lock)=0D mov eax, NotVacantFlag=0D =0D TestLock:=0D @@ -131,7 +131,7 @@ TestLock: jz TestLock=0D =0D mov ecx, esi=0D - add ecx, ApIndexLocation=0D + add ecx, MP_CPU_EXCHANGE_INFO_FIELD (ApIndex)=0D inc dword [ecx]=0D mov ebx, [ecx]=0D =0D @@ -140,13 +140,13 @@ Releaselock: xchg [edi], eax=0D =0D mov edi, esi=0D - add edi, StackSizeLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackSize)=0D mov eax, [edi]=0D mov ecx, ebx=0D inc ecx=0D mul ecx ; EAX =3D StackSize * (Cp= uNumber + 1)=0D mov edi, esi=0D - add edi, StackStartAddressLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackStart)=0D add eax, [edi]=0D mov esp, eax=0D jmp CProcedureInvoke=0D @@ -179,18 +179,18 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp()=0D ;=0D xor ebx, ebx=0D - lea eax, [esi + CpuInfoLocation]=0D + lea eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)]=0D mov edi, [eax]=0D =0D GetNextProcNumber:=0D - cmp [edi], edx ; APIC ID match?=0D + cmp dword [edi + CPU_INFO_IN_HOB.InitialApicId], edx ; APIC ID= match?=0D jz ProgramStack=0D - add edi, 20=0D + add edi, CPU_INFO_IN_HOB_size=0D inc ebx=0D jmp GetNextProcNumber=0D =0D ProgramStack:=0D - mov esp, [edi + 12]=0D + mov esp, dword [edi + CPU_INFO_IN_HOB.ApTopOfStack]=0D =0D CProcedureInvoke:=0D push ebp ; push BIST data at top of AP stack=0D @@ -203,11 +203,11 @@ CProcedureInvoke: =0D push ebx ; Push ApIndex=0D mov eax, esi=0D - add eax, LockLocation=0D + add eax, MP_CPU_EXCHANGE_INFO_OFFSET=0D push eax ; push address of exchange info data buff= er=0D =0D mov edi, esi=0D - add edi, ApProcedureLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction)=0D mov eax, [edi]=0D =0D call eax ; Invoke C function=0D @@ -270,17 +270,17 @@ ASM_PFX(AsmGetAddressMap): mov ebp,esp=0D =0D mov ebx, [ebp + 24h]=0D - mov dword [ebx], RendezvousFunnelProcStart=0D - mov dword [ebx + 4h], Flat32Start - RendezvousFunnelProcStart= =0D - mov dword [ebx + 8h], RendezvousFunnelProcEnd - RendezvousFunn= elProcStart=0D - mov dword [ebx + 0Ch], AsmRelocateApLoopStart=0D - mov dword [ebx + 10h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start=0D - mov dword [ebx + 14h], Flat32Start - RendezvousFunnelProcStart= =0D - mov dword [ebx + 18h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize=0D - mov dword [ebx + 1Ch], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset=0D - mov dword [ebx + 20h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset=0D - mov dword [ebx + 24h], 0 = ; SwitchToRealPM16ModeOffset=0D - mov dword [ebx + 28h], 0 = ; SwitchToRealPM16ModeSize=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddres= s], RendezvousFunnelProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], Flat= 32Start - RendezvousFunnelProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize],= RendezvousFunnelProcEnd - RendezvousFunnelProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], AsmRelocateApLoopStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], Swi= tchToRealProcEnd - SwitchToRealProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], S= witchToRealProcStart - RendezvousFunnelProcStart=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], 0=0D + mov dword [ebx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSi= ze], 0=0D =0D popad=0D ret=0D @@ -310,18 +310,18 @@ ASM_PFX(AsmExchangeRole): mov eax, cr0=0D push eax=0D =0D - sgdt [esi + 8]=0D - sidt [esi + 14]=0D + sgdt [esi + CPU_EXCHANGE_ROLE_INFO.Gdtr]=0D + sidt [esi + CPU_EXCHANGE_ROLE_INFO.Idtr]=0D =0D ; Store the its StackPointer=0D - mov [esi + 4],esp=0D + mov [esi + CPU_EXCHANGE_ROLE_INFO.StackPointer],esp=0D =0D ; update its switch state to STORED=0D - mov byte [esi], CPU_SWITCH_STATE_STORED=0D + mov byte [esi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _STORED=0D =0D WaitForOtherStored:=0D ; wait until the other CPU finish storing its state=0D - cmp byte [edi], CPU_SWITCH_STATE_STORED=0D + cmp byte [edi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _STORED=0D jz OtherStored=0D pause=0D jmp WaitForOtherStored=0D @@ -329,21 +329,21 @@ WaitForOtherStored: OtherStored:=0D ; Since another CPU already stored its state, load them=0D ; load GDTR value=0D - lgdt [edi + 8]=0D + lgdt [edi + CPU_EXCHANGE_ROLE_INFO.Gdtr]=0D =0D ; load IDTR value=0D - lidt [edi + 14]=0D + lidt [edi + CPU_EXCHANGE_ROLE_INFO.Idtr]=0D =0D ; load its future StackPointer=0D - mov esp, [edi + 4]=0D + mov esp, [edi + CPU_EXCHANGE_ROLE_INFO.StackPointer]=0D =0D ; update the other CPU's switch state to LOADED=0D - mov byte [edi], CPU_SWITCH_STATE_LOADED=0D + mov byte [edi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _LOADED=0D =0D WaitForOtherLoaded:=0D ; wait until the other CPU finish loading new state,=0D ; otherwise the data in stack may corrupt=0D - cmp byte [esi], CPU_SWITCH_STATE_LOADED=0D + cmp byte [esi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _LOADED=0D jz OtherLoaded=0D pause=0D jmp WaitForOtherLoaded=0D diff --git a/UefiCpuPkg/Library/MpInitLib/MpEqu.inc b/UefiCpuPkg/Library/Mp= InitLib/MpEqu.inc new file mode 100644 index 0000000000..46c2b5c116 --- /dev/null +++ b/UefiCpuPkg/Library/MpInitLib/MpEqu.inc @@ -0,0 +1,103 @@ +;-------------------------------------------------------------------------= ----- ;=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D +; SPDX-License-Identifier: BSD-2-Clause-Patent=0D +;=0D +; Module Name:=0D +;=0D +; MpEqu.inc=0D +;=0D +; Abstract:=0D +;=0D +; This is the equates file for Multiple Processor support=0D +;=0D +;-------------------------------------------------------------------------= ------=0D +%include "Nasm.inc"=0D +=0D +VacantFlag equ 00h=0D +NotVacantFlag equ 0ffh=0D +=0D +CPU_SWITCH_STATE_IDLE equ 0=0D +CPU_SWITCH_STATE_STORED equ 1=0D +CPU_SWITCH_STATE_LOADED equ 2=0D +=0D +;=0D +; Equivalent NASM structure of MP_ASSEMBLY_ADDRESS_MAP=0D +;=0D +struc MP_ASSEMBLY_ADDRESS_MAP=0D + .RendezvousFunnelAddress CTYPE_UINTN 1=0D + .ModeEntryOffset CTYPE_UINTN 1=0D + .RendezvousFunnelSize CTYPE_UINTN 1=0D + .RelocateApLoopFuncAddress CTYPE_UINTN 1=0D + .RelocateApLoopFuncSize CTYPE_UINTN 1=0D + .ModeTransitionOffset CTYPE_UINTN 1=0D + .SwitchToRealSize CTYPE_UINTN 1=0D + .SwitchToRealOffset CTYPE_UINTN 1=0D + .SwitchToRealNoNxOffset CTYPE_UINTN 1=0D + .SwitchToRealPM16ModeOffset CTYPE_UINTN 1=0D + .SwitchToRealPM16ModeSize CTYPE_UINTN 1=0D +endstruc=0D +=0D +;=0D +; Equivalent NASM structure of IA32_DESCRIPTOR=0D +;=0D +struc IA32_DESCRIPTOR=0D + .Limit CTYPE_UINT16 1=0D + .Base CTYPE_UINTN 1=0D +endstruc=0D +=0D +;=0D +; Equivalent NASM structure of CPU_EXCHANGE_ROLE_INFO=0D +;=0D +struc CPU_EXCHANGE_ROLE_INFO=0D + ; State is defined as UINT8 in C header file=0D + ; Define it as UINTN here to guarantee the fields that follow State=0D + ; is naturally aligned. The structure layout doesn't change.=0D + .State CTYPE_UINTN 1=0D + .StackPointer CTYPE_UINTN 1=0D + .Gdtr CTYPE_UINT8 IA32_DESCRIPTOR_size=0D + .Idtr CTYPE_UINT8 IA32_DESCRIPTOR_size=0D +endstruc=0D +=0D +;=0D +; Equivalent NASM structure of CPU_INFO_IN_HOB=0D +;=0D +struc CPU_INFO_IN_HOB=0D + .InitialApicId CTYPE_UINT32 1=0D + .ApicId CTYPE_UINT32 1=0D + .Health CTYPE_UINT32 1=0D + .ApTopOfStack CTYPE_UINT64 1=0D +endstruc=0D +=0D +;=0D +; Equivalent NASM structure of MP_CPU_EXCHANGE_INFO=0D +;=0D +struc MP_CPU_EXCHANGE_INFO=0D + .Lock: CTYPE_UINTN 1=0D + .StackStart: CTYPE_UINTN 1=0D + .StackSize: CTYPE_UINTN 1=0D + .CFunction: CTYPE_UINTN 1=0D + .GdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size=0D + .IdtrProfile: CTYPE_UINT8 IA32_DESCRIPTOR_size=0D + .BufferStart: CTYPE_UINTN 1=0D + .ModeOffset: CTYPE_UINTN 1=0D + .ApIndex: CTYPE_UINTN 1=0D + .CodeSegment: CTYPE_UINTN 1=0D + .DataSegment: CTYPE_UINTN 1=0D + .EnableExecuteDisable: CTYPE_UINTN 1=0D + .Cr3: CTYPE_UINTN 1=0D + .InitFlag: CTYPE_UINTN 1=0D + .CpuInfo: CTYPE_UINTN 1=0D + .NumApsExecuting: CTYPE_UINTN 1=0D + .CpuMpData: CTYPE_UINTN 1=0D + .InitializeFloatingPointUnits: CTYPE_UINTN 1=0D + .ModeTransitionMemory: CTYPE_UINT32 1=0D + .ModeTransitionSegment: CTYPE_UINT16 1=0D + .ModeHighMemory: CTYPE_UINT32 1=0D + .ModeHighSegment: CTYPE_UINT16 1=0D + .Enable5LevelPaging: CTYPE_BOOLEAN 1=0D + .SevEsIsEnabled: CTYPE_BOOLEAN 1=0D + .GhcbBase: CTYPE_UINTN 1=0D +endstruc=0D +=0D +MP_CPU_EXCHANGE_INFO_OFFSET equ (SwitchToRealProcEnd - RendezvousFunnelPro= cStart)=0D +%define MP_CPU_EXCHANGE_INFO_FIELD(Field) (MP_CPU_EXCHANGE_INFO_OFFSET + M= P_CPU_EXCHANGE_INFO. %+ Field)=0D diff --git a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf b/UefiCpuPkg/Lib= rary/MpInitLib/PeiMpInitLib.inf index 34abf25d43..49b0ffe8be 100644 --- a/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf +++ b/UefiCpuPkg/Library/MpInitLib/PeiMpInitLib.inf @@ -1,7 +1,7 @@ ## @file=0D # MP Initialize Library instance for PEI driver.=0D #=0D -# Copyright (c) 2016 - 2020, Intel Corporation. All rights reserved.
= =0D +# Copyright (c) 2016 - 2021, Intel Corporation. All rights reserved.
= =0D # SPDX-License-Identifier: BSD-2-Clause-Patent=0D #=0D ##=0D @@ -22,14 +22,13 @@ [Defines] #=0D =0D [Sources.IA32]=0D - Ia32/MpEqu.inc=0D Ia32/MpFuncs.nasm=0D =0D [Sources.X64]=0D - X64/MpEqu.inc=0D X64/MpFuncs.nasm=0D =0D [Sources.common]=0D + MpEqu.inc=0D PeiMpLib.c=0D MpLib.c=0D MpLib.h=0D diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc b/UefiCpuPkg/Librar= y/MpInitLib/X64/MpEqu.inc deleted file mode 100644 index c92daaaffd..0000000000 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpEqu.inc +++ /dev/null @@ -1,45 +0,0 @@ -;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D -; SPDX-License-Identifier: BSD-2-Clause-Patent=0D -;=0D -; Module Name:=0D -;=0D -; MpEqu.inc=0D -;=0D -; Abstract:=0D -;=0D -; This is the equates file for Multiple Processor support=0D -;=0D -;-------------------------------------------------------------------------= ------=0D -=0D -VacantFlag equ 00h=0D -NotVacantFlag equ 0ffh=0D -=0D -CPU_SWITCH_STATE_IDLE equ 0=0D -CPU_SWITCH_STATE_STORED equ 1=0D -CPU_SWITCH_STATE_LOADED equ 2=0D -=0D -LockLocation equ (SwitchToRealProcEnd - Rendezvous= FunnelProcStart)=0D -StackStartAddressLocation equ LockLocation + 08h=0D -StackSizeLocation equ LockLocation + 10h=0D -ApProcedureLocation equ LockLocation + 18h=0D -GdtrLocation equ LockLocation + 20h=0D -IdtrLocation equ LockLocation + 2Ah=0D -BufferStartLocation equ LockLocation + 34h=0D -ModeOffsetLocation equ LockLocation + 3Ch=0D -ApIndexLocation equ LockLocation + 44h=0D -CodeSegmentLocation equ LockLocation + 4Ch=0D -DataSegmentLocation equ LockLocation + 54h=0D -EnableExecuteDisableLocation equ LockLocation + 5Ch=0D -Cr3Location equ LockLocation + 64h=0D -InitFlagLocation equ LockLocation + 6Ch=0D -CpuInfoLocation equ LockLocation + 74h=0D -NumApsExecutingLocation equ LockLocation + 7Ch=0D -InitializeFloatingPointUnitsAddress equ LockLocation + 8Ch=0D -ModeTransitionMemoryLocation equ LockLocation + 94h=0D -ModeTransitionSegmentLocation equ LockLocation + 98h=0D -ModeHighMemoryLocation equ LockLocation + 9Ah=0D -ModeHighSegmentLocation equ LockLocation + 9Eh=0D -Enable5LevelPagingLocation equ LockLocation + 0A0h=0D -SevEsIsEnabledLocation equ LockLocation + 0A1h=0D -GhcbBaseLocation equ LockLocation + 0A2h=0D diff --git a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm b/UefiCpuPkg/Lib= rary/MpInitLib/X64/MpFuncs.nasm index aecfd07bc0..bf7faaf60b 100644 --- a/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm +++ b/UefiCpuPkg/Library/MpInitLib/X64/MpFuncs.nasm @@ -1,5 +1,5 @@ ;-------------------------------------------------------------------------= ----- ;=0D -; Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.
=0D +; Copyright (c) 2015 - 2021, Intel Corporation. All rights reserved.
=0D ; SPDX-License-Identifier: BSD-2-Clause-Patent=0D ;=0D ; Module Name:=0D @@ -43,21 +43,21 @@ BITS 16 mov fs, ax=0D mov gs, ax=0D =0D - mov si, BufferStartLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (BufferStart)=0D mov ebx, [si]=0D =0D - mov si, DataSegmentLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (DataSegment)=0D mov edx, [si]=0D =0D ;=0D ; Get start address of 32-bit code in low memory (<1MB)=0D ;=0D - mov edi, ModeTransitionMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeTransitionMemory)=0D =0D - mov si, GdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (GdtrProfile)=0D o32 lgdt [cs:si]=0D =0D - mov si, IdtrLocation=0D + mov si, MP_CPU_EXCHANGE_INFO_FIELD (IdtrProfile)=0D o32 lidt [cs:si]=0D =0D ;=0D @@ -85,7 +85,7 @@ Flat32Start: ; protecte= d mode entry point ;=0D ; Enable execute disable bit=0D ;=0D - mov esi, EnableExecuteDisableLocation=0D + mov esi, MP_CPU_EXCHANGE_INFO_FIELD (EnableExecuteDisable)=0D cmp byte [ebx + esi], 0=0D jz SkipEnableExecuteDisableBit=0D =0D @@ -101,7 +101,7 @@ SkipEnableExecuteDisableBit: mov eax, cr4=0D bts eax, 5=0D =0D - mov esi, Enable5LevelPagingLocation=0D + mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Enable5LevelPaging)=0D cmp byte [ebx + esi], 0=0D jz SkipEnable5LevelPaging=0D =0D @@ -117,7 +117,7 @@ SkipEnable5LevelPaging: ;=0D ; Load page table=0D ;=0D - mov esi, Cr3Location ; Save CR3 in ecx=0D + mov esi, MP_CPU_EXCHANGE_INFO_FIELD (Cr3) ; Save CR= 3 in ecx=0D mov ecx, [ebx + esi]=0D mov cr3, ecx ; Load CR3=0D =0D @@ -139,26 +139,26 @@ SkipEnable5LevelPaging: ;=0D ; Far jump to 64-bit code=0D ;=0D - mov edi, ModeHighMemoryLocation=0D + mov edi, MP_CPU_EXCHANGE_INFO_FIELD (ModeHighMemory)=0D add edi, ebx=0D jmp far [edi]=0D =0D BITS 64=0D LongModeStart:=0D mov esi, ebx=0D - lea edi, [esi + InitFlagLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitFlag)]=0D cmp qword [edi], 1 ; ApInitConfig=0D jnz GetApicId=0D =0D ; Increment the number of APs executing here as early as possible=0D ; This is decremented in C code when AP is finished executing=0D mov edi, esi=0D - add edi, NumApsExecutingLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (NumApsExecuting)=0D lock inc dword [edi]=0D =0D ; AP init=0D mov edi, esi=0D - add edi, LockLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (Lock)=0D mov rax, NotVacantFlag=0D =0D TestLock:=0D @@ -166,7 +166,7 @@ TestLock: cmp rax, NotVacantFlag=0D jz TestLock=0D =0D - lea ecx, [esi + ApIndexLocation]=0D + lea ecx, [esi + MP_CPU_EXCHANGE_INFO_FIELD (ApIndex)]=0D inc dword [ecx]=0D mov ebx, [ecx]=0D =0D @@ -175,17 +175,17 @@ Releaselock: xchg qword [edi], rax=0D ; program stack=0D mov edi, esi=0D - add edi, StackSizeLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackSize)=0D mov eax, dword [edi]=0D mov ecx, ebx=0D inc ecx=0D mul ecx ; EAX =3D StackSize * (Cp= uNumber + 1)=0D mov edi, esi=0D - add edi, StackStartAddressLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (StackStart)=0D add rax, qword [edi]=0D mov rsp, rax=0D =0D - lea edi, [esi + SevEsIsEnabledLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]=0D cmp byte [edi], 1 ; SevEsIsEnabled=0D jne CProcedureInvoke=0D =0D @@ -199,7 +199,7 @@ Releaselock: mov ecx, ebx=0D mul ecx ; EAX =3D SIZE_4K * 2 * C= puNumber=0D mov edi, esi=0D - add edi, GhcbBaseLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (GhcbBase)=0D add rax, qword [edi]=0D mov rdx, rax=0D shr rdx, 32=0D @@ -208,7 +208,7 @@ Releaselock: jmp CProcedureInvoke=0D =0D GetApicId:=0D - lea edi, [esi + SevEsIsEnabledLocation]=0D + lea edi, [esi + MP_CPU_EXCHANGE_INFO_FIELD (SevEsIsEnabled)]=0D cmp byte [edi], 1 ; SevEsIsEnabled=0D jne DoCpuid=0D =0D @@ -302,18 +302,18 @@ GetProcessorNumber: ; Note that BSP may become an AP due to SwitchBsp()=0D ;=0D xor ebx, ebx=0D - lea eax, [esi + CpuInfoLocation]=0D + lea eax, [esi + MP_CPU_EXCHANGE_INFO_FIELD (CpuInfo)]=0D mov rdi, [eax]=0D =0D GetNextProcNumber:=0D - cmp dword [rdi], edx ; APIC ID match?=0D + cmp dword [rdi + CPU_INFO_IN_HOB.InitialApicId], edx = ; APIC ID match?=0D jz ProgramStack=0D - add rdi, 20=0D + add rdi, CPU_INFO_IN_HOB_size=0D inc ebx=0D jmp GetNextProcNumber=0D =0D ProgramStack:=0D - mov rsp, qword [rdi + 12]=0D + mov rsp, qword [rdi + CPU_INFO_IN_HOB.ApTopOfStack]=0D =0D CProcedureInvoke:=0D push rbp ; Push BIST data at top of AP stack=0D @@ -321,17 +321,17 @@ CProcedureInvoke: push rbp=0D mov rbp, rsp=0D =0D - mov rax, qword [esi + InitializeFloatingPointUnitsAddress]=0D + mov rax, qword [esi + MP_CPU_EXCHANGE_INFO_FIELD (InitializeFlo= atingPointUnits)]=0D sub rsp, 20h=0D call rax ; Call assembly function to initialize FP= U per UEFI spec=0D add rsp, 20h=0D =0D mov edx, ebx ; edx is ApIndex=0D mov ecx, esi=0D - add ecx, LockLocation ; rcx is address of exchange info data bu= ffer=0D + add ecx, MP_CPU_EXCHANGE_INFO_OFFSET ; rcx is address of exchan= ge info data buffer=0D =0D mov edi, esi=0D - add edi, ApProcedureLocation=0D + add edi, MP_CPU_EXCHANGE_INFO_FIELD (CFunction)=0D mov rax, qword [edi]=0D =0D sub rsp, 20h=0D @@ -667,18 +667,18 @@ AsmRelocateApLoopEnd: global ASM_PFX(AsmGetAddressMap)=0D ASM_PFX(AsmGetAddressMap):=0D lea rax, [ASM_PFX(RendezvousFunnelProc)]=0D - mov qword [rcx], rax=0D - mov qword [rcx + 8h], LongModeStart - RendezvousFunnelProcStar= t=0D - mov qword [rcx + 10h], RendezvousFunnelProcEnd - RendezvousFunn= elProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelAddres= s], rax=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeEntryOffset], Long= ModeStart - RendezvousFunnelProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RendezvousFunnelSize],= RendezvousFunnelProcEnd - RendezvousFunnelProcStart=0D lea rax, [ASM_PFX(AsmRelocateApLoop)]=0D - mov qword [rcx + 18h], rax=0D - mov qword [rcx + 20h], AsmRelocateApLoopEnd - AsmRelocateApLoop= Start=0D - mov qword [rcx + 28h], Flat32Start - RendezvousFunnelProcStart= =0D - mov qword [rcx + 30h], SwitchToRealProcEnd - SwitchToRealProcSt= art ; SwitchToRealSize=0D - mov qword [rcx + 38h], SwitchToRealProcStart - RendezvousFunnel= ProcStart ; SwitchToRealOffset=0D - mov qword [rcx + 40h], SwitchToRealProcStart - Flat32Start = ; SwitchToRealNoNxOffset=0D - mov qword [rcx + 48h], PM16Mode - RendezvousFunnelProcStart = ; SwitchToRealPM16ModeOffset=0D - mov qword [rcx + 50h], SwitchToRealProcEnd - PM16Mode = ; SwitchToRealPM16ModeSize=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncAddr= ess], rax=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.RelocateApLoopFuncSize= ], AsmRelocateApLoopEnd - AsmRelocateApLoopStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.ModeTransitionOffset],= Flat32Start - RendezvousFunnelProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealSize], Swi= tchToRealProcEnd - SwitchToRealProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealOffset], S= witchToRealProcStart - RendezvousFunnelProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealNoNxOffset= ], SwitchToRealProcStart - Flat32Start=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeOf= fset], PM16Mode - RendezvousFunnelProcStart=0D + mov qword [rcx + MP_ASSEMBLY_ADDRESS_MAP.SwitchToRealPM16ModeSi= ze], SwitchToRealProcEnd - PM16Mode=0D ret=0D =0D ;-------------------------------------------------------------------------= ------------=0D @@ -721,18 +721,18 @@ ASM_PFX(AsmExchangeRole): =0D ;Store EFLAGS, GDTR and IDTR regiter to stack=0D pushfq=0D - sgdt [rsi + 16]=0D - sidt [rsi + 26]=0D + sgdt [rsi + CPU_EXCHANGE_ROLE_INFO.Gdtr]=0D + sidt [rsi + CPU_EXCHANGE_ROLE_INFO.Idtr]=0D =0D ; Store the its StackPointer=0D - mov [rsi + 8], rsp=0D + mov [rsi + CPU_EXCHANGE_ROLE_INFO.StackPointer], rsp=0D =0D ; update its switch state to STORED=0D - mov byte [rsi], CPU_SWITCH_STATE_STORED=0D + mov byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _STORED=0D =0D WaitForOtherStored:=0D ; wait until the other CPU finish storing its state=0D - cmp byte [rdi], CPU_SWITCH_STATE_STORED=0D + cmp byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _STORED=0D jz OtherStored=0D pause=0D jmp WaitForOtherStored=0D @@ -740,21 +740,21 @@ WaitForOtherStored: OtherStored:=0D ; Since another CPU already stored its state, load them=0D ; load GDTR value=0D - lgdt [rdi + 16]=0D + lgdt [rdi + CPU_EXCHANGE_ROLE_INFO.Gdtr]=0D =0D ; load IDTR value=0D - lidt [rdi + 26]=0D + lidt [rdi + CPU_EXCHANGE_ROLE_INFO.Idtr]=0D =0D ; load its future StackPointer=0D - mov rsp, [rdi + 8]=0D + mov rsp, [rdi + CPU_EXCHANGE_ROLE_INFO.StackPointer]=0D =0D ; update the other CPU's switch state to LOADED=0D - mov byte [rdi], CPU_SWITCH_STATE_LOADED=0D + mov byte [rdi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _LOADED=0D =0D WaitForOtherLoaded:=0D ; wait until the other CPU finish loading new state,=0D ; otherwise the data in stack may corrupt=0D - cmp byte [rsi], CPU_SWITCH_STATE_LOADED=0D + cmp byte [rsi + CPU_EXCHANGE_ROLE_INFO.State], CPU_SWITCH_STATE= _LOADED=0D jz OtherLoaded=0D pause=0D jmp WaitForOtherLoaded=0D --=20 2.27.0.windows.1