From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web08.5951.1612517301249351662 for ; Fri, 05 Feb 2021 01:28:21 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: w.sheng@intel.com) IronPort-SDR: geoy2XcYgqTDbZwLgdrFYi3we7LnxaRu1L3WeiHEw/bo9Et/A+PPvVGBwLxQyPYOD0UK1skBvM QgF52+zHsy/g== X-IronPort-AV: E=McAfee;i="6000,8403,9885"; a="180632014" X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="180632014" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Feb 2021 01:28:18 -0800 IronPort-SDR: yx9HXVIWAlqqlD1VdCvyeO8QOu+9i9K+xUaFHUPTSqVVPAbgRAJ6PH45LOYBGkulzOWIgI9aat uyF9GyR3va2Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,154,1610438400"; d="scan'208";a="393778872" Received: from shwdesssddpdwei.ccr.corp.intel.com ([10.239.157.35]) by orsmga008.jf.intel.com with ESMTP; 05 Feb 2021 01:28:15 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao , Roger Feng Subject: [PATCH v2 0/1] Fix CET shadow stack token busy bit clear issue Date: Fri, 5 Feb 2021 17:27:59 +0800 Message-Id: <20210205092800.90624-1-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 If CET shadows stack feature enabled in SMM and stack switch is enabled. When code execute from SMM handler to SMM exception, CPU will check SMM exception shadow stack token busy bit if it is cleared or not. If it is set, it will trigger #DF exception. If it is not set, CPU will set the busy bit when enter SMM exception. So, the busy bit should be cleared when return back form SMM exception to SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF exception when enter SMM exception next time. So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the shadow stack token busy bit before RETF instruction in SMM exception. Since open CI is using NASM 2.14.02, it has not supported CET instructions yet. Use DB xx xx xx xx to replace the assembly instruction before NASM 2.15.01 is used. Change from patch set 1 to patch set 2: 1 Add behavior description in source code comment. 2 Structure interrupt shadow stack memory in InitShadowStack(). 3 Update commit comment. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Cc: Roger Feng Sheng Wei (1): UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit .../DxeCpuExceptionHandlerLib.inf | 3 ++ .../PeiCpuExceptionHandlerLib.inf | 3 ++ .../SecPeiCpuExceptionHandlerLib.inf | 4 ++ .../SmmCpuExceptionHandlerLib.inf | 3 ++ .../X64/Xcode5ExceptionHandlerAsm.nasm | 48 ++++++++++++++++++++-- .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 4 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 5 ++- 7 files changed, 66 insertions(+), 4 deletions(-) -- 2.16.2.windows.1