From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web08.17214.1612676320596081476 for ; Sat, 06 Feb 2021 21:38:40 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: dFV4NnXuVbnnaPDQ9PngtuCny8woVO8XcJH9pVJwVSXOC1o+3WNjBqfERcVXjd8xMa7YFpvce4 M1Vs3LK5WcAw== X-IronPort-AV: E=McAfee;i="6000,8403,9887"; a="160740761" X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="160740761" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2021 21:38:40 -0800 IronPort-SDR: QV4x9HG715ep/ypVIG2+eUWgE3e+uwq8IdrtqrRmZFbwZw4RxZpT8Sbi2ismOnFWp1PpqKXF72 VCbZ1fSBwqxQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="374955942" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 06 Feb 2021 21:38:39 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 2/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add fdf and header file Date: Sun, 7 Feb 2021 13:38:28 +0800 Message-Id: <20210207053834.4048-2-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210207053834.4048-1-heng.luo@intel.com> References: <20210207053834.4048-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Adds the following files: * TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf * TigerlakeURvp/Include/PeiPlatformHookLib.h Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInc= lude.fdf | 54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHook= Lib.h | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 184 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf= /FlashMapInclude.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/I= nclude/Fdf/FlashMapInclude.fdf new file mode 100644 index 0000000000..b21ae6401f --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashM= apInclude.fdf @@ -0,0 +1,54 @@ +## @file=0D +# FDF file of Platform.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +# 12 M BIOS - for FSP wrapper=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +DEFINE FLASH_BASE =3D 0x= FF400000 #=0D +DEFINE FLASH_SIZE =3D 0x= 00C00000 #=0D +DEFINE FLASH_BLOCK_SIZE =3D 0x= 00010000 #=0D +DEFINE FLASH_NUM_BLOCKS =3D 0x= 000000C0 #=0D +#=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D#=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset =3D = 0x00000000 # Flash addr (0xFF400000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize =3D = 0x00060000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset =3D = 0x00000000 # Flash addr (0xFF400000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize =3D = 0x0002E000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset =3D = 0x0002E000 # Flash addr (0xFF42E000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize =3D = 0x00002000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset =3D = 0x00030000 # Flash addr (0xFF430000)=0D +SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize =3D = 0x00030000 #=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset =3D = 0x000E0000 # Flash addr (0xFF4E0000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize =3D = 0x001A0000 #=0D +SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset =3D = 0x00280000 # Flash addr (0xFF680000)=0D +SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize =3D = 0x00300000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset =3D = 0x00580000 # Flash addr (0xFF980000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize =3D = 0x000A0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset =3D = 0x00620000 # Flash addr (0xFFA20000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize =3D = 0x001D0000 #=0D +=0D +## Firmware binaries FV absolute address requires 256kB alignment=0D +## Build script checks the requirement.=0D +SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset =3D = 0x00800000 # Flash addr (0xFFC00000)=0D +SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize =3D = 0x00080000 # Keep 0x80000 or larger=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset =3D = 0x00880000 # Flash addr (0xFFC80000)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D = 0x00070000 # Keep 0x70000 or larger, change MicrocodeFv.fdf in case that t= his value change=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset =3D = 0x008F0000 # Flash addr (0xFFC00000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize =3D = 0x00080000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset =3D = 0x00970000 # Flash addr (0xFFD70000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize =3D = 0x000A0000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset =3D = 0x00A10000 # Flash addr (0xFFE10000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize =3D = 0x00110000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset =3D = 0x00B20000 # Flash addr (0xFFF20000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize =3D = 0x00010000 #=0D +=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset =3D = 0x00B30000 # Flash addr (0xFFF30000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize =3D = 0x00020000 #=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset =3D = 0x00B50000 # Flash addr (0xFFF50000)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize =3D = 0x000B0000 #=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Pei= PlatformHookLib.h b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Incl= ude/PeiPlatformHookLib.h new file mode 100644 index 0000000000..f8611764f5 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatfor= mHookLib.h @@ -0,0 +1,130 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PEI_PLATFORM_HOOK_LIB_H_=0D +#define _PEI_PLATFORM_HOOK_LIB_H_=0D +=0D +#include =0D +#include =0D +=0D +=0D +//EC Command to provide one byte of debug indication=0D +#define BSSB_DEBUG_INDICATION 0xAE=0D +/**=0D + Configure EC for specific devices=0D +=0D + @param[in] PchLan - The PchLan of PCH_SETUP variable.=0D + @param[in] BootMode - The current boot mode.=0D +**/=0D +VOID=0D +EcInit (=0D + IN UINT8 PchLan,=0D + IN EFI_BOOT_MODE BootMode=0D + );=0D +=0D +/**=0D + Checks if Premium PMIC present=0D +=0D + @retval TRUE if present=0D + @retval FALSE it discrete/other PMIC=0D +**/=0D +BOOLEAN=0D +IsPremiumPmicPresent (=0D + VOID=0D + );=0D +=0D +/**=0D + Pmic Programming to supprort LPAL Feature=0D +=0D + @retval NONE=0D +**/=0D +VOID=0D +PremiumPmicDisableSlpS0Voltage (=0D + VOID=0D + );=0D +=0D +/**=0D +Pmic Programming to supprort LPAL Feature=0D + @retval NONE=0D +**/=0D +VOID=0D +PremiumPmicEnableSlpS0Voltage(=0D + VOID=0D + );=0D +=0D +/**=0D + Do platform specific programming pre-memory. For example, EC init, Chips= et programming=0D +=0D + @retval Status=0D +**/=0D +EFI_STATUS=0D +PlatformSpecificInitPreMem (=0D + VOID=0D + );=0D +=0D +/**=0D + Do platform specific programming post-memory.=0D +=0D + @retval Status=0D +**/=0D +EFI_STATUS=0D +PlatformSpecificInit (=0D + VOID=0D + );=0D +=0D +/**=0D + Configure GPIO and SIO Before Memory is ready.=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInitPreMem (=0D + VOID=0D + );=0D +=0D +/**=0D + Configure GPIO and SIO=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInit (=0D + VOID=0D + );=0D +=0D +/**=0D +Voltage Margining Routine=0D +=0D +@retval EFI_SUCCESS Operation success=0D +**/=0D +EFI_STATUS=0D +VoltageMarginingRoutine(=0D + VOID=0D + );=0D +=0D +/**=0D + Detect recovery mode=0D +=0D + @retval EFI_SUCCESS System in Recovery Mode=0D + @retval EFI_UNSUPPORTED System doesn't support Recovery Mode=0D + @retval EFI_NOT_FOUND System is not in Recovery Mode=0D +**/=0D +EFI_STATUS=0D +IsRecoveryMode (=0D + VOID=0D + );=0D +=0D +/**=0D + Early board Configuration before Memory is ready.=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInitEarlyPreMem (=0D + VOID=0D + );=0D +#endif=0D +=0D --=20 2.24.0.windows.2