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06 Feb 2021 21:38:40 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 3/8] TigerlakeOpenBoardPkg: Add library instances Date: Sun, 7 Feb 2021 13:38:29 +0800 Message-Id: <20210207053834.4048-3-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210207053834.4048-1-heng.luo@intel.com> References: <20210207053834.4048-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Adds the following library instances: * FspWrapper/Library/PeiFspPolicyInitLib * FspWrapper/Library/PeiSiDefaultPolicyInitLib * FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib * Library/BasePlatformHookLib * Library/SmmSpiFlashCommonLib * Policy/Library/DxeSiliconPolicyUpdateLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspCpuPolicyInitLib.c | 79 +++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspMePolicyInitLib.c | 51 +++++++++++++++++++= ++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspMiscUpdInitLib.c | 27 +++++++++++++++++++= ++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPchPolicyInitLib.c | 372 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.c | 308 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.h | 187 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspPolicyInitLib.inf | 184 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspSaPolicyInitLib.c | 240 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspSecurityPolicyInitLib.c | 49 +++++++++++++++++++= ++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLi= b/PeiFspSiPolicyInitLib.c | 10 ++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicy= InitLib/PeiSiDefaultPolicyInitLib.c | 39 +++++++++++++++++++= ++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicy= InitLib/PeiSiDefaultPolicyInitLib.inf | 38 +++++++++++++++++++= +++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefault= PolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c | 40 +++++++++++++++++++= +++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefault= PolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf | 38 +++++++++++++++++++= +++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatf= ormHookLib.c | 460 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatf= ormHookLib.inf | 51 +++++++++++++++++++= ++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SmmSpiFl= ashCommonLib.inf | 49 +++++++++++++++++++= ++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlash= Common.c | 210 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/SpiFlash= CommonSmmLib.c | 58 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxeGopPolicyInit.c | 168 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxePchPolicyInit.c | 61 +++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxeSaPolicyInit.c | 61 +++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxeSiliconPolicyUpdateLate.c | 97 +++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++ Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdate= Lib/DxeSiliconPolicyUpdateLib.inf | 49 +++++++++++++++++++= ++++++++++++++++++++++++++++++ 24 files changed, 2926 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspCpuPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardP= kg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspCpuPolicyInitLib.c new file mode 100644 index 0000000000..1358d6a19b --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspCpuPolicyInitLib.c @@ -0,0 +1,79 @@ +/** @file=0D + Implementation of Fsp CPU Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP CPU PEI Policy initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspCpuPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + CPU_CONFIG_LIB_PREMEM_CONFIG *CpuConfigLibPreMemConfig;=0D + CPU_SECURITY_PREMEM_CONFIG *CpuSecurityPreMemConfig;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + EFI_STATUS Status;=0D + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;=0D + SiPreMemPolicyPpi =3D NULL;=0D +#endif=0D +=0D + CpuConfigLibPreMemConfig =3D NULL;=0D + CpuSecurityPreMemConfig =3D NULL;=0D + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem Start\n= "));=0D +=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + //=0D + // Locate SiPreMemPolicyPpi=0D + //=0D + Status =3D PeiServicesLocatePpi (=0D + &gSiPreMemPolicyPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &SiPreMemPolicyPpi=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_NOT_FOUND;=0D + }=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuConfigLibPre= MemConfigGuid, (VOID *) &CpuConfigLibPreMemConfig);=0D + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SiCpuPolicy Pre-Mem End\n")= );=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gCpuSecurityPreM= emConfigGuid, (VOID *) &CpuSecurityPreMemConfig);=0D + ASSERT_EFI_ERROR(Status);=0D +#endif=0D + //=0D + // Cpu Config Lib policies=0D + //=0D + UPDATE_POLICY (FspmUpd->FspmConfig.CpuRatio, CpuConfigLibPreMemConfig->C= puRatio, 0);=0D + DEBUG ((DEBUG_INFO, "BIOS Guard PCD and Policy are disabled\n"));=0D + UPDATE_POLICY (FspmUpd->FspmConfig.BiosGuard, CpuSecurityPreMemConfig->B= iosGuard, 0);=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PrmrrSize, CpuSecurityPreMemConfig->P= rmrrSize, SIZE_1MB);=0D + UPDATE_POLICY (FspmUpd->FspmConfig.EnableC6Dram, CpuSecurityPreMemConfig= ->EnableC6Dram, 1);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspMePolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMePolicyInitLib.c new file mode 100644 index 0000000000..53b5ef43cd --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspMePolicyInitLib.c @@ -0,0 +1,51 @@ +/** @file=0D + Implementation of Fsp Me Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP ME PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMePolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInitPreMem\n"));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs FSP ME PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMePolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "PeiFspMePolicyInit \n"));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspMiscUpdInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg= /FspWrapper/Library/PeiFspPolicyInitLib/PeiFspMiscUpdInitLib.c new file mode 100644 index 0000000000..5a12e569d9 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspMiscUpdInitLib.c @@ -0,0 +1,27 @@ +/** @file=0D + Implementation of Fsp Misc UPD Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +/**=0D + Performs FSP Misc UPD initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSPM_UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMiscUpdInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPchPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardP= kg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPchPolicyInitLib.c new file mode 100644 index 0000000000..67b75d6faf --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPchPolicyInitLib.c @@ -0,0 +1,372 @@ +/** @file=0D + Implementation of Fsp PCH Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +//=0D +// USB limits=0D +//=0D +#define PCH_MAX_USB2_PORTS 16=0D +#define PCH_MAX_USB3_PORTS 10=0D +=0D +//=0D +// TypeC port map GPIO pin=0D +//=0D +IOM_AUX_ORI_PAD_CONFIG mIomAuxNullTable[MAX_IOM_AUX_BIAS_COUNT] =3D {=0D + // Pull UP GPIO Pin, Pull Down GPIO pin=0D + {0, 0}, // Port 0=0D + {0, 0}, // Port 1=0D + {0, 0}, // Port 2=0D + {0, 0}, // Port 3=0D +};=0D +=0D +=0D +VOID=0D +UpdatePcieClockInfo (=0D + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig,=0D + IN FSPM_UPD *FspmUpd,=0D + UINTN Index,=0D + UINT64 Data=0D + )=0D +{=0D + PCD64_BLOB Pcd64;=0D +=0D + Pcd64.Blob =3D Data;=0D + DEBUG ((DEBUG_INFO, "UpdatePcieClockInfo ClkIndex %x ClkUsage %x, Suppor= ted %x\n", Index, Pcd64.PcieClock.ClockUsage, Pcd64.PcieClock.ClkReqSupport= ed));=0D +=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcUsage[Index], PcieRpPreMemC= onfig->PcieClock[Index].Usage, (UINT8)Pcd64.PcieClock.ClockUsage);=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PcieClkSrcClkReq[Index], PcieRpPreMem= Config->PcieClock[Index].ClkReq, Pcd64.PcieClock.ClkReqSupported ? (UINT8)I= ndex : 0xFF);=0D +}=0D +/**=0D + Performs FSP PCH PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + UINTN Index;=0D + PCH_PCIE_RP_PREMEM_CONFIG *PcieRpPreMemConfig;=0D + HDAUDIO_PREMEM_CONFIG *HdaPreMemConfig;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + SI_PREMEM_POLICY_PPI *SiPreMemPolicy;=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Locate PchPreMemPolicyPpi=0D + //=0D + SiPreMemPolicy =3D NULL;=0D + PcieRpPreMemConfig =3D NULL;=0D + HdaPreMemConfig =3D NULL;=0D + Status =3D PeiServicesLocatePpi (=0D + &gSiPreMemPolicyPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &SiPreMemPolicy=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gPcieRpPreMemConfig= Guid, (VOID *) &PcieRpPreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicy, &gHdAudioPreMemConfi= gGuid, (VOID *) &HdaPreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +#else=0D + PcieRpPreMemConfig =3D NULL;=0D + HdaPreMemConfig =3D NULL;=0D +#endif=0D +=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 0, PcdGet64 (PcdPcieC= lock0));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 1, PcdGet64 (PcdPcieC= lock1));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 2, PcdGet64 (PcdPcieC= lock2));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 3, PcdGet64 (PcdPcieC= lock3));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 4, PcdGet64 (PcdPcieC= lock4));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 5, PcdGet64 (PcdPcieC= lock5));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 6, PcdGet64 (PcdPcieC= lock6));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 7, PcdGet64 (PcdPcieC= lock7));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 8, PcdGet64 (PcdPcieC= lock8));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 9, PcdGet64 (PcdPcieC= lock9));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 10, PcdGet64 (PcdPcieC= lock10));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 11, PcdGet64 (PcdPcieC= lock11));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 12, PcdGet64 (PcdPcieC= lock12));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 13, PcdGet64 (PcdPcieC= lock13));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 14, PcdGet64 (PcdPcieC= lock14));=0D + UpdatePcieClockInfo (PcieRpPreMemConfig, FspmUpd, 15, PcdGet64 (PcdPcieC= lock15));=0D +=0D + //=0D + // Update HDA policies=0D + //=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaIDispLinkTmode, HdaPreMemConfig= ->IDispLinkTmode, 0);=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaSdiEnable[0], HdaPreMemConfig->= AudioLinkHda.SdiEnable[0], FALSE);=0D +=0D + for (Index =3D 0; Index < GetPchHdaMaxDmicLinkNum (); Index++) {=0D + UPDATE_POLICY (FspmUpd->FspmConfig.PchHdaAudioLinkDmicClockSelect[Inde= x], HdaPreMemConfig->AudioLinkDmic[Index].DmicClockSelect, 0);=0D + }=0D + DEBUG((DEBUG_INFO | DEBUG_INIT, "UpdatePeiPchPolicyPreMem\n"));=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + This function updates USB Policy per port OC Pin number=0D +=0D + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer=0D + @param[in] PortIndex USB Port index=0D + @param[in] Pin OverCurrent pin number=0D +**/=0D +VOID=0D +UpdateUsb20OverCurrentPolicy (=0D + IN OUT FSPS_UPD *FspsUpd,=0D + IN USB_CONFIG *UsbConfig,=0D + IN UINT8 PortIndex,=0D + UINT8 Pin=0D +)=0D +{=0D + if (PortIndex < MAX_USB2_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin =3D= =3D USB_OC_SKIP))) {=0D + UPDATE_POLICY (=0D + FspsUpd->FspsConfig.Usb2OverCurrentPin[PortIndex],=0D + UsbConfig->PortUsb20[PortIndex].OverCurrentPin,=0D + Pin=0D + );=0D + } else {=0D + if (PortIndex >=3D MAX_USB2_PORTS) {=0D + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: USB2 port number= %d is not a valid USB2 port number\n", PortIndex));=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "UpdateUsb20OverCurrentPolicy: Invalid OverCurr= ent pin specified USB2 port %d\n", PortIndex));=0D + }=0D + }=0D +}=0D +=0D +/**=0D + This function updates USB Policy per port OC Pin number=0D +=0D + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer=0D + @param[in] PortIndex USB Port index=0D + @param[in] Pin OverCurrent pin number=0D +**/=0D +VOID=0D +UpdateUsb30OverCurrentPolicy (=0D + IN OUT FSPS_UPD *FspsUpd,=0D + IN USB_CONFIG *UsbConfig,=0D + IN UINT8 PortIndex,=0D + UINT8 Pin=0D +)=0D +{=0D + if (PortIndex < MAX_USB3_PORTS && ((Pin < USB_OC_MAX_PINS) || (Pin =3D= =3D USB_OC_SKIP))) {=0D + UPDATE_POLICY (=0D + FspsUpd->FspsConfig.Usb3OverCurrentPin[PortIndex],=0D + UsbConfig->PortUsb30[PortIndex].OverCurrentPin,=0D + Pin=0D + );=0D + } else {=0D + if (PortIndex >=3D MAX_USB2_PORTS) {=0D + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: USB3 port number= %d is not a valid USB3 port number\n", PortIndex));=0D + } else {=0D + DEBUG ((DEBUG_ERROR, "UpdateUsb30OverCurrentPolicy: Invalid OverCurr= ent pin specified USB3 port %d\n", PortIndex));=0D + }=0D + }=0D +}=0D +=0D +/**=0D + This function performs PCH USB Platform Policy initialization=0D +=0D + @param[in] PchUsbConfig Pointer to USB_CONFIG data buffer=0D + @param[in] PchSetup Pointer to PCH_SETUP data buffer=0D +**/=0D +VOID=0D +UpdatePchUsbConfig (=0D + IN OUT FSPS_UPD *FspsUpd,=0D + IN OUT USB_CONFIG *UsbConfig=0D + )=0D +{=0D + UINTN PortIndex;=0D +=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PchUsbOverCurrentEnable, UsbConfig->O= verCurrentEnable, TRUE);=0D +=0D + for (PortIndex =3D 0; PortIndex < GetPchUsb2MaxPhysicalPortNum (); PortI= ndex++) {=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb20Enable[PortIndex], UsbConf= ig->PortUsb20[PortIndex].Enable, TRUE);=0D + }=0D + for (PortIndex =3D 0; PortIndex < GetPchXhciMaxUsb3PortNum (); PortIndex= ++) {=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PortUsb30Enable[PortIndex], UsbConf= ig->PortUsb30[PortIndex].Enable, TRUE);=0D + }=0D +=0D + UPDATE_POLICY (FspsUpd->FspsConfig.XdciEnable, UsbConfig->XdciConfig.Ena= ble, FALSE);=0D +=0D + //=0D + // Platform Board programming per the layout of each port.=0D + //=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb20Ov= erCurrentPinPort0));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb20Ov= erCurrentPinPort1));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb20Ov= erCurrentPinPort2));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb20Ov= erCurrentPinPort3));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb20Ov= erCurrentPinPort4));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb20Ov= erCurrentPinPort5));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb20Ov= erCurrentPinPort6));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb20Ov= erCurrentPinPort7));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb20Ov= erCurrentPinPort8));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb20Ov= erCurrentPinPort9));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,10, PcdGet8 (PcdUsb20Ov= erCurrentPinPort10));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,11, PcdGet8 (PcdUsb20Ov= erCurrentPinPort11));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,12, PcdGet8 (PcdUsb20Ov= erCurrentPinPort12));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,13, PcdGet8 (PcdUsb20Ov= erCurrentPinPort13));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,14, PcdGet8 (PcdUsb20Ov= erCurrentPinPort14));=0D + UpdateUsb20OverCurrentPolicy (FspsUpd, UsbConfig,15, PcdGet8 (PcdUsb20Ov= erCurrentPinPort15));=0D +=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 0, PcdGet8 (PcdUsb30Ov= erCurrentPinPort0));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 1, PcdGet8 (PcdUsb30Ov= erCurrentPinPort1));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 2, PcdGet8 (PcdUsb30Ov= erCurrentPinPort2));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 3, PcdGet8 (PcdUsb30Ov= erCurrentPinPort3));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 4, PcdGet8 (PcdUsb30Ov= erCurrentPinPort4));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 5, PcdGet8 (PcdUsb30Ov= erCurrentPinPort5));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 6, PcdGet8 (PcdUsb30Ov= erCurrentPinPort6));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 7, PcdGet8 (PcdUsb30Ov= erCurrentPinPort7));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 8, PcdGet8 (PcdUsb30Ov= erCurrentPinPort8));=0D + UpdateUsb30OverCurrentPolicy (FspsUpd, UsbConfig, 9, PcdGet8 (PcdUsb30Ov= erCurrentPinPort9));=0D +=0D +}=0D +=0D +/**=0D + Update CNVi config=0D +=0D + @param[in] SiPolicy Pointer to SI_POLICY_PPI=0D + @param[in] FspsUpd Pointer to FspsUpd structure=0D + @param[in] PchSetup Pointer to PCH_SETUP buffer=0D +**/=0D +STATIC=0D +VOID=0D +UpdateCnviConfig (=0D + IN OUT FSPS_UPD *FspsUpd,=0D + IN OUT CNVI_CONFIG *CnviConfig=0D + )=0D +{=0D +=0D + UPDATE_POLICY (FspsUpd->FspsConfig.CnviMode, CnviConfig->Mode,= CnviModeDisabled);=0D + UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtCore, CnviConfig->BtCor= e, FALSE);=0D + UPDATE_POLICY (FspsUpd->FspsConfig.CnviBtAudioOffload, CnviConfig->BtAud= ioOffload, 0);=0D +}=0D +=0D +/**=0D + Performs FSP PCH PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + UINTN Index;=0D + SATA_CONFIG *SataConfig;=0D + USB_CONFIG *UsbConfig;=0D + TCSS_PEI_CONFIG *TcssConfig;=0D + SERIAL_IO_CONFIG *SerialIoConfig;=0D + CNVI_CONFIG *CnviConfig;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + SI_POLICY_PPI *SiPolicy;=0D + EFI_STATUS Status;=0D +#endif=0D + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP UpdatePeiPchPolicy\n"));=0D +=0D + SataConfig =3D NULL;=0D + UsbConfig =3D NULL;=0D + TcssConfig =3D NULL;=0D + SerialIoConfig =3D NULL;=0D + CnviConfig =3D NULL;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + //=0D + // Locate SiPolicyPpi=0D + //=0D + SiPolicy =3D NULL;=0D + Status =3D PeiServicesLocatePpi (=0D + &gSiPolicyPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &SiPolicy=0D + );=0D + if (EFI_ERROR (Status)) {=0D + return EFI_NOT_FOUND;=0D + }=0D +=0D + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSataConfigGuid, (VOID *)= &SataConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gUsbConfigGuid, (VOID *) = &UsbConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gTcssPeiConfigGuid, (VOID= *) &TcssConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gSerialIoConfigGuid, (VOI= D *) &SerialIoConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPolicy, &gCnviConfigGuid, (VOID *)= &CnviConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + if (EFI_ERROR (Status)) {=0D + return Status;=0D + }=0D +#endif=0D +=0D + //=0D + // Update Sata Policies=0D + //=0D + UPDATE_POLICY (FspsUpd->FspsConfig.SataEnable, SataConfig->Enable, TRUE)= ;=0D + UPDATE_POLICY (FspsUpd->FspsConfig.SataMode, SataConfig->SataMode, SataM= odeAhci);=0D +=0D + for (Index =3D 0; Index < PCH_MAX_SATA_PORTS; Index++) {=0D + UPDATE_POLICY (FspsUpd->FspsConfig.SataPortsEnable[Index], SataConfig-= >PortSettings[Index].Enable, TRUE);=0D + }=0D +=0D + //=0D + // Update Pch Usb Config=0D + //=0D + UpdatePchUsbConfig (FspsUpd, UsbConfig);=0D +=0D + //=0D + // I2C=0D + //=0D + for (Index =3D 0; Index < 8; Index++) {=0D + UPDATE_POLICY (FspsUpd->FspsConfig.SerialIoI2cMode[Index], SerialIoCon= fig->I2cDeviceConfig[Index].Mode, 0);=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cPadsTermination[Index= ], SerialIoConfig->I2cDeviceConfig[Index].PadTermination, 0);=0D + }=0D +=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSdaPinMux[4], SerialIo= Config->I2cDeviceConfig[4].PinMux.Sda, GPIO_VER2_LP_MUXING_SERIALIO_I2C4_S= DA_GPP_H8);=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PchSerialIoI2cSclPinMux[4], SerialIo= Config->I2cDeviceConfig[4].PinMux.Scl, GPIO_VER2_LP_MUXING_SERIALIO_I2C4_S= CL_GPP_H9);=0D +=0D + //=0D + // Type C=0D + //=0D + for (Index =3D 0; Index < MAX_IOM_AUX_BIAS_COUNT; Index++) {=0D + UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2)], = TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullN, mIomAuxNullTable[In= dex].GpioPullN);=0D + UPDATE_POLICY (FspsUpd->FspsConfig.IomTypeCPortPadCfg[(Index * 2) + 1]= , TcssConfig->IomConfig.IomAuxPortPad[Index].GpioPullP, mIomAuxNullTable[In= dex].GpioPullP);=0D + }=0D +=0D + //=0D + // Cnvi=0D + //=0D + UpdateCnviConfig (FspsUpd, CnviConfig);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/= FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.c new file mode 100644 index 0000000000..fc523e93d1 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.c @@ -0,0 +1,308 @@ +/** @file=0D + Instance of Fsp Policy Initialization Library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +VOID=0D +EFIAPI=0D +FspPolicyInitPreMem(=0D + IN FSPM_UPD *FspmUpdDataPtr=0D +);=0D +=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyInitPreMem(=0D + IN OUT VOID *FspmUpd=0D +)=0D +{=0D + DEBUG ((DEBUG_INFO, "FspmUpd - 0x%x\n", FspmUpd));=0D + FspPolicyInitPreMem ((FSPM_UPD *) FspmUpd);=0D + return FspmUpd;=0D +}=0D +=0D +/**=0D + SiPreMemInstallPolicyReadyPpi installs SiPreMemPolicyReadyPpi.=0D + While installed, RC assumes the Policy is ready and finalized. So please= update and override=0D + any setting before calling this function.=0D +=0D + @retval EFI_SUCCESS The policy is installed.=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SiPreMemInstallPolicyReadyPpi (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPreMemPpiDesc;=0D +=0D + SiPolicyReadyPreMemPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPo= ol (sizeof (EFI_PEI_PPI_DESCRIPTOR));=0D + if (SiPolicyReadyPreMemPpiDesc =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + SiPolicyReadyPreMemPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_P= EI_PPI_DESCRIPTOR_TERMINATE_LIST;=0D + SiPolicyReadyPreMemPpiDesc->Guid =3D &gSiPreMemPolicyReadyPpiGuid;=0D + SiPolicyReadyPreMemPpiDesc->Ppi =3D NULL;=0D +=0D + //=0D + // Install PreMem Silicon Policy Ready PPI=0D + //=0D + Status =3D PeiServicesInstallPpi (SiPolicyReadyPreMemPpiDesc);=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D +}=0D +=0D +RETURN_STATUS=0D +EFIAPI=0D +SiliconPolicyDonePreMem(=0D + IN VOID *FspmUpd=0D +)=0D +{=0D + EFI_STATUS Status;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + FSPM_ARCH_CONFIG_PPI *FspmArchConfigPpi;=0D + EFI_PEI_PPI_DESCRIPTOR *FspmArchConfigPpiDesc;=0D +=0D + FspmArchConfigPpi =3D (FSPM_ARCH_CONFIG_PPI *) AllocateZeroPool (sizeof = (FSPM_ARCH_CONFIG_PPI));=0D + if (FspmArchConfigPpi =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D + FspmArchConfigPpi->Revision =3D 1;=0D + FspmArchConfigPpi->NvsBufferPtr =3D NULL;=0D + FspmArchConfigPpi->BootLoaderTolumSize =3D 0;=0D +=0D + FspmArchConfigPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (s= izeof (EFI_PEI_PPI_DESCRIPTOR));=0D + if (FspmArchConfigPpiDesc =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D + FspmArchConfigPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PP= I_DESCRIPTOR_TERMINATE_LIST;=0D + FspmArchConfigPpiDesc->Guid =3D &gFspmArchConfigPpiGuid;=0D + FspmArchConfigPpiDesc->Ppi =3D FspmArchConfigPpi;=0D + //=0D + // Install FSP-M Arch Config PPI=0D + //=0D + Status =3D PeiServicesInstallPpi (FspmArchConfigPpiDesc);=0D + ASSERT_EFI_ERROR (Status);=0D +#endif=0D +=0D + //=0D + // Install Policy Ready PPI=0D + // While installed, RC assumes the Policy is ready and finalized. So ple= ase=0D + // update and override any setting before calling this function.=0D + //=0D + Status =3D SiPreMemInstallPolicyReadyPpi ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_INFO, "Silicon PEI Policy Initialization Done in Pre-Memor= y\n"));=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Performs FSP PEI Policy Pre-memory initialization.=0D +=0D + @param[in] FspmUpdDataPtr Pointer to FSPM UPD data.=0D +**/=0D +VOID=0D +EFIAPI=0D +FspPolicyInitPreMem (=0D + IN FSPM_UPD *FspmUpdDataPtr=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // PCH Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspPchPolicyInitPreMem (FspmUpdDataPtr);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // Cpu Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspCpuPolicyInitPreMem (FspmUpdDataPtr);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - CPU Pei Fsp Policy in Pre-Memory Initial= ization fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // Security Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspSecurityPolicyInitPreMem (FspmUpdDataPtr);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy in Pre-Memory In= itialization fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // ME Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspMePolicyInitPreMem (FspmUpdDataPtr);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy in Pre-Memory Initiali= zation fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // SystemAgent Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspSaPolicyInitPreMem (FspmUpdDataPtr);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy in Pre-Memory= Initialization fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // Other Upd Initialization=0D + //=0D + Status =3D PeiFspMiscUpdInitPreMem (FspmUpdDataPtr);=0D +=0D +}=0D +=0D +/**=0D + Performs FSP PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer UPD data region=0D +=0D +**/=0D +VOID=0D +EFIAPI=0D +FspPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // PCH Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspPchPolicyInit (FspsUpd);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - PCH Pei Fsp Policy iInitialization fail,= Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // ME Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspMePolicyInit (FspsUpd);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - ME Pei Fsp Policy Initialization fail, S= tatus =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // SystemAgent Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspSaPolicyInit (FspsUpd);=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "ERROR - SystemAgent Pei Fsp Policy Initializatio= n fail, Status =3D %r\n", Status));=0D + }=0D +=0D + //=0D + // Security Pei Fsp Policy Initialization=0D + //=0D + Status =3D PeiFspSecurityPolicyInit(FspsUpd);=0D + if (EFI_ERROR(Status)) {=0D + DEBUG((DEBUG_ERROR, "ERROR - Security Pei Fsp Policy Initialization fa= il, Status =3D %r\n", Status));=0D + }=0D +=0D +}=0D +=0D +/**=0D +Performs silicon post-mem policy initialization.=0D +=0D +The meaning of Policy is defined by silicon code.=0D +It could be the raw data, a handle, a PPI, etc.=0D +=0D +The returned data must be used as input data for SiliconPolicyDonePostMem(= ),=0D +and SiliconPolicyUpdateLib.SiliconPolicyUpdatePostMem().=0D +=0D +1) In FSP path, the input Policy should be FspsUpd.=0D +Value of FspsUpd has been initialized by FSP binary default value.=0D +Only a subset of FspsUpd needs to be updated for different silicon sku.=0D +The return data is same FspsUpd.=0D +=0D +2) In non-FSP path, the input policy could be NULL.=0D +The return data is the initialized policy.=0D +=0D +@param[in, out] Policy Pointer to policy.=0D +=0D +@return the initialized policy.=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyInitPostMem(=0D + IN OUT VOID *FspsUpd=0D +)=0D +{=0D + DEBUG ((DEBUG_INFO, "FspsUpd - 0x%x\n", FspsUpd));=0D + FspPolicyInit ((FSPS_UPD *) FspsUpd);=0D + return FspsUpd;=0D +}=0D +=0D +/**=0D + SiInstallPolicyReadyPpi installs SiPolicyReadyPpi.=0D + While installed, RC assumes the Policy is ready and finalized. So please= update and override=0D + any setting before calling this function.=0D +=0D + @retval EFI_SUCCESS The policy is installed.=0D + @retval EFI_OUT_OF_RESOURCES Insufficient resources to create buffer=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SiInstallPolicyReadyPpi (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_PEI_PPI_DESCRIPTOR *SiPolicyReadyPpiDesc;=0D +=0D + SiPolicyReadyPpiDesc =3D (EFI_PEI_PPI_DESCRIPTOR *) AllocateZeroPool (si= zeof (EFI_PEI_PPI_DESCRIPTOR));=0D + if (SiPolicyReadyPpiDesc =3D=3D NULL) {=0D + ASSERT (FALSE);=0D + return EFI_OUT_OF_RESOURCES;=0D + }=0D +=0D + SiPolicyReadyPpiDesc->Flags =3D EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI= _DESCRIPTOR_TERMINATE_LIST;=0D + SiPolicyReadyPpiDesc->Guid =3D &gSiPolicyReadyPpiGuid;=0D + SiPolicyReadyPpiDesc->Ppi =3D NULL;=0D +=0D + //=0D + // Install Silicon Policy Ready PPI=0D + //=0D + Status =3D PeiServicesInstallPpi (SiPolicyReadyPpiDesc);=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D +}=0D +=0D +/*=0D +The silicon post-mem policy is finalized.=0D +Silicon code can do initialization based upon the policy data.=0D +=0D +The input Policy must be returned by SiliconPolicyInitPostMem().=0D +=0D +@param[in] Policy Pointer to policy.=0D +=0D +@retval EFI_SUCCESS The policy is handled consumed by silicon code.=0D +*/=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconPolicyDonePostMem(=0D + IN OUT VOID *FspsUpd=0D +)=0D +{=0D + SiInstallPolicyReadyPpi();=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.h b/Platform/Intel/TigerlakeOpenBoardPkg/= FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.h new file mode 100644 index 0000000000..cce0de0089 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.h @@ -0,0 +1,187 @@ +/** @file=0D + Internal header file for Fsp Policy Initialization Library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PEI_FSP_POLICY_INIT_LIB_H_=0D +#define _PEI_FSP_POLICY_INIT_LIB_H_=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP PCH PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP PCH PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspPchPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D +/**=0D + Performs FSP CPU PEI Policy initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspCpuPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D +Performs FSP Security PEI Policy initialization.=0D +=0D +@param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D +@retval EFI_SUCCESS FSP UPD Data is updated.=0D +@retval EFI_NOT_FOUND Fail to locate required PPI.=0D +@retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSecurityPolicyInitPreMem(=0D +IN OUT FSPM_UPD *FspmUpd=0D +);=0D +=0D +/**=0D + Performs FSP ME PEI Policy pre mem initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMePolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP ME PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMePolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization in pre-memory.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + );=0D +=0D +=0D +/**=0D +Performs FSP Security PEI Policy post memory initialization.=0D +=0D +@param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D +@retval EFI_SUCCESS FSP UPD Data is updated.=0D +@retval EFI_NOT_FOUND Fail to locate required PPI.=0D +@retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSecurityPolicyInit(=0D +IN OUT FSPS_UPD *FspsUpd=0D +);=0D +=0D +/**=0D + PeiGetSectionFromFv finds the file in FV and gets file Address and Size= =0D +=0D + @param[in] NameGuid - File GUID=0D + @param[out] Address - Pointer to the File Address=0D + @param[out] Size - Pointer to File Size=0D +=0D + @retval EFI_SUCCESS Successfull in reading the section fr= om FV=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiGetSectionFromFv (=0D + IN CONST EFI_GUID NameGuid,=0D + OUT VOID **Address,=0D + OUT UINT32 *Size=0D + );=0D +=0D +/**=0D + Performs FSP Misc UPD initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSPM_UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspMiscUpdInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + );=0D +=0D +#endif // _PEI_FSP_POLICY_INIT_LIB_H_=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf new file mode 100644 index 0000000000..936d331073 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf @@ -0,0 +1,184 @@ +## @file=0D +# Library functions for Fsp Policy Initialization Library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiFspPolicyInitLib=0D + FILE_GUID =3D 2CB87D67-D1A4-4CD3-8CD7-91A1FA1DF6E0= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SiliconPolicyInitLib=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32=0D +#=0D +=0D +##########################################################################= ######=0D +#=0D +# Sources Section - list of files that are required for the build to succe= ed.=0D +#=0D +##########################################################################= ######=0D +=0D +[Sources]=0D + PeiFspPolicyInitLib.c=0D + PeiFspSiPolicyInitLib.c=0D + PeiFspPchPolicyInitLib.c=0D + PeiFspCpuPolicyInitLib.c=0D + PeiFspMePolicyInitLib.c=0D + PeiFspSaPolicyInitLib.c=0D + PeiFspSecurityPolicyInitLib.c=0D + PeiFspMiscUpdInitLib.c=0D +=0D +##########################################################################= ######=0D +#=0D +# Package Dependency Section - list of Package files that are required for= =0D +# this module.=0D +#=0D +##########################################################################= ######=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D + TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + UefiCpuPkg/UefiCpuPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D + IntelFsp2WrapperPkg/IntelFsp2WrapperPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D +=0D +[LibraryClasses]=0D + BaseMemoryLib=0D + DebugLib=0D + IoLib=0D + PeiServicesLib=0D + ConfigBlockLib=0D + PcdLib=0D + MemoryAllocationLib=0D + PchInfoLib=0D + FspWrapperApiLib=0D + PeiLib=0D + BmpSupportLib=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdTsegSize ## CON= SUMES=0D +=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CON= SUMES=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CON= SUMES=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CON= SUMES=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CON= SUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress ## CON= SUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress ## CON= SUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress ## CON= SUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress ## CON= SUMES=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection ## CON= SUMES=0D + # SA Misc Config=0D + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd ## CON= SUMES=0D + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment ## CON= SUMES=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdData ## CON= SUMES=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize ## CON= SUMES=0D +=0D + # SPD Address Table=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3 ## CONSUMES= =0D +=0D + # PCIe Clock Info=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock0 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock1 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock2 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock3 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock4 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock5 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock6 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock7 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock8 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock9 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock10 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock11 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock12 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock13 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock14 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdPcieClock15 ## CONSUMES= =0D +=0D + # USB 2.0 Port Over Current Pin=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15 ## CONSUMES= =0D +=0D + # USB 3.0 Port Over Current Pin=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8 ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9 ## CONSUMES= =0D +=0D + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid ## CONSUMES= =0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr ## = CONSUMES=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateSmmDataPtr ## = CONSUMES=0D +=0D +[Ppis]=0D + gSiPolicyPpiGuid ## CONSUMES=0D + gSiPreMemPolicyPpiGuid ## CONSUMES=0D + gSiPreMemPolicyReadyPpiGuid ## CONSUMES=0D + gSiPolicyReadyPpiGuid ## CONSUMES=0D + gFspmArchConfigPpiGuid ## SOMETIMES_PRODUCES=0D +=0D +[Guids]=0D + gPcieRpPreMemConfigGuid ## CONSUMES=0D + gPchGeneralPreMemConfigGuid ## CONSUMES=0D + gPcieRpPreMemConfigGuid ## CONSUMES=0D + gSataConfigGuid ## CONSUMES=0D + gHdAudioConfigGuid ## CONSUMES=0D + gSataConfigGuid ## CONSUMES=0D + gUsbConfigGuid ## CONSUMES=0D + gSaMiscPeiPreMemConfigGuid ## PRODUCES=0D + gHostBridgePeiPreMemConfigGuid ## CONSUMES=0D + gSaMiscPeiConfigGuid ## PRODUCES=0D + gMemoryConfigNoCrcGuid ## CONSUMES=0D + gSaMiscPeiConfigGuid ## CONSUMES=0D + gGraphicsPeiConfigGuid ## CONSUMES=0D + gMePeiPreMemConfigGuid ## CONSUMES=0D + gMePeiConfigGuid ## CONSUMES=0D + gPchGeneralConfigGuid ## CONSUMES=0D + gCpuConfigGuid ## CONSUMES=0D + gCpuConfigLibPreMemConfigGuid ## CONSUMES=0D + gTcssPeiConfigGuid ## CONSUMES=0D + gSerialIoConfigGuid ## CONSUMES=0D + gCpuSecurityPreMemConfigGuid ## CONSUMES=0D + gTianoLogoGuid ## CONSUMES=0D + gCnviConfigGuid ## CONSUMES=0D + gHdAudioPreMemConfigGuid ## CONSUMES=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspSaPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSaPolicyInitLib.c new file mode 100644 index 0000000000..8f426ddb8d --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspSaPolicyInitLib.c @@ -0,0 +1,240 @@ +/** @file=0D + Implementation of Fsp SA Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization in pre-memory.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + SA_MISC_PEI_PREMEM_CONFIG *MiscPeiPreMemConfig;=0D + HOST_BRIDGE_PREMEM_CONFIG *HostBridgePreMemConfig;=0D + MEMORY_CONFIG_NO_CRC *MemConfigNoCrc;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + EFI_STATUS Status;=0D + SI_PREMEM_POLICY_PPI *SiPreMemPolicyPpi;=0D +#endif=0D +=0D + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Pre Mem\n"));=0D + MiscPeiPreMemConfig =3D NULL;=0D + HostBridgePreMemConfig =3D NULL;=0D + MemConfigNoCrc =3D NULL;=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + //=0D + // Locate SiPreMemPolicyPpi=0D + //=0D + SiPreMemPolicyPpi =3D NULL;=0D + Status =3D PeiServicesLocatePpi(=0D + &gSiPreMemPolicyPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &SiPreMemPolicyPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if ((Status =3D=3D EFI_SUCCESS) && (SiPreMemPolicyPpi !=3D NULL)) {=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gSaMiscPeiPreM= emConfigGuid, (VOID *) &MiscPeiPreMemConfig);=0D + ASSERT_EFI_ERROR (Status);=0D + Status =3D GetConfigBlock((VOID *) SiPreMemPolicyPpi, &gHostBridgePeiP= reMemConfigGuid, (VOID *) &HostBridgePreMemConfig);=0D + ASSERT_EFI_ERROR(Status);=0D + Status =3D GetConfigBlock ((VOID *) SiPreMemPolicyPpi, &gMemoryConfigN= oCrcGuid, (VOID *) &MemConfigNoCrc);=0D + ASSERT_EFI_ERROR (Status);=0D + ZeroMem ((VOID *) MemConfigNoCrc->SpdData->SpdData, sizeof (SPD_DATA_B= UFFER));=0D + }=0D +#endif=0D +=0D + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[0], MiscPeiPreMemConf= ig->SpdAddressTable[0], PcdGet8 (PcdMrcSpdAddressTable0));=0D + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[1], MiscPeiPreMemConf= ig->SpdAddressTable[1], PcdGet8 (PcdMrcSpdAddressTable1));=0D + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[2], MiscPeiPreMemConf= ig->SpdAddressTable[2], PcdGet8 (PcdMrcSpdAddressTable2));=0D + UPDATE_POLICY (FspmUpd->FspmConfig.SpdAddressTable[3], MiscPeiPreMemConf= ig->SpdAddressTable[3], PcdGet8 (PcdMrcSpdAddressTable3));=0D +=0D + if (PcdGet32 (PcdMrcSpdData)) {=0D + DEBUG((DEBUG_INFO, "PcdMrcSpdData !=3D NULL, MemConfigNoCrc->SpdData\n= "));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr00= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][0][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr01= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][1][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr02= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][2][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr03= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[0][3][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr10= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][0][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr11= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][1][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr12= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][2][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + COPY_POLICY ((VOID *)((FSPM_UPD *) FspmUpd)->FspmConfig.MemorySpdPtr13= 0, (VOID *)MemConfigNoCrc->SpdData->SpdData[1][3][0], (VOID *)(UINTN)PcdGet= 32 (PcdMrcSpdData), PcdGet16(PcdMrcSpdDataSize));=0D + }=0D + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.TsegSize, Mi= scPeiPreMemConfig->TsegSize, PcdGet32 (PcdTsegSize));=0D + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.UserBd, Mi= scPeiPreMemConfig->UserBd, PcdGet8 (PcdSaMiscUserBd));=0D + UPDATE_POLICY (((FSPM_UPD *) FspmUpd)->FspmConfig.MmioSizeAdjustment, Ho= stBridgePreMemConfig->MmioSizeAdjustment, PcdGet16 (PcdSaMiscMmioSizeAdjust= ment));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +UpdateGraphics(=0D + IN OUT FSPS_UPD *FspsUpd,=0D + GRAPHICS_PEI_CONFIG *GtConfig=0D + )=0D +{=0D + EFI_STATUS Status;=0D + VOID *Buffer;=0D + UINT32 Size;=0D + EFI_GRAPHICS_OUTPUT_BLT_PIXEL *Blt;=0D + UINTN BltSize;=0D + UINTN Height;=0D + UINTN Width;=0D +=0D + DEBUG((DEBUG_INFO, "\nUpdating SA Policy in Post Mem\n"));=0D + UPDATE_POLICY (FspsUpd->FspsConfig.PeiGraphicsPeimInit, GtConfig->PeiGra= phicsPeimInit, 1);=0D +=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv(PcdGetPtr(PcdIntelGraphicsVbtFileGuid), EFI_SECTI= ON_RAW, 0, &Buffer, &Size);=0D + DEBUG((DEBUG_INFO, "Vbt Pointer from PeiGetSectionFromAnyFv is 0x%x\n", = Buffer));=0D + DEBUG((DEBUG_INFO, "Vbt Size from PeiGetSectionFromAnyFv is 0x%x\n", Siz= e));=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1=0D + FspsUpd->FspsConfig.GraphicsConfigPtr =3D (UINT32)(UINTN)Buffer;=0D +#else=0D + GtConfig->GraphicsConfigPtr =3D Buffer;=0D +#endif=0D +=0D + Size =3D 0;=0D + Buffer =3D NULL;=0D + PeiGetSectionFromAnyFv(&gTianoLogoGuid, EFI_SECTION_RAW, 0, &Buffer, &Si= ze);=0D + DEBUG((DEBUG_INFO, "LogoPtr from PeiGetSectionFromAnyFv is 0x%x\n", Buff= er));=0D + DEBUG((DEBUG_INFO, "LogoSize from PeiGetSectionFromAnyFv is 0x%x\n", Siz= e));=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1=0D + FspsUpd->FspsConfig.LogoPtr =3D (UINT32)Buffer;=0D + FspsUpd->FspsConfig.LogoSize =3D Size;=0D +#else=0D + GtConfig->LogoPtr =3D Buffer;=0D + GtConfig->LogoSize =3D Size;=0D +#endif=0D +=0D + if (Buffer !=3D NULL) {=0D + Blt =3D NULL;=0D + Status =3D TranslateBmpToGopBlt (=0D + Buffer,=0D + Size,=0D + &Blt,=0D + &BltSize,=0D + &Height,=0D + &Width=0D + );=0D + if (EFI_ERROR (Status)) {=0D + DEBUG ((DEBUG_ERROR, "TranslateBmpToGopBlt, Status =3D %r\n", Stat= us));=0D + ASSERT_EFI_ERROR (Status);=0D + return Status;=0D + }=0D +=0D + UPDATE_POLICY(FspsUpd->FspsConfig.BltBufferSize, GtConfig->BltBufferS= ize, BltSize);=0D + UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelWidth, GtConfig->LogoPixel= Width, Width);=0D + UPDATE_POLICY(FspsUpd->FspsConfig.LogoPixelHeight, GtConfig->LogoPixe= lHeight, Height);=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 1=0D + FspsUpd->FspsConfig.BltBufferAddress =3D (UINT32) Blt;=0D +#else=0D + GtConfig->BltBufferAddress =3D (VOID *) Blt;=0D +#endif=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs FSP SA PEI Policy initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSaPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + EFI_STATUS Status;=0D + SI_POLICY_PPI *SiPolicyPpi;=0D +#endif=0D + SA_MISC_PEI_CONFIG *MiscPeiConfig;=0D + GRAPHICS_PEI_CONFIG *GtConfig;=0D +=0D + MiscPeiConfig =3D NULL;=0D + GtConfig =3D NULL;=0D +=0D +#if FixedPcdGet8(PcdFspModeSelection) =3D=3D 0=0D + //=0D + // Locate SiPolicyPpi=0D + //=0D + SiPolicyPpi =3D NULL;=0D + Status =3D PeiServicesLocatePpi(=0D + &gSiPolicyPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **)&SiPolicyPpi=0D + );=0D + if ((Status =3D=3D EFI_SUCCESS) && (SiPolicyPpi !=3D NULL)) {=0D + MiscPeiConfig =3D NULL;=0D + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gSaMiscPeiConfigGuid= , (VOID *) &MiscPeiConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + GtConfig =3D NULL;=0D + Status =3D GetConfigBlock ((VOID *) SiPolicyPpi, &gGraphicsPeiConfigGu= id, (VOID *) &GtConfig);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + }=0D +#endif=0D +=0D + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Wrapper UpdatePeiSaPolicy\n"));=0D +=0D + //=0D + // Update UPD: VBT & LogoPtr=0D + //=0D + UpdateGraphics(FspsUpd, GtConfig);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspSecurityPolicyInitLib.c b/Platform/Intel/TigerlakeOpenB= oardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSecurityPolicyInitLib.c new file mode 100644 index 0000000000..91a60a6bd3 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspSecurityPolicyInitLib.c @@ -0,0 +1,49 @@ +/** @file=0D + Implementation of Fsp Security Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Performs FSP Security PEI Policy initialization.=0D +=0D + @param[in][out] FspmUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSecurityPolicyInitPreMem (=0D + IN OUT FSPM_UPD *FspmUpd=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO | DEBUG_INIT, "FSP Update SecurityPolicy Pre-Mem End\= n"));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Performs FSP Security PEI Policy post memory initialization.=0D +=0D + @param[in][out] FspsUpd Pointer to FSP UPD Data.=0D +=0D + @retval EFI_SUCCESS FSP UPD Data is updated.=0D + @retval EFI_NOT_FOUND Fail to locate required PPI.=0D + @retval Other FSP UPD Data update process fail.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PeiFspSecurityPolicyInit (=0D + IN OUT FSPS_UPD *FspsUpd=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspSiPolicyInitLib.c b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspSiPolicyInitLib.c new file mode 100644 index 0000000000..23390d4cc4 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspSiPolicyInitLib.c @@ -0,0 +1,10 @@ +/** @file=0D + Implementation of Fsp SI Policy Initialization.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiD= efaultPolicyInitLib/PeiSiDefaultPolicyInitLib.c b/Platform/Intel/TigerlakeO= penBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPolicy= InitLib.c new file mode 100644 index 0000000000..b864753258 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultP= olicyInitLib/PeiSiDefaultPolicyInitLib.c @@ -0,0 +1,39 @@ +/** @file=0D + Instance of Fsp Policy Initialization Library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiSiDefaultPolicyInitLibConstructor (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + PEI_SI_DEFAULT_POLICY_INIT_PPI *PeiSiDefaultPolicyInitPpi;=0D +=0D + //=0D + // Locate Policy init PPI to install default silicon policy=0D + //=0D + Status =3D PeiServicesLocatePpi (=0D + &gSiDefaultPolicyInitPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &PeiSiDefaultPolicyInitPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if (PeiSiDefaultPolicyInitPpi =3D=3D NULL) {=0D + return Status;=0D + }=0D + Status =3D PeiSiDefaultPolicyInitPpi->PeiPolicyInit ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiD= efaultPolicyInitLib/PeiSiDefaultPolicyInitLib.inf b/Platform/Intel/Tigerlak= eOpenBoardPkg/FspWrapper/Library/PeiSiDefaultPolicyInitLib/PeiSiDefaultPoli= cyInitLib.inf new file mode 100644 index 0000000000..bcad97c267 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiDefaultP= olicyInitLib/PeiSiDefaultPolicyInitLib.inf @@ -0,0 +1,38 @@ +## @file=0D +# Library functions for Fsp Policy Initialization Library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiSiDefaultPolicyInitLib=0D + FILE_GUID =3D ADA1D87B-6891-453C-A0DB-92D4CFD46693= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiSiDefaultPolicyInitLibConstructor= =0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + PeiSiDefaultPolicyInitLib.c=0D +=0D +[LibraryClasses]=0D + PeiServicesLib=0D + DebugLib=0D +=0D +[Ppis]=0D + gSiDefaultPolicyInitPpiGuid ## CONSUMES=0D +=0D +[Depex]=0D + gSiDefaultPolicyInitPpiGuid=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiP= reMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c b/Platform/Inte= l/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLib/= PeiSiPreMemDefaultPolicyInitLib.c new file mode 100644 index 0000000000..f0eb3f3f14 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDe= faultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.c @@ -0,0 +1,40 @@ +/** @file=0D + Instance of Fsp Policy Initialization Library.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiSiPreMemDefaultPolicyInitLibConstructor (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + PEI_PREMEM_SI_DEFAULT_POLICY_INIT_PPI *PeiPreMemSiDefaultPolicyInitPpi;= =0D +=0D + //=0D + // Locate Policy init PPI to install default silicon policy=0D + //=0D + Status =3D PeiServicesLocatePpi (=0D + &gSiPreMemDefaultPolicyInitPpiGuid,=0D + 0,=0D + NULL,=0D + (VOID **) &PeiPreMemSiDefaultPolicyInitPpi=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D + if (PeiPreMemSiDefaultPolicyInitPpi =3D=3D NULL) {=0D + return Status;=0D + }=0D + DEBUG ((DEBUG_INFO, "PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyIni= t ()\n", Status));=0D + Status =3D PeiPreMemSiDefaultPolicyInitPpi->PeiPreMemPolicyInit ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return Status;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiP= reMemDefaultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf b/Platform/In= tel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDefaultPolicyInitLi= b/PeiSiPreMemDefaultPolicyInitLib.inf new file mode 100644 index 0000000000..c118d7fe2c --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiSiPreMemDe= faultPolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf @@ -0,0 +1,38 @@ +## @file=0D +# Library functions for Fsp Policy Initialization Library.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Defines Section - statements that will be processed to create a Makefile= .=0D +#=0D +##########################################################################= ######=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiSiPreMemDefaultPolicyInitLib=0D + FILE_GUID =3D F13311AD-9C5C-4212-AB02-9D0435B3FCF1= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiSiPreMemDefaultPolicyInitLibConstr= uctor=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + PeiSiPreMemDefaultPolicyInitLib.c=0D +=0D +[LibraryClasses]=0D + PeiServicesLib=0D + DebugLib=0D +=0D +[Ppis]=0D + gSiPreMemDefaultPolicyInitPpiGuid ## CONSUMES=0D +=0D +[Depex]=0D + gSiPreMemDefaultPolicyInitPpiGuid=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/Bas= ePlatformHookLib/BasePlatformHookLib.c new file mode 100644 index 0000000000..230ad36e09 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.c @@ -0,0 +1,460 @@ +/** @file=0D + Platform Hook Library instances=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define COM1_BASE 0x3f8=0D +#define COM2_BASE 0x2f8=0D +=0D +#define SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS 0x0690=0D +=0D +#define LPC_SIO_INDEX_DEFAULT_PORT_2 0x2E=0D +#define LPC_SIO_DATA_DEFAULT_PORT_2 0x2F=0D +#define LPC_SIO_GPIO_REGISTER_ADDRESS_2 0x0A20=0D +=0D +#define LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT 0x2E=0D +#define LEGACY_DAUGHTER_CARD_SIO_DATA_PORT 0x2F=0D +#define LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT 0x4E=0D +#define LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT 0x4F=0D +=0D +#define IT8628_ENTER_CONFIG_WRITE_SEQ_0 0x87=0D +#define IT8628_ENTER_CONFIG_WRITE_SEQ_1 0x01=0D +#define IT8628_ENTER_CONFIG_WRITE_SEQ_2 0x55=0D +#define IT8628_ENTER_CONFIG_WRITE_SEQ_3 0x55=0D +#define IT8628_EXIT_CONFIG 0x2=0D +#define IT8628_CHIPID_BYTE1 0x86=0D +#define IT8628_CHIPID_BYTE2 0x28=0D +=0D +typedef struct {=0D + UINT8 Register;=0D + UINT8 Value;=0D +} EFI_SIO_TABLE;=0D +=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWpcn381u[] =3D {=0D + {0x29, 0x0A0}, // Enable super I/O clock and set to 48M= Hz=0D + {0x22, 0x003}, //=0D + {0x07, 0x003}, // Select UART0 device=0D + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x004}, // Set to IRQ4=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x07, 0x002}, // Select UART1 device=0D + {0x60, (COM2_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM2_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x003}, // Set to IRQ3=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x07, 0x007}, // Select GPIO device=0D + {0x60, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 >> 8)}, // Set Base Address= MSB=0D + {0x61, (LPC_SIO_GPIO_REGISTER_ADDRESS_2 & 0x00FF)}, // Set Base Address= LSB=0D + {0x30, 0x001}, // Enable it with Activation bit=0D + {0x21, 0x001}, // Global Device Enable=0D + {0x26, 0x000} // Fast Enable UART 0 & 1 as their enabl= e & activation bit=0D +};=0D +=0D +//=0D +// IT8628=0D +//=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioIt8628TableSerialPort[] = =3D {=0D + {0x023, 0x09}, // Clock Selection register=0D + {0x007, 0x01}, // Com1 Logical Device Number select=0D + {0x061, 0xF8}, // Serial Port 1 Base Address MSB Register=0D + {0x060, 0x03}, // Serial Port 1 Base Address LSB Register=0D + {0x070, 0x04}, // Serial Port 1 Interrupt Level Select=0D + {0x030, 0x01}, // Serial Port 1 Activate=0D + {0x007, 0x02}, // Com1 Logical Device Number select=0D + {0x061, 0xF8}, // Serial Port 2 Base Address MSB Register=0D + {0x060, 0x02}, // Serial Port 2 Base Address MSB Register=0D + {0x070, 0x03}, // Serial Port 2 Interrupt Level Select=0D + {0x030, 0x01} // Serial Port 2 Activate=0D +=0D +};=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] =3D {= =0D + {0x07, 0x03}, // Select UART0 device=0D + {0x60, (COM1_BASE >> 8)}, // Set Base Address MSB=0D + {0x61, (COM1_BASE & 0x00FF)}, // Set Base Address LSB=0D + {0x70, 0x04}, // Set to IRQ4=0D + {0x30, 0x01} // Enable it with Activation bit=0D +};=0D +=0D +/**=0D + Detect if a National 393 SIO is docked. If yes, enable the docked SIO=0D + and its serial port, and disable the onboard serial port.=0D +=0D + @retval EFI_SUCCESS Operations performed successfully.=0D +**/=0D +STATIC=0D +VOID=0D +CheckNationalSio (=0D + VOID=0D + )=0D +{=0D + UINT8 Data8;=0D +=0D + //=0D + // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).=0D + // We use (0x2e, 0x2f) which is determined by BADD default strapping=0D + //=0D +=0D + //=0D + // Read the Pc87393 signature=0D + //=0D + IoWrite8 (0x2e, 0x20);=0D + Data8 =3D IoRead8 (0x2f);=0D +=0D + if (Data8 =3D=3D 0xea) {=0D + //=0D + // Signature matches - National PC87393 SIO is docked=0D + //=0D +=0D + //=0D + // Enlarge the LPC decode scope to accommodate the Docking LPC Switch= =0D + // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at=0D + // SIO_BASE_ADDRESS + 0x10)=0D + //=0D + PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20);=0D +=0D + //=0D + // Enable port switch=0D + //=0D + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);=0D +=0D + //=0D + // Turn on docking power=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);=0D +=0D + //=0D + // Enable port switch=0D + //=0D + IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);=0D +=0D + //=0D + // GPIO setting=0D + //=0D + IoWrite8 (0x2e, 0x24);=0D + IoWrite8 (0x2f, 0x29);=0D +=0D + //=0D + // Enable chip clock=0D + //=0D + IoWrite8 (0x2e, 0x29);=0D + IoWrite8 (0x2f, 0x1e);=0D +=0D +=0D + //=0D + // Enable serial port=0D + //=0D +=0D + //=0D + // Select com1=0D + //=0D + IoWrite8 (0x2e, 0x7);=0D + IoWrite8 (0x2f, 0x3);=0D +=0D + //=0D + // Base address: 0x3f8=0D + //=0D + IoWrite8 (0x2e, 0x60);=0D + IoWrite8 (0x2f, 0x03);=0D + IoWrite8 (0x2e, 0x61);=0D + IoWrite8 (0x2f, 0xf8);=0D +=0D + //=0D + // Interrupt: 4=0D + //=0D + IoWrite8 (0x2e, 0x70);=0D + IoWrite8 (0x2f, 0x04);=0D +=0D + //=0D + // Enable bank selection=0D + //=0D + IoWrite8 (0x2e, 0xf0);=0D + IoWrite8 (0x2f, 0x82);=0D +=0D + //=0D + // Activate=0D + //=0D + IoWrite8 (0x2e, 0x30);=0D + IoWrite8 (0x2f, 0x01);=0D +=0D + //=0D + // Disable onboard serial port=0D + //=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);=0D +=0D + //=0D + // Power Down UARTs=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);=0D +=0D + //=0D + // Dissable COM1 decode=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D +=0D + //=0D + // Disable COM2 decode=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D +=0D + //=0D + // Disable interrupt=0D + //=0D + IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);=0D + IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);=0D +=0D + IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D +=0D + //=0D + // Enable floppy=0D + //=0D +=0D + //=0D + // Select floppy=0D + //=0D + IoWrite8 (0x2e, 0x7);=0D + IoWrite8 (0x2f, 0x0);=0D +=0D + //=0D + // Base address: 0x3f0=0D + //=0D + IoWrite8 (0x2e, 0x60);=0D + IoWrite8 (0x2f, 0x03);=0D + IoWrite8 (0x2e, 0x61);=0D + IoWrite8 (0x2f, 0xf0);=0D +=0D + //=0D + // Interrupt: 6=0D + //=0D + IoWrite8 (0x2e, 0x70);=0D + IoWrite8 (0x2f, 0x06);=0D +=0D + //=0D + // DMA 2=0D + //=0D + IoWrite8 (0x2e, 0x74);=0D + IoWrite8 (0x2f, 0x02);=0D +=0D + //=0D + // Activate=0D + //=0D + IoWrite8 (0x2e, 0x30);=0D + IoWrite8 (0x2f, 0x01);=0D +=0D + } else {=0D +=0D + //=0D + // No National pc87393 SIO is docked, turn off dock power and=0D + // disable port switch=0D + //=0D + // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);=0D + // IoWrite8 (0x690, 0);=0D +=0D + //=0D + // If no National pc87393, just return=0D + //=0D + return ;=0D + }=0D +}=0D +=0D +/**=0D +Check whether the IT8628 SIO present on LPC. If yes, enable its serial por= ts=0D +=0D +@retval EFI_SUCCESS Operations performed successfully.=0D +**/=0D +STATIC=0D +VOID=0D +It8628SioSerialPortInit (=0D + VOID=0D + )=0D +{=0D + UINT8 ChipId0 =3D 0;=0D + UINT8 ChipId1 =3D 0;=0D + UINT16 LpcIoDecondeRangeSet =3D 0;=0D + UINT16 LpcIoDecoodeSet =3D 0;=0D + UINT8 Index;=0D + UINTN LpcBaseAddr;=0D +=0D +=0D +=0D + //=0D + // Enable I/O decoding for COM1 (3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2= Eh/2Fh.=0D + //=0D + LpcBaseAddr =3D MmPciBase (=0D + DEFAULT_PCI_BUS_NUMBER_PCH,=0D + LpcDevNumber (),=0D + LpcFuncNumber ()=0D + );=0D +=0D + LpcIoDecondeRangeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_LPC_CFG_IO= D);=0D + LpcIoDecoodeSet =3D (UINT16) MmioRead16 (LpcBaseAddr + R_LPC_CFG_IOE);=0D + MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOD), (LpcIoDecondeRangeSet | ((V_= LPC_CFG_IOD_COMB_2F8 << 4) | V_LPC_CFG_IOD_COMA_3F8)));=0D + MmioWrite16 ((LpcBaseAddr + R_LPC_CFG_IOE), (LpcIoDecoodeSet | (B_LPC_CF= G_IOE_SE | B_LPC_CFG_IOE_CBE | B_LPC_CFG_IOE_CAE|B_LPC_CFG_IOE_KE)));=0D +=0D +=0D + //=0D + // Enter MB PnP Mode=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_0)= ;=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_1)= ;=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_2)= ;=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_ENTER_CONFIG_WRITE_SEQ_3)= ;=0D +=0D + //=0D + // Read Chip Id of SIO IT8628 (registers 0x20 and 0x21)=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x20);=0D + ChipId0 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D +=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, 0x21);=0D + ChipId1 =3D IoRead8 (LPC_SIO_DATA_DEFAULT_PORT_2);=0D +=0D + //=0D + // Enable Serial Port 1, Port 2=0D + //=0D + if ((ChipId0 =3D=3D IT8628_CHIPID_BYTE1) && (ChipId1 =3D=3D IT8628_CHIPI= D_BYTE2)) {=0D + for (Index =3D 0; Index < sizeof (mSioIt8628TableSerialPort) / sizeof = (EFI_SIO_TABLE); Index++) {=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, mSioIt8628TableSerialPort[In= dex].Register);=0D + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, mSioIt8628TableSerialPort[Ind= ex].Value);=0D + }=0D + }=0D +=0D + //=0D + // Exit MB PnP Mode=0D + //=0D + IoWrite8 (LPC_SIO_INDEX_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);=0D + IoWrite8 (LPC_SIO_DATA_DEFAULT_PORT_2, IT8628_EXIT_CONFIG);=0D +=0D + return;=0D +}=0D +=0D +/**=0D + Performs platform specific initialization required for the CPU to access= =0D + the hardware associated with a SerialPortLib instance. This function do= es=0D + not initialize the serial port hardware itself. Instead, it initializes= =0D + hardware devices that are required for the CPU to access the serial port= =0D + hardware. This function may be called more than once.=0D +=0D + @retval RETURN_SUCCESS The platform specific initialization succee= ded.=0D + @retval RETURN_DEVICE_ERROR The platform specific initialization could = not be completed.=0D +=0D +**/=0D +RETURN_STATUS=0D +EFIAPI=0D +PlatformHookSerialPortInitialize (=0D + VOID=0D + )=0D +{=0D + UINT16 IndexPort;=0D + UINT16 DataPort;=0D + UINT8 Index;=0D +=0D + IndexPort =3D 0;=0D + DataPort =3D 0;=0D + Index =3D 0;=0D +=0D + //=0D + // Enable I/O decoding for COM1(3F8h-3FFh), COM2(2F8h-2FFh), I/O port 2E= h/2Fh, 4Eh/4Fh, 60h/64Fh and 62h/66h.=0D + //=0D + PchLpcIoDecodeRangesSet (PcdGet16 (PcdLpcIoDecodeRange));=0D + PchLpcIoEnableDecodingSet (PcdGet16 (PchLpcIoEnableDecoding));=0D +=0D + // Configure Sio IT8628=0D + It8628SioSerialPortInit ();=0D +=0D + if (IsMobileSku ()) {=0D + //=0D + // if no EC, it is SV Bidwell Bar board=0D + //=0D + if ((IoRead8 (0x66) !=3D 0xFF) && (IoRead8 (0x62) !=3D 0xFF)) {=0D +=0D + //=0D + // 128 Byte Boundary and SIO Runtime Register Range is 0x0 to 0xF;=0D + //=0D + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdSioBaseAddress) & (~0x7F), 0x= 10);=0D +=0D + //=0D + // Program and Enable Default Super IO Configuration Port Addresses = and range=0D + //=0D + PchLpcGenIoRangeSet (FixedPcdGet16 (PcdLpcSioConfigDefaultPort) & (~= 0xF), 0x10);=0D +=0D + //=0D + // Check if a National Pc87393 SIO is docked=0D + //=0D + CheckNationalSio ();=0D +=0D + //=0D + // Super I/O initialization for Winbond WPCN381U=0D + //=0D + IndexPort =3D LPC_SIO_INDEX_DEFAULT_PORT_2;=0D + DataPort =3D LPC_SIO_DATA_DEFAULT_PORT_2;=0D +=0D + //=0D + // Check for Winbond WPCN381U=0D + //=0D + IoWrite8 (IndexPort, 0x20); // Winbond WPCN381U Device ID re= gister is 0x20=0D + if (IoRead8 (DataPort) =3D=3D 0xF4) { // Winbond WPCN381U Device I= D is 0xF4=0D + //=0D + // Configure SIO=0D + //=0D + for (Index =3D 0; Index < sizeof (mSioTableWpcn381u) / sizeof (EFI= _SIO_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mSioTableWpcn381u[Index].Register);=0D + IoWrite8 (DataPort, mSioTableWpcn381u[Index].Value);=0D + }=0D + }=0D + } //EC is not exist, skip mobile board detection for SV board=0D +=0D + //=0D + //add for SV Bidwell Bar board=0D + //=0D + if (IoRead8 (COM1_BASE) =3D=3D 0xFF) {=0D + //=0D + // Super I/O initialization for Winbond WPCD374 (LDC2) and 8374 (LDC= )=0D + // Looking for LDC2 card first=0D + //=0D + IoWrite8(LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT, 0x55);=0D + if(IoRead8(LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT) =3D=3D 0x55){=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_2_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_2_SIO_DATA_PORT;=0D + } else {=0D + IndexPort =3D LEGACY_DAUGHTER_CARD_SIO_INDEX_PORT;=0D + DataPort =3D LEGACY_DAUGHTER_CARD_SIO_DATA_PORT;=0D + }=0D +=0D + IoWrite8 (IndexPort, 0x20); // Winbond x374 Device ID regist= er is 0x20=0D + if (IoRead8 (DataPort) =3D=3D 0xF1) { // Winbond x374 Device ID is= 0xF1=0D + for (Index =3D 0; Index < sizeof (mSioTableWinbond_x374) / sizeof = (EFI_SIO_TABLE); Index++) {=0D + IoWrite8 (IndexPort, mSioTableWinbond_x374[Index].Register);=0D + IoWrite8 (DataPort, mSioTableWinbond_x374[Index].Value);=0D + }=0D + }=0D + }// end of Bidwell Bar SIO initialization=0D + }=0D +=0D + return RETURN_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/Library/B= asePlatformHookLib/BasePlatformHookLib.inf new file mode 100644 index 0000000000..cf01780101 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.inf @@ -0,0 +1,51 @@ +## @file=0D +# Platform Hook Library instance for Tigerlake Mobile/Desktop CRB.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D BasePlatformHookLib=0D + FILE_GUID =3D E22ADCC6-ED90-4A90-9837-C8E7FF9E963D= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D BASE=0D + LIBRARY_CLASS =3D PlatformHookLib=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciSegmentLib=0D + MmPciLib=0D + PciLib=0D + PchCycleDecodingLib=0D + SaPlatformLib=0D + PchPciBdfLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Pcd]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort ## CONSUMES= =0D +=0D +[FixedPcd]=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding ## CONSUMES= =0D +=0D +[Sources]=0D + BasePlatformHookLib.c=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SmmSpiFlashCommonLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/Library= /SmmSpiFlashCommonLib/SmmSpiFlashCommonLib.inf new file mode 100644 index 0000000000..374f5ea52b --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Smm= SpiFlashCommonLib.inf @@ -0,0 +1,49 @@ +## @file=0D +# SMM Library instance of Spi Flash Common Library Class=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmSpiFlashCommonLib=0D + FILE_GUID =3D 9632D96E-E849-4217-9217-DC500B8AAE47= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + LIBRARY_CLASS =3D SpiFlashCommonLib|DXE_SMM_DRIVER=0D + CONSTRUCTOR =3D SmmSpiFlashCommonLibConstructor=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64=0D +#=0D +=0D +[LibraryClasses]=0D + IoLib=0D + MemoryAllocationLib=0D + BaseLib=0D + UefiLib=0D + SmmServicesTableLib=0D + BaseMemoryLib=0D + DebugLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Pcd]=0D + gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddress ## CONSUMES=0D + gSiPkgTokenSpaceGuid.PcdBiosSize ## CONSUMES=0D +=0D +[Sources]=0D + SpiFlashCommonSmmLib.c=0D + SpiFlashCommon.c=0D +=0D +[Protocols]=0D + gPchSmmSpiProtocolGuid ## CONSUMES=0D +=0D +[Depex.X64.DXE_SMM_DRIVER]=0D + gPchSmmSpiProtocolGuid=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommon.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiF= lashCommonLib/SpiFlashCommon.c new file mode 100644 index 0000000000..f86896dd1f --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Spi= FlashCommon.c @@ -0,0 +1,210 @@ +/** @file=0D + Wrap EFI_SPI_PROTOCOL to provide some library level interfaces=0D + for module use.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +PCH_SPI_PROTOCOL *mSpiProtocol;=0D +=0D +//=0D +// Variables for boottime and runtime usage.=0D +//=0D +UINTN mBiosAreaBaseAddress =3D 0;=0D +UINTN mBiosSize =3D 0;=0D +UINTN mBiosOffset =3D 0;=0D +=0D +/**=0D + Enable block protection on the Serial Flash device.=0D +=0D + @retval EFI_SUCCESS Opertion is successful.=0D + @retval EFI_DEVICE_ERROR If there is any device errors.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashLock (=0D + VOID=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Read NumBytes bytes of data from the address specified by=0D + PAddress into Buffer.=0D +=0D + @param[in] Address The starting physical address of the read.= =0D + @param[in,out] NumBytes On input, the number of bytes to read. On = output, the number=0D + of bytes actually read.=0D + @param[out] Buffer The destination data buffer for the read.= =0D +=0D + @retval EFI_SUCCESS Operation is successful.=0D + @retval EFI_DEVICE_ERROR If there is any device errors.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashRead (=0D + IN UINTN Address,=0D + IN OUT UINT32 *NumBytes,=0D + OUT UINT8 *Buffer=0D + )=0D +{=0D + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL));=0D + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + //=0D + // This function is implemented specifically for those platforms=0D + // at which the SPI device is memory mapped for read. So this=0D + // function just do a memory copy for Spi Flash Read.=0D + //=0D + CopyMem (Buffer, (VOID *) Address, *NumBytes);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Write NumBytes bytes of data from Buffer to the address specified by=0D + PAddresss.=0D +=0D + @param[in] Address The starting physical address of the wri= te.=0D + @param[in,out] NumBytes On input, the number of bytes to write. = On output,=0D + the actual number of bytes written.=0D + @param[in] Buffer The source data buffer for the write.=0D +=0D + @retval EFI_SUCCESS Operation is successful.=0D + @retval EFI_DEVICE_ERROR If there is any device errors.=0D + @retval EFI_INVALID_PARAMETER Invalid parameter.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashWrite (=0D + IN UINTN Address,=0D + IN OUT UINT32 *NumBytes,=0D + IN UINT8 *Buffer=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN Offset;=0D + UINT32 Length;=0D + UINT32 RemainingBytes;=0D +=0D + ASSERT ((NumBytes !=3D NULL) && (Buffer !=3D NULL));=0D + if ((NumBytes =3D=3D NULL) || (Buffer =3D=3D NULL)) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + ASSERT (Address >=3D mBiosAreaBaseAddress);=0D + if (Address < mBiosAreaBaseAddress) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Offset =3D Address - mBiosAreaBaseAddress;=0D +=0D + ASSERT ((*NumBytes + Offset) <=3D mBiosSize);=0D + if ((*NumBytes + Offset) > mBiosSize) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Status =3D EFI_SUCCESS;=0D + RemainingBytes =3D *NumBytes;=0D +=0D +=0D + while (RemainingBytes > 0) {=0D + if (RemainingBytes > SECTOR_SIZE_4KB) {=0D + Length =3D SECTOR_SIZE_4KB;=0D + } else {=0D + Length =3D RemainingBytes;=0D + }=0D + Status =3D mSpiProtocol->FlashWrite (=0D + mSpiProtocol,=0D + FlashRegionBios,=0D + (UINT32) Offset,=0D + Length,=0D + Buffer=0D + );=0D + if (EFI_ERROR (Status)) {=0D + break;=0D + }=0D + RemainingBytes -=3D Length;=0D + Offset +=3D Length;=0D + Buffer +=3D Length;=0D + }=0D +=0D + //=0D + // Actual number of bytes written=0D + //=0D + *NumBytes -=3D RemainingBytes;=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Erase the block starting at Address.=0D +=0D + @param[in] Address The starting physical address of the block t= o be erased.=0D + This library assume that caller garantee tha= t the PAddress=0D + is at the starting address of this block.=0D + @param[in] NumBytes On input, the number of bytes of the logical= block to be erased.=0D + On output, the actual number of bytes erased= .=0D +=0D + @retval EFI_SUCCESS. Operation is successful.=0D + @retval EFI_DEVICE_ERROR If there is any device errors.=0D + @retval EFI_INVALID_PARAMETER Invalid parameter.=0D +=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SpiFlashBlockErase (=0D + IN UINTN Address,=0D + IN UINTN *NumBytes=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN Offset;=0D + UINTN RemainingBytes;=0D +=0D + ASSERT (NumBytes !=3D NULL);=0D + if (NumBytes =3D=3D NULL) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + ASSERT (Address >=3D mBiosAreaBaseAddress);=0D + if (Address < mBiosAreaBaseAddress) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Offset =3D Address - mBiosAreaBaseAddress;=0D +=0D + ASSERT ((*NumBytes % SECTOR_SIZE_4KB) =3D=3D 0);=0D + if ((*NumBytes % SECTOR_SIZE_4KB) !=3D 0) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + ASSERT ((*NumBytes + Offset) <=3D mBiosSize);=0D + if ((*NumBytes + Offset) > mBiosSize) {=0D + return EFI_INVALID_PARAMETER;=0D + }=0D +=0D + Status =3D EFI_SUCCESS;=0D + RemainingBytes =3D *NumBytes;=0D +=0D +=0D + Status =3D mSpiProtocol->FlashErase (=0D + mSpiProtocol,=0D + FlashRegionBios,=0D + (UINT32) Offset,=0D + (UINT32) RemainingBytes=0D + );=0D + return Status;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommon= Lib/SpiFlashCommonSmmLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/S= mmSpiFlashCommonLib/SpiFlashCommonSmmLib.c new file mode 100644 index 0000000000..7941b8f872 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/SmmSpiFlashCommonLib/Spi= FlashCommonSmmLib.c @@ -0,0 +1,58 @@ +/** @file=0D + SMM Library instance of SPI Flash Common Library Class=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +extern PCH_SPI_PROTOCOL *mSpiProtocol;=0D +=0D +extern UINTN mBiosAreaBaseAddress;=0D +extern UINTN mBiosSize;=0D +extern UINTN mBiosOffset;=0D +=0D +/**=0D + The library constructuor.=0D +=0D + The function does the necessary initialization work for this library=0D + instance.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the UEFI= image.=0D + @param[in] SystemTable A pointer to the EFI system table.=0D +=0D + @retval EFI_SUCCESS The function always return EFI_SUCCESS for= now.=0D + It will ASSERT on error for debug version.= =0D + @retval EFI_ERROR Please reference LocateProtocol for error = code details.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmSpiFlashCommonLibConstructor (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT32 BaseAddr;=0D + UINT32 RegionSize;=0D +=0D + mBiosAreaBaseAddress =3D (UINTN)PcdGet32 (PcdBiosAreaBaseAddress);=0D + mBiosSize =3D (UINTN)PcdGet32 (PcdBiosSize);=0D +=0D + //=0D + // Locate the SMM SPI protocol.=0D + //=0D + Status =3D gSmst->SmmLocateProtocol (=0D + &gPchSmmSpiProtocolGuid,=0D + NULL,=0D + (VOID **) &mSpiProtocol=0D + );=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + mSpiProtocol->GetRegionAddress (mSpiProtocol, FlashRegionBios, &BaseAddr= , &RegionSize);=0D + mBiosOffset =3D BaseAddr;=0D + return Status;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeGopPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/P= olicy/Library/DxeSiliconPolicyUpdateLib/DxeGopPolicyInit.c new file mode 100644 index 0000000000..a2367047cd --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeGopPolicyInit.c @@ -0,0 +1,168 @@ +/** @file=0D + This file initialises and Installs GopPolicy Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED GOP_POLICY_PROTOCOL mGOPPolicy;=0D +GLOBAL_REMOVE_IF_UNREFERENCED UINT32 mVbtSize =3D 0;=0D +GLOBAL_REMOVE_IF_UNREFERENCED EFI_PHYSICAL_ADDRESS mVbtAddress =3D 0= ;=0D +=0D +/**=0D + @param[out] CurrentLidStatus=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_UNSUPPORTED=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPlatformLidStatus (=0D + OUT LID_STATUS *CurrentLidStatus=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + @param[out] CurrentDockStatus=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_UNSUPPORTED=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetPlatformDockStatus (=0D + OUT DOCK_STATUS CurrentDockStatus=0D + )=0D +{=0D + return EFI_UNSUPPORTED;=0D +}=0D +=0D +/**=0D + @param[out] VbtAddress=0D + @param[out] VbtSize=0D +=0D + @retval EFI_SUCCESS=0D + @retval EFI_NOT_FOUND=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GetVbtData (=0D + OUT EFI_PHYSICAL_ADDRESS *VbtAddress,=0D + OUT UINT32 *VbtSize=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINTN FvProtocolCount;=0D + EFI_HANDLE *FvHandles;=0D + EFI_FIRMWARE_VOLUME2_PROTOCOL *Fv;=0D + UINTN Index;=0D + UINT32 AuthenticationStatus;=0D + UINT8 *Buffer;=0D + UINTN VbtBufferSize;=0D +=0D +=0D + Status =3D EFI_NOT_FOUND;=0D + if ( mVbtAddress =3D=3D 0) {=0D + Fv =3D NULL;=0D +=0D + Buffer =3D 0;=0D + FvHandles =3D NULL;=0D + Status =3D gBS->LocateHandleBuffer (=0D + ByProtocol,=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + NULL,=0D + &FvProtocolCount,=0D + &FvHandles=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + for (Index =3D 0; Index < FvProtocolCount; Index++) {=0D + Status =3D gBS->HandleProtocol (=0D + FvHandles[Index],=0D + &gEfiFirmwareVolume2ProtocolGuid,=0D + (VOID **) &Fv=0D + );=0D + VbtBufferSize =3D 0;=0D + Status =3D Fv->ReadSection (=0D + Fv,=0D + PcdGetPtr (PcdIntelGraphicsVbtFileGuid),=0D + EFI_SECTION_RAW,=0D + 0,=0D + (VOID **) &Buffer,=0D + &VbtBufferSize,=0D + &AuthenticationStatus=0D + );=0D + if (!EFI_ERROR (Status)) {=0D + *VbtAddress =3D (EFI_PHYSICAL_ADDRESS)Buffer;=0D + *VbtSize =3D (UINT32)VbtBufferSize;=0D + mVbtAddress =3D *VbtAddress;=0D + mVbtSize =3D *VbtSize;=0D + Status =3D EFI_SUCCESS;=0D + break;=0D + }=0D + }=0D + } else {=0D + Status =3D EFI_NOT_FOUND;=0D + }=0D +=0D + if (FvHandles !=3D NULL) {=0D + FreePool (FvHandles);=0D + FvHandles =3D NULL;=0D + }=0D + } else {=0D + *VbtAddress =3D mVbtAddress;=0D + *VbtSize =3D mVbtSize;=0D + Status =3D EFI_SUCCESS;=0D + }=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D +Initialize GOP DXE Policy=0D +=0D +@param[in] ImageHandle Image handle of this driver.=0D +=0D +@retval EFI_SUCCESS Initialization complete.=0D +@retval EFI_UNSUPPORTED The chipset is unsupported by this driver.= =0D +@retval EFI_OUT_OF_RESOURCES Do not have enough resources to initialize= the driver.=0D +@retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GopPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + //=0D + // Initialize the EFI Driver Library=0D + //=0D + SetMem (&mGOPPolicy, sizeof (GOP_POLICY_PROTOCOL), 0);=0D +=0D + mGOPPolicy.Revision =3D GOP_POLICY_PROTOCOL_REVISION_03;= =0D + mGOPPolicy.GetPlatformLidStatus =3D GetPlatformLidStatus;=0D + mGOPPolicy.GetVbtData =3D GetVbtData;=0D + mGOPPolicy.GetPlatformDockStatus =3D GetPlatformDockStatus;=0D +=0D + //=0D + // Install protocol to allow access to this Policy.=0D + //=0D + Status =3D gBS->InstallMultipleProtocolInterfaces (=0D + &ImageHandle,=0D + &gGopPolicyProtocolGuid,=0D + &mGOPPolicy,=0D + NULL=0D + );=0D +=0D + return Status;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxePchPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/P= olicy/Library/DxeSiliconPolicyUpdateLib/DxePchPolicyInit.c new file mode 100644 index 0000000000..e75abcb42a --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxePchPolicyInit.c @@ -0,0 +1,61 @@ +/** @file=0D + This file initialises and Installs GopPolicy Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +CreatePchDxeConfigBlocks (=0D + IN OUT VOID **SaPolicy=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PchInstallPolicyProtocol (=0D + IN EFI_HANDLE ImageHandle,=0D + IN VOID *PchPolicy=0D + );=0D +=0D +/**=0D + Initialize PCH DXE Policy=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r.=0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PchPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_HANDLE PchHandle;=0D + VOID *PchPolicy;=0D +=0D + //=0D + // Call CreatePchDxeConfigBlocks to create & initialize platform policy = structure=0D + // and get all Intel default policy settings.=0D + //=0D + Status =3D CreatePchDxeConfigBlocks (&PchPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Install PchInstallPolicyProtocol.=0D + // While installed, RC assumes the Policy is ready and finalized. So ple= ase=0D + // update and override any setting before calling this function.=0D + //=0D + PchHandle =3D NULL;=0D + Status =3D PchInstallPolicyProtocol (PchHandle, PchPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSaPolicyInit.c b/Platform/Intel/TigerlakeOpenBoardPkg/Po= licy/Library/DxeSiliconPolicyUpdateLib/DxeSaPolicyInit.c new file mode 100644 index 0000000000..5a9def9d13 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSaPolicyInit.c @@ -0,0 +1,61 @@ +/** @file=0D + This file initialises and Installs GopPolicy Protocol.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +CreateSaDxeConfigBlocks (=0D + IN OUT VOID **SaPolicy=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SaInstallPolicyProtocol (=0D + IN EFI_HANDLE ImageHandle,=0D + IN VOID *SaPolicy=0D + );=0D +=0D +/**=0D + Initialize SA DXE Policy=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r.=0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SaPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_HANDLE SaHandle;=0D + VOID *SaPolicy;=0D +=0D + //=0D + // Call CreateSaDxeConfigBlocks to create & initialize platform policy s= tructure=0D + // and get all Intel default policy settings.=0D + //=0D + Status =3D CreateSaDxeConfigBlocks (&SaPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Install SaInstallPolicyProtocol.=0D + // While installed, RC assumes the Policy is ready and finalized. So ple= ase=0D + // update and override any setting before calling this function.=0D + //=0D + SaHandle =3D NULL;=0D + Status =3D SaInstallPolicyProtocol (SaHandle, SaPolicy);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpen= BoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLat= e.c new file mode 100644 index 0000000000..2eee9958be --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c @@ -0,0 +1,97 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Initialize SA DXE Policy=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r.=0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SaPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + );=0D +=0D +/**=0D + Initialize PCH DXE Policy=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r.=0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PchPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + );=0D +=0D +/**=0D + Initialize GOP DXE Policy=0D +=0D + @param[in] ImageHandle Image handle of this driver.=0D +=0D + @retval EFI_SUCCESS Initialization complete.=0D + @retval EFI_UNSUPPORTED The chipset is unsupported by this drive= r.=0D + @retval EFI_OUT_OF_RESOURCES Do not have enough resources to initiali= ze the driver.=0D + @retval EFI_DEVICE_ERROR Device error, driver exits abnormally.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +GopPolicyInitDxe (=0D + IN EFI_HANDLE ImageHandle=0D + );=0D +=0D +/**=0D + Performs silicon late policy update.=0D +=0D + The meaning of Policy is defined by silicon code.=0D + It could be the raw data, a handle, a Protocol, etc.=0D +=0D + The input Policy must be returned by SiliconPolicyDoneLate().=0D +=0D + In FSP or non-FSP path, the board may use additional way to get=0D + the silicon policy data field based upon the input Policy.=0D +=0D + @param[in, out] Policy Pointer to policy.=0D +=0D + @return the updated policy.=0D +**/=0D +VOID *=0D +EFIAPI=0D +SiliconPolicyUpdateLate (=0D + IN OUT VOID *Policy=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + SaPolicyInitDxe (gImageHandle);=0D + PchPolicyInitDxe (gImageHandle);=0D +=0D + if (PcdGetBool (PcdIntelGopEnable)) {=0D + //=0D + // GOP Dxe Policy Initialization=0D + //=0D + Status =3D GopPolicyInitDxe (gImageHandle);=0D + RETURN_ERROR (Status);=0D + DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D + }=0D +=0D + return Policy;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf b/Platform/Intel/TigerlakeOpe= nBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLi= b.inf new file mode 100644 index 0000000000..573dbfa04a --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLib.inf @@ -0,0 +1,49 @@ +## @file=0D +# Component information file for Silicon Policy Update Library=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D DxeSiliconUpdateLib=0D + FILE_GUID =3D C523609D-E354-416B-B24F-33468D4BD21D= =0D + MODULE_TYPE =3D DXE_DRIVER=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D SiliconPolicyUpdateLib=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + PcdLib=0D + DebugLib=0D + UefiBootServicesTableLib=0D + DxeSaPolicyLib=0D + DxePchPolicyLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Sources]=0D + DxeSiliconPolicyUpdateLate.c=0D + DxeSaPolicyInit.c=0D + DxePchPolicyInit.c=0D + DxeGopPolicyInit.c=0D +=0D +[Pcd]=0D + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable=0D + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid=0D + gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFileGuid=0D +=0D +[Protocols]=0D + gEfiFirmwareVolume2ProtocolGuid ## CONSUMES=0D + gGopPolicyProtocolGuid ## PRODUCES=0D +=0D +[Depex]=0D + gEfiVariableArchProtocolGuid=0D --=20 2.24.0.windows.2