From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web08.17214.1612676320596081476 for ; Sat, 06 Feb 2021 21:38:44 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: rEtZRABDpIui3oCEyr01qNJf0jxWpA+3mOCprn0Woz48ZfhI8j6z/kkphaBEROYDzvYAAKhpZs vkkEqQm8sltg== X-IronPort-AV: E=McAfee;i="6000,8403,9887"; a="160740782" X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="160740782" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2021 21:38:44 -0800 IronPort-SDR: QeHU4OO+bt5iDNlntBUkPXBXEDhcUK+WDVNPEJ7xRNqYP59VBCE/vmCac5uO1lGSXgy9nS7uMo 6qzvbRSYa+Yg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="374956043" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 06 Feb 2021 21:38:42 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add library instances Date: Sun, 7 Feb 2021 13:38:30 +0800 Message-Id: <20210207053834.4048-4-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210207053834.4048-1-heng.luo@intel.com> References: <20210207053834.4048-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Adds the following library instances: * TigerlakeURvp/Library/BoardAcpiLib * TigerlakeURvp/Library/BoardInitLib * TigerlakeURvp/Library/PeiPlatformHookLib Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/Sm= mMultiBoardAcpiSupportLib.c | 88 ++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/Sm= mMultiBoardAcpiSupportLib.inf | 43 ++++++++++++++++++++++++++++++++++++= +++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/Sm= mSiliconAcpiEnableLib.c | 160 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/Sm= mTigerlakeURvpAcpiEnableLib.c | 51 ++++++++++++++++++++++++++++++++++++= +++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Bo= ardPchInitPreMemLib.c | 160 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Bo= ardSaInitPreMemLib.c | 96 ++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Gp= ioTableTigerlakeUDdr4Rvp.h | 93 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Gp= ioTableTigerlakeUDdr4RvpPreMem.h | 33 +++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iMultiBoardInitPostMemLib.c | 41 ++++++++++++++++++++++++++++++++++++= +++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iMultiBoardInitPostMemLib.inf | 49 ++++++++++++++++++++++++++++++++++++= +++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iMultiBoardInitPreMemLib.c | 88 ++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iMultiBoardInitPreMemLib.inf | 115 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iTigerlakeURvpDetect.c | 39 ++++++++++++++++++++++++++++++++++++= +++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iTigerlakeURvpInitPostMemLib.c | 153 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Pe= iTigerlakeURvpInitPreMemLib.c | 445 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/Ti= gerlakeURvpInit.h | 23 +++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHook= Lib/PeiPlatformHooklib.c | 212 ++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHook= Lib/PeiPlatformHooklib.inf | 58 ++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++ 18 files changed, 1947 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/TigerlakeOpenBoard= Pkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c new file mode 100644 index 0000000000..1436d9b79a --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiL= ib/SmmMultiBoardAcpiSupportLib.c @@ -0,0 +1,88 @@ +/** @file=0D + Tiger Lake U RVP SMM Multi-Board ACPI Support library=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TglBoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TglBoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +MultiBoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + SiliconEnableAcpi (EnableSci);=0D + return TglBoardEnableAcpi (EnableSci);=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +MultiBoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + SiliconDisableAcpi (DisableSci);=0D + return TglBoardDisableAcpi (DisableSci);=0D +}=0D +=0D +BOARD_ACPI_ENABLE_FUNC mBoardAcpiEnableFunc =3D {=0D + MultiBoardEnableAcpi,=0D + MultiBoardDisableAcpi,=0D +};=0D +=0D +/**=0D + The constructor function to register mBoardAcpiEnableFunc function.=0D +=0D + @param[in] ImageHandle The firmware allocated handle for the EFI image= .=0D + @param[in] SystemTable A pointer to the EFI System Table.=0D +=0D + @retval EFI_SUCCESS This constructor always return EFI_SUCCESS.=0D + It will ASSERT on errors.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SmmMultiBoardAcpiSupportLibConstructor (=0D + IN EFI_HANDLE ImageHandle,=0D + IN EFI_SYSTEM_TABLE *SystemTable=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));=0D + return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/TigerlakeOpenBoa= rdPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf new file mode 100644 index 0000000000..6f6a9272f9 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiL= ib/SmmMultiBoardAcpiSupportLib.inf @@ -0,0 +1,43 @@ +## @file=0D +# Tiger Lake U RVP SMM Multi-Board ACPI Support library=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D SmmMultiBoardAcpiSupportLib=0D + FILE_GUID =3D 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D DXE_SMM_DRIVER=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D SmmMultiBoardAcpiSupportLibConstructo= r=0D +=0D +#=0D +# The following information is for reference only and not required by the = build tools.=0D +#=0D +# VALID_ARCHITECTURES =3D IA32 X64 IPF EBC=0D +#=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + IoLib=0D + PciLib=0D + MmPciLib=0D + PchCycleDecodingLib=0D + PchPciBdfLib=0D + PmcLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + SmmTigerlakeURvpAcpiEnableLib.c=0D + SmmSiliconAcpiEnableLib.c=0D + SmmMultiBoardAcpiSupportLib.c=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/= TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c new file mode 100644 index 0000000000..32afeb405e --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiL= ib/SmmSiliconAcpiEnableLib.c @@ -0,0 +1,160 @@ +/** @file=0D + Tiger Lake U RVP SMM Silicon ACPI Enable library=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Clear Port 80h=0D +=0D + SMI handler to enable ACPI mode=0D +=0D + Dispatched on reads from APM port with value EFI_ACPI_ENABLE_SW_SMI=0D +=0D + Disables the SW SMI Timer.=0D + ACPI events are disabled and ACPI event status is cleared.=0D + SCI mode is then enabled.=0D +=0D + Clear SLP SMI status=0D + Enable SLP SMI=0D +=0D + Disable SW SMI Timer=0D +=0D + Clear all ACPI event status and disable all ACPI events=0D +=0D + Disable PM sources except power button=0D + Clear status bits=0D +=0D + Disable GPE0 sources=0D + Clear status bits=0D +=0D + Disable GPE1 sources=0D + Clear status bits=0D +=0D + Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)=0D +=0D + Enable SCI=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D +=0D + UINT32 SmiEn;=0D + UINT32 SmiSts;=0D + UINT32 ULKMC;=0D + UINTN LpcBaseAddress;=0D + UINT16 AcpiBaseAddr;=0D + UINT32 Pm1Cnt;=0D +=0D + LpcBaseAddress =3D LpcPciCfgBase ();=0D +=0D + //=0D + // Get the ACPI Base Address=0D + //=0D + AcpiBaseAddr =3D PmcGetAcpiBase();=0D + //=0D + // BIOS must also ensure that CF9GR is cleared and locked before handing= control to the=0D + // OS in order to prevent the host from issuing global resets and resett= ing ME=0D + //=0D + // EDK2: To match PCCG current BIOS behavior, do not lock CF9 Global Res= et=0D + // MmioWrite32 (=0D + // PmcBaseAddress + R_PCH_PMC_ETR3),=0D + // PmInit);=0D +=0D + //=0D + // Clear Port 80h=0D + //=0D + IoWrite8 (0x80, 0);=0D +=0D + //=0D + // Disable SW SMI Timer and clean the status=0D + //=0D + SmiEn =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);=0D + SmiEn &=3D ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR |= B_ACPI_IO_SMI_EN_LEGACY_USB);=0D + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);=0D +=0D + SmiSts =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);=0D + SmiSts |=3D B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | = B_ACPI_IO_SMI_EN_LEGACY_USB;=0D + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);=0D +=0D + //=0D + // Disable port 60/64 SMI trap if they are enabled=0D + //=0D + ULKMC =3D MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_UL= KMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC= _64WEN | B_LPC_CFG_ULKMC_A20PASSEN);=0D + MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);=0D +=0D + //=0D + // Disable PM sources except power button=0D + //=0D + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);=0D +=0D + //=0D + // Clear PM status except Power Button status for RapidStart Resume=0D + //=0D + IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);=0D +=0D + //=0D + // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)=0D + //=0D + IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);=0D + IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);=0D +=0D + //=0D + // Enable SCI=0D + //=0D + if (EnableSci) {=0D + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);=0D + Pm1Cnt |=3D B_ACPI_IO_PM1_CNT_SCI_EN;=0D + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +SiliconDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D +=0D + UINT16 AcpiBaseAddr;=0D + UINT32 Pm1Cnt;=0D +=0D + //=0D + // Get the ACPI Base Address=0D + //=0D + AcpiBaseAddr =3D PmcGetAcpiBase();=0D + //=0D + // Disable SCI=0D + //=0D + if (DisableSci) {=0D + Pm1Cnt =3D IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);=0D + Pm1Cnt &=3D ~B_ACPI_IO_PM1_CNT_SCI_EN;=0D + IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c b/Platform/Intel/TigerlakeOpenBoa= rdPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c new file mode 100644 index 0000000000..3eb302c30d --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiL= ib/SmmTigerlakeURvpAcpiEnableLib.c @@ -0,0 +1,51 @@ +/** @file=0D + Tiger Lake U RVP SMM Board ACPI Enable library=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + Enable Board Acpi=0D +=0D + @param[in] EnableSci Enable SCI if EnableSci parameters is True.=0D +=0D + @retval EFI_SUCCESS The function always return successfully.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +TglBoardEnableAcpi (=0D + IN BOOLEAN EnableSci=0D + )=0D +{=0D + // enable additional board register=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Disable Board Acpi=0D +=0D + @param[in] DisableSci Disable SCI if DisableSci parameters is True.= =0D +=0D + @retval EFI_SUCCESS The function always return successfully.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +TglBoardDisableAcpi (=0D + IN BOOLEAN DisableSci=0D + )=0D +{=0D + // enable additional board register=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Ti= gerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c new file mode 100644 index 0000000000..1c7e574f7d --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/BoardPchInitPreMemLib.c @@ -0,0 +1,160 @@ +/** @file=0D + Source code for the board PCH configuration Pcd init functions for Pre-M= emory Init phase.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "TigerlakeURvpInit.h"=0D +#include "GpioTableTigerlakeUDdr4RvpPreMem.h"=0D +=0D +#include =0D +#include =0D +=0D +#include =0D +=0D +/**=0D + Board Root Port Clock Info configuration init function for PEI pre-memor= y phase.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +RootPortClkInfoInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];=0D + UINT32 Index;=0D +=0D + //=0D + // The default clock assignment will be FREE_RUNNING, which corresponds = to PchClockUsageUnspecified=0D + // This is safe but power-consuming setting. If Platform code doesn't co= ntain port-clock map for a given board,=0D + // the clocks will keep on running anyway, allowing PCIe devices to oper= ate. Downside is that clocks will=0D + // continue to draw power. To prevent this, remember to provide port-clo= ck map for every board.=0D + //=0D + for (Index =3D 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {=0D + Clock[Index].PcieClock.ClkReqSupported =3D TRUE;=0D + Clock[Index].PcieClock.ClockUsage =3D FREE_RUNNING;=0D + }=0D +=0D + ///=0D + /// Assign ClkReq signal to root port. (Base 0)=0D + /// For LP, Set 0 - 6=0D + /// For H, Set 0 - 15=0D + /// Note that if GbE is enabled, ClkReq assigned to GbE will not be avai= lable for Root Port.=0D + ///=0D +=0D + switch (BoardId) {=0D + // CLKREQ=0D + case BoardIdTglUDdr4:=0D + Clock[0].PcieClock.ClockUsage =3D PCIE_PEG;=0D + Clock[1].PcieClock.ClockUsage =3D PCIE_PCH + 2;=0D + Clock[2].PcieClock.ClockUsage =3D PCIE_PCH + 3;=0D + Clock[3].PcieClock.ClockUsage =3D PCIE_PCH + 8;=0D + Clock[4].PcieClock.ClockUsage =3D LAN_CLOCK;=0D + Clock[5].PcieClock.ClockUsage =3D PCIE_PCH + 7;=0D + Clock[6].PcieClock.ClockUsage =3D PCIE_PCH + 4;=0D + break;=0D + default:=0D +=0D + break;=0D + }=0D +=0D + PcdSet64S (PcdPcieClock0, Clock[ 0].Blob);=0D + PcdSet64S (PcdPcieClock1, Clock[ 1].Blob);=0D + PcdSet64S (PcdPcieClock2, Clock[ 2].Blob);=0D + PcdSet64S (PcdPcieClock3, Clock[ 3].Blob);=0D + PcdSet64S (PcdPcieClock4, Clock[ 4].Blob);=0D + PcdSet64S (PcdPcieClock5, Clock[ 5].Blob);=0D + PcdSet64S (PcdPcieClock6, Clock[ 6].Blob);=0D + PcdSet64S (PcdPcieClock7, Clock[ 7].Blob);=0D + PcdSet64S (PcdPcieClock8, Clock[ 8].Blob);=0D + PcdSet64S (PcdPcieClock9, Clock[ 9].Blob);=0D + PcdSet64S (PcdPcieClock10, Clock[10].Blob);=0D + PcdSet64S (PcdPcieClock11, Clock[11].Blob);=0D + PcdSet64S (PcdPcieClock12, Clock[12].Blob);=0D + PcdSet64S (PcdPcieClock13, Clock[13].Blob);=0D + PcdSet64S (PcdPcieClock14, Clock[14].Blob);=0D + PcdSet64S (PcdPcieClock15, Clock[15].Blob);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Board USB related configuration init function for PEI pre-memory phase.= =0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +UsbConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + Board GPIO Group Tier configuration init function for PEI pre-memory pha= se.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +GpioGroupTierInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +=0D +/**=0D + GPIO init function for PEI pre-memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +GpioTablePreMemInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + //=0D + // GPIO Table Init.=0D + //=0D + switch (BoardId) {=0D + case BoardIdTglUDdr4:=0D + PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTablePreMemTglUDdr4= );=0D + PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTablePreMemTglUDdr4Size= );=0D + break;=0D +=0D + default:=0D + break;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + PmConfig init function for PEI pre-memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +PchPmConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Tig= erlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c new file mode 100644 index 0000000000..b468e21ec9 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/BoardSaInitPreMemLib.c @@ -0,0 +1,96 @@ +/** @file=0D + Source code for the board SA configuration Pcd init functions in Pre-Memo= ry init phase.=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include "TigerlakeURvpInit.h"=0D +#include =0D +#include =0D +#include =0D +=0D +/**=0D + MRC configuration init function for PEI pre-memory phase.=0D +=0D + @param[in] BoardId An unsigned integer represent the board id= .=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +SaMiscConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + //=0D + // UserBd=0D + //=0D + switch (BoardId) {=0D + case BoardIdTglUDdr4:=0D + //=0D + // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUs= er4 for ULT platforms.=0D + // This is required to skip Memory voltage programming based on GPIO= 's in MRC=0D + //=0D + PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platf= orm=0D + break;=0D +=0D + default:=0D + // MiscPeiPreMemConfig.UserBd =3D 0 by default.=0D + break;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Board Memory Init related configuration init function for PEI pre-memory= phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +MrcConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);=0D + PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);=0D + PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);=0D + PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Board SA related GPIO configuration init function for PEI pre-memory pha= se.=0D +=0D + @param[in] BoardId An unsigned integer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +SaGpioConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + SA Display DDI configuration init function for PEI pre-memory phase.=0D +=0D + @param[in] BoardId An unsigned integer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +SaDisplayConfigInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/GpioTableTigerlakeUDdr4Rvp.h b/Platform/Intel/TigerlakeOpenBoardP= kg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h new file mode 100644 index 0000000000..0b605698c0 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/GpioTableTigerlakeUDdr4Rvp.h @@ -0,0 +1,93 @@ +/** @file=0D + GPIO definition table for Tiger Lake U RVP=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_=0D +#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +GPIO_INIT_CONFIG mGpioTableTglUDdr4[] =3D=0D +{=0D + // M.2 Key-E - WLAN/BT=0D + {GPIO_VER2_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, // BT_RF_KILL_N=0D + {GPIO_VER2_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, // WIFI_RF_KILL_N=0D + {GPIO_VER2_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,= GpioOutHigh, GpioIntDis, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, // WLAN_RST_N=0D + {GPIO_VER2_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, // WIFI_WAKE_N=0D + {GPIO_VER2_LP_GPP_H19, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInIn= v, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset, GpioTermNon= e, GpioPadConfigUnlock }}, // UART_BT_WAKE_N : Not default POR=0D + {GPIO_VER2_LP_GPP_A10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, = GpioOutDefault, GpioIntDis, GpioPlatformReset, GpioTermNon= e}}, // M.2 BT=0D +=0D + // X4 Pcie Slot for Gen3 and Gen 4=0D + {GPIO_VER2_LP_GPP_A14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_P= CIE_SLOT1_PWREN_N=0D + {GPIO_VER2_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_= PCIE_SLOT1_RESET_N=0D + {GPIO_VER2_LP_GPP_F5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, = GpioPadConfigUnlock }}, //ONBOARD_X4_PCIE_SLOT1_WAKE_N=0D + {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_= PCIE_SLOT1_DGPU_SEL=0D + {GPIO_VER2_LP_GPP_F21, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn, Gp= ioOutDefault,GpioIntDis,GpioPlatformReset, GpioTermNone}}, //ONBOARD_X4_P= CIE_SLOT1_DGPU_PWROK=0D +=0D + // TBT Re-Timers=0D + {GPIO_VER2_LP_GPD7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioDswReset, GpioTermNone}}, //TCP_RETIMER_PERST= _N=0D +=0D + // Battery Charger Vmin to PCH PROCHOT, derived from ICL=0D + {GPIO_VER2_LP_GPP_B2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault,GpioIntEdge|GpioIntSci,GpioPlatformReset, GpioTermNone, G= pioPadConfigUnlock }}, //BC_PROCHOT_N=0D +=0D + // SATA Direct Connect=0D + {GPIO_VER2_LP_GPP_B4, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SATA_DIRECT= _PWREN=0D +=0D + // FPS=0D + {GPIO_VER2_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //FPS_RST_N=0D + {GPIO_VER2_LP_GPP_E3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, Gp= ioPadConfigUnlock }}, //FPS_INT=0D +=0D + // PCH M.2 SSD=0D + {GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_PCH_SSD_= PWREN=0D + {GPIO_VER2_LP_GPP_H0, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //M2_SSD_RST_= N=0D +=0D +=0D + // Camera=0D + {GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_PWR= EN - CAM1=0D + {GPIO_VER2_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_RST_= N - CAM1=0D +=0D + {GPIO_VER2_LP_GPP_H12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM2_RST_N= =0D +=0D + {GPIO_VER2_LP_GPP_H15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_PWREN= =0D + {GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CAM3_RST_N= =0D +=0D + // Camera Common GPIO's for all Camera, Rework Options=0D + {GPIO_VER2_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //CRD_CAM_STRO= BE_1=0D + {GPIO_VER2_LP_GPP_C2, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //WF_CAM_CLK_= EN=0D +=0D + // Audio=0D + {GPIO_VER2_LP_GPP_C5, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //SPKR_PD_N=0D + {GPIO_VER2_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, = GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock }}, // CODEC_INT_N=0D +=0D + // Touch Pad=0D + // Touch Pad and Touch Panel 2 share the same Power Enable, default is T= ouch pad=0D + {GPIO_VER2_LP_GPP_H1, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //TCH_PAD_LS_= EN - PWR_En=0D + {GPIO_VER2_LP_GPP_C8, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, = GpioOutDefault,GpioIntEdge|GpioIntApic,GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock }}, //TCH_PAD_INT_N=0D +=0D + // EC=0D + {GPIO_VER2_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset, GpioTermNone, = GpioPadConfigUnlock }}, //EC_SMI_N=0D + {GPIO_VER2_LP_GPP_E8, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //EC_SLP_S0_C= S_N=0D +=0D + // SPI TPM, derived from ICL=0D + {GPIO_VER2_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, Gp= ioOutDefault,GpioIntLevel | GpioIntApic, GpioHostDeepReset, GpioTermWpu20K= , GpioPadConfigUnlock }}, //SPI_TPM_INT_N=0D +=0D + // TypeC BIAS : Not used by default in RVP, derived from ICL=0D + {GPIO_VER2_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutLow, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_P_B= IAS_GPIO=0D + {GPIO_VER2_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //DISP_AUX_N_= BIAS_GPIO=0D +=0D + // LAN : Not used by Default in RVP=0D +=0D + // X1 Pcie Slot=0D + {GPIO_VER2_LP_GPP_F4, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv, = GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset, GpioTermNone, = GpioPadConfigUnlock }}, //X1 Slot WAKE=0D + {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, G= pioOutHigh, GpioIntDis,GpioPlatformReset, GpioTermNone}}, //X1 Slot RES= ET=0D +};=0D +=0D +=0D +UINT16 mGpioTableTglUDdr4Size =3D sizeof (mGpioTableTglUDdr4) / sizeof (GP= IO_INIT_CONFIG);=0D +=0D +#endif // _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h b/Platform/Intel/TigerlakeOpen= BoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMe= m.h new file mode 100644 index 0000000000..7b08676037 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/GpioTableTigerlakeUDdr4RvpPreMem.h @@ -0,0 +1,33 @@ +/** @file=0D + GPIO definition table for Tiger Lake U DDR4 RVP Pre-Memory=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_=0D +#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +GPIO_INIT_CONFIG mGpioTablePreMemTglUDdr4[] =3D=0D +{=0D + { GPIO_VER2_LP_GPP_A14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //ONBOARD_X4= _PCIE_SLOT1_PWREN_N=0D + { GPIO_VER2_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //ONBOARD_X4= _PCIE_SLOT1_RESET_N=0D + // CPU M.2 SSD=0D + { GPIO_VER2_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD PW= REN=0D + { GPIO_VER2_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CPU SSD RE= SET=0D + // X1 Pcie Slot=0D + { GPIO_VER2_LP_GPP_F9, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //X1 Slot PW= REN=0D + { GPIO_VER2_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //TC_RETIMER= _FORCE_PWR=0D + // Camera=0D + { GPIO_VER2_LP_GPP_R6, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CAM2_PWREN= /BIOS_REC=0D + { GPIO_VER2_LP_GPP_R5, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, = GpioOutLow, GpioIntDis, GpioPlatformReset, GpioTermNone } }, //CRD_CAM_PR= IVACY_LED_1=0D +};=0D +=0D +UINT16 mGpioTablePreMemTglUDdr4Size =3D sizeof (mGpioTablePreMemTglUDdr4) = / sizeof (GPIO_INIT_CONFIG);=0D +=0D +#endif //_GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/TigerlakeOpenBoard= Pkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c new file mode 100644 index 0000000000..f652dcf8e6 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPostMemLib.c @@ -0,0 +1,41 @@ +/** @file=0D + Tiger Lake U RVP Multi-Board Initialization Post-Memory library=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardInitBeforeSiliconInit(=0D + VOID=0D + );=0D +=0D +BOARD_POST_MEM_INIT_FUNC mTigerlakeURvpBoardInitFunc =3D {=0D + TigerlakeURvpBoardInitBeforeSiliconInit,=0D + NULL, // BoardInitAfterSiliconInit=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiTigerlakeURvpMultiBoardInitLibConstructor (=0D + VOID=0D + )=0D +{=0D + if (LibPcdGetSku () =3D=3D SkuIdTglU) {=0D + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));=0D + return RegisterBoardPostMemInit (&mTigerlakeURvpBoardInitFunc);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/TigerlakeOpenBoa= rdPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf new file mode 100644 index 0000000000..d00f350dfe --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPostMemLib.inf @@ -0,0 +1,49 @@ +## @file=0D +# Component information file for TigerlakeURvpInitLib in PEI post memory = phase.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiTigerlakeURvpMultiBoardInitLib=0D + FILE_GUID =3D C7D39F17-E5BA-41D9-8DFE-FF9017499280= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiTigerlakeURvpMultiBoardInitLibCons= tructor=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PcdLib=0D + MultiBoardInitSupportLib=0D + PeiPlatformHookLib=0D + PciSegmentLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + PeiTigerlakeURvpInitPostMemLib.c=0D + PeiMultiBoardInitPostMemLib.c=0D +=0D + GpioTableTigerlakeUDdr4Rvp.h=0D +=0D +[FixedPcd]=0D +=0D +[Pcd]=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase=0D + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardP= kg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c new file mode 100644 index 0000000000..6200f3b86e --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPreMemLib.c @@ -0,0 +1,88 @@ +/** @file=0D + Tiger Lake U RVP Multi-Board Initialization Pre-Memory library=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardDetect (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpMultiBoardDetect (=0D + VOID=0D + );=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +TigerlakeURvpBoardBootModeDetect (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardDebugInit (=0D + VOID=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardInitBeforeMemoryInit (=0D + VOID=0D + );=0D +=0D +=0D +BOARD_DETECT_FUNC mTigerlakeURvpBoardDetectFunc =3D {=0D + TigerlakeURvpMultiBoardDetect=0D +};=0D +=0D +BOARD_PRE_MEM_INIT_FUNC mTigerlakeURvpBoardPreMemInitFunc =3D {=0D + TigerlakeURvpBoardDebugInit,=0D + TigerlakeURvpBoardBootModeDetect,=0D + TigerlakeURvpBoardInitBeforeMemoryInit,=0D + NULL, // BoardInitAfterMemoryInit=0D + NULL, // BoardInitBeforeTempRamExit=0D + NULL, // BoardInitAfterTempRamExit=0D +};=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpMultiBoardDetect (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, " In TglUMultiBoardDetect \n"));=0D +=0D + TigerlakeURvpBoardDetect ();=0D +=0D + if (LibPcdGetSku () =3D=3D SkuIdTglU) {=0D + RegisterBoardPreMemInit (&mTigerlakeURvpBoardPreMemInitFunc);=0D + } else {=0D + DEBUG ((DEBUG_WARN,"Not a Valid TigerLake U Board\n"));=0D + }=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PeiTigerlakeURvpMultiBoardInitPreMemLibConstructor (=0D + VOID=0D + )=0D +{=0D + return RegisterBoardDetect (&mTigerlakeURvpBoardDetectFunc);=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/TigerlakeOpenBoar= dPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf new file mode 100644 index 0000000000..b8f1cf8aee --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiMultiBoardInitPreMemLib.inf @@ -0,0 +1,115 @@ +## @file=0D +# Component information file for PEI TigerlakeURvp Board Init Pre-Mem Lib= rary=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010005=0D + BASE_NAME =3D PeiTigerlakeURvpMultiBoardInitPreMemL= ib=0D + FILE_GUID =3D EA05BD43-136F-45EE-BBBA-27D75817574F= =0D + MODULE_TYPE =3D BASE=0D + VERSION_STRING =3D 1.0=0D + LIBRARY_CLASS =3D NULL=0D + CONSTRUCTOR =3D PeiTigerlakeURvpMultiBoardInitPreMemL= ibConstructor=0D +=0D +[LibraryClasses]=0D + BaseLib=0D + DebugLib=0D + BaseMemoryLib=0D + MemoryAllocationLib=0D + PcdLib=0D + PeiPlatformHookLib=0D + MultiBoardInitSupportLib=0D + PeiLib=0D +=0D +[Packages]=0D + MinPlatformPkg/MinPlatformPkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + MdePkg/MdePkg.dec=0D + MdeModulePkg/MdeModulePkg.dec=0D + IntelFsp2Pkg/IntelFsp2Pkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D +=0D +[Sources]=0D + PeiTigerlakeURvpInitPreMemLib.c=0D + PeiMultiBoardInitPreMemLib.c=0D + PeiTigerlakeURvpDetect.c=0D + BoardSaInitPreMemLib.c=0D + BoardPchInitPreMemLib.c=0D + GpioTableTigerlakeUDdr4RvpPreMem.h=0D +=0D +[Ppis]=0D + gEfiPeiReadOnlyVariable2PpiGuid=0D + gEfiPeiMemoryDiscoveredPpiGuid ## CONSUMES=0D + gEfiPeiResetPpiGuid ## PRODUCES=0D +[Pcd]=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort=0D +=0D + # SA Misc Config=0D + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdData=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize=0D +=0D + # SPD Address Table=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3=0D +=0D + #=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=0D + # Board Init Table List=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize=0D +=0D + # Board Information=0D + gBoardModuleTokenSpaceGuid.PcdCpuRatio=0D + gBoardModuleTokenSpaceGuid.PcdBiosGuard=0D +=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize ## CONSUMES= =0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize ## CONSUMES= =0D +=0D + # SA USB Config=0D + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable=0D +=0D + # PCIe Clock Info=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock0=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock1=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock2=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock3=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock4=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock5=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock6=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock7=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock8=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock9=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock10=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock11=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock12=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock13=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock14=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock15=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength=0D + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress=0D + gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize=0D +=0D + gSiPkgTokenSpaceGuid.PcdMchBaseAddress=0D + gSiPkgTokenSpaceGuid.PcdMchMmioSize=0D +=0D + gBoardModuleTokenSpaceGuid.PcdDmiBaseAddress=0D + gBoardModuleTokenSpaceGuid.PcdDmiMmioSize=0D + gBoardModuleTokenSpaceGuid.PcdEpBaseAddress=0D + gBoardModuleTokenSpaceGuid.PcdEpMmioSize=0D +=0D +[Guids]=0D + gFspNonVolatileStorageHobGuid=0D + gEfiMemoryOverwriteControlDataGuid=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiTigerlakeURvpDetect.c b/Platform/Intel/TigerlakeOpenBoardPkg/T= igerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c new file mode 100644 index 0000000000..a11724072f --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiTigerlakeURvpDetect.c @@ -0,0 +1,39 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +=0D +#include =0D +=0D +BOOLEAN=0D +TigerlakeURvp(=0D + VOID=0D + )=0D +{=0D + return TRUE;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardDetect (=0D + VOID=0D + )=0D +{=0D + if (LibPcdGetSku () !=3D 0) {=0D + return EFI_SUCCESS;=0D + }=0D +=0D + DEBUG ((DEBUG_INFO, "TigerLakeU Board Detection Callback\n"));=0D +=0D + if (TigerlakeURvp ()) {=0D + LibPcdSetSku (SkuIdTglU);=0D + DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));=0D + ASSERT (LibPcdGetSku() =3D=3D SkuIdTglU);=0D + }=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiTigerlakeURvpInitPostMemLib.c b/Platform/Intel/TigerlakeOpenBo= ardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c new file mode 100644 index 0000000000..e775f83cce --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiTigerlakeURvpInitPostMemLib.c @@ -0,0 +1,153 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include "TigerlakeURvpInit.h"=0D +#include "GpioTableTigerlakeUDdr4Rvp.h"=0D +#include =0D +=0D +/**=0D + GPIO init function for PEI post memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +BoardGpioInit(=0D + IN UINT16 BoardId=0D + )=0D +{=0D + //=0D + // GPIO Table Init.=0D + //=0D + switch (BoardId) {=0D +=0D + case BoardIdTglUDdr4:=0D + PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableTglUDdr4);=0D + PcdSet16S (PcdBoardGpioTableSize, mGpioTableTglUDdr4Size);=0D + break;=0D +=0D + default:=0D + break;=0D + }=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Touch panel GPIO init function for PEI post memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +TouchPanelGpioInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Misc. init function for PEI post memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +BoardMiscInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Security GPIO init function for PEI post memory phase.=0D +=0D + @param[in] BoardId An unsigned integrer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +BoardSecurityInit (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Board configuration initialization in the post-memory boot phase.=0D +**/=0D +VOID=0D +BoardConfigInit (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 BoardId;=0D +=0D + BoardId =3D BoardIdTglUDdr4;=0D +=0D + Status =3D BoardGpioInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D TouchPanelGpioInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D BoardMiscInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D BoardSecurityInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +=0D +/**=0D + Configure GPIO and SIO=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardInitBeforeSiliconInit(=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "Board Init before Silicon Init\n"));=0D +=0D + BoardConfigInit ();=0D + //=0D + // Configure GPIO and SIO=0D + //=0D + Status =3D BoardInit ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + //=0D + // Initializing Platform Specific Programming=0D + //=0D + Status =3D PlatformSpecificInit ();=0D + ASSERT_EFI_ERROR(Status);=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/PeiTigerlakeURvpInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoa= rdPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c new file mode 100644 index 0000000000..2ad229c1cd --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/PeiTigerlakeURvpInitPreMemLib.c @@ -0,0 +1,445 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +///=0D +/// Reset Generator I/O Port=0D +///=0D +#define RESET_GENERATOR_PORT 0xCF9=0D +=0D +typedef struct {=0D + EFI_PHYSICAL_ADDRESS BaseAddress;=0D + UINT64 Length;=0D +} MEMORY_MAP;=0D +=0D +GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] =3D {=0D + { FixedPcdGet64 (PcdLocalApicAddress), FixedPcdGet32 (PcdLocalApicMmioS= ize) },=0D + { FixedPcdGet64 (PcdMchBaseAddress), FixedPcdGet32 (PcdMchMmioSize) }= ,=0D + { FixedPcdGet64 (PcdDmiBaseAddress), FixedPcdGet32 (PcdDmiMmioSize) }= ,=0D + { FixedPcdGet64 (PcdEpBaseAddress), FixedPcdGet32 (PcdEpMmioSize) }= =0D +};=0D +=0D +EFI_STATUS=0D +MrcConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +SaGpioConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +SaMiscConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +RootPortClkInfoInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +UsbConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +GpioGroupTierInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +GpioTablePreMemInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +PchPmConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +SaDisplayConfigInit (=0D + IN UINT16 BoardId=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PlatformInitPreMemCallBack (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D + IN VOID *Ppi=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +MemoryDiscoveredPpiNotify (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D + IN VOID *Ppi=0D + );=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +PchReset (=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + );=0D +=0D +static EFI_PEI_RESET_PPI mResetPpi =3D {=0D + PchReset=0D +};=0D +=0D +static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] =3D {=0D + {=0D + (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),= =0D + &gEfiPeiResetPpiGuid,=0D + &mResetPpi=0D + }=0D +};=0D +=0D +static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList =3D {=0D + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST),=0D + &gEfiPeiReadOnlyVariable2PpiGuid,=0D + (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack=0D +};=0D +=0D +static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList =3D {=0D + (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINA= TE_LIST),=0D + &gEfiPeiMemoryDiscoveredPpiGuid,=0D + (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify=0D +};=0D +=0D +/**=0D + Board misc init function for PEI pre-memory phase.=0D +=0D + @param[in] BoardId An unsigned integer represent the board id.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +BoardMiscInitPreMem (=0D + IN UINT16 BoardId=0D + )=0D +{=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Board configuration initialization in the pre-memory boot phase.=0D +**/=0D +VOID=0D +BoardConfigInitPreMem (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + UINT16 BoardId;=0D +=0D + BoardId =3D BoardIdTglUDdr4;=0D +=0D + Status =3D MrcConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D SaGpioConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D SaMiscConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D RootPortClkInfoInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D UsbConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GpioGroupTierInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D GpioTablePreMemInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D PchPmConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D BoardMiscInitPreMem (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + Status =3D SaDisplayConfigInit (BoardId);=0D + ASSERT_EFI_ERROR (Status);=0D +}=0D +=0D +/**=0D + This function handles PlatformInit task after PeiReadOnlyVariable2 PPI p= roduced=0D +=0D + @param[in] PeiServices Pointer to PEI Services Table.=0D + @param[in] NotifyDesc Pointer to the descriptor for the Notification= event that=0D + caused this function to execute.=0D + @param[in] Ppi Pointer to the PPI data associated with this f= unction.=0D +=0D + @retval EFI_SUCCESS The function completes successfully=0D + @retval others Failure=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PlatformInitPreMemCallBack (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D + IN VOID *Ppi=0D + )=0D +{=0D + EFI_STATUS Status;=0D +=0D + DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack Start...\n"));=0D + //=0D + // Init Board Config Pcd.=0D + //=0D + BoardConfigInitPreMem ();=0D +=0D + ///=0D + /// Configure GPIO and SIO=0D + ///=0D + Status =3D BoardInitPreMem ();=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + ///=0D + /// Install Pre Memory PPIs=0D + ///=0D + Status =3D PeiServicesInstallPpi (&mPreMemPpiList[0]);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack End...\n"));=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Provide hard reset PPI service.=0D + To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xC= F9).=0D +=0D + @param[in] PeiServices General purpose services available to ever= y PEIM.=0D +=0D + @retval Not return System reset occured.=0D + @retval EFI_DEVICE_ERROR Device error, could not reset the system.= =0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +PchReset (=0D + IN CONST EFI_PEI_SERVICES **PeiServices=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));=0D + IoWrite8 (RESET_GENERATOR_PORT, 0x0E);=0D +=0D + CpuDeadLoop ();=0D +=0D + ///=0D + /// System reset occured, should never reach at this line.=0D + ///=0D + ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);=0D + return EFI_DEVICE_ERROR;=0D +}=0D +=0D +/**=0D + Install Firmware Volume Hob's once there is main memory=0D +=0D + @param[in] PeiServices General purpose services available to ever= y PEIM.=0D + @param[in] NotifyDescriptor Notify that this module published.=0D + @param[in] Ppi PPI that was installed.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +MemoryDiscoveredPpiNotify (=0D + IN CONST EFI_PEI_SERVICES **PeiServices,=0D + IN EFI_PEI_NOTIFY_DESCRIPTOR *NotifyDescriptor,=0D + IN VOID *Ppi=0D + )=0D +{=0D + EFI_STATUS Status;=0D + EFI_BOOT_MODE BootMode;=0D + UINTN Index;=0D + UINT8 PhysicalAddressBits;=0D + UINT32 RegEax;=0D + MEMORY_MAP PcieMmioMap;=0D +=0D + DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify Start!\n"));=0D +=0D + Index =3D 0;=0D +=0D + Status =3D PeiServicesGetBootMode (&BootMode);=0D + ASSERT_EFI_ERROR (Status);=0D +=0D + AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);=0D + if (RegEax >=3D 0x80000008) {=0D + AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);=0D + PhysicalAddressBits =3D (UINT8)RegEax;=0D + }=0D + else {=0D + PhysicalAddressBits =3D 36;=0D + }=0D +=0D + ///=0D + /// Create a CPU hand-off information=0D + ///=0D + BuildCpuHob (PhysicalAddressBits, 16);=0D +=0D + ///=0D + /// Build Memory Mapped IO Resource which is used to build E820 Table in= LegacyBios.=0D + ///=0D + PcieMmioMap.BaseAddress =3D FixedPcdGet64 (PcdPciExpressBaseAddress);=0D + PcieMmioMap.Length =3D PcdGet32 (PcdPciExpressRegionLength);=0D +=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + (EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),=0D + PcieMmioMap.BaseAddress,=0D + PcieMmioMap.Length=0D + );=0D + BuildMemoryAllocationHob (=0D + PcieMmioMap.BaseAddress,=0D + PcieMmioMap.Length,=0D + EfiMemoryMappedIO=0D + );=0D + for (Index =3D 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index+= +) {=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + (EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),=0D + MmioMap[Index].BaseAddress,=0D + MmioMap[Index].Length=0D + );=0D + BuildMemoryAllocationHob (=0D + MmioMap[Index].BaseAddress,=0D + MmioMap[Index].Length,=0D + EfiMemoryMappedIO=0D + );=0D + }=0D +=0D + //=0D + // Report resource HOB for flash FV=0D + //=0D + BuildResourceDescriptorHob (=0D + EFI_RESOURCE_MEMORY_MAPPED_IO,=0D + (EFI_RESOURCE_ATTRIBUTE_PRESENT |=0D + EFI_RESOURCE_ATTRIBUTE_INITIALIZED |=0D + EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),=0D + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),=0D + (UINTN) FixedPcdGet32 (PcdFlashAreaSize)=0D + );=0D +=0D + BuildMemoryAllocationHob (=0D + (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),=0D + (UINTN) FixedPcdGet32 (PcdFlashAreaSize),=0D + EfiMemoryMappedIO=0D + );=0D +=0D + BuildFvHob (=0D + (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),=0D + (UINTN)FixedPcdGet32 (PcdFlashAreaSize)=0D + );=0D +=0D + DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify End!\n"));=0D +=0D + return Status;=0D +}=0D +=0D +/**=0D + Board configuration init function for PEI pre-memory phase.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D + @retval EFI_INVALID_PARAMETER The parameter is NULL.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpInitPreMem (=0D + VOID=0D + )=0D +{=0D + EFI_STATUS Status;=0D + DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem Start!\n"));=0D + ///=0D + /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI= produced=0D + ///=0D + Status =3D PeiServicesNotifyPpi (&mPreMemNotifyList);=0D +=0D + ///=0D + /// After code reorangized, memorycallback will run because the PPI is a= lready=0D + /// installed when code run to here, it is supposed that the InstallEfiM= emory is=0D + /// done before.=0D + ///=0D + Status =3D PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);=0D +=0D + DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem End!\n"));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Configure GPIO and SIO before memory ready=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardInitBeforeMemoryInit(=0D + VOID=0D + )=0D +{=0D +=0D + TigerlakeURvpInitPreMem();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_STATUS=0D +EFIAPI=0D +TigerlakeURvpBoardDebugInit(=0D + VOID=0D + )=0D +{=0D + ///=0D + /// Do Early PCH init=0D + ///=0D + return EFI_SUCCESS;=0D +}=0D +=0D +EFI_BOOT_MODE=0D +EFIAPI=0D +TigerlakeURvpBoardBootModeDetect(=0D + VOID=0D + )=0D +{=0D + return BOOT_WITH_FULL_CONFIGURATION;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Boa= rdInitLib/TigerlakeURvpInit.h b/Platform/Intel/TigerlakeOpenBoardPkg/Tigerl= akeURvp/Library/BoardInitLib/TigerlakeURvpInit.h new file mode 100644 index 0000000000..ccffcc6761 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitL= ib/TigerlakeURvpInit.h @@ -0,0 +1,23 @@ +/** @file=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _TIGER_LAKE_U_RVP_INIT_H_=0D +#define _TIGER_LAKE_U_RVP_INIT_H_=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +extern GPIO_INIT_CONFIG mGpioTableTglUDdr4[];=0D +extern UINT16 mGpioTableTglUDdr4Size;=0D +=0D +=0D +#endif // _TIGER_LAKE_U_RVP_INIT_H_=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Pei= PlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/TigerlakeOpenBoardPkg= /TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c new file mode 100644 index 0000000000..6c2587391d --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatfor= mHookLib/PeiPlatformHooklib.c @@ -0,0 +1,212 @@ +/** @file=0D + PEI Library Functions. Initialize GPIOs=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +#include =0D +=0D +#define SIO_RUNTIME_REG_BASE_ADDRESS 0x0680=0D +=0D +#define RECOVERY_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD=0D +=0D +#define MANUFACTURE_MODE_GPIO_PIN 0 // = Platform specific @todo use PCD=0D +=0D +/**=0D + Configures GPIO=0D +=0D + @param[in] GpioTable Point to Platform Gpio table=0D + @param[in] GpioTableCount Number of Gpio table entries=0D +=0D +**/=0D +VOID=0D +ConfigureGpio (=0D + IN GPIO_INIT_CONFIG *GpioDefinition,=0D + IN UINT16 GpioTableCount=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));=0D +=0D +=0D + CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount);=0D +=0D +=0D + GpioConfigurePads (GpioTableCount, GpioDefinition);=0D +=0D + DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));=0D +}=0D +=0D +/**=0D + Configure GPIO group GPE tier.=0D +=0D + @retval none.=0D +**/=0D +VOID=0D +GpioGroupTierInitHook(=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n"));=0D +=0D + DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n"));=0D +}=0D +=0D +/**=0D + Configure single GPIO pad for touchpanel interrupt=0D +**/=0D +VOID=0D +TouchpanelGpioInit (=0D + VOID=0D + )=0D +{=0D +=0D +}=0D +=0D +/**=0D + Configure GPIO Before Memory is not ready.=0D +=0D +**/=0D +VOID=0D +GpioInitPreMem (=0D + VOID=0D + )=0D +{=0D + if (PcdGet32 (PcdBoardGpioTablePreMem) !=3D 0 && PcdGet16 (PcdBoardGpioT= ablePreMemSize) !=3D 0) {=0D + DEBUG ((DEBUG_INFO, "Pre-mem Gpio Config\n"));=0D + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (U= INTN) PcdGet16 (PcdBoardGpioTablePreMemSize));=0D + }=0D +}=0D +=0D +/**=0D + Basic GPIO configuration before memory is ready=0D +=0D +**/=0D +VOID=0D +GpioInitEarlyPreMem (=0D + VOID=0D + )=0D +{=0D +=0D +}=0D +=0D +/**=0D + Configure GPIO=0D +=0D +**/=0D +=0D +VOID=0D +GpioInit (=0D + VOID=0D + )=0D +{=0D + DEBUG ((DEBUG_INFO, "Post-mem Gpio Config\n"));=0D + ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) Pc= dGet16 (PcdBoardGpioTableSize));=0D +=0D + TouchpanelGpioInit();=0D +=0D + return;=0D +}=0D +=0D +/**=0D + Configure Super IO=0D +=0D +**/=0D +VOID=0D +SioInit (=0D + VOID=0D + )=0D +{=0D + //=0D + // Program and Enable Default Super IO Configuration Port Addresses and = range=0D + //=0D + PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x1= 0);=0D +=0D + PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS & (~0x7F), 0x10);=0D + return;=0D +}=0D +=0D +/**=0D + Configure GPIO and SIO before memory ready=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInitPreMem (=0D + VOID=0D + )=0D +{=0D + //=0D + // Obtain Platform Info from HOB.=0D + //=0D + GpioInitPreMem ();=0D + GpioGroupTierInitHook ();=0D + SioInit ();=0D +=0D + DEBUG ((DEBUG_INFO, "BoardInitPreMem Done\n"));=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Configure GPIO and SIO=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInit (=0D + VOID=0D + )=0D +{=0D +=0D + GpioInit ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Do platform specific programming post-memory.=0D +=0D + @retval EFI_SUCCESS The function completed successfully.=0D +**/=0D +=0D +EFI_STATUS=0D +PlatformSpecificInit (=0D + VOID=0D + )=0D +{=0D +=0D + return EFI_SUCCESS;=0D +}=0D +=0D +/**=0D + Early Board Configuration before memory is ready=0D +=0D + @retval EFI_SUCCESS Operation success.=0D +**/=0D +EFI_STATUS=0D +BoardInitEarlyPreMem (=0D + VOID=0D + )=0D +{=0D + GpioInitEarlyPreMem ();=0D +=0D + return EFI_SUCCESS;=0D +}=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/Pei= PlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/TigerlakeOpenBoardP= kg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf new file mode 100644 index 0000000000..8e4ce47d5a --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatfor= mHookLib/PeiPlatformHooklib.inf @@ -0,0 +1,58 @@ +## @file=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + INF_VERSION =3D 0x00010017=0D + BASE_NAME =3D PeiPlatformHookLib=0D + FILE_GUID =3D AD901798-B0DA-4B20-B90C-283F886E76D0= =0D + VERSION_STRING =3D 1.0=0D + MODULE_TYPE =3D PEIM=0D + LIBRARY_CLASS =3D PeiPlatformHookLib|PEIM PEI_CORE SEC= =0D +=0D +[LibraryClasses]=0D + DebugLib=0D + BaseMemoryLib=0D + IoLib=0D + HobLib=0D + PcdLib=0D + TimerLib=0D + PchCycleDecodingLib=0D + GpioLib=0D + PeiServicesLib=0D + ConfigBlockLib=0D + PmcLib=0D + PchPcrLib=0D + PciSegmentLib=0D + GpioCheckConflictLib=0D +=0D +[Packages]=0D + MdePkg/MdePkg.dec=0D + TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D + TigerlakeSiliconPkg/SiPkg.dec=0D + IntelSiliconPkg/IntelSiliconPkg.dec=0D +=0D +[Pcd]=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress = ## CONSUMES=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem ## CONSUMES= =0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize ## CONSUMES= =0D +=0D +[Sources]=0D + PeiPlatformHooklib.c=0D +=0D +[Ppis]=0D + gEfiPeiReadOnlyVariable2PpiGuid ## CONSUMES=0D + gSiPolicyPpiGuid ## CONSUMES=0D +=0D +[Guids]=0D + gSaDataHobGuid ## CONSUMES=0D + gEfiGlobalVariableGuid ## CONSUMES=0D + gGpioCheckConflictHobGuid ## CONSUMES=0D +=0D --=20 2.24.0.windows.2