From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga12.intel.com (mga12.intel.com []) by mx.groups.io with SMTP id smtpd.web08.17214.1612676320596081476 for ; Sat, 06 Feb 2021 21:38:46 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=fail (domain: intel.com, ip: , mailfrom: heng.luo@intel.com) IronPort-SDR: w8VcJ/7gJPWOdjq/pobo/44YYb09UovCGt8jcVKs+u99wRO9n8hfVaQ1mS+0rRglIJcxAYhj2C vve4Ygsv4NSg== X-IronPort-AV: E=McAfee;i="6000,8403,9887"; a="160740790" X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="160740790" Received: from fmsmga008.fm.intel.com ([10.253.24.58]) by fmsmga106.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Feb 2021 21:38:46 -0800 IronPort-SDR: Frl0Ktf4KmTVldZ0ThfZ7VGptW59l/Qqtw/pFhtINIMXe3Qsw7F1wKMHEG3wY3rYDjTinbimhx PgTMcSd0GgWg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,158,1610438400"; d="scan'208";a="374956061" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by fmsmga008.fm.intel.com with ESMTP; 06 Feb 2021 21:38:44 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [PATCH 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files Date: Sun, 7 Feb 2021 13:38:32 +0800 Message-Id: <20210207053834.4048-6-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 In-Reply-To: <20210207053834.4048-1-heng.luo@intel.com> References: <20210207053834.4048-1-heng.luo@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Adds the DSC and build files necessary to build the TigerlakeURvp board instance. Key files: * build_config.cfg - Board-specific build configuration file. * OpenBoardPkg.dsc - The TigerlakeURvp board description file. * OpenBoardPkgPcd.dsc - Used for other PCD customization. * OpenBoardPkg.fdf - The TigerlakeURvp board flash file. * OpenBoardPkgBuildOption.dsc - Sets build options Based on PCD values. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc = | 347 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf = | 702 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildOption= .dsc | 141 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc = | 392 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg = | 34 ++++++++++++++++++++++++++++++++++ 5 files changed, 1616 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPk= g.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc new file mode 100644 index 0000000000..a4265a839c --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc @@ -0,0 +1,347 @@ +## @file=0D +# The main build description file for the TigerlakeURvp board.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + DEFINE PLATFORM_PACKAGE =3D MinPlatformPkg=0D + DEFINE PLATFORM_SI_PACKAGE =3D TigerlakeSiliconPkg=0D + DEFINE PLATFORM_SI_BIN_PACKAGE =3D TigerlakeSiliconBinPkg=0D + DEFINE PLATFORM_FSP_BIN_PACKAGE =3D TigerLakeFspBinPkg/Client=0D + DEFINE PLATFORM_BOARD_PACKAGE =3D TigerlakeOpenBoardPkg=0D + DEFINE BOARD =3D TigerlakeURvp=0D + DEFINE PROJECT =3D $(PLATFORM_BOARD_PACKAGE)/$(BO= ARD)=0D + DEFINE PEI_ARCH =3D IA32=0D + DEFINE DXE_ARCH =3D X64=0D + DEFINE TOP_MEMORY_ADDRESS =3D 0x0=0D +=0D + #=0D + # Default value for OpenBoardPkg.fdf use=0D + #=0D + DEFINE BIOS_SIZE_OPTION =3D SIZE_120=0D +=0D +[Defines]=0D + PLATFORM_NAME =3D $(PLATFORM_BOARD_PACKAGE)=0D + PLATFORM_GUID =3D 465B0A0B-7AC1-443b-8F67-7B8DEC= 145F90=0D + PLATFORM_VERSION =3D 0.1=0D + DSC_SPECIFICATION =3D 0x00010005=0D + OUTPUT_DIRECTORY =3D Build/$(PROJECT)=0D + SUPPORTED_ARCHITECTURES =3D IA32|X64=0D + BUILD_TARGETS =3D DEBUG|RELEASE=0D + SKUID_IDENTIFIER =3D ALL=0D +=0D + FLASH_DEFINITION =3D $(PROJECT)/OpenBoardPkg.fdf=0D + FIX_LOAD_TOP_MEMORY_ADDRESS =3D 0x0=0D +=0D + #=0D + # Include PCD configuration for this board.=0D + #=0D + !include OpenBoardPkgPcd.dsc=0D +=0D +##########################################################################= ######=0D +#=0D +# SKU Identification section - list of all SKU IDs supported by this board= .=0D +#=0D +##########################################################################= ######=0D +[SkuIds]=0D + 0|DEFAULT # 0|DEFAULT is reserved and always required.=0D + 0x01|SkuIdTglU=0D +=0D +=0D +##########################################################################= ######=0D +#=0D +# Includes section - other DSC file contents included for this board build= .=0D +#=0D +##########################################################################= ######=0D +=0D +#######################################=0D +# Library Includes=0D +#######################################=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreCommonLib.dsc=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiLib.dsc=0D +!include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeLib.dsc=0D +=0D +[LibraryClasses.common]=0D +=0D + PeiLib|$(PLATFORM_PACKAGE)/Library/PeiLib/PeiLib.inf=0D + ReportFvLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/PeiReportFvLib/PeiR= eportFvLib.inf=0D +=0D + PciHostBridgeLib|$(PLATFORM_PACKAGE)/Pci/Library/PciHostBridgeLibSimple/= PciHostBridgeLibSimple.inf=0D + PciSegmentInfoLib|$(PLATFORM_PACKAGE)/Pci/Library/PciSegmentInfoLibSimpl= e/PciSegmentInfoLibSimple.inf=0D + PlatformBootManagerLib|$(PLATFORM_PACKAGE)/Bds/Library/DxePlatformBootMa= nagerLib/DxePlatformBootManagerLib.inf=0D +=0D + PlatformHookLib|$(PLATFORM_BOARD_PACKAGE)/Library/BasePlatformHookLib/Ba= sePlatformHookLib.inf=0D +=0D + FspWrapperHobProcessLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWra= pperHobProcessLib/PeiFspWrapperHobProcessLib.inf=0D + PlatformSecLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/SecFspWrapperPlatf= ormSecLib/SecFspWrapperPlatformSecLib.inf=0D + PeiGetVtdPmrAlignmentLib|IntelSiliconPkg/Library/PeiGetVtdPmrAlignmentLi= b/PeiGetVtdPmrAlignmentLib.inf=0D +=0D + FspWrapperApiLib|IntelFsp2WrapperPkg/Library/BaseFspWrapperApiLib/BaseFs= pWrapperApiLib.inf=0D + FspWrapperApiTestLib|IntelFsp2WrapperPkg/Library/PeiFspWrapperApiTestLib= /PeiFspWrapperApiTestLib.inf=0D +=0D + ConfigBlockLib|IntelSiliconPkg/Library/BaseConfigBlockLib/BaseConfigBloc= kLib.inf=0D +=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/BoardInitLibNull/B= oardInitLibNull.inf=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf=0D +=0D + PciSegmentLib|$(PLATFORM_SI_PACKAGE)/Library/BasePciSegmentMultiSegLibPc= i/BasePciSegmentMultiSegLibPci.inf=0D + PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf=0D + ReportCpuHobLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/ReportCpuHobLib= /ReportCpuHobLib.inf=0D +=0D + #=0D + # Silicon Init Package=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgCommonLib.dsc=0D +=0D + #=0D + # Shell=0D + #=0D + ShellCommandLib|ShellPkg/Library/UefiShellCommandLib/UefiShellCommandLib= .inf=0D + HandleParsingLib|ShellPkg/Library/UefiHandleParsingLib/UefiHandleParsing= Lib.inf=0D + BcfgCommandLib|ShellPkg/Library/UefiShellBcfgCommandLib/UefiShellBcfgCom= mandLib.inf=0D +=0D +[LibraryClasses.IA32]=0D + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/PeiFspWrappe= rPlatformLib/PeiFspWrapperPlatformLib.inf=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Pei= TestPointCheckLib.inf=0D +!endif=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/PeiTestPointL= ib.inf=0D + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/PeiMultiBoardInitSupportLib.inf=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/PeiMultiBoardInitSupportLib.inf=0D +=0D + #=0D + # Silicon Init Package=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgPeiLib.dsc=0D +=0D + #=0D + # Use Null library instance to skip MTRR initialization from MinPlatform= Pkg PlatformInit modules.=0D + # MTRR configuration will be done by FSP or PlatformInitAdvanced modules= .=0D + #=0D + SetCacheMtrrLib|$(PLATFORM_PACKAGE)/Library/SetCacheMtrrLib/SetCacheMtrr= LibNull.inf=0D +=0D + #=0D + # SmmAccess=0D + #=0D + SmmAccessLib|IntelSiliconPkg/Feature/SmmAccess/Library/PeiSmmAccessLib/P= eiSmmAccessLib.inf=0D +=0D + SiliconPolicyInitLib|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf=0D + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconP= olicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf=0D +=0D + #######################################=0D + # Board-specific=0D + #######################################=0D + PeiPlatformHookLib|$(PROJECT)/Library/PeiPlatformHookLib/PeiPlatformHook= lib.inf=0D +=0D +!if $(TARGET) =3D=3D DEBUG=0D + GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpi= oCheckConflictLib/BaseGpioCheckConflictLib.inf=0D +!else=0D + GpioCheckConflictLib|$(PLATFORM_SI_PACKAGE)/IpBlock/Gpio/Library/BaseGpi= oCheckConflictLibNull/BaseGpioCheckConflictLibNull.inf=0D +!endif=0D +=0D +[LibraryClasses.IA32.SEC]=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Sec= TestPointCheckLib.inf=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLibNull= /TestPointCheckLibNull.inf=0D + SecBoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SecBoardInitLib= Null/SecBoardInitLibNull.inf=0D +=0D +[LibraryClasses.X64]=0D + #=0D + # DXE phase common=0D + #=0D + FspWrapperPlatformLib|$(PLATFORM_PACKAGE)/FspWrapper/Library/DxeFspWrapp= erPlatformLib/DxeFspWrapperPlatformLib.inf=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Dxe= TestPointCheckLib.inf=0D +!endif=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/DxeTestPointL= ib.inf=0D + MultiBoardInitSupportLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiB= oardInitSupportLib/DxeMultiBoardInitSupportLib.inf=0D + BoardInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/MultiBoardInitSupp= ortLib/DxeMultiBoardInitSupportLib.inf=0D + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/DxeMultiBoardAcpiSupportLib.inf=0D + BoardAcpiTableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSupport= Lib/DxeMultiBoardAcpiSupportLib.inf=0D + AslUpdateLib|$(PLATFORM_PACKAGE)/Acpi/Library/DxeAslUpdateLib/DxeAslUpda= teLib.inf=0D +=0D + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/SiliconPol= icyInitLibNull/SiliconPolicyInitLibNull.inf=0D + SiliconPolicyUpdateLib|$(PLATFORM_BOARD_PACKAGE)/Policy/Library/DxeSilic= onPolicyUpdateLib/DxeSiliconPolicyUpdateLib.inf=0D + BoardBdsHookLib|BoardModulePkg/Library/BoardBdsHookLib/BoardBdsHookLib.i= nf=0D + BoardBootManagerLib|BoardModulePkg/Library/BoardBootManagerLib/BoardBoot= ManagerLib.inf=0D +=0D + #=0D + # Silicon Init Package=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgDxeLib.dsc=0D +=0D +[LibraryClasses.X64.DXE_SMM_DRIVER]=0D + SpiFlashCommonLib|$(PLATFORM_BOARD_PACKAGE)/Library/SmmSpiFlashCommonLib= /SmmSpiFlashCommonLib.inf=0D +!if $(TARGET) =3D=3D DEBUG=0D + TestPointCheckLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointCheckLib/Smm= TestPointCheckLib.inf=0D +!endif=0D + BoardAcpiEnableLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpiSuppor= tLib/SmmMultiBoardAcpiSupportLib.inf=0D + MultiBoardAcpiSupportLib|$(PLATFORM_PACKAGE)/Acpi/Library/MultiBoardAcpi= SupportLib/SmmMultiBoardAcpiSupportLib.inf=0D + TestPointLib|$(PLATFORM_PACKAGE)/Test/Library/TestPointLib/SmmTestPointL= ib.inf=0D +=0D +[LibraryClasses.X64.DXE_RUNTIME_DRIVER]=0D + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/Bas= eResetSystemLib.inf=0D +=0D +[Components.IA32]=0D +=0D + #=0D + # Common=0D + #=0D + !include $(PLATFORM_PACKAGE)/Include/Dsc/CorePeiInclude.dsc=0D +=0D + #=0D + # FSP wrapper SEC Core=0D + #=0D + UefiCpuPkg/SecCore/SecCore.inf {=0D + =0D + PcdLib|MdePkg/Library/PeiPcdLib/PeiPcdLib.inf=0D + }=0D +=0D + #=0D + # Silicon=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgPei.dsc=0D +=0D + #=0D + # Platform=0D + #=0D + $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.inf = {=0D + =0D + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf= =0D + }=0D + IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf {=0D + =0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D + SiliconPolicyInitLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Silico= nPolicyInitLibNull/SiliconPolicyInitLibNull.inf=0D + SiliconPolicyUpdateLib|$(PLATFORM_PACKAGE)/PlatformInit/Library/Sili= conPolicyUpdateLibNull/SiliconPolicyUpdateLibNull.inf=0D +!endif=0D + }=0D +=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.inf= {=0D + =0D + NULL|$(PROJECT)/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf= =0D + }=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPostMe= m.inf {=0D + =0D + NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiDefaultPolicy= InitLib/PeiSiDefaultPolicyInitLib.inf=0D + }=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreMem= .inf {=0D + =0D + NULL|$(PLATFORM_BOARD_PACKAGE)/FspWrapper/Library/PeiSiPreMemDefault= PolicyInitLib/PeiSiPreMemDefaultPolicyInitLib.inf=0D + #=0D + # In FSP Dispatch mode below dummy library should be linked to bootl= oader PEIM=0D + # to build all DynamicEx PCDs that FSP consumes into bootloader PCD = database.=0D + #=0D + NULL|$(PLATFORM_FSP_BIN_PACKAGE)/Library/FspPcdListLib/FspPcdListLib= Null.inf=0D + }=0D +!endif=0D + $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf=0D + $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf=0D +=0D + IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf=0D +=0D + #=0D + MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf=0D + # Security=0D + #=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformPei/Tcg2PlatformPei.inf=0D +!endif=0D + MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf {=0D + =0D + ResetSystemLib|$(PLATFORM_SI_PACKAGE)/Pch/Library/BaseResetSystemLib/= BaseResetSystemLib.inf=0D + }=0D +=0D +[Components.X64]=0D +=0D + #=0D + # Common=0D + #=0D + !include $(PLATFORM_PACKAGE)/Include/Dsc/CoreDxeInclude.dsc=0D +=0D + #=0D + #UEFI Shell=0D + #=0D + ShellPkg/Application/Shell/Shell.inf {=0D + =0D + NULL|ShellPkg/Library/UefiShellLevel2CommandsLib/UefiShellLevel2Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel1CommandsLib/UefiShellLevel1Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellLevel3CommandsLib/UefiShellLevel3Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDriver1CommandsLib/UefiShellDriver1Co= mmandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellInstall1CommandsLib/UefiShellInstall1= CommandsLib.inf=0D + NULL|ShellPkg/Library/UefiShellDebug1CommandsLib/UefiShellDebug1Comm= andsLib.inf=0D + NULL|ShellPkg/Library/UefiShellNetwork1CommandsLib/UefiShellNetwork1= CommandsLib.inf=0D +=0D + =0D + gEfiShellPkgTokenSpaceGuid.PcdShellLibAutoInitialize|FALSE=0D + }=0D +=0D + UefiCpuPkg/CpuDxe/CpuDxe.inf=0D + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +=0D + MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D + MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D + MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D + MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D + MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.inf=0D +=0D + BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D +=0D + #=0D + # Silicon=0D + #=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgDxe.dsc=0D + $(PLATFORM_SI_BIN_PACKAGE)/Microcode/MicrocodeUpdates.inf=0D +=0D + #=0D + # SmmAccess=0D + #=0D + IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf=0D +=0D + #=0D + # Platform=0D + #=0D + $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf=0D +!endif=0D + $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf=0D +=0D + $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf=0D + $(PLATFORM_PACKAGE)/Test/TestPointDumpApp/TestPointDumpApp.inf=0D +=0D + #=0D + # OS Boot=0D + #=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D + $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf=0D + $(PLATFORM_PACKAGE)/Acpi/MinDsdt/MinDsdt.inf=0D + $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf {=0D + =0D + NULL|$(PROJECT)/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf= =0D + }=0D +=0D + $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf=0D + $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf=0D +=0D + UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf {=0D + =0D + SmmCpuFeaturesLib|UefiCpuPkg/Library/SmmCpuFeaturesLib/SmmCpuFeature= sLib.inf=0D + }=0D +!endif=0D +=0D + #=0D + # Security=0D + #=0D + $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D + $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf=0D +!endif=0D +=0D + !include $(PLATFORM_SI_PACKAGE)/SiPkgBuildOption.dsc=0D + !include OpenBoardPkgBuildOption.dsc=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPk= g.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf new file mode 100644 index 0000000000..0f645ed63e --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.fdf @@ -0,0 +1,702 @@ +## @file=0D +# FDF file of Platform.=0D +#=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[Defines]=0D + !include $(PROJECT)/Include/Fdf/FlashMapInclude.fdf=0D +=0D +##########################################################################= ######=0D +#=0D +# FD Section=0D +# The [FD] Section is made up of the definition statements and a=0D +# description of what goes into the Flash Device Image. Each FD section= =0D +# defines one flash "device" image. A flash device image may be one of=0D +# the following: Removable media bootable image (like a boot floppy=0D +# image,) an Option ROM image (that would be "flashed" into an add-in=0D +# card,) a System "Flash" image (that would be burned into a system's=0D +# flash) or an Update ("Capsule") image that will be used to update and=0D +# existing system flash.=0D +#=0D +##########################################################################= ######=0D +[FD.TigerlakeURvp]=0D +#=0D +# FD Tokens, BaseAddress, Size, ErasePolarity, BlockSize, and NumBlocks, c= annot be=0D +# assigned with PCD values. Instead, it uses the definitions for its varie= ty, which=0D +# are FLASH_BASE, FLASH_SIZE, FLASH_BLOCK_SIZE and FLASH_NUM_BLOCKS.=0D +#=0D +BaseAddress =3D $(FLASH_BASE) | gSiPkgTokenSpaceGuid.PcdBiosAreaBaseAddr= ess #The base address of the FLASH Device.=0D +Size =3D $(FLASH_SIZE) | gSiPkgTokenSpaceGuid.PcdBiosSize = #The size in bytes of the FLASH Device=0D +ErasePolarity =3D 1=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +NumBlocks =3D $(FLASH_NUM_BLOCKS)=0D +=0D +DEFINE SIPKG_DXE_SMM_BIN =3D INF=0D +DEFINE SIPKG_PEI_BIN =3D INF=0D +=0D +# Set FLASH_REGION_FV_RECOVERY_OFFSET to PcdNemCodeCacheBase, because macr= o expression is not supported.=0D +# So, PlatformSecLib uses PcdFlashAreaBaseAddress + PcdNemCodeCacheBase to= get the real CodeCache base address.=0D +SET gSiPkgTokenSpaceGuid.PcdNemCodeCacheBase =3D $(gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvPreMemoryOffset)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffse= t)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeOffset =3D 0x1000=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase =3D $(gSiPkgTokenSpaceGui= d.PcdBiosAreaBaseAddress) + $(gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffse= t)=0D +SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize =3D $(gSiPkgTokenSpaceGui= d.PcdFlashMicrocodeFvSize)=0D +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gSiPkgToke= nSpaceGuid.PcdFlashMicrocodeFvBase) + $(gSiPkgTokenSpaceGuid.PcdFlashMicroc= odeOffset)=0D +SET gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(gSiPkgT= okenSpaceGuid.PcdFlashMicrocodeFvSize) - $(gSiPkgTokenSpaceGuid.PcdFlashMic= rocodeOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchAddress =3D $(gUef= iCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchAddress)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize =3D $(g= UefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashMicrocodeOffset =3D $(gSiPkgTo= kenSpaceGuid.PcdFlashMicrocodeOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFlashCodeCacheSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress =3D $(gSiPkgTokenSp= aceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashF= vFspTOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress =3D $(gSiPkgTokenSp= aceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashF= vFspMOffset)=0D +SET gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress =3D $(gSiPkgTokenSp= aceGuid.PcdBiosAreaBaseAddress) + $(gMinPlatformPkgTokenSpaceGuid.PcdFlashF= vFspSOffset)=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeBase =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvBase=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeSize =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvSize=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvMicrocodeOffset =3D gSiPkgTok= enSpaceGuid.PcdFlashMicrocodeFvOffset=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress =3D gSiPkgTok= enSpaceGuid.PcdBiosAreaBaseAddress=0D +SET gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize =3D gSiPkgTok= enSpaceGuid.PcdBiosSize=0D +##########################################################################= ######=0D +#=0D +# Following are lists of FD Region layout which correspond to the location= s of different=0D +# images within the flash device.=0D +#=0D +# Regions must be defined in ascending order and may not overlap.=0D +#=0D +# A Layout Region start with a eight digit hex offset (leading "0x" requir= ed) followed by=0D +# the pipe "|" character, followed by the size of the region, also in hex = with the leading=0D +# "0x" characters. Like:=0D +# Offset|Size=0D +# PcdOffsetCName|PcdSizeCName=0D +# RegionType =0D +# Fv Size can be adjusted=0D +#=0D +##########################################################################= ######=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageVariableSize=0D +#NV_VARIABLE_STORE=0D +DATA =3D {=0D + ## This is the EFI_FIRMWARE_VOLUME_HEADER=0D + # ZeroVector []=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + # FileSystemGuid=0D + 0x8D, 0x2B, 0xF1, 0xFF, 0x96, 0x76, 0x8B, 0x4C,=0D + 0xA9, 0x85, 0x27, 0x47, 0x07, 0x5B, 0x4F, 0x50,=0D + # FvLength: 0x60000=0D + 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + #Signature "_FVH" #Attributes=0D + 0x5F, 0x46, 0x56, 0x48, 0xFF, 0xFE, 0x04, 0x00,=0D + #HeaderLength #CheckSum #ExtHeaderOffset #Reserved #Revision=0D + #=0D + # Be careful on CheckSum field.=0D + #=0D + 0x48, 0x00, 0x2E, 0x09, 0x00, 0x00, 0x00, 0x02,=0D + #Blockmap[0]: 6 Blocks 0x10000 Bytes / Block=0D + 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00,=0D + #Blockmap[1]: End=0D + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,=0D + ## This is the VARIABLE_STORE_HEADER=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable =3D=3D TRUE=0D + # Signature: gEfiAuthenticatedVariableGuid =3D { 0xaaf32c78, 0x947b, 0x= 439a, { 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92 }}=0D + 0x78, 0x2c, 0xf3, 0xaa, 0x7b, 0x94, 0x9a, 0x43,=0D + 0xa1, 0x80, 0x2e, 0x14, 0x4e, 0xc3, 0x77, 0x92,=0D +!else=0D + # Signature: gEfiVariableGuid =3D { 0xddcf3616, 0x3275, 0x4164, { 0x98,= 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d }}=0D + 0x16, 0x36, 0xcf, 0xdd, 0x75, 0x32, 0x64, 0x41,=0D + 0x98, 0xb6, 0xfe, 0x85, 0x70, 0x7f, 0xfe, 0x7d,=0D +!endif=0D + #Size: 0x2E000 (gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariable= Size) - 0x48 (size of EFI_FIRMWARE_VOLUME_HEADER) =3D 0x2DFB8=0D + # This can speed up the Variable Dispatch a bit.=0D + 0xB8, 0xDF, 0x02, 0x00,=0D + #FORMATTED: 0x5A #HEALTHY: 0xFE #Reserved: UINT16 #Reserved1: UINT32=0D + 0x5A, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset|gEfiMdeMod= ulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingBase|gEfiMdeModu= lePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize=0D +#NV_FTW_WORKING=0D +DATA =3D {=0D + # EFI_FAULT_TOLERANT_WORKING_BLOCK_HEADER->Signature =3D gEdkiiWorkingBl= ockSignatureGuid =3D=0D + # { 0x9e58292b, 0x7c68, 0x497d, { 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0= x1b, 0x95 }}=0D + 0x2b, 0x29, 0x58, 0x9e, 0x68, 0x7c, 0x7d, 0x49,=0D + 0xa0, 0xce, 0x65, 0x0, 0xfd, 0x9f, 0x1b, 0x95,=0D + # Crc:UINT32 #WorkingBlockValid:1, WorkingBlockInvalid:1, Res= erved=0D + 0xE2, 0x33, 0xF2, 0x03, 0xFE, 0xFF, 0xFF, 0xFF,=0D + # WriteQueueSize: UINT64=0D + 0xE0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00=0D +}=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset|gEfiMdeModul= ePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D +gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareBase|gEfiMdeModule= PkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize=0D +#NV_FTW_SPARE=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvAdvancedSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvAdvancedSize=0D +FV =3D FvAdvanced=0D +=0D +gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|gBoardModuleTokenSpace= Guid.PcdFlashFvOptionalSize=0D +gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|gBoardModuleTokenSpaceGu= id.PcdFlashFvOptionalSize=0D +FV =3D FvOptional=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvOsBootSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootBase|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvOsBootSize=0D +FV =3D FvOsBoot=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvUefiBootSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvUefiBootSize=0D +FV =3D FvUefiBoot=0D +=0D +gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|gBoardModuleTo= kenSpaceGuid.PcdFlashFvFirmwareBinariesSize=0D +gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|gBoardModuleToke= nSpaceGuid.PcdFlashFvFirmwareBinariesSize=0D +FV =3D FvFwBinaries=0D +=0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset|gSiPkgTokenSpaceGuid.PcdFla= shMicrocodeFvSize=0D +gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvBase|gSiPkgTokenSpaceGuid.PcdFlash= MicrocodeFvSize=0D +#Microcode=0D +FV =3D FvMicrocode=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset|gMinPlatformPkgTo= kenSpaceGuid.PcdFlashFvPostMemorySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvPostMemorySize=0D +FV =3D FvPostMemory=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspSSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspSSize=0D +# FSP_S Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_S.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspMSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspMSize=0D +# FSP_M Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_M.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset|gMinPlatformPkgTokenSpa= ceGuid.PcdFlashFvFspTSize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTBase|gMinPlatformPkgTokenSpace= Guid.PcdFlashFvFspTSize=0D +# FSP_T Section=0D +FILE =3D $(PLATFORM_FSP_BIN_PACKAGE)/Fsp_Rebased_T.fd=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset|gMinPlatformPkgToke= nSpaceGuid.PcdFlashFvSecuritySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityBase|gMinPlatformPkgTokenS= paceGuid.PcdFlashFvSecuritySize=0D +FV =3D FvSecurityPreMemory=0D +=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset|gMinPlatformPkgTok= enSpaceGuid.PcdFlashFvPreMemorySize=0D +gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryBase|gMinPlatformPkgToken= SpaceGuid.PcdFlashFvPreMemorySize=0D +FV =3D FvPreMemory=0D +=0D +##########################################################################= ######=0D +#=0D +# FV Section=0D +#=0D +# [FV] section is used to define what components or modules are placed wit= hin a flash=0D +# device file. This section also defines order the components and modules= are positioned=0D +# within the image. The [FV] section consists of define statements, set s= tatements and=0D +# module statements.=0D +#=0D +##########################################################################= ######=0D +[FV.FvMicrocode]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +=0D +INF RuleOverride =3D MICROCODE $(PLATFORM_SI_BIN_PACKAGE)/Microcode/Microc= odeUpdates.inf=0D +=0D +[FV.FvPreMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D FC8FE6B5-CD9B-411E-BD8F-31824D0CDE3D=0D +=0D +INF UefiCpuPkg/SecCore/SecCore.inf=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D +INF MdeModulePkg/Core/Pei/PeiMain.inf=0D +!endif=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePreMemoryInclude.fdf=0D +=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/ReportFv/ReportFvPei.inf=0D +INF IntelFsp2WrapperPkg/FspmWrapperPeim/FspmWrapperPeim.inf=0D +=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPreMem.in= f=0D +INF $(PLATFORM_BOARD_PACKAGE)/BiosInfo/BiosInfo.inf=0D +INF MdeModulePkg/Universal/ResetSystemPei/ResetSystemPei.inf=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPreM= em.inf=0D +# Provide gEfiPeiStallPpiGuid for FSP dispatch mode=0D +INF $(PLATFORM_PACKAGE)/Services/StallServicePei/StallServicePei.inf=0D +!endif=0D +=0D +[FV.FvPostMemoryUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 7C4DCFC6-AECA-4707-85B9-FD4B2EEA49E7=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CorePostMemoryInclude.fdf=0D +=0D +# Init Board Config PCD=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitPei/PlatformInitPostMem.i= nf=0D +INF IntelFsp2WrapperPkg/FspsWrapperPeim/FspsWrapperPeim.inf=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyPei/SiliconPolicyPeiPost= Mem.inf=0D +=0D +!endif=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable =3D=3D TRUE=0D +FILE FREEFORM =3D PCD(gIntelSiliconPkgTokenSpaceGuid.PcdIntelGraphicsVbtFi= leGuid) {=0D + SECTION RAW =3D $(PLATFORM_FSP_BIN_PACKAGE)/SampleCode/Vbt/Vbt.bin=0D + SECTION UI =3D "Vbt"=0D +}=0D +FILE FREEFORM =3D 7BB28B99-61BB-11D5-9A5D-0090273FC14D {=0D + SECTION RAW =3D MdeModulePkg/Logo/Logo.bmp=0D +}=0D +!endif # PcdPeiDisplayEnable=0D +INF MdeModulePkg/Bus/Pci/NvmExpressPei/NvmExpressPei.inf=0D +=0D +[FV.FvPostMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 9DFE49DB-8EF0-4D9C-B273-0036144DE917=0D +=0D +FILE FV_IMAGE =3D 244FAAF4-FAE1-4892-8B7D-7EF84CBFA709 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvPostMemoryUncompact=0D + }=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvSecurityPostMemory=0D + }=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQUI= RED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvSecurityLate=0D + }=0D +}=0D +=0D +[FV.FvUefiBootUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D A881D567-6CB0-4eee-8435-2E72D33E45B5=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreUefiBootInclude.fdf=0D +=0D +INF UefiCpuPkg/CpuDxe/CpuDxe.inf=0D +INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf=0D +=0D +INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf=0D +INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf=0D +INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf=0D +INF MdeModulePkg/Bus/Pci/NvmExpressDxe/NvmExpressDxe.inf=0D +INF MdeModulePkg/Universal/Console/GraphicsOutputDxe/GraphicsOutputDxe.in= f=0D +INF BoardModulePkg/BoardBdsHookDxe/BoardBdsHookDxe.inf=0D +=0D +#=0D +#UEFI Shell=0D +#=0D +# Note : gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.in= f/Shell.inf.=0D +# The GUID has to be changed according to the change you make to ov= erride MinUefiShell.inf/UefiShell.inf/Shell.inf FILE_GUID.=0D +#=0D +FILE APPLICATION =3D 7C04A583-9E3E-4F1C-AD65-E05268D0B4D1 {=0D +!if $(TARGET) =3D=3D DEBUG=0D + SECTION PE32 =3D $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/She= llPkg/Application/Shell/Shell/OUTPUT/Shell.efi=0D +!else=0D + SECTION PE32 =3D $(OUTPUT_DIRECTORY)/$(TARGET)_$(TOOL_CHAIN_TAG)/X64/She= llPkg/Application/Shell/Shell/OUTPUT/Shell.efi=0D +!endif=0D + SECTION UI =3D "EdkShell"=0D +}=0D +=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitDxe/PlatformInitDxe.inf= =0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D +INF IntelFsp2WrapperPkg/FspWrapperNotifyDxe/FspWrapperNotifyDxe.inf=0D +!endif=0D +INF $(PLATFORM_PACKAGE)/Test/TestPointStubDxe/TestPointStubDxe.inf=0D +=0D +FILE FV_IMAGE =3D C6CE361E-4554-41E5-AF27-C3FADBA6DA9C {=0D + SECTION FV_IMAGE =3D $(PLATFORM_FSP_BIN_PACKAGE)/FvLateSilicon.fv=0D +}=0D +=0D +[FV.FvUefiBoot]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 0496D33D-EA79-495C-B65D-ABF607184E3B=0D +=0D +FILE FV_IMAGE =3D 9E21FD93-9C72-4c15-8C4B-E77F1DB2D792 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvUefiBootUncompact=0D + }=0D + }=0D +=0D +[FV.FvOsBootUncompact]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D A0F04529-B715-44C6-BCA4-2DEBDD01EEEC=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreOsBootInclude.fdf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/SiliconPolicyDxe/SiliconPolicyDxe.in= f=0D +INF $(PLATFORM_PACKAGE)/PlatformInit/PlatformInitSmm/PlatformInitSmm.inf= =0D +INF $(PLATFORM_PACKAGE)/Flash/SpiFvbService/SpiFvbServiceSmm.inf=0D +=0D +INF UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.inf=0D +INF $(PLATFORM_PACKAGE)/Acpi/AcpiTables/AcpiPlatform.inf=0D +INF $(PLATFORM_PACKAGE)/Acpi/AcpiSmm/AcpiSmm.inf=0D +=0D +INF RuleOverride =3D DRIVER_ACPITABLE $(PLATFORM_PACKAGE)/Acpi/MinDsdt/Mi= nDsdt.inf=0D +INF $(PLATFORM_PACKAGE)/FspWrapper/SaveMemoryConfig/SaveMemoryConfig.inf= =0D +=0D +!endif=0D +=0D +[FV.FvLateSilicon]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 97F09B89-9E83-4DDC-A3D1-10C4AF539D1E=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Dxe/PchInitDxeTgl.= inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Dxe/SaInitD= xe.inf=0D +=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchSmiDispatcher/Smm/PchSm= iDispatcher.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/SmmControl/RuntimeDxe/SmmC= ontrol.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/IpBlock/Spi/Smm/SpiSmm.inf=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/Pch/PchInit/Smm/PchInitSmm.inf= =0D +=0D +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE=0D +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/SystemAgent/AcpiTab= les/SaSsdt/SaSsdt.inf=0D +INF RuleOverride =3D ACPITABLE $(PLATFORM_SI_PACKAGE)/IpBlock/Graphics/Ac= piTables/IgfxSsdt.inf=0D +!endif=0D +!endif #PcdBootToShellOnly=0D +=0D +$(SIPKG_DXE_SMM_BIN) $(PLATFORM_SI_PACKAGE)/SystemAgent/SaInit/Smm/SaLateI= nitSmm.inf=0D +=0D +[FV.FvOsBoot]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 13BF8810-75FD-4B1A-91E6-E16C4201F80A=0D +=0D +FILE FV_IMAGE =3D B9020753-84A8-4BB6-947C-CE7D41F5CE39 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvOsBootUncompact=0D + }=0D + }=0D +=0D +FILE FV_IMAGE =3D D4632741-510C-44E3-BE21-C3D6D7881485 {=0D + SECTION GUIDED EE4E5898-3914-4259-9D6E-DC7BD79403CF PROCESSING_REQU= IRED =3D TRUE {=0D + SECTION FV_IMAGE =3D FvLateSilicon=0D + }=0D + }=0D +=0D +[FV.FvSecurityPreMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16 #FV alignment and FV attributes setting.= =0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 9B7FA59D-71C6-4A36-906E-9725EA6ADD5B=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPreMemoryInclude.fdf= =0D +=0D +[FV.FvSecurityPostMemory]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16 #FV alignment and FV attributes setting.= =0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 4199E560-54AE-45E5-91A4-F7BC3804E14A=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityPostMemoryInclude.fdf= =0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D +INF $(CLIENT_COMMON_PACKAGE)/Universal/Tcg2PlatformPei/Tcg2PlatformPei.inf= =0D +!endif=0D +=0D +[FV.FvSecurityLate]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D F753FE9A-EEFD-485B-840B-E032D538102C=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/CoreSecurityLateInclude.fdf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly =3D=3D FALSE=0D +=0D +INF $(PLATFORM_PACKAGE)/Hsti/HstiIbvPlatformDxe/HstiIbvPlatformDxe.inf=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable =3D=3D TRUE=0D +INF $(PLATFORM_PACKAGE)/Tcg/Tcg2PlatformDxe/Tcg2PlatformDxe.inf=0D +!endif=0D +=0D +!endif=0D +INF IntelSiliconPkg/Feature/SmmAccess/SmmAccessDxe/SmmAccess.inf=0D +=0D +#=0D +# Do not use nested FV in PEI phase as current FMMT cannot handle it prope= rly when deleting modules.=0D +#=0D +#[FV.FvSecurity]=0D +#BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +#FvAlignment =3D 16=0D +#ERASE_POLARITY =3D 1=0D +#MEMORY_MAPPED =3D TRUE=0D +#STICKY_WRITE =3D TRUE=0D +#LOCK_CAP =3D TRUE=0D +#LOCK_STATUS =3D TRUE=0D +#WRITE_DISABLED_CAP =3D TRUE=0D +#WRITE_ENABLED_CAP =3D TRUE=0D +#WRITE_STATUS =3D TRUE=0D +#WRITE_LOCK_CAP =3D TRUE=0D +#WRITE_LOCK_STATUS =3D TRUE=0D +#READ_DISABLED_CAP =3D TRUE=0D +#READ_ENABLED_CAP =3D TRUE=0D +#READ_STATUS =3D TRUE=0D +#READ_LOCK_CAP =3D TRUE=0D +#READ_LOCK_STATUS =3D TRUE=0D +#FvNameGuid =3D 5A9A8B4E-149A-4CB2-BDC7-C8D62DE2C8CF=0D +=0D +#FILE FV_IMAGE =3D 757CC075-1428-423D-A73C-22639706C119 {=0D +# SECTION FV_IMAGE =3D FvSecurityPreMemory=0D +# }=0D +=0D +=0D +[FV.FvAdvanced]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D B23E7388-9953-45C7-9201-0473DDE5487A=0D +=0D +=0D +[FV.FvFwBinaries]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 8B98AB22-E354-42f0-88B9-049810F0FDAA=0D +=0D +=0D +=0D +=0D +=0D +[FV.FvOptional]=0D +BlockSize =3D $(FLASH_BLOCK_SIZE)=0D +FvAlignment =3D 16=0D +ERASE_POLARITY =3D 1=0D +MEMORY_MAPPED =3D TRUE=0D +STICKY_WRITE =3D TRUE=0D +LOCK_CAP =3D TRUE=0D +LOCK_STATUS =3D TRUE=0D +WRITE_DISABLED_CAP =3D TRUE=0D +WRITE_ENABLED_CAP =3D TRUE=0D +WRITE_STATUS =3D TRUE=0D +WRITE_LOCK_CAP =3D TRUE=0D +WRITE_LOCK_STATUS =3D TRUE=0D +READ_DISABLED_CAP =3D TRUE=0D +READ_ENABLED_CAP =3D TRUE=0D +READ_STATUS =3D TRUE=0D +READ_LOCK_CAP =3D TRUE=0D +READ_LOCK_STATUS =3D TRUE=0D +FvNameGuid =3D 9574B1CE-EE93-451E-B500-3E5F564244DE=0D +##########################################################################= ######=0D +#=0D +# Rules are use with the [FV] section's module INF type to define=0D +# how an FFS file is created for a given INF file. The following Rule are = the default=0D +# rules for the different module type. User can add the customized rules t= o define the=0D +# content of the FFS file.=0D +#=0D +##########################################################################= ######=0D +=0D +!include $(PLATFORM_PACKAGE)/Include/Fdf/RuleInclude.fdf=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPk= gBuildOption.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenB= oardPkgBuildOption.dsc new file mode 100644 index 0000000000..b72329846a --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgBuildO= ption.dsc @@ -0,0 +1,141 @@ +## @file=0D +# platform build option configuration file.=0D +#=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +[BuildOptions]=0D +# Define Build Options both for EDK and EDKII drivers.=0D +=0D +=0D + DEFINE DSC_S3_BUILD_OPTIONS =3D=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdAcpiEnable =3D=3D TRUE=0D + DEFINE DSC_ACPI_BUILD_OPTIONS =3D -DACPI_SUPPORT=3D1=0D +!else=0D + DEFINE DSC_ACPI_BUILD_OPTIONS =3D=0D +!endif=0D +=0D + DEFINE BIOS_GUARD_BUILD_OPTIONS =3D=0D +=0D + DEFINE OVERCLOCKING_BUILD_OPTION =3D=0D +=0D + DEFINE FSP_BINARY_BUILD_OPTIONS =3D=0D +=0D + DEFINE FSP_WRAPPER_BUILD_OPTIONS =3D -DFSP_WRAPPER_FLAG=0D +=0D + DEFINE SKIP_FSP_TEMPRAM_INIT_AND_EXIT_OPTIONS =3D=0D +=0D +!if gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable =3D=3D FALSE=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D -Od -GL-=0D +!else=0D + DEFINE OPTIMIZE_DISABLE_OPTIONS =3D=0D +!endif=0D +=0D + DEFINE UP_SERVER_SUPPORT_BUILD_OPTIONS =3D=0D +=0D +=0D + DEFINE TPM_BUILD_OPTION =3D=0D +=0D + DEFINE TPM2_BUILD_OPTION =3D=0D +=0D + DEFINE DSC_TBT_BUILD_OPTIONS =3D=0D +=0D + DEFINE DSC_DCTT_BUILD_OPTIONS =3D=0D +=0D + DEFINE EMB_BUILD_OPTIONS =3D=0D +=0D + DEFINE DSC_MEMORY_DOWN_BUILD_OPTIONS =3D -DMEM_DOWN_FLAG=3D1=0D +=0D + DEFINE DSC_KBCEMUL_BUILD_OPTIONS =3D=0D +=0D + DEFINE BOOT_GUARD_BUILD_OPTIONS =3D=0D +=0D + DEFINE SECURE_BOOT_BUILD_OPTIONS =3D=0D +=0D + DEFINE USBTYPEC_BUILD_OPTION =3D=0D +=0D + DEFINE CAPSULE_BUILD_OPTIONS =3D=0D +=0D + DEFINE PERFORMANCE_BUILD_OPTION =3D=0D +=0D + DEFINE DEBUGUSEUSB_BUILD_OPTION =3D=0D +=0D + DEFINE DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION =3D -DDISABLE_NEW_= DEPRECATED_INTERFACES=3D1=0D +=0D + DEFINE SINITBIN_BUILD_OPTION =3D=0D +=0D + DEFINE MINTREE_FLAG_BUILD_OPTION =3D -DMINTREE_FLAG=3D1=0D +=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_SIPKG_FEATURE_BUILD_OPTI= ONS) $(OVERCLOCKING_BUILD_OPTION) $(PERFORMANCE_BUILD_OPTION) $(EMB_BUILD_= OPTIONS) $(BIOS_GUARD_BUILD_OPTIONS) $(DSC_TBT_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(BOOT_GUARD_BUILD_OPTIONS) $(DSC_MEMORY_DOWN_BUILD_OPTIONS) $(DEBUGU= SEUSB_BUILD_OPTION) $(DSC_S3_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(FSP_BINARY_BUILD_OPTIONS) $(FSP_WRAPPER_BUILD_OPTIONS) $(SKIP_FSP_T= EMPRAM_INIT_AND_EXIT_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_KBCEMUL_BUILD_OPTIONS) $(CAPSULE_BUILD_OPTIONS) $(SECURE_BOOT_B= UILD_OPTIONS) $(DISABLE_NEW_DEPRECATED_INTERFACES_BUILD_OPTION)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(TPM2_BUILD_OPTION) $(TPM_BUILD_OPTION) $(DSC_DCTT_BUILD_OPTIONS)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS) $(DSC_ACPI_BUILD_OPTIONS) $(UP_SERVER_SUPPORT_BUILD_OPTIONS) $(USBTYP= EC_BUILD_OPTION) $(SINITBIN_BUILD_OPTION) $(MINTREE_FLAG_BUILD_OPTION)=0D +DEFINE DSC_PLTPKG_FEATURE_BUILD_OPTIONS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPT= IONS)=0D +=0D +[BuildOptions.Common.EDKII]=0D +=0D +#=0D +# For IA32 Global Build Flag=0D +#=0D + *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI=0D + *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_IA32_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +#=0D +# For IA32 Specific Build Flag=0D +#=0D +GCC: *_*_IA32_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_IA32_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_IA32_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015 -DASF_PEI= =0D +MSFT: *_*_IA32_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_IA32_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +=0D +#=0D +# For X64 Global Build Flag=0D +#=0D + *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) -D P= I_SPECIFICATION_VERSION=3D0x00010015=0D + *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D + *_*_X64_NASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +=0D +#=0D +# For X64 Specific Build Flag=0D +#=0D +GCC: *_*_X64_PP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_ASM_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_CC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS) -D PI_SPECIFICATION_VERSION=3D0x00010015=0D +MSFT: *_*_X64_VFRPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_APP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS) $(OP= TIMIZE_DISABLE_OPTIONS)=0D +MSFT: *_*_X64_ASLPP_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +MSFT: *_*_X64_ASLCC_FLAGS =3D $(DSC_PLTPKG_FEATURE_BUILD_OPTIONS)=0D +=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support page l= evel protection=0D +[BuildOptions.common.EDKII.DXE_SMM_DRIVER, BuildOptions.common.EDKII.SMM_C= ORE]=0D + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support Memory= Attribute table=0D +[BuildOptions.common.EDKII.DXE_RUNTIME_DRIVER]=0D + MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D +# Force PE/COFF sections to be aligned at 4KB boundaries to support NX pro= tection=0D +[BuildOptions.common.EDKII.DXE_DRIVER, BuildOptions.common.EDKII.DXE_CORE,= BuildOptions.common.EDKII.UEFI_DRIVER, BuildOptions.common.EDKII.UEFI_APPL= ICATION]=0D + #MSFT:*_*_*_DLINK_FLAGS =3D /ALIGN:4096=0D + #GCC:*_*_*_DLINK_FLAGS =3D -z common-page-size=3D0x1000=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPk= gPcd.dsc b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgP= cd.dsc new file mode 100644 index 0000000000..a048efcc18 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.dsc @@ -0,0 +1,392 @@ +## @file=0D +# PCD configuration build description file for the TigerlakeURvp board.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +##########################################################################= ######=0D +#=0D +# Pcd Section - list of all PCD Entries used by this board.=0D +#=0D +##########################################################################= ######=0D +=0D +[PcdsFixedAtBuild.common]=0D + ######################################=0D + # Key Boot Stage and FSP configuration=0D + ######################################=0D + #=0D + # Please select the Boot Stage here.=0D + # Stage 1 - enable debug (system deadloop after debug init)=0D + # Stage 2 - mem init (system deadloop after mem init)=0D + # Stage 3 - boot to shell only=0D + # Stage 4 - boot to OS=0D + # Stage 5 - boot to OS with security boot enabled=0D + # Stage 6 - boot with advanced features enabled=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootStage|4=0D +=0D + #=0D + # 0: FSP Wrapper is running in Dispatch mode.=0D + # 1: FSP Wrapper is running in API mode.=0D + # Note: Dispatch mode is currently NOT supported for this board.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection|0=0D +=0D + #=0D + # FALSE: The board is not a FSP wrapper (FSP binary not used)=0D + # TRUE: The board is a FSP wrapper (FSP binary is used)=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdFspWrapperBootMode|TRUE=0D +=0D + #=0D + # FSP Base address PCD will be updated in FDF basing on flash map.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFsptBaseAddress|0=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmBaseAddress|0=0D +=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF00000=0D + gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize|0x00080000=0D + gSiPkgTokenSpaceGuid.PcdTemporaryRamBase|0xFEF80000=0D + gSiPkgTokenSpaceGuid.PcdTemporaryRamSize|0x00040000=0D + gSiPkgTokenSpaceGuid.PcdTsegSize|0x1000000=0D +=0D + #=0D + # PCD declared for TigerlakeSiliconPkg Fru=0D + #=0D + gSiPkgTokenSpaceGuid.PcdBiosGuardEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdCpuPcieEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdEmbeddedEnable|0x0=0D + gSiPkgTokenSpaceGuid.PcdThcEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdMrcTraceMessageSupported|TRUE=0D +=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D + # Build switches=0D + gSiPkgTokenSpaceGuid.PcdOptimizeCompilerEnable|TRUE=0D +=0D + # CPU=0D + gSiPkgTokenSpaceGuid.PcdSourceDebugEnable|FALSE=0D +=0D + # SA=0D + gSiPkgTokenSpaceGuid.PcdIgdEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPegEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSaDmiEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdVtdEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPeiDisplayEnable|TRUE=0D +=0D + # ME=0D + gSiPkgTokenSpaceGuid.PcdAtaEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPttEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdJhiEnable|TRUE=0D +=0D + # Others=0D + gSiPkgTokenSpaceGuid.PcdAcpiEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdBdatEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdCpuPowerOnConfigEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdIntegratedTouchEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdOcWdtEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdOverclockEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdPpmEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdS3Enable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSiCatalogDebugEnable|FALSE=0D + gSiPkgTokenSpaceGuid.PcdSmbiosEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdSmmVariableEnable|TRUE=0D + gSiPkgTokenSpaceGuid.PcdFspWrapperEnable|TRUE=0D +=0D + #=0D + # When sharing stack with boot loader, FSP only needs a small temp ram f= or heap=0D + #=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0x00020000=0D +!else=0D + #=0D + # FSP Dispatch mode will not establish separate Stack or Heap.=0D + #=0D + gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize|0=0D +!endif=0D +=0D + #=0D + # Boot loader stack size has to be large enough for FSP execution=0D + #=0D + gSiPkgTokenSpaceGuid.PcdPeiTemporaryRamStackSize|0x30000=0D +=0D + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0xC0000000=0D +#!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength|0x10000000=0D +#!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreMaxPeiStackSize|0x40000=0D +[PcdsFeatureFlag.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdPeiCoreImageLoaderSearchTeSectionFirst= |FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmEnableBspElection|FALSE=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmProfileEnable|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdInstallAcpiSdtProtocol|TRUE=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdSerialTerminalEnable|TRUE=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 2=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterDebugInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 3=0D + gMinPlatformPkgTokenSpaceGuid.PcdStopAfterMemInit|FALSE=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|TRUE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 4=0D + gMinPlatformPkgTokenSpaceGuid.PcdBootToShellOnly|FALSE=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 5=0D + gMinPlatformPkgTokenSpaceGuid.PcdUefiSecureBootEnable|TRUE=0D + gMinPlatformPkgTokenSpaceGuid.PcdTpm2Enable|TRUE=0D +!endif=0D +=0D +!if $(TARGET) =3D=3D DEBUG=0D + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|TRUE=0D +!else=0D + gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable|FALSE=0D +!endif=0D +=0D + ######################################=0D + # Board Configuration=0D + ######################################=0D + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable|TRUE=0D +=0D +[PcdsFixedAtBuild.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D +!if $(TARGET) =3D=3D RELEASE=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x0=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x3=0D +!else=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPropertyMask|0x2F=0D + gEfiMdePkgTokenSpaceGuid.PcdReportStatusCodePropertyMask|0x07=0D +!endif=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdePkgTokenSpaceGuid.PcdPerformanceLibraryPropertyMask|0x1=0D +!endif=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseMemory|FALSE=0D +!if $(TARGET) =3D=3D RELEASE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|FALSE=0D +!else=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdStatusCodeUseSerial|TRUE=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAriSupport|FALSE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserFieldTextColor|0x01=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdBrowserSubtitleTextColor|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdHwErrStorageSize|0x00000800=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdLoadModuleAtFixAddressEnable|$(TOP_MEM= ORY_ADDRESS)=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxHardwareErrorVariableSize|0x400=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxPeiPerformanceLogEntries|140=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdMaxVariableSize|0x10000=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdReclaimVariableSpaceAtEndOfDxe|TRUE=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdSmiHandlerProfileEnable =3D=3D TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmiHandlerProfilePropertyMask|0x1=0D +!endif=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSrIovSupport|FALSE=0D +!if $(TARGET) =3D=3D DEBUG=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSerialUseHardwareFlowControl|FALSE=0D +!endif=0D +=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoBarEnableMask|0x80=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBarRegisterOffset|0x00=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciBusNumber|0x0=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciDeviceNumber|0x1F=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciEnableRegisterOffset|0x44=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPciFunctionNumber|0x2=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddress|0x1800=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiIoPortBaseAddressMask|0xFFFC=0D + gPcAtChipsetPkgTokenSpaceGuid.PcdAcpiPm1TmrOffset|0x08=0D +=0D + # Specifies timeout value in microseconds for the BSP to detect all APs = for the first time.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApInitTimeOutInMicroSeconds|50000=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuNumberOfReservedVariableMtrrs|0x0=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmApSyncTimeout|10000=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmStackSize|0x20000=0D +=0D + #=0D + # In non-FSP build (EDK2 build) or FSP API mode below PCD are FixedAtBui= ld=0D + # (They will be DynamicEx in FSP Dispatch mode)=0D + #=0D +=0D + ## Specifies the size of the microcode Region.=0D + # @Prompt Microcode Region size.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMicrocodePatchRegionSize|0=0D +=0D + ## Specifies the AP wait loop state during POST phase.=0D + # The value is defined as below.=0D + # 1: Place AP in the Hlt-Loop state.=0D + # 2: Place AP in the Mwait-Loop state.=0D + # 3: Place AP in the Run-Loop state.=0D + # @Prompt The AP wait loop state.=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApLoopMode|2=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuSocketCount|1=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuCoreCount|8=0D + gMinPlatformPkgTokenSpaceGuid.PcdMaxCpuThreadCount|2=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemBase|0xA0000000=0D + gMinPlatformPkgTokenSpaceGuid.PcdPciReservedMemLimit|0xDFFFFFFF=0D + #=0D + # The PCDs are used to control the Windows SMM Security Mitigations Tabl= e - Protection Flags=0D + #=0D + # BIT0: If set, expresses that for all synchronous SMM entries,SMM will = validate that input and output buffers lie entirely within the expected fix= ed memory regions.=0D + # BIT1: If set, expresses that for all synchronous SMM entries, SMM will= validate that input and output pointers embedded within the fixed communic= ation buffer only refer to address ranges \=0D + # that lie entirely within the expected fixed memory regions.=0D + # BIT2: Firmware setting this bit is an indication that it will not allo= w reconfiguration of system resources via non-architectural mechanisms.=0D + # BIT3-31: Reserved=0D + #=0D + gMinPlatformPkgTokenSpaceGuid.PcdWsmtProtectionFlags|0x07=0D +=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiReclaimMemorySize|0xCC=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiAcpiNvsMemorySize|0xA2=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiReservedMemorySize|0x3100=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtDataMemorySize|0x2A=0D + gMinPlatformPkgTokenSpaceGuid.PcdPlatformEfiRtCodeMemorySize|0xC4=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 1=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x00= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 2=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 3=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 4=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x07= , 0x03, 0x05, 0x1F, 0x00, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage =3D=3D 5=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdBootStage >=3D 6=0D + gMinPlatformPkgTokenSpaceGuid.PcdTestPointIbvPlatformFeature|{0x03, 0x0F= , 0x07, 0x1F, 0x1F, 0x0F, 0x0F, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0= x00, 0x00}=0D +!endif=0D +=0D +[PcdsFixedAtBuild.IA32]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVpdBaseAddress|0x0=0D + gIntelFsp2PkgTokenSpaceGuid.PcdGlobalDataPointerAddress|0xFED00148=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdPeiMinMemSize|0x3800000=0D +=0D + ######################################=0D + # Platform Configuration=0D + ######################################=0D + gMinPlatformPkgTokenSpaceGuid.PcdPeiPhaseStackTop|0xA0000=0D +=0D +[PcdsFixedAtBuild.X64]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D +=0D + # Default platform supported RFC 4646 languages: (American) English=0D + gEfiMdePkgTokenSpaceGuid.PcdUefiVariableDefaultPlatformLangCodes|"en-US"= =0D +=0D +[PcdsPatchableInModule.common]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdSmbiosVersion|0x0301=0D + gEfiMdePkgTokenSpaceGuid.PcdDebugPrintErrorLevel|0x80000046=0D +=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D +!if $(TARGET) =3D=3D DEBUG=0D + gSiPkgTokenSpaceGuid.PcdSerialIoUartDebugEnable|1=0D +!endif=0D +=0D +[PcdsDynamicDefault]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdAtaSmartEnable|TRUE=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConInConnectOnDemand|FALSE=0D + ######################################=0D + # Silicon Configuration=0D + ######################################=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 1=0D + gSiPkgTokenSpaceGuid.PcdPciExpressRegionLength|gMinPlatformPkgTokenSpace= Guid.PcdPciExpressRegionLength=0D +!endif=0D +=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutColumn|0x0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdConOutRow|0x0=0D + #gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0=0D +=0D + #=0D + # Set video to native resolution as Windows 8 WHCK requirement.=0D + #=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoHorizontalResolution|0=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdVideoVerticalResolution|0=0D +=0D + gEfiSecurityPkgTokenSpaceGuid.PcdTpm2CurrentIrqNum|0x00=0D +=0D + #=0D + # FSP Base address PCD will be updated in FDF basing on flash map.=0D + #=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsBaseAddress|0=0D +=0D + # Platform will pre-allocate UPD buffer and pass it to FspWrapper=0D + # Those dummy address will be patched before FspWrapper executing=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspmUpdDataAddress|0x0=0D + gIntelFsp2WrapperTokenSpaceGuid.PcdFspsUpdDataAddress|0x0=0D +=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuApTargetCstate|0=0D + gUefiCpuPkgTokenSpaceGuid.PcdCpuMaxLogicalProcessorNumber|16=0D +=0D +[PcdsDynamicHii.X64.DEFAULT]=0D + ######################################=0D + # Edk2 Configuration=0D + ######################################=0D + gEfiMdePkgTokenSpaceGuid.PcdHardwareErrorRecordLevel|L"HwErrRecSupport"|= gEfiGlobalVariableGuid|0x0|1 # Variable: L"HwErrRecSupport"=0D +!if gMinPlatformPkgTokenSpaceGuid.PcdPerformanceEnable =3D=3D TRUE=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|1 # Variable: L"Timeout"=0D +!else=0D + gEfiMdePkgTokenSpaceGuid.PcdPlatformBootTimeOut|L"Timeout"|gEfiGlobalVar= iableGuid|0x0|5 # Variable: L"Timeout"=0D +!endif=0D +=0D +[PcdsDynamicExDefault]=0D + gEfiMdeModulePkgTokenSpaceGuid.PcdS3BootScriptTablePrivateDataPtr|0x0=0D +=0D +!if gIntelFsp2WrapperTokenSpaceGuid.PcdFspModeSelection =3D=3D 0=0D + #=0D + # Include FSP PCD settings.=0D + #=0D + !include $(PLATFORM_FSP_BIN_PACKAGE)/TigerLakeFspPcds.dsc=0D +!endif=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_confi= g.cfg b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg new file mode 100644 index 0000000000..f8047701f8 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/build_config.cfg @@ -0,0 +1,34 @@ +# @ build_config.cfg=0D +# This is the WhiskeylakeURvp board specific build settings=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +=0D +=0D +[CONFIG]=0D +WORKSPACE_PLATFORM_BIN =3D=0D +EDK_SETUP_OPTION =3D=0D +openssl_path =3D=0D +PLATFORM_BOARD_PACKAGE =3D TigerlakeOpenBoardPkg=0D +PROJECT =3D TigerlakeOpenBoardPkg/TigerlakeURvp=0D +BOARD =3D TigerlakeURvp=0D +FLASH_MAP_FDF =3D TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMap= Include.fdf=0D +PROJECT_DSC =3D TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkg.dsc=0D +BOARD_PKG_PCD_DSC =3D TigerlakeOpenBoardPkg/TigerlakeURvp/OpenBoardPkgPcd.= dsc=0D +PrepRELEASE =3D DEBUG=0D +SILENT_MODE =3D FALSE=0D +EXT_CONFIG_CLEAR =3D=0D +CapsuleBuild =3D FALSE=0D +EXT_BUILD_FLAGS =3D=0D +CAPSULE_BUILD =3D 0=0D +TARGET =3D DEBUG=0D +TARGET_SHORT =3D D=0D +PERFORMANCE_BUILD =3D FALSE=0D +FSP_WRAPPER_BUILD =3D TRUE=0D +FSP_BIN_PKG =3D TigerLakeFspBinPkg/Client=0D +FSP_PKG_NAME =3D TigerlakeSiliconPkg=0D +FSP_BINARY_BUILD =3D FALSE=0D +FSP_TEST_RELEASE =3D FALSE=0D +SECURE_BOOT_ENABLE =3D FALSE=0D +BIOS_INFO_GUID =3D 4A4CA1C6-871C-45BB-8801-6910A7AA5807=0D --=20 2.24.0.windows.2