From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) by mx.groups.io with SMTP id smtpd.web09.29015.1612745589331868608 for ; Sun, 07 Feb 2021 16:53:09 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=E67t0AJH; spf=pass (domain: nuviainc.com, ip: 209.85.216.42, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f42.google.com with SMTP id lw17so8541391pjb.0 for ; Sun, 07 Feb 2021 16:53:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D2gEjFelyPSjnUpcU9RoYvNbAEFfhxFoj8ehlO3TW7A=; b=E67t0AJHAccSgsa83xcp6y4sfhtcx1F1uvhkHtWrVjOBPxHl/tdkyleT+aF6GnEdRL SthBAxbmHiiJTn0qzBMV6ordBWnYnTwfdr98s/CWEWlabTKVCL2ZREvYZt5TQ8FZZ7Nf czJqY6mLddSgsDGAp1gDVyQJsLG5elAdTlatOsMsx3MJ+3AgMwPCN2rALKAIhT7rYmko LArkq53VFaxOW/NLOlFENKYioRMH/W3B2NN1wPE3u95l5lGC5JISw9MB+M/urZlO3FbY +DUGPq/pf0YawDZ7/73yMqFjU/Y5JKi+6rU6+M8cu45NpCuDS7LNlLim9IJ06T94RVAN 4wAA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D2gEjFelyPSjnUpcU9RoYvNbAEFfhxFoj8ehlO3TW7A=; b=m0p2L0uWp8XT6NfgpRcKj+YerTS40DgMYxnJVSfO6HnNUEEY+ZX55SxyeUkAEIh13s JXWezlyn8DwxGEuwK9h+LRKrzKr2nNjJY6bVzN6uuc7s+7pl8XdY7y7Pp9pdQk1o1PHg tWoPOQZXNBSrV0UF8EBdaeMBX0HEEbYVXpIR9afWqNS6p/LYSVMiPcIHj2rFKGulqsLJ S5cTG6TtX00MYhcm+FJ7RjvMcq6ZztrTAHWcrguI55wuIUwwJyTyPJGze+EmicpIsnTO 9YhCBStlKzLL2b4mW/H4aids3zk09IQe0OQP36Te6XV6MagG94MTzOCv1ISsQSck6iPm rUBQ== X-Gm-Message-State: AOAM533OiLtP81uv5IMZ71VpQ3+DuT1B3QfRNLcCuazva1ZE5F1QAGnQ SB57NUK8Mlv0YA9SpWxRaib4K0KlRxkV1GqhuRYwKI7vdYsTY+e6aV8J7vByYHdVy6L46uHuJRZ 6ZM3d+fwx0UKnwfCh+gDFCg4rIumxh7/7SUmNAys73gjEVXcibqbEcHyy9+GjipvrZKCwIQ== X-Google-Smtp-Source: ABdhPJwGvvdJ771G8cSjta9cDjMpStRODoNqA6j5JAcfQG3NIlwJPYepWtOKkdEcOJhSCyID44Nf2A== X-Received: by 2002:a17:90a:7525:: with SMTP id q34mr15134594pjk.88.1612745588624; Sun, 07 Feb 2021 16:53:08 -0800 (PST) Return-Path: Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id c6sm11095883pjd.21.2021.02.07.16.53.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 16:53:07 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [PATCH v8 03/21] ArmPkg: Add register encoding definition for MMFR2 Date: Sun, 7 Feb 2021 17:52:36 -0700 Message-Id: <20210208005254.12176-4-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208005254.12176-1-rebecca@nuviainc.com> References: <20210208005254.12176-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add register encoding definition for Memory Model Feature Register 2. We need to define it here because we build for ARMv8.0, which doesn't have it. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Include/Chipset/AArch64.h | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 0ade5cce91c3..7c2b592f92ee 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -112,6 +112,10 @@ #define ARM_VECTOR_LOW_A32_FIQ 0x700 #define ARM_VECTOR_LOW_A32_SERR 0x780 +// The ID_AA64MMFR2_EL1 register was added in ARMv8.2. Since we +// build for ARMv8.0, we need to define the register here. +#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2 + #define VECTOR_BASE(tbl) \ .section .text.##tbl##,"ax"; \ .align 11; \ -- 2.26.2