From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f42.google.com (mail-pj1-f42.google.com [209.85.216.42]) by mx.groups.io with SMTP id smtpd.web10.29068.1612745597234519814 for ; Sun, 07 Feb 2021 16:53:17 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@nuviainc-com.20150623.gappssmtp.com header.s=20150623 header.b=AgBPkmJU; spf=pass (domain: nuviainc.com, ip: 209.85.216.42, mailfrom: rebecca@nuviainc.com) Received: by mail-pj1-f42.google.com with SMTP id nm1so7293277pjb.3 for ; Sun, 07 Feb 2021 16:53:17 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=nuviainc-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n37rP8qCbZVfdGqsOgFEYJESOKjyV2IL/DaylKOCiHg=; b=AgBPkmJUZWanZ8r2p7mCu7msqkvstAhsknCKAVnOz9ROzRFT8r5h4CRuDJRG+BiIZE Gbo2XGzkeB7cWGezXdi+b1XjakFyv8KisrjNs+7VltGcd7ux4PdZE1+dvWsMK7OxIbHT Gi09Fy6Jb6RrhBt6IPBR2WU70dqZbyDaeUUEecVuo26olxl7+bvUMX4qrJCURe877+fL A0XRxkeGzvVShOtIcFwJi6O1lRHsLQPzMwxnxt+ZwThg9gX+Jc7hLcMQJjFeYHxXy3lQ T/8YI7KzH62wUU1twTYZ1kzoUlegSiP4Xkr5JnKAZ/9tPq2zit8Ug8zeKc4RPNZd0Fsk p3Fg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n37rP8qCbZVfdGqsOgFEYJESOKjyV2IL/DaylKOCiHg=; b=D+Qauf2j0V2Bkajr6HGyWHVldienSTrgBB1OUTqot3KeGVQ8GGgbXwFA3p9xT6bixc 0//9AvfCe0gCQwzTn+lDXgmJuqKnM9YLs0Me0z8IHftxHau/YBuTcEDUdbI5+fGkpoLT 10IT8fUKZhLVaD8/sLWKvE9K2Dn5G2FWioFepsoLmpKvqtEyjeQNzbyIFeX0qvwhrnaV gKyWY/+LkKhvigoX6c5LiG6UMeck0ZE0F7qtfubuz5vTQ4p1x1yw0sKojQVgjpOwNHrA BixGrOW9UH0zzi+H+VNT9PtgDIHeAyfus8F4Rutw+gwLp9iWcIVDIRjY82bNKccFR/cY 8slQ== X-Gm-Message-State: AOAM531Gfldz2YqX9f9mejoXj8dArvs853374qWx+QTqphpxzkUC8Ggw dVM17hqr+1Qt+/O0MckmLZ4OKDtqU8e2p/fO/DHz7oC1WkkR/dYvGoRE+CCliZGjWTySTk0Pcvw ZrlNxKqjEQ2NhTcEK+rDTz1Mtp7Vgxvc/I6/clsZj4ydKCSZPB+gmyqgdGcfjavaqwg7Bog== X-Google-Smtp-Source: ABdhPJyORrv9r+IVoC4j00np/UilD7iWWbXo9wl17U83xkAitCjTlbNgvuui+URDrO9dx6eaLi9gkQ== X-Received: by 2002:a17:902:654d:b029:e1:7103:c5af with SMTP id d13-20020a170902654db02900e17103c5afmr13626480pln.47.1612745596370; Sun, 07 Feb 2021 16:53:16 -0800 (PST) Return-Path: Received: from cube.int.bluestop.org (c-174-52-16-57.hsd1.ut.comcast.net. [174.52.16.57]) by smtp.gmail.com with ESMTPSA id c6sm11095883pjd.21.2021.02.07.16.53.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 07 Feb 2021 16:53:15 -0800 (PST) From: "Rebecca Cran" To: devel@edk2.groups.io Cc: Rebecca Cran , leif@nuviainc.com, Ard Biesheuvel , nd@arm.com, Sami Mujawar , Liming Gao , Michael D Kinney , Zhiguang Liu , Samer El-Haj-Mahmoud , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Sami Mujawar Subject: [PATCH v8 07/21] ArmPkg: Update ArmLibPrivate.h with cache register definitions Date: Sun, 7 Feb 2021 17:52:40 -0700 Message-Id: <20210208005254.12176-8-rebecca@nuviainc.com> X-Mailer: git-send-email 2.26.2 In-Reply-To: <20210208005254.12176-1-rebecca@nuviainc.com> References: <20210208005254.12176-1-rebecca@nuviainc.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Update the cache definitions in ArmLibPrivate.h based on current ARMv8 documentation. Signed-off-by: Rebecca Cran Reviewed-by: Leif Lindholm Reviewed-by: Sami Mujawar --- ArmPkg/Library/ArmLib/ArmLibPrivate.h | 97 ++++++++++++++++++++ 1 file changed, 97 insertions(+) diff --git a/ArmPkg/Library/ArmLib/ArmLibPrivate.h b/ArmPkg/Library/ArmLib/ArmLibPrivate.h index 8959bdd9d73c..25560a01e9cf 100644 --- a/ArmPkg/Library/ArmLib/ArmLibPrivate.h +++ b/ArmPkg/Library/ArmLib/ArmLibPrivate.h @@ -1,5 +1,7 @@ /** @file + ArmLibPrivate.h + Copyright (c) 2020, NUVIA Inc. All rights reserved.
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -50,6 +52,101 @@ #define CACHE_ARCHITECTURE_UNIFIED (0UL) #define CACHE_ARCHITECTURE_SEPARATE (1UL) + +/// Defines the structure of the CSSELR (Cache Size Selection) register +typedef union { + struct { + UINT32 InD :1; ///< Instruction not Data bit + UINT32 Level :3; ///< Cache level (zero based) + UINT32 TnD :1; ///< Allocation not Data bit + UINT32 Reserved :27; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CSSELR_DATA; + +/// The cache type values for the InD field of the CSSELR register +typedef enum +{ + /// Select the data or unified cache + CsselrCacheTypeDataOrUnified = 0, + /// Select the instruction cache + CsselrCacheTypeInstruction, + CsselrCacheTypeMax +} CSSELR_CACHE_TYPE; + +/// Defines the structure of the CCSIDR (Current Cache Size ID) register +typedef union { + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :10; ///< Associativity - 1 + UINT64 NumSets :15; ///< Number of sets in the cache -1 + UINT64 Unknown :4; ///< Reserved, UNKNOWN + UINT64 Reserved :32; ///< Reserved, RES0 + } BitsNonCcidx; ///< Bitfield definition of the register when FEAT_CCIDX is not supported. + struct { + UINT64 LineSize :3; ///< Line size (Log2(Num bytes in cache) - 4) + UINT64 Associativity :21; ///< Associativity - 1 + UINT64 Reserved1 :8; ///< Reserved, RES0 + UINT64 NumSets :24; ///< Number of sets in the cache -1 + UINT64 Reserved2 :8; ///< Reserved, RES0 + } BitsCcidxAA64; ///< Bitfield definition of the register when FEAT_IDX is supported. + struct { + UINT64 LineSize : 3; + UINT64 Associativity : 21; + UINT64 Reserved : 8; + UINT64 Unallocated : 32; + } BitsCcidxAA32; + UINT64 Data; ///< The entire 64-bit value +} CCSIDR_DATA; + +/// Defines the structure of the AARCH32 CCSIDR2 register. +typedef union { + struct { + UINT32 NumSets :24; ///< Number of sets in the cache - 1 + UINT32 Reserved :8; ///< Reserved, RES0 + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CCSIDR2_DATA; + +/** Defines the structure of the CLIDR (Cache Level ID) register. + * + * The lower 32 bits are the same for both AARCH32 and AARCH64 + * so we can use the same structure for both. +**/ +typedef union { + struct { + UINT32 Ctype1 : 3; ///< Level 1 cache type + UINT32 Ctype2 : 3; ///< Level 2 cache type + UINT32 Ctype3 : 3; ///< Level 3 cache type + UINT32 Ctype4 : 3; ///< Level 4 cache type + UINT32 Ctype5 : 3; ///< Level 5 cache type + UINT32 Ctype6 : 3; ///< Level 6 cache type + UINT32 Ctype7 : 3; ///< Level 7 cache type + UINT32 LoUIS : 3; ///< Level of Unification Inner Shareable + UINT32 LoC : 3; ///< Level of Coherency + UINT32 LoUU : 3; ///< Level of Unification Uniprocessor + UINT32 Icb : 3; ///< Inner Cache Boundary + } Bits; ///< Bitfield definition of the register + UINT32 Data; ///< The entire 32-bit value +} CLIDR_DATA; + +/// The cache types reported in the CLIDR register. +typedef enum { + /// No cache is present + ClidrCacheTypeNone = 0, + /// There is only an instruction cache + ClidrCacheTypeInstructionOnly, + /// There is only a data cache + ClidrCacheTypeDataOnly, + /// There are separate data and instruction caches + ClidrCacheTypeSeparate, + /// There is a unified cache + ClidrCacheTypeUnified, + ClidrCacheTypeMax +} CLIDR_CACHE_TYPE; + +#define CLIDR_GET_CACHE_TYPE(x, level) ((x >> (3 * (level))) & 0b111) + VOID CPSRMaskInsert ( IN UINT32 Mask, -- 2.26.2