From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga14.intel.com (mga14.intel.com [192.55.52.115]) by mx.groups.io with SMTP id smtpd.web11.1063.1612929623254110077 for ; Tue, 09 Feb 2021 20:00:23 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 192.55.52.115, mailfrom: heng.luo@intel.com) IronPort-SDR: piRT1ydYIiGhu2X6HoQhHs6fQT+Jktt20ahjGrO9ItJe6AWNPIgTnGrDyvEO8GV8xi9sxAUegh 2cM7KtMSfXcg== X-IronPort-AV: E=McAfee;i="6000,8403,9890"; a="181233698" X-IronPort-AV: E=Sophos;i="5.81,167,1610438400"; d="scan'208";a="181233698" Received: from orsmga008.jf.intel.com ([10.7.209.65]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 09 Feb 2021 20:00:22 -0800 IronPort-SDR: 0IEi35olx61TC3vKJfGsgkxiOaxhs+qdNsqaHCNQmC1kDXrGke1cK1v3VZFui90Afs8buVVCAU 1+t+kWix82QA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,167,1610438400"; d="scan'208";a="396530714" Received: from hengluo-dev.ccr.corp.intel.com ([10.239.153.154]) by orsmga008.jf.intel.com with ESMTP; 09 Feb 2021 20:00:20 -0800 From: "Heng Luo" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone Subject: [Patch V3 1/8] TigerlakeOpenBoardPkg: Add package and headers Date: Wed, 10 Feb 2021 12:00:05 +0800 Message-Id: <20210210040012.4564-1-heng.luo@intel.com> X-Mailer: git-send-email 2.24.0.windows.2 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3D3175 Create the TigerlakeOpenBoardPkg to provide board support code. The package may support Tigerlake boards. The package serves as a board support package in the EDK II Minimum Platform design. Silicon support for this package is provided in TigerLakeFspBinPkg in the FSP repository and TigerlakeSiliconPkg in the edk2-platforms repository. Cc: Sai Chaganty Cc: Nate DeSimone Signed-off-by: Heng Luo --- Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h | 61 += ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h | 17 += ++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h | 49 += ++++++++++++++++++++++++++++++++++++++++++++++++ Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec | 153 += +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++= ++ 4 files changed, 280 insertions(+) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConf= ig.h b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h new file mode 100644 index 0000000000..148abcce74 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardConfig.h @@ -0,0 +1,61 @@ +/** @file=0D + Header file for Platform Boards Configurations.=0D +=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PLATFORM_BOARD_CONFIG_H=0D +#define _PLATFORM_BOARD_CONFIG_H=0D +=0D +#include =0D +#include =0D +=0D +=0D +#pragma pack(1)=0D +=0D +typedef struct {=0D + UINT8 ClkReqNumber : 4;=0D + UINT8 ClkReqSupported : 1;=0D + UINT8 DeviceResetPadActiveHigh : 1;=0D + UINT32 DeviceResetPad;=0D +} ROOT_PORT_CLK_INFO;=0D +=0D +typedef struct {=0D + UINT8 Section;=0D + UINT8 Pin;=0D +} EXPANDER_GPIO_CONFIG;=0D +=0D +typedef struct {=0D + UINT8 Type;=0D + UINT8 Reserved[3]; // alignment for COMMON_GPIO_CONFIG=0D + union {=0D + UINT32 Pin;=0D + EXPANDER_GPIO_CONFIG Expander;=0D + } u;=0D +} BOARD_GPIO_CONFIG;=0D +=0D +// Do not change the encoding. It must correspond with PCH_PCIE_CLOCK_USAG= E from PCH RC.=0D +#define NOT_USED 0xFF=0D +#define FREE_RUNNING 0x80=0D +#define LAN_CLOCK 0x70=0D +#define PCIE_PEG 0x40=0D +#define PCIE_PCH 0x00=0D +=0D +typedef struct {=0D + UINT32 ClockUsage;=0D + UINT32 ClkReqSupported;=0D +} PCIE_CLOCK_CONFIG;=0D +=0D +typedef union {=0D + UINT64 Blob;=0D + BOARD_GPIO_CONFIG BoardGpioConfig;=0D + ROOT_PORT_CLK_INFO Info;=0D + PCIE_CLOCK_CONFIG PcieClock;=0D +} PCD64_BLOB;=0D +=0D +#pragma pack()=0D +=0D +#endif // _PLATFORM_BOARD_CONFIG_H=0D +=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h= b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h new file mode 100644 index 0000000000..2e1ee9eca4 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PlatformBoardId.h @@ -0,0 +1,17 @@ +/** @file=0D + Defines Platform BoardIds=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _PLATFORM_BOARD_ID_H_=0D +#define _PLATFORM_BOARD_ID_H_=0D +=0D +// TigerLake Sku IDs=0D +#define SkuIdTglU 0x1=0D +=0D +// TigerLake Board Id 0x01=0D +#define BoardIdTglUDdr4 0x01=0D +=0D +#endif // _PLATFORM_BOARD_ID_H_=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro= .h b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h new file mode 100644 index 0000000000..0848efe5b6 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Include/PolicyUpdateMacro.h @@ -0,0 +1,49 @@ +=0D +/** @file=0D + Macros for platform to update different types of policy.=0D +=0D + Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D + SPDX-License-Identifier: BSD-2-Clause-Patent=0D +**/=0D +=0D +#ifndef _POLICY_UPDATE_MACRO_H_=0D +#define _POLICY_UPDATE_MACRO_H_=0D +=0D +#ifdef UPDATE_POLICY=0D +#undef UPDATE_POLICY=0D +#endif=0D +=0D +#ifdef COPY_POLICY=0D +#undef COPY_POLICY=0D +#endif=0D +=0D +#ifdef GET_POLICY=0D +#undef GET_POLICY=0D +#endif=0D +=0D +#ifdef AND_POLICY=0D +#undef AND_POLICY=0D +#endif=0D +=0D +#ifdef OR_POLICY=0D +#undef OR_POLICY=0D +#endif=0D +=0D +#if FixedPcdGetBool(PcdFspModeSelection) =3D=3D 1=0D +//=0D +// MACROS for platform code use=0D +//=0D +#define UPDATE_POLICY(UpdField, ConfigField, Value) UpdField =3D Value;=0D +#define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (UpdField= , Value, Size);=0D +#define GET_POLICY(UpdField, ConfigField, Value) Value =3D UpdField;=0D +#define AND_POLICY(UpdField, ConfigField, Value) UpdField &=3D Value;=0D +#define OR_POLICY(UpdField, ConfigField, Value) UpdField |=3D Value;=0D +#else=0D +#define UPDATE_POLICY(UpdField, ConfigField, Value) ConfigField =3D Value= ;=0D +#define COPY_POLICY(UpdField, ConfigField, Value, Size) CopyMem (ConfigFi= eld, Value, Size);=0D +#define GET_POLICY(UpdField, ConfigField, Value) Value =3D ConfigField;=0D +#define AND_POLICY(UpdField, ConfigField, Value) ConfigField &=3D Value;= =0D +#define OR_POLICY(UpdField, ConfigField, Value) ConfigField |=3D Value;=0D +#endif=0D +=0D +#endif //_POLICY_UPDATE_MACRO_H_=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec b/Platfo= rm/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec new file mode 100644 index 0000000000..91f0a88470 --- /dev/null +++ b/Platform/Intel/TigerlakeOpenBoardPkg/OpenBoardPkg.dec @@ -0,0 +1,153 @@ +## @file=0D +#=0D +# The DEC files are used by the utilities that parse DSC and=0D +# INF files to generate AutoGen.c and AutoGen.h files=0D +# for the build infrastructure.=0D +#=0D +# Copyright (c) 2021, Intel Corporation. All rights reserved.
=0D +# SPDX-License-Identifier: BSD-2-Clause-Patent=0D +#=0D +##=0D +=0D +=0D +[Defines]=0D +DEC_SPECIFICATION =3D 0x00010017=0D +PACKAGE_NAME =3D OpenBoardPkg=0D +PACKAGE_VERSION =3D 0.1=0D +PACKAGE_GUID =3D 734F5E12-4C70-4EC9-908B-D7421B4B128C=0D +=0D +[Includes]=0D +Include=0D +TigerlakeURvp/Include=0D +=0D +[Guids]=0D + gBoardModuleTokenSpaceGuid =3D {0x72d1fff7, 0xa42a, 0x4219, = {0xb9, 0x95, 0x5a, 0x67, 0x53, 0x6e, 0xa4, 0x2a}}=0D + # gUefiShellFileGuid is FILE GUID for MinUefiShell.inf/UefiShell.inf/She= ll.inf.=0D + gUefiShellFileGuid =3D {0x7c04a583, 0x9e3e, 0x4f1c, = {0xad, 0x65, 0xe0, 0x52, 0x68, 0xd0, 0xb4, 0xd1}}=0D + gPlatformInitFvLocationGuid =3D {0xa564010a, 0x1d90, 0x4b1c, = {0x8d, 0x10, 0xcb, 0xba, 0xff, 0xb2, 0x55, 0x42}}=0D + gTianoLogoGuid =3D {0x7BB28B99, 0x61BB, 0x11D5, = {0x9A, 0x5D, 0x00, 0x90, 0x27, 0x3F, 0xC1, 0x4D}}=0D +=0D +[Protocols]=0D + gPlatformNvsAreaProtocolGuid =3D {0xc77ae556, 0x40a3, 0x41c0, = {0xac, 0xe6, 0x71, 0x43, 0x8c, 0x60, 0xf8, 0x71}}=0D +=0D +[Ppis]=0D +=0D +[LibraryClasses]=0D +=0D +[PcdsFixedAtBuild, PcdsPatchableInModule]=0D +=0D +[PcdsFixedAtBuild]=0D + gBoardModuleTokenSpaceGuid.PcdLpcIoDecodeRange|0x0010|UINT16|0x10001004= =0D + gBoardModuleTokenSpaceGuid.PchLpcIoEnableDecoding|0x3c03|UINT16|0x100010= 05=0D +=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioIndexPort|0x4e|UINT16|0x90000018=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioDataPort|0x4f|UINT16|0x9000001F=0D +=0D + gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort|0x164E|UINT16|0x90= 00001C=0D + gBoardModuleTokenSpaceGuid.PcdSioBaseAddress|0x0680|UINT16|0x9000001D=0D +=0D + gBoardModuleTokenSpaceGuid.PcdDmiBaseAddress|0xFED18000|UINT64|0x9000000= 3=0D + gBoardModuleTokenSpaceGuid.PcdDmiMmioSize|0x1000|UINT32|0x90000004=0D +=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesBase|0x00000000|UIN= T32|0x20000040=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize|0x00000000|UIN= T32|0x20000041=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset|0x00000000|U= INT32|0x20000042=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalBase|0x00000000|UINT32|0x20= 00004C=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize|0x00000000|UINT32|0x20= 00004D=0D + gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset|0x00000000|UINT32|0x= 2000004E=0D + gBoardModuleTokenSpaceGuid.PcdEpBaseAddress|0xFED19000|UINT64|0x90000005= =0D + gBoardModuleTokenSpaceGuid.PcdEpMmioSize|0x1000|UINT32|0x90000006=0D +=0D +[PcdsDynamic]=0D + # Board GPIO Table=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTable|0|UINT32|0x00000040=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize|0|UINT16|0x00000041=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem|0|UINT32|0x00000042=0D + gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize|0|UINT16|0x000000= 43=0D +=0D + # SA Misc Configuration=0D + gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd|0|UINT8|0x00000066=0D + gBoardModuleTokenSpaceGuid.PcdSaMiscMmioSizeAdjustment|0|UINT16|0x000000= 67=0D +=0D + # DRAM Configuration=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdData|0|UINT32|0x00000174=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize|0|UINT16|0x00000175=0D +=0D + # SPD Address Table=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0|0|UINT8|0x00000099=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1|0|UINT8|0x0000009A=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2|0|UINT8|0x0000009B=0D + gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3|0|UINT8|0x0001009C=0D +=0D + # Root Port Clock Info=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock0|0|UINT64|0x0000009E=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock1|0|UINT64|0x0000009F=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock2|0|UINT64|0x000000A0=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock3|0|UINT64|0x000000A1=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock4|0|UINT64|0x000000A2=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock5|0|UINT64|0x000000A3=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock6|0|UINT64|0x000000A4=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock7|0|UINT64|0x000000A5=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock8|0|UINT64|0x000000A6=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock9|0|UINT64|0x000000A7=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock10|0|UINT64|0x000000A8=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock11|0|UINT64|0x000000A9=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock12|0|UINT64|0x000000AA=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock13|0|UINT64|0x000000AB=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock14|0|UINT64|0x000000AC=0D + gBoardModuleTokenSpaceGuid.PcdPcieClock15|0|UINT64|0x000000AD=0D +=0D + # USB 2.0 Port Over Current Pin=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort0|0xFF|UINT8|0x0000= 00CF=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort1|0xFF|UINT8|0x0000= 00D0=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort2|0xFF|UINT8|0x0000= 00D1=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort3|0xFF|UINT8|0x0000= 00D2=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort4|0xFF|UINT8|0x0000= 00D3=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort5|0xFF|UINT8|0x0000= 00D4=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort6|0xFF|UINT8|0x0000= 00D5=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort7|0xFF|UINT8|0x0000= 00D6=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort8|0xFF|UINT8|0x0000= 00D7=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort9|0xFF|UINT8|0x0000= 00D8=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort10|0xFF|UINT8|0x000= 000D9=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort11|0xFF|UINT8|0x000= 000DA=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort12|0xFF|UINT8|0x000= 000DB=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort13|0xFF|UINT8|0x000= 000DC=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort14|0xFF|UINT8|0x000= 000DD=0D + gBoardModuleTokenSpaceGuid.PcdUsb20OverCurrentPinPort15|0xFF|UINT8|0x000= 000DE=0D +=0D + # USB 3.0 Port Over Current Pin=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort0|0xFF|UINT8|0x0000= 00DF=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort1|0xFF|UINT8|0x0000= 00E0=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort2|0xFF|UINT8|0x0000= 00E1=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort3|0xFF|UINT8|0x0000= 00E2=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort4|0xFF|UINT8|0x0000= 00E3=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort5|0xFF|UINT8|0x0000= 00E4=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort6|0xFF|UINT8|0x0000= 00E5=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort7|0xFF|UINT8|0x0000= 00E6=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort8|0xFF|UINT8|0x0000= 00E7=0D + gBoardModuleTokenSpaceGuid.PcdUsb30OverCurrentPinPort9|0xFF|UINT8|0x0000= 00E8=0D + gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable|0|UINT8|0x00100032=0D +=0D + # CPU=0D + gBoardModuleTokenSpaceGuid.PcdCpuRatio|0x0|UINT8|0x00000200=0D + gBoardModuleTokenSpaceGuid.PcdBiosGuard|0x0|UINT8|0x00000201=0D +=0D + # ACPI=0D + gBoardModuleTokenSpaceGuid.PcdAcpiSleepState|1|UINT8|0x40000002=0D + gBoardModuleTokenSpaceGuid.PcdAcpiHibernate|1|UINT8|0x40000003=0D + gBoardModuleTokenSpaceGuid.PcdLowPowerS0Idle|0|UINT8|0x40000004=0D + gBoardModuleTokenSpaceGuid.PcdDisableActiveTripPoints|1|UINT8|0x4000000A= =0D + gBoardModuleTokenSpaceGuid.PcdDisablePassiveTripPoints|0|UINT8|0x4000000= B=0D + gBoardModuleTokenSpaceGuid.PcdDisableCriticalTripPoints|1|UINT8|0x400000= 0C=0D + gBoardModuleTokenSpaceGuid.PcdAcpiGnvsAddress|0|UINT64|0x40000013=0D +=0D + gBoardModuleTokenSpaceGuid.PcdGraphicsVbtGuid|{0x22, 0x61, 0xd4, 0x4a, 0= xeb, 0xff, 0x52, 0x4a, 0xbf, 0xb0, 0x51, 0x8c, 0xfc, 0xa0, 0x2d, 0xb0}|VOID= *|0x40000014=0D +=0D +[PcdsDynamicEx]=0D +=0D +[PcdsDynamic, PcdsDynamicEx]=0D +=0D +[PcdsPatchableInModule]=0D +=0D +[PcdsFeatureFlag]=0D + gBoardModuleTokenSpaceGuid.PcdIntelGopEnable |TRUE|BOOLEAN|0xF00000= 62=0D --=20 2.24.0.windows.2