public inbox for devel@edk2.groups.io
 help / color / mirror / Atom feed
From: "Heng Luo" <heng.luo@intel.com>
To: devel@edk2.groups.io
Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>,
	Nate DeSimone <nathaniel.l.desimone@intel.com>
Subject: [Patch V3 2/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add fdf and header file
Date: Wed, 10 Feb 2021 12:00:06 +0800	[thread overview]
Message-ID: <20210210040012.4564-2-heng.luo@intel.com> (raw)
In-Reply-To: <20210210040012.4564-1-heng.luo@intel.com>

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following files:
  * TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
  * TigerlakeURvp/Include/PeiPlatformHookLib.h

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf |  54 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHookLib.h    | 130 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 184 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
new file mode 100644
index 0000000000..b21ae6401f
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/Fdf/FlashMapInclude.fdf
@@ -0,0 +1,54 @@
+## @file
+#  FDF file of Platform.
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+#=================================================================================#
+# 12 M BIOS - for FSP wrapper
+#=================================================================================#
+DEFINE FLASH_BASE                                                   = 0xFF400000  #
+DEFINE FLASH_SIZE                                                   = 0x00C00000  #
+DEFINE FLASH_BLOCK_SIZE                                             = 0x00010000  #
+DEFINE FLASH_NUM_BLOCKS                                             = 0x000000C0  #
+#=================================================================================#
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageOffset             = 0x00000000  # Flash addr (0xFF400000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageSize               = 0x00060000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageVariableOffset     = 0x00000000  # Flash addr (0xFF400000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageVariableSize      = 0x0002E000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingOffset   = 0x0002E000  # Flash addr (0xFF42E000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwWorkingSize    = 0x00002000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareOffset     = 0x00030000  # Flash addr (0xFF430000)
+SET gEfiMdeModulePkgTokenSpaceGuid.PcdFlashNvStorageFtwSpareSize      = 0x00030000  #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedOffset            = 0x000E0000  # Flash addr (0xFF4E0000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvAdvancedSize              = 0x001A0000  #
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalOffset               = 0x00280000  # Flash addr (0xFF680000)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvOptionalSize                 = 0x00300000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootOffset              = 0x00580000  # Flash addr (0xFF980000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvOsBootSize                = 0x000A0000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootOffset            = 0x00620000  # Flash addr (0xFFA20000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvUefiBootSize              = 0x001D0000  #
+
+## Firmware binaries FV absolute address requires 256kB alignment
+## Build script checks the requirement.
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesOffset       = 0x00800000  # Flash addr (0xFFC00000)
+SET gBoardModuleTokenSpaceGuid.PcdFlashFvFirmwareBinariesSize         = 0x00080000  # Keep 0x80000 or larger
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvOffset                    = 0x00880000  # Flash addr (0xFFC80000)
+SET gSiPkgTokenSpaceGuid.PcdFlashMicrocodeFvSize                      = 0x00070000  # Keep 0x70000 or larger, change MicrocodeFv.fdf in case that this value change
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryOffset          = 0x008F0000  # Flash addr (0xFFC00000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemorySize            = 0x00080000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSOffset                = 0x00970000  # Flash addr (0xFFD70000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspSSize                  = 0x000A0000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMOffset                = 0x00A10000  # Flash addr (0xFFE10000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspMSize                  = 0x00110000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTOffset                = 0x00B20000  # Flash addr (0xFFF20000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvFspTSize                  = 0x00010000  #
+
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecurityOffset            = 0x00B30000  # Flash addr (0xFFF30000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvSecuritySize              = 0x00020000  #
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemoryOffset           = 0x00B50000  # Flash addr (0xFFF50000)
+SET gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPreMemorySize             = 0x000B0000  #
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHookLib.h b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHookLib.h
new file mode 100644
index 0000000000..f8611764f5
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Include/PeiPlatformHookLib.h
@@ -0,0 +1,130 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _PEI_PLATFORM_HOOK_LIB_H_
+#define _PEI_PLATFORM_HOOK_LIB_H_
+
+#include <Library/PeiServicesLib.h>
+#include <Library/GpioLib.h>
+
+
+//EC Command to provide one byte of debug indication
+#define BSSB_DEBUG_INDICATION 0xAE
+/**
+  Configure EC for specific devices
+
+  @param[in] PchLan       - The PchLan of PCH_SETUP variable.
+  @param[in] BootMode     - The current boot mode.
+**/
+VOID
+EcInit (
+  IN UINT8                PchLan,
+  IN EFI_BOOT_MODE        BootMode
+  );
+
+/**
+  Checks if Premium PMIC present
+
+  @retval  TRUE  if present
+  @retval  FALSE it discrete/other PMIC
+**/
+BOOLEAN
+IsPremiumPmicPresent (
+  VOID
+  );
+
+/**
+  Pmic Programming to supprort LPAL Feature
+
+  @retval     NONE
+**/
+VOID
+PremiumPmicDisableSlpS0Voltage (
+  VOID
+  );
+
+/**
+Pmic Programming to supprort LPAL Feature
+  @retval     NONE
+**/
+VOID
+PremiumPmicEnableSlpS0Voltage(
+  VOID
+  );
+
+/**
+  Do platform specific programming pre-memory. For example, EC init, Chipset programming
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInitPreMem (
+  VOID
+  );
+
+/**
+  Do platform specific programming post-memory.
+
+  @retval  Status
+**/
+EFI_STATUS
+PlatformSpecificInit (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO Before Memory is ready.
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+  VOID
+  );
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  VOID
+  );
+
+/**
+Voltage Margining Routine
+
+@retval  EFI_SUCCESS   Operation success
+**/
+EFI_STATUS
+VoltageMarginingRoutine(
+  VOID
+  );
+
+/**
+  Detect recovery mode
+
+  @retval  EFI_SUCCESS       System in Recovery Mode
+  @retval  EFI_UNSUPPORTED   System doesn't support Recovery Mode
+  @retval  EFI_NOT_FOUND     System is not in Recovery Mode
+**/
+EFI_STATUS
+IsRecoveryMode (
+  VOID
+  );
+
+/**
+  Early board Configuration before Memory is ready.
+
+  @retval  EFI_SUCCESS  Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+  VOID
+  );
+#endif
+
-- 
2.24.0.windows.2


  reply	other threads:[~2021-02-10  4:00 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-02-10  4:00 [Patch V3 1/8] TigerlakeOpenBoardPkg: Add package and headers Heng Luo
2021-02-10  4:00 ` Heng Luo [this message]
2021-02-10  4:00 ` [Patch V3 3/8] TigerlakeOpenBoardPkg: Add library instances Heng Luo
2021-02-10  4:00 ` [Patch V3 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: " Heng Luo
2021-02-10  7:03   ` Chaganty, Rangasai V
2021-02-10  4:00 ` [Patch V3 5/8] TigerlakeOpenBoardPkg: Add modules Heng Luo
2021-02-10  4:00 ` [Patch V3 6/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add DSC and build files Heng Luo
2021-02-10  4:00 ` [Patch V3 7/8] Enable build for TigerlakeOpenBoardPkg Heng Luo
2021-02-10  4:00 ` [Patch V3 8/8] Update Maintainers.txt " Heng Luo
2021-02-10  7:58   ` Chaganty, Rangasai V
2021-02-11  1:31   ` Nate DeSimone
2021-02-11  1:57   ` Nate DeSimone

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-list from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20210210040012.4564-2-heng.luo@intel.com \
    --to=devel@edk2.groups.io \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox