[Patch V3 4/8] TigerlakeOpenBoardPkg/TigerlakeURvp: Add library instances

["Heng Luo" <heng.luo@intel.com>]

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3175

Adds the following library instances:
  * TigerlakeURvp/Library/BoardAcpiLib
  * TigerlakeURvp/Library/BoardInitLib
  * TigerlakeURvp/Library/PeiPlatformHookLib

Cc: Sai Chaganty <rangasai.v.chaganty@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Signed-off-by: Heng Luo <heng.luo@intel.com>
---
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c      |  88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf    |  43 +++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c          | 136 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c    |  51 +++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c            | 160 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c             |  96 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h       |  93 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h |  33 +++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c      |  41 +++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf    |  49 +++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c       |  88 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf     | 115 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c           |  39 +++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c   | 153 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c    | 445 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/TigerlakeURvpInit.h                |  23 +++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c         | 212 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf       |  58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
 18 files changed, 1923 insertions(+)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
new file mode 100644
index 0000000000..1436d9b79a
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.c
@@ -0,0 +1,88 @@
+/** @file
+  Tiger Lake U RVP SMM Multi-Board ACPI Support library
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/MultiBoardAcpiSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+TglBoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+TglBoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+  IN BOOLEAN  EnableSci
+  );
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+  IN BOOLEAN  DisableSci
+  );
+
+EFI_STATUS
+EFIAPI
+MultiBoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  SiliconEnableAcpi (EnableSci);
+  return TglBoardEnableAcpi (EnableSci);
+}
+
+EFI_STATUS
+EFIAPI
+MultiBoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  SiliconDisableAcpi (DisableSci);
+  return TglBoardDisableAcpi (DisableSci);
+}
+
+BOARD_ACPI_ENABLE_FUNC  mBoardAcpiEnableFunc = {
+  MultiBoardEnableAcpi,
+  MultiBoardDisableAcpi,
+};
+
+/**
+  The constructor function to register mBoardAcpiEnableFunc function.
+
+  @param[in]  ImageHandle  The firmware allocated handle for the EFI image.
+  @param[in]  SystemTable  A pointer to the EFI System Table.
+
+  @retval     EFI_SUCCESS  This constructor always return EFI_SUCCESS.
+                           It will ASSERT on errors.
+**/
+EFI_STATUS
+EFIAPI
+SmmMultiBoardAcpiSupportLibConstructor (
+  IN EFI_HANDLE        ImageHandle,
+  IN EFI_SYSTEM_TABLE  *SystemTable
+  )
+{
+  DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+  return RegisterBoardAcpiEnableFunc (&mBoardAcpiEnableFunc);
+}
+
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
new file mode 100644
index 0000000000..6f6a9272f9
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmMultiBoardAcpiSupportLib.inf
@@ -0,0 +1,43 @@
+## @file
+#  Tiger Lake U RVP SMM Multi-Board ACPI Support library
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = SmmMultiBoardAcpiSupportLib
+  FILE_GUID                      = 8929A54E-7ED8-4AB3-BEBB-C0367BDBBFF5
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = DXE_SMM_DRIVER
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = SmmMultiBoardAcpiSupportLibConstructor
+
+#
+# The following information is for reference only and not required by the build tools.
+#
+# VALID_ARCHITECTURES = IA32 X64 IPF EBC
+#
+
+[LibraryClasses]
+  BaseLib
+  IoLib
+  PciLib
+  MmPciLib
+  PchCycleDecodingLib
+  PchPciBdfLib
+  PmcLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  MinPlatformPkg/MinPlatformPkg.dec
+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec
+  TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  SmmTigerlakeURvpAcpiEnableLib.c
+  SmmSiliconAcpiEnableLib.c
+  SmmMultiBoardAcpiSupportLib.c
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
new file mode 100644
index 0000000000..7ce993e3ea
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmSiliconAcpiEnableLib.c
@@ -0,0 +1,136 @@
+/** @file
+  Tiger Lake U RVP SMM Silicon ACPI Enable library
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/BoardAcpiEnableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <Library/MmPciLib.h>
+#include <Library/PmcLib.h>
+#include <Library/PchPciBdfLib.h>
+#include <Register/PchRegs.h>
+#include <Register/PchRegsLpc.h>
+#include <Register/PmcRegs.h>
+#include <Register/RtcRegs.h>
+
+/**
+  Clear Port 80h
+
+  Disables the SW SMI Timer.
+  ACPI events are disabled and ACPI event status is cleared.
+
+  Disable port 60/64 SMI trap if they are enabled
+
+  Disable PM sources except power button
+  Clear status bits
+
+  Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+
+  Enable SCI
+**/
+EFI_STATUS
+EFIAPI
+SiliconEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+
+  UINT32                              SmiEn;
+  UINT32                              SmiSts;
+  UINT32                              ULKMC;
+  UINTN                               LpcBaseAddress;
+  UINT16                              AcpiBaseAddr;
+  UINT32                              Pm1Cnt;
+
+  LpcBaseAddress = LpcPciCfgBase ();
+
+  //
+  // Get the ACPI Base Address
+  //
+  AcpiBaseAddr = PmcGetAcpiBase();
+
+  //
+  // Clear Port 80h
+  //
+  IoWrite8 (0x80, 0);
+
+  //
+  // Disable SW SMI Timer and clean the status
+  //
+  SmiEn = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN);
+  SmiEn &= ~(B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB);
+  IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_EN, SmiEn);
+
+  SmiSts = IoRead32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS);
+  SmiSts |= B_ACPI_IO_SMI_EN_LEGACY_USB2 | B_ACPI_IO_SMI_EN_SWSMI_TMR | B_ACPI_IO_SMI_EN_LEGACY_USB;
+  IoWrite32 (AcpiBaseAddr + R_ACPI_IO_SMI_STS, SmiSts);
+
+  //
+  // Disable port 60/64 SMI trap if they are enabled
+  //
+  ULKMC = MmioRead32 (LpcBaseAddress + R_LPC_CFG_ULKMC) & ~(B_LPC_CFG_ULKMC_60REN | B_LPC_CFG_ULKMC_60WEN | B_LPC_CFG_ULKMC_64REN | B_LPC_CFG_ULKMC_64WEN | B_LPC_CFG_ULKMC_A20PASSEN);
+  MmioWrite32 (LpcBaseAddress + R_LPC_CFG_ULKMC, ULKMC);
+
+  //
+  // Disable PM sources except power button
+  //
+  IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_EN, B_ACPI_IO_PM1_EN_PWRBTN);
+
+  //
+  // Clear PM status except Power Button status for RapidStart Resume
+  //
+  IoWrite16 (AcpiBaseAddr + R_ACPI_IO_PM1_STS, 0xFEFF);
+
+  //
+  // Guarantee day-of-month alarm is invalid (ACPI 1.0 section 4.7.2.4)
+  //
+  IoWrite8 (R_RTC_IO_INDEX_ALT, R_RTC_IO_REGD);
+  IoWrite8 (R_RTC_IO_TARGET_ALT, 0x0);
+
+  //
+  // Enable SCI
+  //
+  if (EnableSci) {
+    Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+    Pm1Cnt |= B_ACPI_IO_PM1_CNT_SCI_EN;
+    IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+  }
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+SiliconDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+
+  UINT16                              AcpiBaseAddr;
+  UINT32                              Pm1Cnt;
+
+  //
+  // Get the ACPI Base Address
+  //
+  AcpiBaseAddr = PmcGetAcpiBase();
+  //
+  // Disable SCI
+  //
+  if (DisableSci) {
+    Pm1Cnt = IoRead32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT);
+    Pm1Cnt &= ~B_ACPI_IO_PM1_CNT_SCI_EN;
+    IoWrite32 (AcpiBaseAddr + R_ACPI_IO_PM1_CNT, Pm1Cnt);
+  }
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c
new file mode 100644
index 0000000000..3eb302c30d
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardAcpiLib/SmmTigerlakeURvpAcpiEnableLib.c
@@ -0,0 +1,51 @@
+/** @file
+  Tiger Lake U RVP SMM Board ACPI Enable library
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <Base.h>
+#include <Uefi.h>
+#include <PiDxe.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardAcpiTableLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+#include <PlatformBoardId.h>
+
+/**
+  Enable Board Acpi
+
+  @param[in]  EnableSci     Enable SCI if EnableSci parameters is True.
+
+  @retval     EFI_SUCCESS   The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+TglBoardEnableAcpi (
+  IN BOOLEAN  EnableSci
+  )
+{
+  // enable additional board register
+  return EFI_SUCCESS;
+}
+
+/**
+  Disable Board Acpi
+
+  @param[in]  DisableSci    Disable SCI if DisableSci parameters is True.
+
+  @retval     EFI_SUCCESS   The function always return successfully.
+**/
+EFI_STATUS
+EFIAPI
+TglBoardDisableAcpi (
+  IN BOOLEAN  DisableSci
+  )
+{
+  // enable additional board register
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
new file mode 100644
index 0000000000..1c7e574f7d
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardPchInitPreMemLib.c
@@ -0,0 +1,160 @@
+/** @file
+  Source code for the board PCH configuration Pcd init functions for Pre-Memory Init phase.
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "TigerlakeURvpInit.h"
+#include "GpioTableTigerlakeUDdr4RvpPreMem.h"
+
+#include <PlatformBoardConfig.h>
+#include <Include/PlatformBoardId.h>
+
+#include <Library/GpioLib.h>
+
+/**
+  Board Root Port Clock Info configuration init function for PEI pre-memory phase.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+RootPortClkInfoInit (
+  IN UINT16    BoardId
+  )
+{
+  PCD64_BLOB Clock[PCH_MAX_PCIE_CLOCKS];
+  UINT32 Index;
+
+  //
+  // The default clock assignment will be FREE_RUNNING, which corresponds to PchClockUsageUnspecified
+  // This is safe but power-consuming setting. If Platform code doesn't contain port-clock map for a given board,
+  // the clocks will keep on running anyway, allowing PCIe devices to operate. Downside is that clocks will
+  // continue to draw power. To prevent this, remember to provide port-clock map for every board.
+  //
+  for (Index = 0; Index < PCH_MAX_PCIE_CLOCKS; Index++) {
+    Clock[Index].PcieClock.ClkReqSupported = TRUE;
+    Clock[Index].PcieClock.ClockUsage = FREE_RUNNING;
+  }
+
+  ///
+  /// Assign ClkReq signal to root port. (Base 0)
+  /// For LP, Set 0 - 6
+  /// For H,  Set 0 - 15
+  /// Note that if GbE is enabled, ClkReq assigned to GbE will not be available for Root Port.
+  ///
+
+  switch (BoardId) {
+    // CLKREQ
+    case BoardIdTglUDdr4:
+      Clock[0].PcieClock.ClockUsage = PCIE_PEG;
+      Clock[1].PcieClock.ClockUsage = PCIE_PCH + 2;
+      Clock[2].PcieClock.ClockUsage = PCIE_PCH + 3;
+      Clock[3].PcieClock.ClockUsage = PCIE_PCH + 8;
+      Clock[4].PcieClock.ClockUsage = LAN_CLOCK;
+      Clock[5].PcieClock.ClockUsage = PCIE_PCH + 7;
+      Clock[6].PcieClock.ClockUsage = PCIE_PCH + 4;
+      break;
+    default:
+
+      break;
+  }
+
+  PcdSet64S (PcdPcieClock0,  Clock[ 0].Blob);
+  PcdSet64S (PcdPcieClock1,  Clock[ 1].Blob);
+  PcdSet64S (PcdPcieClock2,  Clock[ 2].Blob);
+  PcdSet64S (PcdPcieClock3,  Clock[ 3].Blob);
+  PcdSet64S (PcdPcieClock4,  Clock[ 4].Blob);
+  PcdSet64S (PcdPcieClock5,  Clock[ 5].Blob);
+  PcdSet64S (PcdPcieClock6,  Clock[ 6].Blob);
+  PcdSet64S (PcdPcieClock7,  Clock[ 7].Blob);
+  PcdSet64S (PcdPcieClock8,  Clock[ 8].Blob);
+  PcdSet64S (PcdPcieClock9,  Clock[ 9].Blob);
+  PcdSet64S (PcdPcieClock10, Clock[10].Blob);
+  PcdSet64S (PcdPcieClock11, Clock[11].Blob);
+  PcdSet64S (PcdPcieClock12, Clock[12].Blob);
+  PcdSet64S (PcdPcieClock13, Clock[13].Blob);
+  PcdSet64S (PcdPcieClock14, Clock[14].Blob);
+  PcdSet64S (PcdPcieClock15, Clock[15].Blob);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Board USB related configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+UsbConfigInit (
+  IN UINT16 BoardId
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  Board GPIO Group Tier configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+GpioGroupTierInit (
+  IN UINT16 BoardId
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+
+/**
+  GPIO init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+GpioTablePreMemInit (
+  IN UINT16 BoardId
+  )
+{
+
+  //
+  // GPIO Table Init.
+  //
+  switch (BoardId) {
+    case BoardIdTglUDdr4:
+      PcdSet32S (PcdBoardGpioTablePreMem, (UINTN) mGpioTablePreMemTglUDdr4);
+      PcdSet16S (PcdBoardGpioTablePreMemSize, mGpioTablePreMemTglUDdr4Size);
+      break;
+
+    default:
+      break;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  PmConfig init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+PchPmConfigInit (
+  IN UINT16 BoardId
+  )
+{
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
new file mode 100644
index 0000000000..b468e21ec9
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/BoardSaInitPreMemLib.c
@@ -0,0 +1,96 @@
+/** @file
+ Source code for the board SA configuration Pcd init functions in Pre-Memory init phase.
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include "TigerlakeURvpInit.h"
+#include <Pins/GpioPinsVer2Lp.h>
+#include <PlatformBoardId.h>
+#include <PlatformBoardConfig.h>
+
+/**
+  MRC configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId           An unsigned integer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+SaMiscConfigInit (
+  IN UINT16         BoardId
+  )
+{
+  //
+  // UserBd
+  //
+  switch (BoardId) {
+    case BoardIdTglUDdr4:
+      //
+      // Assign UserBd to 5 which is assigned to MrcInputs->BoardType btUser4 for ULT platforms.
+      // This is required to skip Memory voltage programming based on GPIO's in MRC
+      //
+      PcdSet8S (PcdSaMiscUserBd, 5); // MrcBoardType btUser4 for ULT platform
+      break;
+
+    default:
+      // MiscPeiPreMemConfig.UserBd = 0 by default.
+      break;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Board Memory Init related configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integrer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+MrcConfigInit (
+  IN UINT16 BoardId
+  )
+{
+
+  PcdSet8S (PcdMrcSpdAddressTable0, 0xA0);
+  PcdSet8S (PcdMrcSpdAddressTable1, 0xA2);
+  PcdSet8S (PcdMrcSpdAddressTable2, 0xA4);
+  PcdSet8S (PcdMrcSpdAddressTable3, 0xA6);
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Board SA related GPIO configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId   An unsigned integer represent the board id.
+
+  @retval EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+SaGpioConfigInit (
+  IN UINT16 BoardId
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  SA Display DDI configuration init function for PEI pre-memory phase.
+
+  @param[in]  BoardId       An unsigned integer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+SaDisplayConfigInit (
+  IN UINT16 BoardId
+  )
+{
+  return EFI_SUCCESS;
+}
+
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h
new file mode 100644
index 0000000000..0b605698c0
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4Rvp.h
@@ -0,0 +1,93 @@
+/** @file
+  GPIO definition table for Tiger Lake U RVP
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_
+#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_
+
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTableTglUDdr4[] =
+{
+  // M.2 Key-E - WLAN/BT
+  {GPIO_VER2_LP_GPP_A13, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioHostDeepReset,  GpioTermNone, GpioPadConfigUnlock }}, // BT_RF_KILL_N
+  {GPIO_VER2_LP_GPP_B15, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioHostDeepReset,  GpioTermNone, GpioPadConfigUnlock }}, // WIFI_RF_KILL_N
+  {GPIO_VER2_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnDefault, GpioDirOut,   GpioOutHigh,    GpioIntDis,              GpioHostDeepReset,  GpioTermNone, GpioPadConfigUnlock }}, // WLAN_RST_N
+  {GPIO_VER2_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnAcpi,    GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset,  GpioTermNone, GpioPadConfigUnlock }}, // WIFI_WAKE_N
+  {GPIO_VER2_LP_GPP_H19, {GpioPadModeGpio, GpioHostOwnAcpi,    GpioDirInInv, GpioOutDefault, GpioIntLevel|GpioIntSci, GpioHostDeepReset,  GpioTermNone, GpioPadConfigUnlock }}, // UART_BT_WAKE_N : Not default POR
+  {GPIO_VER2_LP_GPP_A10, {GpioPadModeGpio, GpioHostOwnAcpi,    GpioDirIn,    GpioOutDefault, GpioIntDis,              GpioPlatformReset,  GpioTermNone}},                       // M.2 BT
+
+  // X4 Pcie Slot for Gen3 and Gen 4
+  {GPIO_VER2_LP_GPP_A14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutLow,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //ONBOARD_X4_PCIE_SLOT1_PWREN_N
+  {GPIO_VER2_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //ONBOARD_X4_PCIE_SLOT1_RESET_N
+  {GPIO_VER2_LP_GPP_F5,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,  GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //ONBOARD_X4_PCIE_SLOT1_WAKE_N
+  {GPIO_VER2_LP_GPP_F20, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //ONBOARD_X4_PCIE_SLOT1_DGPU_SEL
+  {GPIO_VER2_LP_GPP_F21, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirIn,  GpioOutDefault,GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //ONBOARD_X4_PCIE_SLOT1_DGPU_PWROK
+
+  // TBT Re-Timers
+  {GPIO_VER2_LP_GPD7,    {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,  GpioIntDis,GpioDswReset,  GpioTermNone}},  //TCP_RETIMER_PERST_N
+
+  // Battery Charger Vmin to PCH PROCHOT, derived from ICL
+  {GPIO_VER2_LP_GPP_B2,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,  GpioOutDefault,GpioIntEdge|GpioIntSci,GpioPlatformReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //BC_PROCHOT_N
+
+  // SATA Direct Connect
+  {GPIO_VER2_LP_GPP_B4,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //SATA_DIRECT_PWREN
+
+  // FPS
+  {GPIO_VER2_LP_GPP_B14, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //FPS_RST_N
+  {GPIO_VER2_LP_GPP_E3,  {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //FPS_INT
+
+  // PCH M.2 SSD
+  {GPIO_VER2_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //M2_PCH_SSD_PWREN
+  {GPIO_VER2_LP_GPP_H0,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //M2_SSD_RST_N
+
+
+  // Camera
+  {GPIO_VER2_LP_GPP_B23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //CRD_CAM_PWREN - CAM1
+  {GPIO_VER2_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //WF_CAM_RST_N  - CAM1
+
+  {GPIO_VER2_LP_GPP_H12, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //CAM2_RST_N
+
+  {GPIO_VER2_LP_GPP_H15, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //CAM3_PWREN
+  {GPIO_VER2_LP_GPP_H13, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //CAM3_RST_N
+
+  // Camera Common GPIO's for all Camera, Rework Options
+  {GPIO_VER2_LP_GPP_B18, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutLow,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //CRD_CAM_STROBE_1
+  {GPIO_VER2_LP_GPP_C2,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //WF_CAM_CLK_EN
+
+  // Audio
+  {GPIO_VER2_LP_GPP_C5,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //SPKR_PD_N
+  {GPIO_VER2_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,  GpioOutDefault,GpioIntLevel|GpioIntApic,GpioPlatformReset,  GpioTermNone,  GpioPadConfigUnlock  }},  // CODEC_INT_N
+
+  // Touch Pad
+  // Touch Pad and Touch Panel 2 share the same Power Enable, default is Touch pad
+  {GPIO_VER2_LP_GPP_H1,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //TCH_PAD_LS_EN - PWR_En
+  {GPIO_VER2_LP_GPP_C8,  {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv,  GpioOutDefault,GpioIntEdge|GpioIntApic,GpioPlatformReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //TCH_PAD_INT_N
+
+  // EC
+  {GPIO_VER2_LP_GPP_E7,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,  GpioOutDefault,GpioIntLevel|GpioIntSmi,GpioPlatformReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //EC_SMI_N
+  {GPIO_VER2_LP_GPP_E8,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //EC_SLP_S0_CS_N
+
+  // SPI TPM, derived from ICL
+  {GPIO_VER2_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,  GpioOutDefault,GpioIntLevel | GpioIntApic, GpioHostDeepReset,  GpioTermWpu20K,  GpioPadConfigUnlock  }},  //SPI_TPM_INT_N
+
+  // TypeC BIAS : Not used by default in RVP, derived from ICL
+  {GPIO_VER2_LP_GPP_E22, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutLow,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //DISP_AUX_P_BIAS_GPIO
+  {GPIO_VER2_LP_GPP_E23, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //DISP_AUX_N_BIAS_GPIO
+
+  // LAN : Not used by Default in RVP
+
+  // X1 Pcie Slot
+  {GPIO_VER2_LP_GPP_F4,  {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirInInv,  GpioOutDefault,GpioIntLevel|GpioIntSci,GpioHostDeepReset,  GpioTermNone,  GpioPadConfigUnlock  }},  //X1 Slot WAKE
+  {GPIO_VER2_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut,  GpioOutHigh,   GpioIntDis,GpioPlatformReset,  GpioTermNone}},  //X1 Slot RESET
+};
+
+
+UINT16 mGpioTableTglUDdr4Size = sizeof (mGpioTableTglUDdr4) / sizeof (GPIO_INIT_CONFIG);
+
+#endif // _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_H_
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h
new file mode 100644
index 0000000000..7b08676037
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/GpioTableTigerlakeUDdr4RvpPreMem.h
@@ -0,0 +1,33 @@
+/** @file
+  GPIO definition table for Tiger Lake U DDR4 RVP Pre-Memory
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_
+#define _GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_
+
+#include <Pins/GpioPinsVer2Lp.h>
+#include <Library/GpioLib.h>
+#include <Library/GpioConfig.h>
+
+GPIO_INIT_CONFIG mGpioTablePreMemTglUDdr4[] =
+{
+  { GPIO_VER2_LP_GPP_A14, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow,  GpioIntDis, GpioPlatformReset, GpioTermNone } },  //ONBOARD_X4_PCIE_SLOT1_PWREN_N
+  { GPIO_VER2_LP_GPP_C13, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } },  //ONBOARD_X4_PCIE_SLOT1_RESET_N
+  // CPU M.2 SSD
+  { GPIO_VER2_LP_GPP_D16, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } },  //CPU SSD PWREN
+  { GPIO_VER2_LP_GPP_A11, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } },  //CPU SSD RESET
+  // X1 Pcie Slot
+  { GPIO_VER2_LP_GPP_F9,  { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } },  //X1 Slot PWREN
+  { GPIO_VER2_LP_GPP_A23, { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow,  GpioIntDis, GpioPlatformReset, GpioTermNone } },  //TC_RETIMER_FORCE_PWR
+  // Camera
+  { GPIO_VER2_LP_GPP_R6,  { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutHigh, GpioIntDis, GpioPlatformReset, GpioTermNone } },  //CAM2_PWREN/BIOS_REC
+  { GPIO_VER2_LP_GPP_R5,  { GpioPadModeGpio, GpioHostOwnAcpi, GpioDirOut, GpioOutLow,  GpioIntDis, GpioPlatformReset, GpioTermNone } },  //CRD_CAM_PRIVACY_LED_1
+};
+
+UINT16 mGpioTablePreMemTglUDdr4Size = sizeof (mGpioTablePreMemTglUDdr4) / sizeof (GPIO_INIT_CONFIG);
+
+#endif  //_GPIO_TABLE_TIGER_LAKE_U_DDR4_RVP_PREMEM_H_
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
new file mode 100644
index 0000000000..f652dcf8e6
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.c
@@ -0,0 +1,41 @@
+/** @file
+  Tiger Lake U RVP Multi-Board Initialization Post-Memory library
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardInitBeforeSiliconInit(
+  VOID
+  );
+
+BOARD_POST_MEM_INIT_FUNC  mTigerlakeURvpBoardInitFunc = {
+  TigerlakeURvpBoardInitBeforeSiliconInit,
+  NULL, // BoardInitAfterSiliconInit
+};
+
+EFI_STATUS
+EFIAPI
+PeiTigerlakeURvpMultiBoardInitLibConstructor (
+  VOID
+  )
+{
+  if (LibPcdGetSku () == SkuIdTglU) {
+    DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+    return RegisterBoardPostMemInit (&mTigerlakeURvpBoardInitFunc);
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
new file mode 100644
index 0000000000..d00f350dfe
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPostMemLib.inf
@@ -0,0 +1,49 @@
+## @file
+#  Component information file for TigerlakeURvpInitLib in PEI post memory phase.
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiTigerlakeURvpMultiBoardInitLib
+  FILE_GUID                      = C7D39F17-E5BA-41D9-8DFE-FF9017499280
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = PeiTigerlakeURvpMultiBoardInitLibConstructor
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  PcdLib
+  MultiBoardInitSupportLib
+  PeiPlatformHookLib
+  PciSegmentLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiTigerlakeURvpInitPostMemLib.c
+  PeiMultiBoardInitPostMemLib.c
+
+  GpioTableTigerlakeUDdr4Rvp.h
+
+[FixedPcd]
+
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTable
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize
+
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashFvPostMemoryBase
+  gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable
+
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
new file mode 100644
index 0000000000..6200f3b86e
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.c
@@ -0,0 +1,88 @@
+/** @file
+  Tiger Lake U RVP Multi-Board Initialization Pre-Memory library
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/BaseLib.h>
+#include <Library/IoLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/MultiBoardInitSupportLib.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpMultiBoardDetect (
+  VOID
+  );
+
+EFI_BOOT_MODE
+EFIAPI
+TigerlakeURvpBoardBootModeDetect (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardDebugInit (
+  VOID
+  );
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardInitBeforeMemoryInit (
+  VOID
+  );
+
+
+BOARD_DETECT_FUNC  mTigerlakeURvpBoardDetectFunc = {
+  TigerlakeURvpMultiBoardDetect
+};
+
+BOARD_PRE_MEM_INIT_FUNC  mTigerlakeURvpBoardPreMemInitFunc = {
+  TigerlakeURvpBoardDebugInit,
+  TigerlakeURvpBoardBootModeDetect,
+  TigerlakeURvpBoardInitBeforeMemoryInit,
+  NULL, // BoardInitAfterMemoryInit
+  NULL, // BoardInitBeforeTempRamExit
+  NULL, // BoardInitAfterTempRamExit
+};
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpMultiBoardDetect (
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, " In TglUMultiBoardDetect \n"));
+
+  TigerlakeURvpBoardDetect ();
+
+  if (LibPcdGetSku () == SkuIdTglU) {
+    RegisterBoardPreMemInit (&mTigerlakeURvpBoardPreMemInitFunc);
+  } else {
+    DEBUG ((DEBUG_WARN,"Not a Valid TigerLake U Board\n"));
+  }
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+PeiTigerlakeURvpMultiBoardInitPreMemLibConstructor (
+  VOID
+  )
+{
+  return RegisterBoardDetect (&mTigerlakeURvpBoardDetectFunc);
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
new file mode 100644
index 0000000000..b8f1cf8aee
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiMultiBoardInitPreMemLib.inf
@@ -0,0 +1,115 @@
+## @file
+#  Component information file for PEI TigerlakeURvp Board Init Pre-Mem Library
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010005
+  BASE_NAME                      = PeiTigerlakeURvpMultiBoardInitPreMemLib
+  FILE_GUID                      = EA05BD43-136F-45EE-BBBA-27D75817574F
+  MODULE_TYPE                    = BASE
+  VERSION_STRING                 = 1.0
+  LIBRARY_CLASS                  = NULL
+  CONSTRUCTOR                    = PeiTigerlakeURvpMultiBoardInitPreMemLibConstructor
+
+[LibraryClasses]
+  BaseLib
+  DebugLib
+  BaseMemoryLib
+  MemoryAllocationLib
+  PcdLib
+  PeiPlatformHookLib
+  MultiBoardInitSupportLib
+  PeiLib
+
+[Packages]
+  MinPlatformPkg/MinPlatformPkg.dec
+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec
+  MdePkg/MdePkg.dec
+  MdeModulePkg/MdeModulePkg.dec
+  IntelFsp2Pkg/IntelFsp2Pkg.dec
+  TigerlakeSiliconPkg/SiPkg.dec
+
+[Sources]
+  PeiTigerlakeURvpInitPreMemLib.c
+  PeiMultiBoardInitPreMemLib.c
+  PeiTigerlakeURvpDetect.c
+  BoardSaInitPreMemLib.c
+  BoardPchInitPreMemLib.c
+  GpioTableTigerlakeUDdr4RvpPreMem.h
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid
+  gEfiPeiMemoryDiscoveredPpiGuid                ## CONSUMES
+  gEfiPeiResetPpiGuid                           ## PRODUCES
+[Pcd]
+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort
+
+  # SA Misc Config
+  gBoardModuleTokenSpaceGuid.PcdSaMiscUserBd
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdData
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdDataSize
+
+  # SPD Address Table
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable0
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable1
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable2
+  gBoardModuleTokenSpaceGuid.PcdMrcSpdAddressTable3
+
+  #===========================================================
+  # Board Init Table List
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize
+
+  # Board Information
+  gBoardModuleTokenSpaceGuid.PcdCpuRatio
+  gBoardModuleTokenSpaceGuid.PcdBiosGuard
+
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamBase              ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdTemporaryRamSize              ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspTemporaryRamSize           ## CONSUMES
+  gIntelFsp2PkgTokenSpaceGuid.PcdFspReservedBufferSize         ## CONSUMES
+
+  # SA USB Config
+  gBoardModuleTokenSpaceGuid.PcdCpuUsb30PortEnable
+
+  # PCIe Clock Info
+  gBoardModuleTokenSpaceGuid.PcdPcieClock0
+  gBoardModuleTokenSpaceGuid.PcdPcieClock1
+  gBoardModuleTokenSpaceGuid.PcdPcieClock2
+  gBoardModuleTokenSpaceGuid.PcdPcieClock3
+  gBoardModuleTokenSpaceGuid.PcdPcieClock4
+  gBoardModuleTokenSpaceGuid.PcdPcieClock5
+  gBoardModuleTokenSpaceGuid.PcdPcieClock6
+  gBoardModuleTokenSpaceGuid.PcdPcieClock7
+  gBoardModuleTokenSpaceGuid.PcdPcieClock8
+  gBoardModuleTokenSpaceGuid.PcdPcieClock9
+  gBoardModuleTokenSpaceGuid.PcdPcieClock10
+  gBoardModuleTokenSpaceGuid.PcdPcieClock11
+  gBoardModuleTokenSpaceGuid.PcdPcieClock12
+  gBoardModuleTokenSpaceGuid.PcdPcieClock13
+  gBoardModuleTokenSpaceGuid.PcdPcieClock14
+  gBoardModuleTokenSpaceGuid.PcdPcieClock15
+
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+
+  gMinPlatformPkgTokenSpaceGuid.PcdPciExpressRegionLength
+  gMinPlatformPkgTokenSpaceGuid.PcdLocalApicAddress
+  gMinPlatformPkgTokenSpaceGuid.PcdLocalApicMmioSize
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaBaseAddress
+  gMinPlatformPkgTokenSpaceGuid.PcdFlashAreaSize
+
+  gSiPkgTokenSpaceGuid.PcdMchBaseAddress
+  gSiPkgTokenSpaceGuid.PcdMchMmioSize
+
+  gBoardModuleTokenSpaceGuid.PcdDmiBaseAddress
+  gBoardModuleTokenSpaceGuid.PcdDmiMmioSize
+  gBoardModuleTokenSpaceGuid.PcdEpBaseAddress
+  gBoardModuleTokenSpaceGuid.PcdEpMmioSize
+
+[Guids]
+  gFspNonVolatileStorageHobGuid
+  gEfiMemoryOverwriteControlDataGuid
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c
new file mode 100644
index 0000000000..a11724072f
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpDetect.c
@@ -0,0 +1,39 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/PcdLib.h>
+#include <Library/DebugLib.h>
+
+#include <PlatformBoardId.h>
+
+BOOLEAN
+TigerlakeURvp(
+  VOID
+  )
+{
+  return TRUE;
+}
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardDetect (
+  VOID
+  )
+{
+  if (LibPcdGetSku () != 0) {
+    return EFI_SUCCESS;
+  }
+
+  DEBUG ((DEBUG_INFO, "TigerLakeU Board Detection Callback\n"));
+
+  if (TigerlakeURvp ()) {
+    LibPcdSetSku (SkuIdTglU);
+    DEBUG ((DEBUG_INFO, "SKU_ID: 0x%x\n", LibPcdGetSku()));
+    ASSERT (LibPcdGetSku() == SkuIdTglU);
+  }
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c
new file mode 100644
index 0000000000..e775f83cce
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPostMemLib.c
@@ -0,0 +1,153 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/BoardInitLib.h>
+#include <PeiPlatformHookLib.h>
+#include "TigerlakeURvpInit.h"
+#include "GpioTableTigerlakeUDdr4Rvp.h"
+#include <Library/ConfigBlockLib.h>
+
+/**
+  GPIO init function for PEI post memory phase.
+
+  @param[in]  BoardId       An unsigned integrer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+BoardGpioInit(
+  IN UINT16 BoardId
+  )
+{
+  //
+  // GPIO Table Init.
+  //
+  switch (BoardId) {
+
+    case BoardIdTglUDdr4:
+      PcdSet32S (PcdBoardGpioTable, (UINTN) mGpioTableTglUDdr4);
+      PcdSet16S (PcdBoardGpioTableSize, mGpioTableTglUDdr4Size);
+      break;
+
+    default:
+      break;
+  }
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Touch panel GPIO init function for PEI post memory phase.
+
+  @param[in]  BoardId       An unsigned integrer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+TouchPanelGpioInit (
+  IN UINT16 BoardId
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Misc. init function for PEI post memory phase.
+
+  @param[in]  BoardId       An unsigned integrer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInit (
+  IN UINT16 BoardId
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Security GPIO init function for PEI post memory phase.
+
+  @param[in]  BoardId       An unsigned integrer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+BoardSecurityInit (
+  IN UINT16 BoardId
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Board configuration initialization in the post-memory boot phase.
+**/
+VOID
+BoardConfigInit (
+  VOID
+  )
+{
+  EFI_STATUS  Status;
+  UINT16      BoardId;
+
+  BoardId = BoardIdTglUDdr4;
+
+  Status = BoardGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = TouchPanelGpioInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardSecurityInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+}
+
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardInitBeforeSiliconInit(
+  VOID
+  )
+{
+  EFI_STATUS      Status;
+
+  DEBUG ((DEBUG_INFO, "Board Init before Silicon Init\n"));
+
+  BoardConfigInit ();
+  //
+  // Configure GPIO and SIO
+  //
+  Status = BoardInit ();
+  ASSERT_EFI_ERROR (Status);
+
+  //
+  // Initializing Platform Specific Programming
+  //
+  Status = PlatformSpecificInit ();
+  ASSERT_EFI_ERROR(Status);
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c
new file mode 100644
index 0000000000..2ad229c1cd
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/PeiTigerlakeURvpInitPreMemLib.c
@@ -0,0 +1,445 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciLib.h>
+#include <Library/PcdLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/BoardInitLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <Library/PchPcrLib.h>
+#include <ConfigBlock.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PchPcrLib.h>
+#include <Register/PchRegsLpc.h>
+#include <Ppi/Reset.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PmcLib.h>
+#include <Library/PciSegmentLib.h>
+#include <PeiPlatformHookLib.h>
+#include <PlatformBoardId.h>
+
+///
+/// Reset Generator I/O Port
+///
+#define RESET_GENERATOR_PORT           0xCF9
+
+typedef struct {
+  EFI_PHYSICAL_ADDRESS    BaseAddress;
+  UINT64                  Length;
+} MEMORY_MAP;
+
+GLOBAL_REMOVE_IF_UNREFERENCED MEMORY_MAP MmioMap[] = {
+  { FixedPcdGet64 (PcdLocalApicAddress),  FixedPcdGet32 (PcdLocalApicMmioSize) },
+  { FixedPcdGet64 (PcdMchBaseAddress),    FixedPcdGet32 (PcdMchMmioSize) },
+  { FixedPcdGet64 (PcdDmiBaseAddress),    FixedPcdGet32 (PcdDmiMmioSize) },
+  { FixedPcdGet64 (PcdEpBaseAddress),     FixedPcdGet32 (PcdEpMmioSize) }
+};
+
+EFI_STATUS
+MrcConfigInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+SaGpioConfigInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+SaMiscConfigInit (
+  IN UINT16         BoardId
+  );
+
+EFI_STATUS
+RootPortClkInfoInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+UsbConfigInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+GpioGroupTierInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+GpioTablePreMemInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+PchPmConfigInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+SaDisplayConfigInit (
+  IN UINT16 BoardId
+  );
+
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack (
+  IN CONST EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR   *NotifyDescriptor,
+  IN VOID                        *Ppi
+  );
+
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify (
+  IN CONST EFI_PEI_SERVICES      **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR   *NotifyDescriptor,
+  IN VOID                        *Ppi
+  );
+
+EFI_STATUS
+EFIAPI
+PchReset (
+  IN CONST EFI_PEI_SERVICES    **PeiServices
+  );
+
+static EFI_PEI_RESET_PPI mResetPpi = {
+  PchReset
+};
+
+static EFI_PEI_PPI_DESCRIPTOR mPreMemPpiList[] = {
+  {
+    (EFI_PEI_PPI_DESCRIPTOR_PPI | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+    &gEfiPeiResetPpiGuid,
+    &mResetPpi
+  }
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mPreMemNotifyList = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiReadOnlyVariable2PpiGuid,
+  (EFI_PEIM_NOTIFY_ENTRY_POINT)PlatformInitPreMemCallBack
+};
+
+static EFI_PEI_NOTIFY_DESCRIPTOR mMemDiscoveredNotifyList = {
+  (EFI_PEI_PPI_DESCRIPTOR_NOTIFY_CALLBACK | EFI_PEI_PPI_DESCRIPTOR_TERMINATE_LIST),
+  &gEfiPeiMemoryDiscoveredPpiGuid,
+  (EFI_PEIM_NOTIFY_ENTRY_POINT)MemoryDiscoveredPpiNotify
+};
+
+/**
+  Board misc init function for PEI pre-memory phase.
+
+  @param[in]  BoardId       An unsigned integer represent the board id.
+
+  @retval     EFI_SUCCESS   The function completed successfully.
+**/
+EFI_STATUS
+BoardMiscInitPreMem (
+  IN UINT16 BoardId
+  )
+{
+  return EFI_SUCCESS;
+}
+
+/**
+  Board configuration initialization in the pre-memory boot phase.
+**/
+VOID
+BoardConfigInitPreMem (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  UINT16 BoardId;
+
+  BoardId = BoardIdTglUDdr4;
+
+  Status = MrcConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaGpioConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaMiscConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = RootPortClkInfoInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = UsbConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioGroupTierInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = GpioTablePreMemInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = PchPmConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = BoardMiscInitPreMem (BoardId);
+  ASSERT_EFI_ERROR (Status);
+
+  Status = SaDisplayConfigInit (BoardId);
+  ASSERT_EFI_ERROR (Status);
+}
+
+/**
+  This function handles PlatformInit task after PeiReadOnlyVariable2 PPI produced
+
+  @param[in]  PeiServices   Pointer to PEI Services Table.
+  @param[in]  NotifyDesc    Pointer to the descriptor for the Notification event that
+                            caused this function to execute.
+  @param[in]  Ppi           Pointer to the PPI data associated with this function.
+
+  @retval     EFI_SUCCESS  The function completes successfully
+  @retval     others       Failure
+**/
+EFI_STATUS
+EFIAPI
+PlatformInitPreMemCallBack (
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID                       *Ppi
+  )
+{
+  EFI_STATUS                        Status;
+
+  DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack Start...\n"));
+  //
+  // Init Board Config Pcd.
+  //
+  BoardConfigInitPreMem ();
+
+  ///
+  /// Configure GPIO and SIO
+  ///
+  Status = BoardInitPreMem ();
+  ASSERT_EFI_ERROR (Status);
+
+  ///
+  /// Install Pre Memory PPIs
+  ///
+  Status = PeiServicesInstallPpi (&mPreMemPpiList[0]);
+  ASSERT_EFI_ERROR (Status);
+
+  DEBUG ((DEBUG_INFO, "PlatformInitPreMemCallBack End...\n"));
+
+  return Status;
+}
+
+/**
+  Provide hard reset PPI service.
+  To generate full hard reset, write 0x0E to PCH RESET_GENERATOR_PORT (0xCF9).
+
+  @param[in]  PeiServices       General purpose services available to every PEIM.
+
+  @retval     Not return        System reset occured.
+  @retval     EFI_DEVICE_ERROR  Device error, could not reset the system.
+**/
+EFI_STATUS
+EFIAPI
+PchReset (
+  IN CONST EFI_PEI_SERVICES    **PeiServices
+  )
+{
+  DEBUG ((DEBUG_INFO, "Perform Cold Reset\n"));
+  IoWrite8 (RESET_GENERATOR_PORT, 0x0E);
+
+  CpuDeadLoop ();
+
+  ///
+  /// System reset occured, should never reach at this line.
+  ///
+  ASSERT_EFI_ERROR (EFI_DEVICE_ERROR);
+  return EFI_DEVICE_ERROR;
+}
+
+/**
+  Install Firmware Volume Hob's once there is main memory
+
+  @param[in]  PeiServices       General purpose services available to every PEIM.
+  @param[in]  NotifyDescriptor  Notify that this module published.
+  @param[in]  Ppi               PPI that was installed.
+
+  @retval     EFI_SUCCESS       The function completed successfully.
+**/
+EFI_STATUS
+EFIAPI
+MemoryDiscoveredPpiNotify (
+  IN CONST EFI_PEI_SERVICES     **PeiServices,
+  IN EFI_PEI_NOTIFY_DESCRIPTOR  *NotifyDescriptor,
+  IN VOID                       *Ppi
+  )
+{
+  EFI_STATUS                    Status;
+  EFI_BOOT_MODE                 BootMode;
+  UINTN                         Index;
+  UINT8                         PhysicalAddressBits;
+  UINT32                        RegEax;
+  MEMORY_MAP                    PcieMmioMap;
+
+ DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify Start!\n"));
+
+  Index = 0;
+
+  Status = PeiServicesGetBootMode (&BootMode);
+  ASSERT_EFI_ERROR (Status);
+
+  AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
+  if (RegEax >= 0x80000008) {
+    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
+    PhysicalAddressBits = (UINT8)RegEax;
+  }
+  else {
+    PhysicalAddressBits = 36;
+  }
+
+  ///
+  /// Create a CPU hand-off information
+  ///
+  BuildCpuHob (PhysicalAddressBits, 16);
+
+  ///
+  /// Build Memory Mapped IO Resource which is used to build E820 Table in LegacyBios.
+  ///
+  PcieMmioMap.BaseAddress = FixedPcdGet64 (PcdPciExpressBaseAddress);
+  PcieMmioMap.Length = PcdGet32 (PcdPciExpressRegionLength);
+
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_MEMORY_MAPPED_IO,
+     (EFI_RESOURCE_ATTRIBUTE_PRESENT      |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED  |
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+    PcieMmioMap.BaseAddress,
+    PcieMmioMap.Length
+    );
+  BuildMemoryAllocationHob (
+    PcieMmioMap.BaseAddress,
+    PcieMmioMap.Length,
+    EfiMemoryMappedIO
+    );
+  for (Index = 0; Index < sizeof(MmioMap) / (sizeof(MEMORY_MAP)); Index++) {
+    BuildResourceDescriptorHob (
+      EFI_RESOURCE_MEMORY_MAPPED_IO,
+       (EFI_RESOURCE_ATTRIBUTE_PRESENT      |
+        EFI_RESOURCE_ATTRIBUTE_INITIALIZED  |
+        EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+      MmioMap[Index].BaseAddress,
+      MmioMap[Index].Length
+      );
+    BuildMemoryAllocationHob (
+      MmioMap[Index].BaseAddress,
+      MmioMap[Index].Length,
+      EfiMemoryMappedIO
+      );
+  }
+
+  //
+  // Report resource HOB for flash FV
+  //
+  BuildResourceDescriptorHob (
+    EFI_RESOURCE_MEMORY_MAPPED_IO,
+     (EFI_RESOURCE_ATTRIBUTE_PRESENT      |
+      EFI_RESOURCE_ATTRIBUTE_INITIALIZED  |
+      EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE),
+    (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+    (UINTN) FixedPcdGet32 (PcdFlashAreaSize)
+    );
+
+  BuildMemoryAllocationHob (
+    (UINTN) FixedPcdGet32 (PcdFlashAreaBaseAddress),
+    (UINTN) FixedPcdGet32 (PcdFlashAreaSize),
+    EfiMemoryMappedIO
+    );
+
+  BuildFvHob (
+    (UINTN)FixedPcdGet32 (PcdFlashAreaBaseAddress),
+    (UINTN)FixedPcdGet32 (PcdFlashAreaSize)
+    );
+
+ DEBUG ((DEBUG_INFO, "MemoryDiscoveredPpiNotify End!\n"));
+
+  return Status;
+}
+
+/**
+  Board configuration init function for PEI pre-memory phase.
+
+  @retval EFI_SUCCESS             The function completed successfully.
+  @retval EFI_INVALID_PARAMETER   The parameter is NULL.
+**/
+EFI_STATUS
+EFIAPI
+TigerlakeURvpInitPreMem (
+  VOID
+  )
+{
+  EFI_STATUS Status;
+  DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem Start!\n"));
+  ///
+  /// Performing PlatformInitPreMemCallBack after PeiReadOnlyVariable2 PPI produced
+  ///
+  Status = PeiServicesNotifyPpi (&mPreMemNotifyList);
+
+  ///
+  /// After code reorangized, memorycallback will run because the PPI is already
+  /// installed when code run to here, it is supposed that the InstallEfiMemory is
+  /// done before.
+  ///
+  Status = PeiServicesNotifyPpi (&mMemDiscoveredNotifyList);
+
+  DEBUG ((DEBUG_INFO, "TigerlakeURvpInitPreMem End!\n"));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Configure GPIO and SIO before memory ready
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardInitBeforeMemoryInit(
+  VOID
+  )
+{
+
+  TigerlakeURvpInitPreMem();
+
+  return EFI_SUCCESS;
+}
+
+EFI_STATUS
+EFIAPI
+TigerlakeURvpBoardDebugInit(
+  VOID
+  )
+{
+  ///
+  /// Do Early PCH init
+  ///
+  return EFI_SUCCESS;
+}
+
+EFI_BOOT_MODE
+EFIAPI
+TigerlakeURvpBoardBootModeDetect(
+  VOID
+  )
+{
+  return BOOT_WITH_FULL_CONFIGURATION;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/TigerlakeURvpInit.h b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/TigerlakeURvpInit.h
new file mode 100644
index 0000000000..ccffcc6761
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/BoardInitLib/TigerlakeURvpInit.h
@@ -0,0 +1,23 @@
+/** @file
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#ifndef _TIGER_LAKE_U_RVP_INIT_H_
+#define _TIGER_LAKE_U_RVP_INIT_H_
+
+#include <Uefi.h>
+#include <PlatformBoardId.h>
+#include <Library/BaseLib.h>
+#include <Library/PcdLib.h>
+#include <Library/MemoryAllocationLib.h>
+#include <Library/DebugLib.h>
+#include <Ppi/SiPolicy.h>
+
+extern GPIO_INIT_CONFIG mGpioTableTglUDdr4[];
+extern UINT16 mGpioTableTglUDdr4Size;
+
+
+#endif // _TIGER_LAKE_U_RVP_INIT_H_
+
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
new file mode 100644
index 0000000000..6c2587391d
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.c
@@ -0,0 +1,212 @@
+/** @file
+  PEI Library Functions. Initialize GPIOs
+
+
+  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+  SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+
+#include <PiPei.h>
+#include <PeiPlatformHookLib.h>
+#include <Library/DebugLib.h>
+#include <Library/BaseMemoryLib.h>
+#include <Library/IoLib.h>
+#include <Library/HobLib.h>
+#include <Library/PcdLib.h>
+#include <Library/TimerLib.h>
+#include <Library/PchCycleDecodingLib.h>
+#include <Library/PciSegmentLib.h>
+#include <Library/PeiServicesLib.h>
+#include <Library/PmcLib.h>
+#include <Library/GpioNativeLib.h>
+#include <Library/GpioLib.h>
+#include <PlatformBoardConfig.h>
+#include <Library/PchPcrLib.h>
+#include <Library/GpioCheckConflictLib.h>
+
+#define SIO_RUNTIME_REG_BASE_ADDRESS                          0x0680
+
+#define RECOVERY_MODE_GPIO_PIN                    0                    // Platform specific @todo use PCD
+
+#define MANUFACTURE_MODE_GPIO_PIN                 0                    // Platform specific @todo use PCD
+
+/**
+  Configures GPIO
+
+  @param[in]  GpioTable       Point to Platform Gpio table
+  @param[in]  GpioTableCount  Number of Gpio table entries
+
+**/
+VOID
+ConfigureGpio (
+  IN GPIO_INIT_CONFIG                 *GpioDefinition,
+  IN UINT16                           GpioTableCount
+  )
+{
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() Start\n"));
+
+
+  CreateGpioCheckConflictHob (GpioDefinition, GpioTableCount);
+
+
+  GpioConfigurePads (GpioTableCount, GpioDefinition);
+
+  DEBUG ((DEBUG_INFO, "ConfigureGpio() End\n"));
+}
+
+/**
+  Configure GPIO group GPE tier.
+
+  @retval     none.
+**/
+VOID
+GpioGroupTierInitHook(
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook Start\n"));
+
+  DEBUG ((DEBUG_INFO, "GpioGroupTierInitHook End\n"));
+}
+
+/**
+  Configure single GPIO pad for touchpanel interrupt
+**/
+VOID
+TouchpanelGpioInit (
+  VOID
+  )
+{
+
+}
+
+/**
+  Configure GPIO Before Memory is not ready.
+
+**/
+VOID
+GpioInitPreMem (
+  VOID
+  )
+{
+  if (PcdGet32 (PcdBoardGpioTablePreMem) != 0 && PcdGet16 (PcdBoardGpioTablePreMemSize) != 0) {
+    DEBUG ((DEBUG_INFO, "Pre-mem Gpio Config\n"));
+    ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTablePreMem), (UINTN) PcdGet16 (PcdBoardGpioTablePreMemSize));
+  }
+}
+
+/**
+  Basic GPIO configuration before memory is ready
+
+**/
+VOID
+GpioInitEarlyPreMem (
+  VOID
+  )
+{
+
+}
+
+/**
+  Configure GPIO
+
+**/
+
+VOID
+GpioInit (
+  VOID
+  )
+{
+  DEBUG ((DEBUG_INFO, "Post-mem Gpio Config\n"));
+  ConfigureGpio ((VOID *) (UINTN) PcdGet32 (PcdBoardGpioTable), (UINTN) PcdGet16 (PcdBoardGpioTableSize));
+
+  TouchpanelGpioInit();
+
+  return;
+}
+
+/**
+  Configure Super IO
+
+**/
+VOID
+SioInit (
+  VOID
+  )
+{
+  //
+  // Program and Enable Default Super IO Configuration Port Addresses and range
+  //
+  PchLpcGenIoRangeSet (PcdGet16 (PcdLpcSioConfigDefaultPort) & (~0xF), 0x10);
+
+  PchLpcGenIoRangeSet (SIO_RUNTIME_REG_BASE_ADDRESS  & (~0x7F), 0x10);
+  return;
+}
+
+/**
+  Configure GPIO and SIO before memory ready
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInitPreMem (
+  VOID
+  )
+{
+  //
+  // Obtain Platform Info from HOB.
+  //
+  GpioInitPreMem ();
+  GpioGroupTierInitHook ();
+  SioInit ();
+
+  DEBUG ((DEBUG_INFO, "BoardInitPreMem Done\n"));
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Configure GPIO and SIO
+
+  @retval  EFI_SUCCESS   Operation success.
+**/
+EFI_STATUS
+BoardInit (
+  VOID
+  )
+{
+
+  GpioInit ();
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Do platform specific programming post-memory.
+
+  @retval  EFI_SUCCESS       The function completed successfully.
+**/
+
+EFI_STATUS
+PlatformSpecificInit (
+  VOID
+  )
+{
+
+  return EFI_SUCCESS;
+}
+
+/**
+  Early Board Configuration before memory is ready
+
+  @retval  EFI_SUCCESS  Operation success.
+**/
+EFI_STATUS
+BoardInitEarlyPreMem (
+  VOID
+  )
+{
+  GpioInitEarlyPreMem ();
+
+  return EFI_SUCCESS;
+}
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
new file mode 100644
index 0000000000..8e4ce47d5a
--- /dev/null
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/TigerlakeURvp/Library/PeiPlatformHookLib/PeiPlatformHooklib.inf
@@ -0,0 +1,58 @@
+## @file
+#
+#  Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>
+#  SPDX-License-Identifier: BSD-2-Clause-Patent
+#
+##
+
+[Defines]
+  INF_VERSION                    = 0x00010017
+  BASE_NAME                      = PeiPlatformHookLib
+  FILE_GUID                      = AD901798-B0DA-4B20-B90C-283F886E76D0
+  VERSION_STRING                 = 1.0
+  MODULE_TYPE                    = PEIM
+  LIBRARY_CLASS                  = PeiPlatformHookLib|PEIM PEI_CORE SEC
+
+[LibraryClasses]
+  DebugLib
+  BaseMemoryLib
+  IoLib
+  HobLib
+  PcdLib
+  TimerLib
+  PchCycleDecodingLib
+  GpioLib
+  PeiServicesLib
+  ConfigBlockLib
+  PmcLib
+  PchPcrLib
+  PciSegmentLib
+  GpioCheckConflictLib
+
+[Packages]
+  MdePkg/MdePkg.dec
+  TigerlakeOpenBoardPkg/OpenBoardPkg.dec
+  TigerlakeSiliconPkg/SiPkg.dec
+  IntelSiliconPkg/IntelSiliconPkg.dec
+
+[Pcd]
+  gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress                        ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdLpcSioConfigDefaultPort        ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdSioBaseAddress                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTable                 ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTableSize             ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMem           ## CONSUMES
+  gBoardModuleTokenSpaceGuid.PcdBoardGpioTablePreMemSize       ## CONSUMES
+
+[Sources]
+  PeiPlatformHooklib.c
+
+[Ppis]
+  gEfiPeiReadOnlyVariable2PpiGuid               ## CONSUMES
+  gSiPolicyPpiGuid                              ## CONSUMES
+
+[Guids]
+  gSaDataHobGuid                                ## CONSUMES
+  gEfiGlobalVariableGuid                        ## CONSUMES
+  gGpioCheckConflictHobGuid                     ## CONSUMES
+
-- 
2.24.0.windows.2