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[82.27.183.148]) by smtp.gmail.com with ESMTPSA id z185sm4108622wmb.0.2021.02.10.11.04.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 10 Feb 2021 11:04:51 -0800 (PST) Date: Wed, 10 Feb 2021 19:04:49 +0000 From: "Leif Lindholm" To: Ling Jia Cc: devel@edk2.groups.io Subject: Re: [PATCH v1 05/10] Silicon/Phytium: Added PciHostBridgeLib to FT2000/4 Message-ID: <20210210190449.GQ1664@vanye> References: <20210205100630.46848-1-jialing@phytium.com.cn> <20210205100630.46848-17-jialing@phytium.com.cn> MIME-Version: 1.0 In-Reply-To: <20210205100630.46848-17-jialing@phytium.com.cn> User-Agent: Mutt/1.10.1 (2018-07-13) Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Fri, Feb 05, 2021 at 18:06:25 +0800, Ling Jia wrote: > The Pci host bridge library is mainly > to get Pci bridge information. > > Signed-off-by: Ling Jia > --- > Platform/Phytium/DurianPkg/DurianPkg.dsc | 9 + > Platform/Phytium/DurianPkg/DurianPkg.fdf | 6 + > Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf | 47 ++++++ > Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c | 175 ++++++++++++++++++++ > 4 files changed, 237 insertions(+) > > diff --git a/Platform/Phytium/DurianPkg/DurianPkg.dsc b/Platform/Phytium/DurianPkg/DurianPkg.dsc > index 0b615081c83b..8ca167329d99 100644 > --- a/Platform/Phytium/DurianPkg/DurianPkg.dsc > +++ b/Platform/Phytium/DurianPkg/DurianPkg.dsc > @@ -37,6 +37,7 @@ [LibraryClasses.common] > [LibraryClasses.common.DXE_DRIVER] > # Pci dependencies > PciSegmentLib|Silicon/Phytium/FT2000-4Pkg/Library/PciSegmentLib/PciSegmentLib.inf > + PciHostBridgeLib|Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf > > ################################################################################ > # > @@ -243,6 +244,14 @@ [Components.common] > MdeModulePkg/Bus/Scsi/ScsiDiskDxe/ScsiDiskDxe.inf > MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf > > + # > + # PCI Support > + # > + ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf > + MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + MdeModulePkg/Bus/Pci/NonDiscoverablePciDeviceDxe/NonDiscoverablePciDeviceDxe.inf > + > # > # The following 2 module perform the same work except one operate variable. > # Only one of both should be put into fdf. > diff --git a/Platform/Phytium/DurianPkg/DurianPkg.fdf b/Platform/Phytium/DurianPkg/DurianPkg.fdf > index 58317f24c725..96736693db83 100644 > --- a/Platform/Phytium/DurianPkg/DurianPkg.fdf > +++ b/Platform/Phytium/DurianPkg/DurianPkg.fdf > @@ -135,6 +135,12 @@ [FV.FvMain] > INF FatPkg/EnhancedFatDxe/Fat.inf > INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf > > + # > + # PCI Support > + # > + INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf > + INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf > + > # > # SATA Controller > # > diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf > new file mode 100644 > index 000000000000..0e6f0797b0fe > --- /dev/null > +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.inf > @@ -0,0 +1,47 @@ > +#/** @file > +# PCI Host Bridge Library instance for Phytium SOC. > +# > +# Copyright (C) 2020, Phytium Technology Co, Ltd. All rights reserved.
> +# > +# SPDX-License-Identifier: BSD-2-Clause-Patent > +# > +#**/ > + > +[Defines] > + INF_VERSION = 0x0001001b > + BASE_NAME = PciHostBridgeLib > + FILE_GUID = f965de0e-40fe-11eb-8290-3f9d1f895a80 > + MODULE_TYPE = DXE_DRIVER > + VERSION_STRING = 1.0 > + LIBRARY_CLASS = PciHostBridgeLib|DXE_DRIVER > + > +# > +# The following information is for reference only and not required by the build > +# tools. > +# > +# VALID_ARCHITECTURES = ARM AARCH64 > +# > + > +[Sources] > + PciHostBridgeLib.c > + > +[Packages] > + ArmPkg/ArmPkg.dec > + MdePkg/MdePkg.dec > + MdeModulePkg/MdeModulePkg.dec > + Silicon/Phytium/PhytiumCommonPkg/PhytiumCommonPkg.dec > + > +[LibraryClasses] > + DebugLib > + > +[Guids] > + > +[FixedPcd] > + gArmTokenSpaceGuid.PcdPciBusMin > + gArmTokenSpaceGuid.PcdPciBusMax > + gArmTokenSpaceGuid.PcdPciIoBase > + gArmTokenSpaceGuid.PcdPciIoSize > + gArmTokenSpaceGuid.PcdPciMmio32Base > + gArmTokenSpaceGuid.PcdPciMmio32Size > + gArmTokenSpaceGuid.PcdPciMmio64Base > + gArmTokenSpaceGuid.PcdPciMmio64Size > diff --git a/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > new file mode 100644 > index 000000000000..a5bd7880d4ad > --- /dev/null > +++ b/Silicon/Phytium/FT2000-4Pkg/Library/PciHostBridgeLib/PciHostBridgeLib.c > @@ -0,0 +1,175 @@ > +/** @file > + PCI Host Bridge Library instance for Phytium SOC. > + > + Copyright (C) 2020, Phytium Technology Co Ltd. All rights reserved.
> + > + SPDX-License-Identifier: BSD-2-Clause-Patent > + > +**/ > + > +#include > +#include > +#include > +#include > +#include > + > +#pragma pack(1) > + > +typedef struct { > + ACPI_HID_DEVICE_PATH AcpiDevicePath; > + EFI_DEVICE_PATH_PROTOCOL EndDevicePath; > +} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH; > + > +#pragma pack () > + > +#define END_DEVICE_PATH_DEF { END_DEVICE_PATH_TYPE, \ > + END_ENTIRE_DEVICE_PATH_SUBTYPE, \ > + { END_DEVICE_PATH_LENGTH, 0 } \ > + } > + > +#define ACPI_DEVICE_PATH_DEF(UID) {{ ACPI_DEVICE_PATH, ACPI_DP, \ > + {(UINT8)(sizeof (ACPI_HID_DEVICE_PATH)), (UINT8)(sizeof (ACPI_HID_DEVICE_PATH) >> 8)} \ > + }, \ > + EISA_PNP_ID (0x0A03), UID \ > + } > + > +STATIC CONST EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath[] = { > + { > + ACPI_DEVICE_PATH_DEF(0), > + END_DEVICE_PATH_DEF > + }, > +}; > + > +GLOBAL_REMOVE_IF_UNREFERENCED > +CHAR16 *mPciHostBridgeLibAcpiAddressSpaceTypeStr[] = { > + L"Mem", L"I/O", L"Bus" > +}; > + > +STATIC PCI_ROOT_BRIDGE mRootBridge = { > + 0, // Segment > + 0, // Supports > + 0, // Attributes > + TRUE, // DmaAbove4G > + FALSE, // NoExtendedConfigSpace > + FALSE, // ResourceAssigned > + EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes > + EFI_PCI_HOST_BRIDGE_MEM64_DECODE, > + { > + // Bus > + FixedPcdGet32 (PcdPciBusMin), > + FixedPcdGet32 (PcdPciBusMax) > + }, { > + // Io > + FixedPcdGet64 (PcdPciIoBase), > + FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1 > + }, { > + // Mem > + FixedPcdGet32 (PcdPciMmio32Base), > + FixedPcdGet32 (PcdPciMmio32Base) + (FixedPcdGet32 (PcdPciMmio32Size) - 1) > + //0x7FFFFFFF > + }, { > + // MemAbove4G > + FixedPcdGet64 (PcdPciMmio64Base), > + FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1 > + }, { > + // PMem > + MAX_UINT64, > + 0 > + }, { > + // PMemAbove4G > + MAX_UINT64, > + 0 > + }, > + (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath > +}; > + > +/** > + Return all the root bridge instances in an array. > + > + @param[out] Count Return the count of root bridge instances. > + > + @return All the root bridge instances in an array. > + The array should be passed into PciHostBridgeFreeRootBridges() > + when it's not used. > + > +**/ > +PCI_ROOT_BRIDGE * > +EFIAPI > +PciHostBridgeGetRootBridges ( > + OUT UINTN *Count > + ) > +{ > + *Count = 1; > + return &mRootBridge; > +} > + > + > +/** > + Free the root bridge instances array returned from PciHostBridgeGetRootBridges(). > + > + @param[in] Bridges The root bridge instances array. > + @param[in] Count The count of the array. > + > +**/ > +VOID > +EFIAPI > +PciHostBridgeFreeRootBridges ( > + IN PCI_ROOT_BRIDGE *Bridges, > + IN UINTN Count > + ) > +{ > + > +} > + > + > +/** > + Inform the platform that the resource conflict happens. > + > + @param[in] HostBridgeHandle Handle of the Host Bridge. > + @param[in] Configuration Pointer to PCI I/O and PCI memory resource > + descriptors. The Configuration contains the resources > + for all the root bridges. The resource for each root > + bridge is terminated with END descriptor and an > + additional END is appended indicating the end of the > + entire resources. The resource descriptor field > + values follow the description in > + EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL > + SubmitResources(). > + > +**/ > +VOID > +EFIAPI > +PciHostBridgeResourceConflict ( > + IN EFI_HANDLE HostBridgeHandle, > + IN VOID *Configuration > + ) > +{ > + EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor; > + > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration; > + while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) { > + for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) { > + ASSERT (Descriptor->ResType < > + ARRAY_SIZE (mPciHostBridgeLibAcpiAddressSpaceTypeStr)); > + DEBUG ((DEBUG_INFO, " %s: Length/Alignment = 0x%lx / 0x%lx\n", > + mPciHostBridgeLibAcpiAddressSpaceTypeStr[Descriptor->ResType], > + Descriptor->AddrLen, Descriptor->AddrRangeMax > + )); > + if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) { > + DEBUG ((DEBUG_INFO, " Granularity/SpecificFlag = %ld / %02x%s\n", > + Descriptor->AddrSpaceGranularity, Descriptor->SpecificFlag, > + ((Descriptor->SpecificFlag & > + EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE > + ) != 0) ? L" (Prefetchable)" : L"" This would be more readable with the test broken out separately. BOOL IsPrefetchable; IsPrefetchable = (Descriptor->SpecificFlag & EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE) != 0; Then used like: Prefetchable ? L" (Prefetchable)" : L""; / Leif > + )); > + } > + } > + // > + // Skip the end descriptor for root bridge > + // > + ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR); > + Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)( > + (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1 > + ); > + } > +} > -- > 2.25.1 >