* [PATCH edk2-platforms v1 01/12] Platform/ARM/VExpressPkg: FVP RevC SysID.Rev defintion
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 02/12] Platform/ARM/VExpressPkg: Add PCIe Host Bridge lib for FVP Sami Mujawar
` (11 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
The Base Platform RevC model is a configuration of the Base Platform
that includes a PCIe subsystem. It also includes system IP like SMMUv3.
The Base Platform FVP model and the Base Platform RevC FVP model
can be differentiated by examining the System ID register. For the
FVP RevC model the SysID.Rev is 0x2. Therefore, add this definition
so that software can read the System ID register to detect a FVP
RevC model.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h b/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h
index c06adb159ec5532b1c77429ee0a4f6f3f4c018e3..1fe13809d6f77936abb3e13a1eb30c5cfb54d23f 100644
--- a/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h
+++ b/Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h
@@ -1,7 +1,7 @@
/** @file
* Header defining Versatile Express constants (Base addresses, sizes, flags)
*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -131,4 +131,7 @@
#define ARM_FVP_BASE_SYS_ID (ARM_FVP_BASE_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
#define ARM_FVP_FOUNDATION_SYS_ID (ARM_FVP_FOUNDATION_BOARD_SYS_ID | ARM_FVP_GIC_BASE_MMAP)
+// FVP RevC model revision.
+#define ARM_FVP_BASE_REVC_REV (UINT32)(0x2UL << 28)
+
#endif /* VEXPRESSMOTHERBOARD_H_ */
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 02/12] Platform/ARM/VExpressPkg: Add PCIe Host Bridge lib for FVP
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 01/12] Platform/ARM/VExpressPkg: FVP RevC SysID.Rev defintion Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 03/12] Platform/ARM/VExpressPkg: Memory map for FVP RevC model Sami Mujawar
` (10 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
The Base Platform RevC (FVP_Base_RevC-2xAEMv8A model) includes a PCI
subsystem. It has a PCIe config region and two PCIe memory regions.
To enable PCIe support for the FVP RevC model add an instance of the
PCIe Host Bridge library.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c | 208 ++++++++++++++++++++
Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf | 48 +++++
Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni | 14 ++
3 files changed, 270 insertions(+)
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c
new file mode 100644
index 0000000000000000000000000000000000000000..54add33b8912db93aaa634907c625a032436f106
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c
@@ -0,0 +1,208 @@
+/** @file
+ PCI Host Bridge Library instance for ARM FVP Model
+
+ Copyright (c) 2021, Arm Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+**/
+#include <PiDxe.h>
+#include <Library/DebugLib.h>
+#include <Library/DevicePathLib.h>
+#include <Library/IoLib.h>
+#include <Library/PcdLib.h>
+#include <Library/PciHostBridgeLib.h>
+#include <Protocol/PciHostBridgeResourceAllocation.h>
+#include <Protocol/PciRootBridgeIo.h>
+#include <ArmPlatform.h>
+
+#pragma pack(1)
+
+/** A structure describing the PCI root bridge device path.
+*/
+typedef struct {
+ /// ACPI Device path.
+ ACPI_HID_DEVICE_PATH AcpiDevicePath;
+ /// END Device Path tag.
+ EFI_DEVICE_PATH_PROTOCOL EndDevicePath;
+} EFI_PCI_ROOT_BRIDGE_DEVICE_PATH;
+
+#pragma pack ()
+
+STATIC EFI_PCI_ROOT_BRIDGE_DEVICE_PATH mEfiPciRootBridgeDevicePath = {
+ // ACPI device path
+ {
+ {
+ ACPI_DEVICE_PATH,
+ ACPI_DP,
+ {
+ (UINT8)(sizeof (ACPI_HID_DEVICE_PATH)),
+ (UINT8)((sizeof (ACPI_HID_DEVICE_PATH)) >> 8)
+ }
+ },
+ EISA_PNP_ID (0x0A08), // PCIe
+ 0
+ },
+ // End device path tag
+ {
+ END_DEVICE_PATH_TYPE,
+ END_ENTIRE_DEVICE_PATH_SUBTYPE,
+ {
+ END_DEVICE_PATH_LENGTH,
+ 0
+ }
+ }
+};
+
+STATIC PCI_ROOT_BRIDGE mRootBridge = {
+ 0, // Segment
+ 0, // Supports
+ 0, // Attributes
+ FALSE, // DmaAbove4G
+ FALSE, // NoExtendedConfigSpace
+ FALSE, // ResourceAssigned
+ EFI_PCI_HOST_BRIDGE_COMBINE_MEM_PMEM | // AllocationAttributes
+ EFI_PCI_HOST_BRIDGE_MEM64_DECODE,
+ {
+ // Bus
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ },
+ {
+ // Io
+ FixedPcdGet64 (PcdPciIoBase),
+ FixedPcdGet64 (PcdPciIoBase) + FixedPcdGet64 (PcdPciIoSize) - 1
+ },
+ {
+ // Mem
+ FixedPcdGet32 (PcdPciMmio32Base),
+ FixedPcdGet32 (PcdPciMmio32Base) + FixedPcdGet32 (PcdPciMmio32Size) - 1
+ },
+ {
+ // MemAbove4G
+ FixedPcdGet64 (PcdPciMmio64Base),
+ FixedPcdGet64 (PcdPciMmio64Base) + FixedPcdGet64 (PcdPciMmio64Size) - 1
+ },
+ {
+ // PMem
+ MAX_UINT64,
+ 0
+ },
+ {
+ // PMemAbove4G
+ MAX_UINT64,
+ 0
+ },
+ (EFI_DEVICE_PATH_PROTOCOL *)&mEfiPciRootBridgeDevicePath
+};
+
+#ifndef MDEPKG_NDEBUG
+STATIC CONST CHAR16 mAcpiAddrSpaceTypeStr[][4] = {
+ L"Mem", L"I/O", L"Bus"
+};
+#endif
+
+/**
+ Return all the root bridge instances in an array.
+
+ @param [out] Count Return the count of root bridge instances.
+
+ @returns All the root bridge instances in an array.
+ The array should be passed into PciHostBridgeFreeRootBridges()
+ when it's not used.
+**/
+PCI_ROOT_BRIDGE *
+EFIAPI
+PciHostBridgeGetRootBridges (
+ OUT UINTN *Count
+ )
+{
+ UINT32 SysId;
+
+ // Check if the platform is FVP RevC
+ SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
+ if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) {
+ // There is a single Root Bridge instance on the FVP RevC Model
+ *Count = 1;
+ return &mRootBridge;
+ }
+
+ // Other FVP models do not have PCIe
+ *Count = 0;
+ return NULL;
+}
+
+/**
+ Free the root bridge instances array returned
+ from PciHostBridgeGetRootBridges().
+
+ @param [in] Bridges The root bridge instances array.
+ @param [in] Count The count of the array.
+**/
+VOID
+EFIAPI
+PciHostBridgeFreeRootBridges (
+ IN PCI_ROOT_BRIDGE *Bridges,
+ IN UINTN Count
+ )
+{
+}
+
+/**
+ Inform the platform that the resource conflict happens.
+
+ @param [in] HostBridgeHandle Handle of the Host Bridge.
+ @param [in] Configuration Pointer to PCI I/O and PCI memory resource
+ descriptors. The Configuration contains the
+ resources for all the root bridges. The
+ resource for each root bridge is terminated
+ with END descriptor and an additional END is
+ appended indicating the end of the entire
+ resources. The resource descriptor field
+ values follow the description in
+ EFI_PCI_HOST_BRIDGE_RESOURCE_ALLOCATION_PROTOCOL
+ .SubmitResources().
+**/
+VOID
+EFIAPI
+PciHostBridgeResourceConflict (
+ IN EFI_HANDLE HostBridgeHandle,
+ IN VOID *Configuration
+ )
+{
+ EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptor;
+ UINTN RootBridgeIndex;
+
+ DEBUG ((DEBUG_ERROR, "PciHostBridge: Resource conflict happens!\n"));
+
+ RootBridgeIndex = 0;
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *) Configuration;
+ while (Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR) {
+ DEBUG ((DEBUG_ERROR, "RootBridge[%d]:\n", RootBridgeIndex++));
+ for (; Descriptor->Desc == ACPI_ADDRESS_SPACE_DESCRIPTOR; Descriptor++) {
+ ASSERT (Descriptor->ResType < ARRAY_SIZE (mAcpiAddrSpaceTypeStr));
+ DEBUG ((
+ DEBUG_ERROR,
+ " %s: Length/Alignment = 0x%lx / 0x%lx\n",
+ mAcpiAddrSpaceTypeStr[Descriptor->ResType],
+ Descriptor->AddrLen, Descriptor->AddrRangeMax
+ ));
+ if (Descriptor->ResType == ACPI_ADDRESS_SPACE_TYPE_MEM) {
+ DEBUG ((
+ DEBUG_ERROR,
+ " Granularity/SpecificFlag = %ld / %02x%s\n",
+ Descriptor->AddrSpaceGranularity,
+ Descriptor->SpecificFlag,
+ ((Descriptor->SpecificFlag &
+ EFI_ACPI_MEMORY_RESOURCE_SPECIFIC_FLAG_CACHEABLE_PREFETCHABLE
+ ) != 0) ? L" (Prefetchable)" : L""
+ ));
+ }
+ }
+
+ // Skip the END descriptor for root bridge
+ ASSERT (Descriptor->Desc == ACPI_END_TAG_DESCRIPTOR);
+ Descriptor = (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *)(
+ (EFI_ACPI_END_TAG_DESCRIPTOR *)Descriptor + 1
+ );
+ }
+}
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf
new file mode 100644
index 0000000000000000000000000000000000000000..e5080074e2e96f258b004a086ec61af8cc263fd6
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf
@@ -0,0 +1,48 @@
+## @file
+# PCI Host Bridge Library instance for ARM FVP Model
+#
+# Copyright (c) 2021, Arm Ltd. All rights reserved.<BR>
+#
+# SPDX-License-Identifier: BSD-2-Clause-Patent
+##
+
+[Defines]
+ INF_VERSION = 0x0001001B
+ BASE_NAME = ArmVExpressPciHostBridgeLib
+ MODULE_UNI_FILE = ArmVExpressPciHostBridgeLib.uni
+ FILE_GUID = 4226FB49-3049-4A60-AF7A-90B6DBD4BF26
+ MODULE_TYPE = DXE_DRIVER
+ VERSION_STRING = 1.0
+ LIBRARY_CLASS = PciHostBridgeLib
+
+#
+# The following information is for reference only and not required by the build
+# tools.
+#
+# VALID_ARCHITECTURES = AARCH64 ARM
+#
+
+[Sources]
+ ArmVExpressPciHostBridgeLib.c
+
+[Packages]
+ ArmPkg/ArmPkg.dec
+ MdeModulePkg/MdeModulePkg.dec
+ MdePkg/MdePkg.dec
+ Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
+
+[LibraryClasses]
+ IoLib
+
+[FixedPcd]
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
+ gArmTokenSpaceGuid.PcdPciIoBase
+ gArmTokenSpaceGuid.PcdPciIoSize
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni
new file mode 100644
index 0000000000000000000000000000000000000000..8913c7fea0d825dabc436eb3b7029e84bf08167f
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni
@@ -0,0 +1,14 @@
+// /** @file
+// Instance of PCI Host Bridge Library for FVP Platform.
+//
+// Copyright (c) 2021, Arm Ltd. All rights reserved.<BR>
+//
+// SPDX-License-Identifier: BSD-2-Clause-Patent
+//
+// **/
+
+#langdef en-US "English"
+
+#string STR_MODULE_ABSTRACT #language en-US "Instance of PCI Host Bridge Library for FVP Platform."
+
+#string STR_MODULE_DESCRIPTION #language en-US "Instance of PCI Host Bridge Library for FVP Platform."
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 03/12] Platform/ARM/VExpressPkg: Memory map for FVP RevC model
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 01/12] Platform/ARM/VExpressPkg: FVP RevC SysID.Rev defintion Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 02/12] Platform/ARM/VExpressPkg: Add PCIe Host Bridge lib for FVP Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 04/12] Platform/ARM/VExpressPkg: Configure SMMUv3 for FVP RevC Sami Mujawar
` (9 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
FVP Base Platform RevC is a configuration of the Base Platform that
includes a SMMUv3 and a PCIe subsystem. The PCIe subsystem has a
PCIe config region (ECAM) and two PCIe memory regions.
Add the SMMUv3 and PCIe config and memory regions to the memory map
so that the firmware can access and configure these components.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 6 +++-
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | 12 +++++++-
Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 31 ++++++++++++++++++--
3 files changed, 45 insertions(+), 4 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
index 499f62b2dc405c777e2266f4cbdaba963f5d26a2..96cc131dac91e428881f2506d277222490b649cb 100644
--- a/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
+++ b/Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h
@@ -1,7 +1,7 @@
/** @file
* Header defining Versatile Express constants (Base addresses, sizes, flags)
*
-* Copyright (c) 2011, ARM Limited. All rights reserved.
+* Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -73,4 +73,8 @@
#define SBSA_WATCHDOG_BASE 0x2a440000
#define SBSA_WATCHDOG_SIZE (2 * SIZE_64KB)
+// SMMUv3 - FVP RevC
+#define FVP_REVC_SMMUV3_BASE 0x2B400000
+#define FVP_REVC_SMMUV3_SIZE SIZE_1MB
+
#endif
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
index d3441b0852c67b697067191f6b46f3ac6dce7707..929dadc28a84cdb2ca6c6a733b75a5c352922112 100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf
@@ -1,5 +1,5 @@
#/* @file
-# Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -54,5 +54,15 @@ [FixedPcd]
gArmPlatformTokenSpaceGuid.PcdArmMaliDpBase
gArmPlatformTokenSpaceGuid.PcdArmMaliDpMemoryRegionLength
+ # PCI Configuration space
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base
+ gArmTokenSpaceGuid.PcdPciMmio32Size
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base
+ gArmTokenSpaceGuid.PcdPciMmio64Size
+
[Ppis]
gArmMpCoreInfoPpiGuid
diff --git a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
index 21ffd64fb6350608b661298e4f336493696081df..13f181834ba8a3a8225a18147cbdbbde3807eb53 100644
--- a/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
+++ b/Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c
@@ -1,6 +1,6 @@
/** @file
*
-* Copyright (c) 2011-2018, ARM Limited. All rights reserved.
+* Copyright (c) 2011-2021, Arm Limited. All rights reserved.
*
* SPDX-License-Identifier: BSD-2-Clause-Patent
*
@@ -17,7 +17,7 @@
#define DP_BASE_DESCRIPTOR ((FixedPcdGet64 (PcdArmMaliDpBase) != 0) ? 1 : 0)
// Number of Virtual Memory Map Descriptors
-#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (10 + DP_BASE_DESCRIPTOR)
+#define MAX_VIRTUAL_MEMORY_MAP_DESCRIPTORS (14 + DP_BASE_DESCRIPTOR)
// DDR attributes
#define DDR_ATTRIBUTES_CACHED ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
@@ -161,6 +161,33 @@ ArmPlatformGetVirtualMemoryMap (
VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
}
+ // Map the PCI configration and memory space if the platform is FVP RevC.
+ if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) {
+ // SMMUv3
+ VirtualMemoryTable[++Index].PhysicalBase = FVP_REVC_SMMUV3_BASE;
+ VirtualMemoryTable[Index].VirtualBase = FVP_REVC_SMMUV3_BASE;
+ VirtualMemoryTable[Index].Length = FVP_REVC_SMMUV3_SIZE;
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCI Configuration Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciExpressBaseAddress);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciExpressBaseSize);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // PCI Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet32 (PcdPciMmio32Base);
+ VirtualMemoryTable[Index].Length = FixedPcdGet32 (PcdPciMmio32Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+
+ // 64-bit PCI Memory Space
+ VirtualMemoryTable[++Index].PhysicalBase = FixedPcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].VirtualBase = FixedPcdGet64 (PcdPciMmio64Base);
+ VirtualMemoryTable[Index].Length = FixedPcdGet64 (PcdPciMmio64Size);
+ VirtualMemoryTable[Index].Attributes = ARM_MEMORY_REGION_ATTRIBUTE_DEVICE;
+ }
+
// Map sparse memory region if present
if (HasSparseMemory) {
VirtualMemoryTable[++Index].PhysicalBase = SparseMemoryBase;
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 04/12] Platform/ARM/VExpressPkg: Configure SMMUv3 for FVP RevC
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (2 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 03/12] Platform/ARM/VExpressPkg: Memory map for FVP RevC model Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 05/12] Platform/ARM/VExpressPkg: Helper macro to map reference token Sami Mujawar
` (8 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Base Platform RevC is a configuration of the Base Platform
that includes a SMMUv3. TF-A configures the SMMUv3 to 'Abort
all incoming transactions in order to implement a default
deny policy on reset'. This prevents the firmware from using
the AHCI-SATA disk that is available as a PCIe device.
According to Server Base System Architecture (SBSA) 6.1,
Section A Level 3 - firmware, Sub-section A.1 Memory map,
'All Non-secure on-chip masters in a base server system
that are expected to be used by the platform firmware must
be capable of addressing all of the Non-secure address
space. If the master goes through a SMMU then the master
must be capable of addressing all of the Non-secure address
space even when the SMMU is off.'
Therefore, configure the SMMUv3 to set Non-secure streams
to bypass the SMMU. On firmware hand-off the OS is expected
to reconfigure the SMMU.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c | 110 +++++++++++++++++++-
Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf | 4 +-
2 files changed, 112 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c
index 189069484b57533ce43bcdccb30c85c882fc7ffb..1f1dfd3de5b9aedc1515d55a15963df75a295326 100644
--- a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c
+++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c
@@ -1,6 +1,6 @@
/** @file
- Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+ Copyright (c) 2013-2021, Arm Ltd. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@@ -11,6 +11,8 @@
#include <Library/ArmShellCmdLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/DebugLib.h>
+#include <Library/IoLib.h>
+#include <Library/TimerLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/VirtioMmioDeviceLib.h>
@@ -18,6 +20,13 @@
#define ARM_FVP_BASE_VIRTIO_BLOCK_BASE 0x1c130000
+// SMMUv3 Global Bypass Attribute (GBPA) register offset.
+#define SMMU_GBPA 0x0044
+
+// SMMU_GBPA register fields.
+#define SMMU_GBPA_UPDATE BIT31
+#define SMMU_GBPA_ABORT BIT20
+
#pragma pack(1)
typedef struct {
VENDOR_DEVICE_PATH Vendor;
@@ -49,6 +58,92 @@ VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath =
};
/**
+ Poll the SMMU register and test the value based on the mask.
+
+ @param [in] SmmuReg Base address of the SMMU register.
+ @param [in] Mask Mask of register bits to monitor.
+ @param [in] Value Expected value.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_TIMEOUT Timeout.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SmmuV3Poll (
+ IN UINT64 SmmuReg,
+ IN UINT32 Mask,
+ IN UINT32 Value
+ )
+{
+ UINT32 RegVal;
+ UINTN Count;
+
+ // Set 1ms timeout value.
+ Count = 10;
+ do {
+ RegVal = MmioRead32 (SmmuReg);
+ if ((RegVal & Mask) == Value) {
+ return EFI_SUCCESS;
+ }
+ MicroSecondDelay (100);
+ } while ((--Count) > 0);
+
+ DEBUG ((DEBUG_ERROR, "Timeout polling SMMUv3 register @%p\n", SmmuReg));
+ DEBUG ((
+ DEBUG_ERROR,
+ "Read value 0x%x, expected 0x%x\n",
+ RegVal,
+ ((Value == 0) ? (RegVal & ~Mask) : (RegVal | Mask))
+ ));
+ return EFI_TIMEOUT;
+}
+
+/**
+ Initialise the SMMUv3 to set Non-secure streams to bypass the SMMU.
+
+ @param [in] SmmuReg Base address of the SMMUv3.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_TIMEOUT Timeout.
+**/
+STATIC
+EFI_STATUS
+EFIAPI
+SmmuV3Init (
+ IN UINT64 SmmuBase
+ )
+{
+ EFI_STATUS Status;
+ UINT32 RegVal;
+
+ // Attribute update has completed when SMMU_(S)_GBPA.Update bit is 0.
+ Status = SmmuV3Poll (SmmuBase + SMMU_GBPA, SMMU_GBPA_UPDATE, 0);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ // SMMU_(S)_CR0 resets to zero with all streams bypassing the SMMU,
+ // so just abort all incoming transactions.
+ RegVal = MmioRead32 (SmmuBase + SMMU_GBPA);
+
+ // TF-A configures the SMMUv3 to abort all incoming transactions.
+ // Clear the SMMU_GBPA.ABORT to allow Non-secure streams to bypass
+ // the SMMU.
+ RegVal &= ~SMMU_GBPA_ABORT;
+ RegVal |= SMMU_GBPA_UPDATE;
+
+ MmioWrite32 (SmmuBase + SMMU_GBPA, RegVal);
+
+ Status = SmmuV3Poll (SmmuBase + SMMU_GBPA, SMMU_GBPA_UPDATE, 0);
+ if (EFI_ERROR (Status)) {
+ return Status;
+ }
+
+ return EFI_SUCCESS;
+}
+
+/**
* Generic UEFI Entrypoint for 'ArmFvpDxe' driver
* See UEFI specification for the details of the parameters
*/
@@ -60,6 +155,7 @@ ArmFvpInitialise (
)
{
EFI_STATUS Status;
+ UINT32 SysId;
Status = gBS->InstallProtocolInterface (&ImageHandle,
&gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE,
@@ -80,5 +176,17 @@ ArmFvpInitialise (
DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n"));
}
+ // If FVP RevC - Configure SMMUv3 to set NS transactions in bypass mode.
+ SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
+ if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) {
+ Status = SmmuV3Init (FVP_REVC_SMMUV3_BASE);
+ if (EFI_ERROR (Status)) {
+ DEBUG ((
+ DEBUG_ERROR,
+ "ArmFvpDxe: Failed to initialise SMMUv3 in bypass mode.\n"
+ ));
+ }
+ }
+
return Status;
}
diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf
index a4021c2d9e241845736eea428a479a4abddd6413..c5f41795310141ae9d7c175c26d5694590a0a08a 100644
--- a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf
+++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf
@@ -1,6 +1,6 @@
#/** @file
#
-# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.<BR>
+# Copyright (c) 2013-2021, Arm Ltd. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -28,6 +28,8 @@ [Packages]
[LibraryClasses]
ArmShellCmdRunAxfLib
BaseMemoryLib
+ IoLib
+ TimerLib
UefiDriverEntryPoint
UefiBootServicesTableLib
VirtioMmioDeviceLib
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 05/12] Platform/ARM/VExpressPkg: Helper macro to map reference token
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (3 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 04/12] Platform/ARM/VExpressPkg: Configure SMMUv3 for FVP RevC Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 06/12] Platform/ARM/VExpressPkg: ACPI support for FVP RevC model Sami Mujawar
` (7 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Introduce helper macro REFERENCE_TOKEN() to map reference tokens.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 3 +--
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 6 ++++++
2 files changed, 7 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 3298f9f9f79a2b23f181d3e961298f1c366976ee..49aa16184a2da587471239a7c90ed864f963896c 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -150,8 +150,7 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
// The number of timer frames implemented in the GT Block
FVP_TIMER_FRAMES_COUNT,
// Reference token for the GT Block timer frame list
- (CM_OBJECT_TOKEN)((UINT8*)&VExpressPlatRepositoryInfo +
- OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, GTBlock0TimerInfo))
+ REFERENCE_TOKEN (GTBlock0TimerInfo)
}
},
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
index c25ba9fac52fe049236948185dfc052c44a71e4b..c21f160dd082bddb9e8e1ab666143887d67869cd 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -71,6 +71,12 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
);
+/** A helper macro for mapping a reference token.
+*/
+#define REFERENCE_TOKEN(Field) \
+ (CM_OBJECT_TOKEN)((UINT8*)&VExpressPlatRepositoryInfo + \
+ OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field))
+
/** The number of CPUs
*/
#define PLAT_CPU_COUNT 8
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 06/12] Platform/ARM/VExpressPkg: ACPI support for FVP RevC model
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (4 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 05/12] Platform/ARM/VExpressPkg: Helper macro to map reference token Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 07/12] Platform/ARM/VExpressPkg: Add " Sami Mujawar
` (6 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Base Platform RevC is a configuration of the Base Platform that includes
a PCIe subsystem and a SMMUv3. It also has an AHCI-SATA disk controller
as a device on the PCIe bus.
To enable an OS to use these features add the following ACPI tables:
- IORT
- MCFG
- SSDT PCIe
Also add checks such that these additional tables are only installed if
the FVP model is RevC. This allows a unified firmware for use with both
the FVP_Base_AEMv8A-AEMv8A model and the FVP_Base_RevC-2xAEMv8A model.
Note: The CPU affinities are shifted in the FVP_Base_RevC-2xAEMv8A model
and this is adjusted in InitializePlatformRepository().
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl | 204 ++++++++++++
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 349 +++++++++++++++++++-
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 30 +-
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf | 10 +-
4 files changed, 588 insertions(+), 5 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
new file mode 100644
index 0000000000000000000000000000000000000000..e4b5a02cc9571743c4a0300a0657f090ae996326
--- /dev/null
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
@@ -0,0 +1,204 @@
+/** @file
+ SSDT for FVP PCIe
+
+ Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.<BR>
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
+
+**/
+
+#include "ArmPlatform.h"
+
+/*
+ See ACPI 6.1 Section 6.2.13
+
+ There are two ways that _PRT can be used.
+
+ In the first model, a PCI Link device is used to provide additional
+ configuration information such as whether the interrupt is Level or
+ Edge triggered, it is active High or Low, Shared or Exclusive, etc.
+
+ In the second model, the PCI interrupts are hardwired to specific
+ interrupt inputs on the interrupt controller and are not
+ configurable. In this case, the Source field in _PRT does not
+ reference a device, but instead contains the value zero, and the
+ Source Index field contains the global system interrupt to which the
+ PCI interrupt is hardwired.
+
+ We use the first model with link indirection to set the correct
+ interrupt type as PCI defaults (Level Triggered, Active Low) are not
+ compatible with GICv2.
+*/
+#define LNK_DEVICE(Unique_Id, Link_Name, irq) \
+ Device (Link_Name) { \
+ Name (_HID, EISAID("PNP0C0F")) \
+ Name (_UID, Unique_Id) \
+ Name (_PRS, ResourceTemplate() { \
+ Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \
+ }) \
+ Method (_CRS, 0) { Return (_PRS) } \
+ Method (_SRS, 1) { } \
+ Method (_DIS) { } \
+}
+
+#define PRT_ENTRY(Address, Pin, Link) \
+ Package (4) { \
+ Address, /* uses the same format as _ADR */ \
+ Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC, 3-INTD) */ \
+ Link, /* Interrupt allocated via Link device */ \
+ Zero /* global system interrupt number (no used) */ \
+}
+
+/*
+ See Reference [1] 6.1.1
+ "High word�Device #, Low word�Function #. (for example, device 3,
+ function 2 is 0x00030002). To refer to all the functions on a device #,
+ use a function number of FFFF)."
+*/
+#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY (0x0000FFFF, Pin, Link) // Device 0 for Bridge.
+
+DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "ARMLTD", "FVP-REVC", 1) {
+ Scope(_SB) {
+ //
+ // PCI Root Complex
+ //
+ LNK_DEVICE (1, LNKA, 168)
+ LNK_DEVICE (2, LNKB, 169)
+ LNK_DEVICE (3, LNKC, 170)
+ LNK_DEVICE (4, LNKD, 171)
+
+ Device(PCI0)
+ {
+ Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge
+ Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge
+ Name (_SEG, Zero) // PCI Segment Group number
+ Name (_BBN, Zero) // PCI Base Bus Number
+ Name (_CCA, 1) // Initially mark the PCI coherent
+
+ // Root Complex 0
+ Device (RP0) {
+ Name (_ADR, 0xF0000000) // Dev 0, Func 0
+ }
+
+ // PCI Routing Table
+ Name (_PRT, Package () {
+ ROOT_PRT_ENTRY (0, LNKA), // INTA
+ ROOT_PRT_ENTRY (1, LNKB), // INTB
+ ROOT_PRT_ENTRY (2, LNKC), // INTC
+ ROOT_PRT_ENTRY (3, LNKD), // INTD
+ })
+ // Root complex resources
+ Method (_CRS, 0, Serialized) {
+ Name (RBUF, ResourceTemplate () {
+ WordBusNumber ( // Bus numbers assigned to this root
+ ResourceProducer,
+ MinFixed, MaxFixed, PosDecode,
+ 0, // AddressGranularity
+ 0, // AddressMinimum - Minimum Bus Number
+ 255, // AddressMaximum - Maximum Bus Number
+ 0, // AddressTranslation - Set to 0
+ 256 // RangeLength - Number of Busses
+ )
+
+ DWordMemory ( // 32-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x50000000, // Min Base Address
+ 0x57FFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x08000000 // Length
+ )
+
+ QWordMemory ( // 64-bit BAR Windows
+ ResourceProducer,
+ PosDecode,
+ MinFixed,
+ MaxFixed,
+ Cacheable,
+ ReadWrite,
+ 0x00000000, // Granularity
+ 0x4000000000, // Min Base Address
+ 0x40FFFFFFFF, // Max Base Address
+ 0x00000000, // Translate
+ 0x100000000 // Length
+ )
+
+ DWordIo ( // IO window
+ ResourceProducer,
+ MinFixed,
+ MaxFixed,
+ PosDecode,
+ EntireRange,
+ 0x00000000, // Granularity
+ 0x00000000, // Min Base Address
+ 0x007fffff, // Max Base Address
+ 0x5f800000, // Translate
+ 0x00800000, // Length
+ ,
+ ,
+ ,
+ TypeTranslation
+ )
+ }) // Name (RBUF)
+
+ Return (RBUF)
+ } // Method(_CRS)
+
+ //
+ // OS Control Handoff
+ //
+ Name (SUPP, Zero) // PCI _OSC Support Field value
+ Name (CTRL, Zero) // PCI _OSC Control Field value
+
+ /*
+ See [1] 6.2.10, [2] 4.5
+ */
+ Method (_OSC,4) {
+ // Check for proper UUID
+ If(LEqual (Arg0,ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) {
+ // Create DWord-adressable fields from the Capabilities Buffer
+ CreateDWordField (Arg3, 0, CDW1)
+ CreateDWordField (Arg3, 4, CDW2)
+ CreateDWordField (Arg3, 8, CDW3)
+
+ // Save Capabilities DWord2 & 3
+ Store (CDW2, SUPP)
+ Store (CDW3, CTRL)
+
+ // Only allow native hot plug control if OS supports:
+ // * ASPM
+ // * Clock PM
+ // * MSI/MSI-X
+ If(LNotEqual (And (SUPP, 0x16), 0x16)) {
+ And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits)
+ }
+
+ // Always allow native PME, AER (no dependencies)
+
+ // Never allow SHPC (no SHPC controller in this system)
+ And (CTRL, 0x1D, CTRL)
+
+ If(LNotEqual (Arg1, One)) { // Unknown revision
+ Or (CDW1, 0x08, CDW1)
+ }
+
+ If(LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked
+ Or (CDW1, 0x10, CDW1)
+ }
+
+ // Update DWORD3 in the buffer
+ Store (CTRL,CDW3)
+ Return (Arg3)
+ } Else {
+ Or (CDW1, 4, CDW1) // Unrecognized UUID
+ Return (Arg3)
+ }
+ } // End _OSC
+ } // PCI0
+ }
+}
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 49aa16184a2da587471239a7c90ed864f963896c..273ae35ffcdae2fbe1214676a10f6a3ca04e4242 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -12,6 +12,8 @@
#include <IndustryStandard/DebugPort2Table.h>
#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
+#include <IndustryStandard/IoRemappingTable.h>
+#include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>
#include <Library/ArmLib.h>
#include <Library/DebugLib.h>
#include <Library/IoLib.h>
@@ -74,7 +76,30 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
NULL
- }
+ },
+
+ // Note: The last 3 tables in this list are for FVP RevC only.
+ // IORT Table - FVP RevC
+ {
+ EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE,
+ EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
+ NULL
+ },
+ // PCI MCFG Table - FVP RevC
+ {
+ EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
+ NULL
+ },
+ // SSDT table describing the PCI root complex - FVP RevC
+ {
+ EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ 0, // Unused
+ CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
+ (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
+ },
},
// Boot architecture information
@@ -90,6 +115,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
/* GIC CPU Interface information
GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency)
+ Note: The MPIDR is fixed up in InitializePlatformRepository() if the
+ platform is FVP RevC.
*/
{
GICC_ENTRY (0, GET_MPID (0, 0), 92, 25, 0),
@@ -215,7 +242,121 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
0,
// The physical address for the Interrupt Translation Service
0x2f020000
- }
+ },
+
+ // SMMUv3 Node
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (SmmuV3Info),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[0]),
+
+ // SMMU Base Address
+ FVP_REVC_SMMUV3_BASE,
+ // SMMU flags
+ EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE,
+ // VATOS address
+ 0,
+ // Model
+ EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC,
+ // GSIV of the Event interrupt if SPI based
+ 0x6A,
+ // PRI Interrupt if SPI based
+ 0x6B,
+ // GERR interrupt if GSIV based
+ 0x6F,
+ // Sync interrupt if GSIV based
+ 0x6D,
+
+ // Proximity domain flag, ignored in this case
+ 0,
+ // Index into the array of ID mapping, ignored as SMMU
+ // control interrupts are GSIV based
+ 0
+ },
+
+ // ITS group node
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (ItsGroupInfo),
+ // The number of ITS identifiers in the ITS node.
+ 1,
+ // Reference token for the ITS identifier array
+ REFERENCE_TOKEN (ItsIdentifierArray)
+ },
+ // ITS identifier array
+ {
+ {
+ // The ITS Identifier
+ 0
+ }
+ },
+
+ // Root Complex node info
+ {
+ // Reference token for this Iort node
+ REFERENCE_TOKEN (RootComplexInfo),
+ // Number of ID mappings
+ 1,
+ // Reference token for the ID mapping array
+ REFERENCE_TOKEN (DeviceIdMapping[1]),
+
+ // Memory access properties : Cache coherent attributes
+ EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA,
+ // Memory access properties : Allocation hints
+ 0,
+ // Memory access properties : Memory access flags
+ 0,
+ // ATS attributes
+ EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,
+ // PCI segment number
+ 0
+ },
+
+ // Array of Device ID mappings
+ {
+ /* Mapping When SMMUv3 is defined
+ RootComplex -> SMMUv3 -> ITS Group
+ */
+
+ // SMMUv3 device ID mapping
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference
+ REFERENCE_TOKEN (ItsGroupInfo),
+ // Flags
+ 0
+ },
+ // Device ID mapping for Root complex node
+ {
+ // Input base
+ 0x0,
+ // Number of input IDs
+ 0x0000FFFF,
+ // Output Base
+ 0x0,
+ // Output reference token for the IORT node
+ REFERENCE_TOKEN (SmmuV3Info),
+ // Flags
+ 0
+ }
+ },
+
+ // PCI Configuration Space Info
+ {
+ FixedPcdGet64 (PcdPciExpressBaseAddress),
+ // PciSegmentGroupNumber
+ 0,
+ FixedPcdGet32 (PcdPciBusMin),
+ FixedPcdGet32 (PcdPciBusMax)
+ },
};
/** A helper function for returning the Configuration Manager Objects.
@@ -324,6 +465,24 @@ InitializePlatformRepository (
IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This
)
{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ PlatformRepo->SysId = MmioRead32 (ARM_VE_SYS_ID_REG);
+ if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) ==
+ ARM_FVP_BASE_REVC_REV) {
+ // REVC affinity is shifted, update the MPIDR
+ PlatformRepo->GicCInfo[0].MPIDR = GET_MPID_MT (0, 0, 0);
+ PlatformRepo->GicCInfo[1].MPIDR = GET_MPID_MT (0, 1, 0);
+ PlatformRepo->GicCInfo[2].MPIDR = GET_MPID_MT (0, 2, 0);
+ PlatformRepo->GicCInfo[3].MPIDR = GET_MPID_MT (0, 3, 0);
+
+ PlatformRepo->GicCInfo[4].MPIDR = GET_MPID_MT (1, 0, 0);
+ PlatformRepo->GicCInfo[5].MPIDR = GET_MPID_MT (1, 1, 0);
+ PlatformRepo->GicCInfo[6].MPIDR = GET_MPID_MT (1, 2, 0);
+ PlatformRepo->GicCInfo[7].MPIDR = GET_MPID_MT (1, 3, 0);
+ }
return EFI_SUCCESS;
}
@@ -370,6 +529,91 @@ GetGTBlockTimerFrameInfo (
return EFI_SUCCESS;
}
+/** Return an ITS identifier array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+*/
+EFI_STATUS
+EFIAPI
+GetItsIdentifierArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ if (Token != (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray) {
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (PlatformRepo->ItsIdentifierArray);
+ CmObject->Data = (VOID*)&PlatformRepo->ItsIdentifierArray;
+ CmObject->Count = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+ return EFI_SUCCESS;
+}
+
+/** Return a device Id mapping array.
+
+ @param [in] This Pointer to the Configuration Manager Protocol.
+ @param [in] CmObjectId The Configuration Manager Object ID.
+ @param [in] Token A token for identifying the object
+ @param [out] CmObject Pointer to the Configuration Manager Object
+ descriptor describing the requested Object.
+
+ @retval EFI_SUCCESS Success.
+ @retval EFI_INVALID_PARAMETER A parameter is invalid.
+ @retval EFI_NOT_FOUND The required object information is not found.
+*/
+EFI_STATUS
+EFIAPI
+GetDeviceIdMappingArray (
+ IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This,
+ IN CONST CM_OBJECT_ID CmObjectId,
+ IN CONST CM_OBJECT_TOKEN Token,
+ IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject
+ )
+{
+ EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+
+ if ((This == NULL) || (CmObject == NULL)) {
+ ASSERT (This != NULL);
+ ASSERT (CmObject != NULL);
+ return EFI_INVALID_PARAMETER;
+ }
+
+ PlatformRepo = This->PlatRepoInfo;
+
+ if ((Token != (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0]) &&
+ (Token != (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1])) {
+ return EFI_NOT_FOUND;
+ }
+
+ CmObject->ObjectId = CmObjectId;
+ CmObject->Size = sizeof (CM_ARM_ID_MAPPING);
+ CmObject->Data = (VOID*)Token;
+ CmObject->Count = 1;
+ return EFI_SUCCESS;
+}
+
/** Return a standard namespace object.
@param [in] This Pointer to the Configuration Manager Protocol.
@@ -394,7 +638,9 @@ GetStandardNameSpaceObject (
{
EFI_STATUS Status;
EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN AcpiTableCount;
+ Status = EFI_SUCCESS;
if ((This == NULL) || (CmObject == NULL)) {
ASSERT (This != NULL);
ASSERT (CmObject != NULL);
@@ -402,8 +648,16 @@ GetStandardNameSpaceObject (
}
Status = EFI_NOT_FOUND;
+ AcpiTableCount = ARRAY_SIZE (PlatformRepo->CmAcpiTableList);
PlatformRepo = This->PlatRepoInfo;
+ if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) !=
+ ARM_FVP_BASE_REVC_REV) {
+ // The last 3 tables in the ACPI table list are for FVP RevC
+ // Reduce the count by 3 if the platform is not FVP RevC
+ AcpiTableCount -= 3;
+ }
+
switch (GET_CM_OBJECT_ID (CmObjectId)) {
case EStdObjCfgMgrInfo:
Status = HandleCmObject (
@@ -420,7 +674,7 @@ GetStandardNameSpaceObject (
CmObjectId,
&PlatformRepo->CmAcpiTableList,
sizeof (PlatformRepo->CmAcpiTableList),
- ARRAY_SIZE (PlatformRepo->CmAcpiTableList),
+ AcpiTableCount,
CmObject
);
break;
@@ -464,6 +718,12 @@ GetArmNameSpaceObject (
{
EFI_STATUS Status;
EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo;
+ UINTN Smmuv3Count;
+ UINTN ItsGroupCount;
+ UINTN ItsIdentifierArrayCount;
+ UINTN RootComplexCount;
+ UINTN DeviceIdMappingArrayCount;
+ UINTN PciConfigSpaceCount;
if ((This == NULL) || (CmObject == NULL)) {
ASSERT (This != NULL);
@@ -474,6 +734,23 @@ GetArmNameSpaceObject (
Status = EFI_NOT_FOUND;
PlatformRepo = This->PlatRepoInfo;
+ if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) ==
+ ARM_FVP_BASE_REVC_REV) {
+ Smmuv3Count = 1;
+ ItsGroupCount = 1;
+ ItsIdentifierArrayCount = ARRAY_SIZE (PlatformRepo->ItsIdentifierArray);
+ RootComplexCount = 1;
+ DeviceIdMappingArrayCount = ARRAY_SIZE (PlatformRepo->DeviceIdMapping);
+ PciConfigSpaceCount = 1;
+ } else {
+ Smmuv3Count = 0;
+ ItsGroupCount = 0;
+ ItsIdentifierArrayCount = 0;
+ RootComplexCount = 0;
+ DeviceIdMappingArrayCount = 0;
+ PciConfigSpaceCount = 0;
+ }
+
switch (GET_CM_OBJECT_ID (CmObjectId)) {
case EArmObjBootArchInfo:
Status = HandleCmObject (
@@ -609,6 +886,72 @@ GetArmNameSpaceObject (
);
break;
+ case EArmObjSmmuV3:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->SmmuV3Info,
+ sizeof (PlatformRepo->SmmuV3Info),
+ Smmuv3Count,
+ CmObject
+ );
+ break;
+
+ case EArmObjItsGroup:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->ItsGroupInfo,
+ sizeof (PlatformRepo->ItsGroupInfo),
+ ItsGroupCount,
+ CmObject
+ );
+ break;
+
+ case EArmObjGicItsIdentifierArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->ItsIdentifierArray,
+ sizeof (PlatformRepo->ItsIdentifierArray),
+ ItsIdentifierArrayCount,
+ Token,
+ GetItsIdentifierArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjRootComplex:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->RootComplexInfo,
+ sizeof (PlatformRepo->RootComplexInfo),
+ 1,
+ CmObject
+ );
+ break;
+
+ case EArmObjIdMappingArray:
+ Status = HandleCmObjectRefByToken (
+ This,
+ CmObjectId,
+ PlatformRepo->DeviceIdMapping,
+ sizeof (PlatformRepo->DeviceIdMapping),
+ ARRAY_SIZE (PlatformRepo->DeviceIdMapping),
+ Token,
+ GetDeviceIdMappingArray,
+ CmObject
+ );
+ break;
+
+ case EArmObjPciConfigSpaceInfo:
+ Status = HandleCmObject (
+ CmObjectId,
+ &PlatformRepo->PciConfigInfo,
+ sizeof (PlatformRepo->PciConfigInfo),
+ PciConfigSpaceCount,
+ CmObject
+ );
+ break;
+
default: {
Status = EFI_NOT_FOUND;
DEBUG ((
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
index c21f160dd082bddb9e8e1ab666143887d67869cd..aebf0a355291df5df5f588e8b7076e21eda9a152 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h
@@ -17,6 +17,7 @@
containing the AML bytecode array.
*/
extern CHAR8 dsdt_aml_code[];
+extern CHAR8 ssdtpci_aml_code[];
/** The configuration manager version.
*/
@@ -77,13 +78,18 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) (
(CM_OBJECT_TOKEN)((UINT8*)&VExpressPlatRepositoryInfo + \
OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field))
+/** Macro to return MPIDR for Multi Threaded Cores
+*/
+#define GET_MPID_MT(Cluster, Core, Thread) \
+ (((Cluster) << 16) | ((Core) << 8) | (Thread))
+
/** The number of CPUs
*/
#define PLAT_CPU_COUNT 8
/** The number of ACPI tables to install
*/
-#define PLAT_ACPI_TABLE_COUNT 6
+#define PLAT_ACPI_TABLE_COUNT 9
/** The number of platform generic timer blocks
*/
@@ -145,6 +151,28 @@ typedef struct PlatformRepositoryInfo {
/// GIC ITS information
CM_ARM_GIC_ITS_INFO GicItsInfo;
+
+ // FVP RevC components
+ /// SMMUv3 node
+ CM_ARM_SMMUV3_NODE SmmuV3Info;
+
+ /// ITS Group node
+ CM_ARM_ITS_GROUP_NODE ItsGroupInfo;
+
+ /// ITS Identifier array
+ CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[1];
+
+ /// PCI Root complex node
+ CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo;
+
+ /// Array of DeviceID mapping
+ CM_ARM_ID_MAPPING DeviceIdMapping[2];
+
+ /// PCI configuration space information
+ CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo;
+
+ /// System ID
+ UINT32 SysId;
} EDKII_PLATFORM_REPOSITORY_INFO;
#endif // CONFIGURATION_MANAGER_H__
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
index c17595b7ec37cdd1c99b258cd32d1bde6c76a5ed..b53daf51d4b1afd45e41d0debb0b9f084f135f6a 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -1,7 +1,7 @@
## @file
# Configuration Manager Dxe
#
-# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.<BR>
+# Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.<BR>
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
##
@@ -23,6 +23,7 @@ [Defines]
[Sources]
ConfigurationManager.c
AslTables/Dsdt.asl
+ AslTables/SsdtPci.asl
[Packages]
ArmPkg/ArmPkg.dec
@@ -68,6 +69,13 @@ [FixedPcd]
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase
gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate
+ # PCI Root complex specific PCDs
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize
+
+ gArmTokenSpaceGuid.PcdPciBusMin
+ gArmTokenSpaceGuid.PcdPciBusMax
+
[Pcd]
[Depex]
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 07/12] Platform/ARM/VExpressPkg: Add support for FVP RevC model
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (5 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 06/12] Platform/ARM/VExpressPkg: ACPI support for FVP RevC model Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 08/12] Platform/ARM/VExpressPkg: Update ACPI Revision to 6.3 Sami Mujawar
` (5 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Base Platform RevC is a configuration of the Base Platform that
includes a PCIe subsystem and a SMMUv3. It also has an AHCI-SATA
disk controller as a device on the PCIe bus.
Add firmware support for the FVP RevC model as it provides a
standard boot environment using a SATA disk.
Note: Checks have been added in appropriate places so that a common
firmware can be used for both the FVP_Base_AEMv8A-AEMv8A model and
the FVP_Base_RevC-2xAEMv8A model. However, this unified firmware is
only available if the firmware is built using Dynamic Firmware Tables
support. This feature can be enabled by building the firmware using
the command line build option '-D DYNAMIC_TABLES_FRAMEWORK'.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 40 +++++++++++++++++++-
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 20 +++++++++-
2 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
index f8c703c4b22b2a26028ba0562e0eae5948c3292d..d01e549f945f2593e6b62a58b204737aff104a40 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011-2021, ARM Limited. All rights reserved.
+# Copyright (c) 2011-2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -65,6 +65,11 @@ [LibraryClasses.common.SEC]
[LibraryClasses.common.UEFI_DRIVER, LibraryClasses.common.UEFI_APPLICATION, LibraryClasses.common.DXE_RUNTIME_DRIVER, LibraryClasses.common.DXE_DRIVER]
PcdLib|MdePkg/Library/DxePcdLib/DxePcdLib.inf
+ PciExpressLib|MdePkg/Library/BasePciExpressLib/BasePciExpressLib.inf
+ PciHostBridgeLib|Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf
+ PciLib|MdePkg/Library/BasePciLibPciExpress/BasePciLibPciExpress.inf
+ PciSegmentLib|MdePkg/Library/BasePciSegmentLibPci/BasePciSegmentLibPci.inf
+
[BuildOptions]
GCC:*_*_AARCH64_PLATFORM_FLAGS == -I$(WORKSPACE)/Platform/ARM/VExpressPkg/Include/Platform/RTSM
@@ -161,6 +166,21 @@ [PcdsFixedAtBuild.common]
gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase|0x2C000000
#
+ # PCI Root Complex
+ #
+ gArmTokenSpaceGuid.PcdPciBusMin|0
+ gArmTokenSpaceGuid.PcdPciBusMax|255
+
+ gArmTokenSpaceGuid.PcdPciMmio32Base|0x50000000
+ gArmTokenSpaceGuid.PcdPciMmio32Size|0x10000000
+
+ gArmTokenSpaceGuid.PcdPciMmio64Base|0x4000000000
+ gArmTokenSpaceGuid.PcdPciMmio64Size|0x4000000000
+
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress|0x40000000
+ gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize|0x10000000
+
+ #
# ARM Architectural Timer Frequency
#
# Set tick frequency value to 100Mhz
@@ -331,3 +351,21 @@ [Components.common]
#
EmbeddedPkg/Drivers/DtPlatformDxe/DtPlatformDxe.inf
!endif
+
+ #
+ # PCI Support
+ #
+ ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+
+ #
+ # AHCI Support
+ #
+ MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ #
+ # SATA Controller
+ #
+ MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
index 513054dbcbc5fd301816400a0471f66673a5aefb..418566673981a9655fbc7a834942443a2005c403 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
@@ -1,5 +1,5 @@
#
-# Copyright (c) 2011 - 2018, ARM Limited. All rights reserved.
+# Copyright (c) 2011 - 2021, Arm Limited. All rights reserved.
#
# SPDX-License-Identifier: BSD-2-Clause-Patent
#
@@ -171,6 +171,24 @@ [FV.FvMain]
INF MdeModulePkg/Universal/BdsDxe/BdsDxe.inf
INF MdeModulePkg/Application/UiApp/UiApp.inf
+
+ #
+ # PCI Support
+ #
+ INF ArmPkg/Drivers/ArmPciCpuIo2Dxe/ArmPciCpuIo2Dxe.inf
+ INF MdeModulePkg/Bus/Pci/PciBusDxe/PciBusDxe.inf
+ INF MdeModulePkg/Bus/Pci/PciHostBridgeDxe/PciHostBridgeDxe.inf
+ #
+ # AHCI Support
+ #
+ INF MdeModulePkg/Bus/Ata/AtaAtapiPassThru/AtaAtapiPassThru.inf
+ INF MdeModulePkg/Bus/Ata/AtaBusDxe/AtaBusDxe.inf
+
+ #
+ # SATA Controller
+ #
+ INF MdeModulePkg/Bus/Pci/SataControllerDxe/SataControllerDxe.inf
+
# FV Filesystem
INF MdeModulePkg/Universal/FvSimpleFileSystemDxe/FvSimpleFileSystemDxe.inf
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 08/12] Platform/ARM/VExpressPkg: Update ACPI Revision to 6.3
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (6 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 07/12] Platform/ARM/VExpressPkg: Add " Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 09/12] Platform/ARM/VExpressPkg: Add SMC91x device description Sami Mujawar
` (4 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Update the revision of the ACPI tables generated by Dynamic
Tables Framework so that the ACPI 6.3 features can be
utilised.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 30 ++++++++++----------
1 file changed, 15 insertions(+), 15 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
index 273ae35ffcdae2fbe1214676a10f6a3ca04e4242..e99fbb654f5109321e32905af3763233dffdbc3e 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c
@@ -37,42 +37,42 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
{
// FADT Table
{
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdFadt),
NULL
},
// GTDT Table
{
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdGtdt),
NULL
},
// MADT Table
{
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_2_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMadt),
NULL
},
// SPCR Table
{
- EFI_ACPI_6_2_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSpcr),
NULL
},
// DSDT Table
{
- EFI_ACPI_6_2_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_DIFFERENTIATED_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
0, // Unused
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDsdt),
(EFI_ACPI_DESCRIPTION_HEADER*)dsdt_aml_code
},
// DBG2 Table
{
- EFI_ACPI_6_2_DEBUG_PORT_2_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_DEBUG_PORT_2_TABLE_SIGNATURE,
EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2),
NULL
@@ -81,21 +81,21 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
// Note: The last 3 tables in this list are for FVP RevC only.
// IORT Table - FVP RevC
{
- EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_IO_REMAPPING_TABLE_SIGNATURE,
EFI_ACPI_IO_REMAPPING_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort),
NULL
},
// PCI MCFG Table - FVP RevC
{
- EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDRESS_DESCRIPTION_TABLE_SIGNATURE,
EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION,
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg),
NULL
},
// SSDT table describing the PCI root complex - FVP RevC
{
- EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
+ EFI_ACPI_6_3_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE,
0, // Unused
CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt),
(EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code
@@ -103,15 +103,15 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInfo = {
},
// Boot architecture information
- { EFI_ACPI_6_2_ARM_PSCI_COMPLIANT }, // BootArchFlags
+ { EFI_ACPI_6_3_ARM_PSCI_COMPLIANT }, // BootArchFlags
#ifdef HEADLESS_PLATFORM
// Fixed feature flag information
- { EFI_ACPI_6_2_HEADLESS }, // Fixed feature flags
+ { EFI_ACPI_6_3_HEADLESS }, // Fixed feature flags
#endif
// Power management profile information
- { EFI_ACPI_6_2_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile
+ { EFI_ACPI_6_3_PM_PROFILE_ENTERPRISE_SERVER }, // PowerManagement Profile
/* GIC CPU Interface information
GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficiency)
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 09/12] Platform/ARM/VExpressPkg: Add SMC91x device description
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (7 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 08/12] Platform/ARM/VExpressPkg: Update ACPI Revision to 6.3 Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 10/12] Platform/ARM/VExpressPkg: Add Virtio Block Device description Sami Mujawar
` (3 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
The FVP model implements a SMSC 91C111 ethernet controller that
can be configured for network access.
Therefore, add description for a SMSC 91C111 device in the DSDT.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl | 16 +++++++++++++++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
index eb5466229d1f10f465ca417166de5c1c1ea212e8..64d697e344ffb5b5b6c4ef31b8245f10a1a18c76 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
@@ -2,7 +2,10 @@
Differentiated System Description Table Fields (DSDT)
Copyright (c) 2014-2021, ARM Ltd. All rights reserved.<BR>
- SPDX-License-Identifier: BSD-2-Clause-Patent
+ Copyright (c) 2013, Al Stone <al.stone@linaro.org>
+ All rights reserved.
+
+ SPDX-License-Identifier: BSD-2-Clause-Patent
**/
@@ -43,5 +46,16 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-VEXP", 1) {
Name(_HID, "ACPI0007")
Name(_UID, 7)
}
+
+ // SMC91X
+ Device (NET0) {
+ Name (_HID, "LNRO0003")
+ Name (_UID, 0)
+
+ Name (_CRS, ResourceTemplate () {
+ Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x2F}
+ })
+ }
} // Scope(_SB)
}
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 10/12] Platform/ARM/VExpressPkg: Add Virtio Block Device description
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (8 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 09/12] Platform/ARM/VExpressPkg: Add SMC91x device description Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 11/12] Platform/ARM/VExpressPkg: Make Dynamic Tables Framework default Sami Mujawar
` (2 subsequent siblings)
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
The FVP model implements a Virtio block device that can be accessed from
a Guest OS if it has an appropriate driver. It is targeted primarily at
Linux, which has a built-in Virtio block driver. VirtioBlockDevice allows
to use a file on the host that is specified using the models image_path
parameter, as a hard drive in the Guest OS.
Therefore, add the Virtio block device description to the DSDT.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
index 64d697e344ffb5b5b6c4ef31b8245f10a1a18c76..e04003d562ddc410d4981d7e4527ecc78c440440 100644
--- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
+++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl
@@ -57,5 +57,16 @@ DefinitionBlock("DsdtTable.aml", "DSDT", 1, "ARMLTD", "ARM-VEXP", 1) {
Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x2F}
})
}
+
+ // VIRTIO block device
+ Device (VIRT) {
+ Name (_HID, "LNRO0005")
+ Name (_UID, 0)
+
+ Name (_CRS, ResourceTemplate() {
+ Memory32Fixed (ReadWrite, 0x1c130000, 0x1000)
+ Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A}
+ })
+ }
} // Scope(_SB)
}
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 11/12] Platform/ARM/VExpressPkg: Make Dynamic Tables Framework default
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (9 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 10/12] Platform/ARM/VExpressPkg: Add Virtio Block Device description Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-12 10:23 ` [PATCH edk2-platforms v1 12/12] Platform/ARM/VExpressPkg: Remove redundant traditional ACPI support Sami Mujawar
2021-02-13 10:26 ` [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Ard Biesheuvel
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
The Dynamic Tables Framework enables unification of the firmware
for FVP_Base_AEMv8A-AEMv8A and FVP_Base_RevC-2xAEMv8A models such
that the same firmware binary can be used by these models.
Therefore, make Dynamic Tables Framework the default option for
building ACPI tables.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 1 +
1 file changed, 1 insertion(+)
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
index d01e549f945f2593e6b62a58b204737aff104a40..12562ceafd8ab020d61d4ba70fdd6c8c128da6a2 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
@@ -30,6 +30,7 @@ [Defines]
!endif
DT_SUPPORT = FALSE
+ DYNAMIC_TABLES_FRAMEWORK = TRUE
!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
!ifdef DYNAMIC_TABLES_FRAMEWORK
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PATCH edk2-platforms v1 12/12] Platform/ARM/VExpressPkg: Remove redundant traditional ACPI support
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (10 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 11/12] Platform/ARM/VExpressPkg: Make Dynamic Tables Framework default Sami Mujawar
@ 2021-02-12 10:23 ` Sami Mujawar
2021-02-13 10:26 ` [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Ard Biesheuvel
12 siblings, 0 replies; 14+ messages in thread
From: Sami Mujawar @ 2021-02-12 10:23 UTC (permalink / raw)
To: devel
Cc: Sami Mujawar, ardb+tianocore, thomas.abraham, leif,
Matteo.Carlini, Ben.Adderson, nd
Dynamic Tables Framework enables unification of the firmware
for FVP_Base_AEMv8A-AEMv8A and FVP_Base_RevC-2xAEMv8A models
such that the same firmware binary can be used by both models.
A single firmware binary cannot be supported using the traditional
ACPI tables. Therefore, remove support for the now redundant
traditional ACPI tables.
Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
---
Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf | 38 -----
Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl | 123 --------------
Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc | 80 ---------
Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h | 40 -----
Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc | 169 --------------------
Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc | 85 ----------
Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc | 82 ----------
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 10 +-
Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 13 +-
9 files changed, 2 insertions(+), 638 deletions(-)
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf b/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf
deleted file mode 100644
index bca1d21de704368caf5e5a290670ddcfcdd5fb80..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf
+++ /dev/null
@@ -1,38 +0,0 @@
-## @file
-#
-# ACPI table data and ASL sources required to boot the platform.
-#
-# Copyright (c) 2014-2017, ARM Ltd. All rights reserved.
-#
-# SPDX-License-Identifier: BSD-2-Clause-Patent
-#
-##
-
-[Defines]
- INF_VERSION = 0x00010005
- BASE_NAME = FvpAcpiTables
- FILE_GUID = 7E374E25-8E01-4FEE-87F2-390C23C606CD
- MODULE_TYPE = USER_DEFINED
- VERSION_STRING = 1.0
-
-[Sources]
- Dsdt.asl
- Spcr.aslc
- Fadt.aslc
- Gtdt.aslc
- Madt.aslc
-
-[Packages]
- ArmPkg/ArmPkg.dec
- ArmPlatformPkg/ArmPlatformPkg.dec
- EmbeddedPkg/EmbeddedPkg.dec
- MdePkg/MdePkg.dec
- MdeModulePkg/MdeModulePkg.dec
- Platform/ARM/VExpressPkg/ArmVExpressPkg.dec
-
-[FixedPcd]
- gArmTokenSpaceGuid.PcdGicDistributorBase
- gArmTokenSpaceGuid.PcdGicInterruptInterfaceBase
- gArmTokenSpaceGuid.PcdGicRedistributorsBase
-
- gArmPlatformTokenSpaceGuid.PcdWatchdogCount
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl b/Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl
deleted file mode 100644
index f9b44bb25f723bf002b7fc82c65fa2d300c4bf05..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl
+++ /dev/null
@@ -1,123 +0,0 @@
-/*
-* Copyright (c) 2013, Al Stone <al.stone@linaro.org>
-* All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-*
-* NB: This License is also known as the "BSD 2-Clause License".
-*
-*
-* [DSDT] Description of the armv8 VE Model
-*
-*/
-
-DefinitionBlock (
- "dsdt.aml", // output filename
- "DSDT", // table signature
- 2, // DSDT compliance revision
- "LINARO", // OEM ID
- "RTSMVEV8", // table ID
- 0x00000004) // OEM revision
-{
- Scope (\_SB)
- {
- Method (_OSC, 4, NotSerialized)
- {
- /* Platform-Wide OSPM Capabilities */
- If(LEqual(Arg0,ToUUID("0811B06E-4A27-44F9-8D60-3CBBC22E7B48")))
- {
- /* APEI support unconditionally */
- Return (Arg3)
- } Else {
- CreateDWordField (Arg3, Zero, CDW1)
- /* Set invalid UUID error bit */
- Or (CDW1, 0x04, CDW1)
- Return (Arg3)
- }
- }
-
- //
- // Two Emulated aarch64 CPUs each with 4 cores
- //
- Device(CPU0) { // Cluster 0, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 0)
- }
- Device(CPU1) { // Cluster 0, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 1)
- }
- Device(CPU2) { // Cluster 0, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 2)
- }
- Device(CPU3) { // Cluster 0, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 3)
- }
- Device(CPU4) { // Cluster 1, Cpu 0
- Name(_HID, "ACPI0007")
- Name(_UID, 4)
- }
- Device(CPU5) { // Cluster 1, Cpu 1
- Name(_HID, "ACPI0007")
- Name(_UID, 5)
- }
- Device(CPU6) { // Cluster 1, Cpu 2
- Name(_HID, "ACPI0007")
- Name(_UID, 6)
- }
- Device(CPU7) { // Cluster 1, Cpu 3
- Name(_HID, "ACPI0007")
- Name(_UID, 7)
- }
-
- // SMC91X
- Device (NET0) {
- Name (_HID, "LNRO0003")
- Name (_UID, 0)
-
- Name (_CRS, ResourceTemplate () {
- Memory32Fixed (ReadWrite, 0x1a000000, 0x00010000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, , , ) {0x2F}
- })
- }
-
- // SYSREG
- Device (SREG) {
- Name (_HID, "LNRO0009")
- Name (_UID, 0)
-
- Method (_CRS, 0x0, Serialized) {
- Name (RBUF, ResourceTemplate() {
- Memory32Fixed (ReadWrite, 0x1c010000, 0x1000)
- })
- Return (RBUF)
- }
- }
-
- // VIRTIO
- Device (VIRT) {
- Name (_HID, "LNRO0005")
- Name (_UID, 0)
-
- Name (_CRS, ResourceTemplate() {
- Memory32Fixed (ReadWrite, 0x1c130000, 0x1000)
- Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive) {0x4A}
- })
- }
-
- // UART PL011
- Device(COM0) {
- Name(_HID, "ARMH0011")
- Name(_CID, "PL011")
- Name(_UID, Zero)
-
- Name(_CRS, ResourceTemplate() {
- Memory32Fixed(ReadWrite, 0x1c090000, 0x1000)
- Interrupt(ResourceConsumer, Level, ActiveHigh, Exclusive) { 0x25 }
- })
- }
- }
-}
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc b/Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc
deleted file mode 100644
index 4eaec61b32605a992bec09e71021e98ed89d3759..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc
+++ /dev/null
@@ -1,80 +0,0 @@
-/** @file
-* Fixed ACPI Description Table (FADT)
-*
-* Copyright (c) 2012 - 2016, ARM Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include "FvpPlatform.h"
-#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi.h>
-
-EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE Fadt = {
- ARM_ACPI_HEADER (
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE,
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_REVISION
- ),
- 0, // UINT32 FirmwareCtrl
- 0, // UINT32 Dsdt
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved0
- EFI_ACPI_6_1_PM_PROFILE_UNSPECIFIED, // UINT8 PreferredPmProfile
- 0, // UINT16 SciInt
- 0, // UINT32 SmiCmd
- 0, // UINT8 AcpiEnable
- 0, // UINT8 AcpiDisable
- 0, // UINT8 S4BiosReq
- 0, // UINT8 PstateCnt
- 0, // UINT32 Pm1aEvtBlk
- 0, // UINT32 Pm1bEvtBlk
- 0, // UINT32 Pm1aCntBlk
- 0, // UINT32 Pm1bCntBlk
- 0, // UINT32 Pm2CntBlk
- 0, // UINT32 PmTmrBlk
- 0, // UINT32 Gpe0Blk
- 0, // UINT32 Gpe1Blk
- 0, // UINT8 Pm1EvtLen
- 0, // UINT8 Pm1CntLen
- 0, // UINT8 Pm2CntLen
- 0, // UINT8 PmTmrLen
- 0, // UINT8 Gpe0BlkLen
- 0, // UINT8 Gpe1BlkLen
- 0, // UINT8 Gpe1Base
- 0, // UINT8 CstCnt
- 0, // UINT16 PLvl2Lat
- 0, // UINT16 PLvl3Lat
- 0, // UINT16 FlushSize
- 0, // UINT16 FlushStride
- 0, // UINT8 DutyOffset
- 0, // UINT8 DutyWidth
- 0, // UINT8 DayAlrm
- 0, // UINT8 MonAlrm
- 0, // UINT8 Century
- 0, // UINT16 IaPcBootArch
- 0, // UINT8 Reserved1
- EFI_ACPI_6_1_HW_REDUCED_ACPI | EFI_ACPI_6_1_LOW_POWER_S0_IDLE_CAPABLE, // UINT32 Flags
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE ResetReg
- 0, // UINT8 ResetValue
- EFI_ACPI_6_1_ARM_PSCI_COMPLIANT, // UINT16 ArmBootArchFlags
- EFI_ACPI_6_1_FIXED_ACPI_DESCRIPTION_TABLE_MINOR_REVISION, // UINT8 MinorRevision
- 0, // UINT64 XFirmwareCtrl
- 0, // UINT64 XDsdt
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bEvtBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1aCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm1bCntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPm2CntBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XPmTmrBlk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe0Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE XGpe1Blk
- NULL_GAS, // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepControlReg
- NULL_GAS // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE SleepStatusReg
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Fadt;
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h b/Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h
deleted file mode 100644
index 21df93f6eee6f2f0201a08b77369d2955e527d78..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/** @file
-*
-* Copyright (c) 2011-2015, ARM Limited. All rights reserved.
-* Copyright (c) 2015, Hisilicon Limited. All rights reserved.
-* Copyright (c) 2015, Linaro Limited. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-* Based on the files under ArmPlatformPkg/ArmJunoPkg/AcpiTables/
-*
-**/
-
-
-#ifndef _FVP_PLATFORM_H_
-#define _FVP_PLATFORM_H_
-
-//
-// ACPI table information used to initialize tables.
-//
-#define EFI_ACPI_ARM_OEM_ID 'L','I','N','A','R','O' // OEMID 6 bytes long
-#define EFI_ACPI_ARM_OEM_TABLE_ID SIGNATURE_64('R','T','S','M','V','E','V','8') // OEM table id 8 bytes long
-#define EFI_ACPI_ARM_OEM_REVISION 0x00000002
-#define EFI_ACPI_ARM_CREATOR_ID SIGNATURE_32('L','N','R','O')
-#define EFI_ACPI_ARM_CREATOR_REVISION 0x00000002
-
-// A macro to initialise the common header part of EFI ACPI tables as defined by
-// EFI_ACPI_DESCRIPTION_HEADER structure.
-#define ARM_ACPI_HEADER(Signature, Type, Revision) { \
- Signature, /* UINT32 Signature */ \
- sizeof (Type), /* UINT32 Length */ \
- Revision, /* UINT8 Revision */ \
- 0, /* UINT8 Checksum */ \
- { EFI_ACPI_ARM_OEM_ID }, /* UINT8 OemId[6] */ \
- EFI_ACPI_ARM_OEM_TABLE_ID, /* UINT64 OemTableId */ \
- EFI_ACPI_ARM_OEM_REVISION, /* UINT32 OemRevision */ \
- EFI_ACPI_ARM_CREATOR_ID, /* UINT32 CreatorId */ \
- EFI_ACPI_ARM_CREATOR_REVISION /* UINT32 CreatorRevision */ \
- }
-
-#endif
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc b/Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc
deleted file mode 100644
index 9007fc936c589295a4cb53ebd25cad3f1ace058e..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc
+++ /dev/null
@@ -1,169 +0,0 @@
-/** @file
-* Generic Timer Description Table (GTDT)
-*
-* Copyright (c) 2012 - 2018, ARM Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Ltd. All rights reserved
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include "FvpPlatform.h"
-#include <Library/AcpiLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi61.h>
-
-#define FVP_SYSTEM_TIMER_BASE_ADDRESS 0x000000002a430000
-#define FVP_CNT_READ_BASE_ADDRESS 0x000000002a800000
-
-#define FVP_SECURE_TIMER_EL1_GSIV 0x1D
-#define FVP_NON_SECURE_TIMER_EL1_GSIV 0x1E
-#define FVP_VIRTUAL_TIMER_GSIV 0x1B
-#define FVP_NON_SECURE_EL2_GSIV 0x1A
-
-#define GTDT_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_MODE
-#define GTDT_TIMER_LEVEL_TRIGGERED 0
-#define GTDT_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
-#define GTDT_TIMER_ACTIVE_HIGH 0
-#define GTDT_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_TIMER_FLAG_ALWAYS_ON_CAPABILITY
-#define GTDT_TIMER_LOSE_CONTEXT 0
-
-#define FVP_GTDT_GTIMER_FLAGS (GTDT_TIMER_LOSE_CONTEXT | GTDT_TIMER_ACTIVE_HIGH | GTDT_TIMER_EDGE_TRIGGERED)
-
-#define FVP_WATCHDOG_COUNT FixedPcdGet32 (PcdWatchdogCount)
-#define FVP_PLATFORM_TIMER_COUNT (FVP_WATCHDOG_COUNT + 1)
-#define FVP_TIMER_FRAMES_COUNT 2
-
-#define FVP_GT_BLOCK_CTL_BASE 0x000000002A810000
-#define FVP_GT_BLOCK_FRAME0_CTL_BASE 0x000000002A820000
-#define FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
-#define FVP_GT_BLOCK_FRAME0_GSIV 0x39
-
-#define FVP_GT_BLOCK_FRAME1_CTL_BASE 0x000000002A830000
-#define FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE 0xFFFFFFFFFFFFFFFF
-#define FVP_GT_BLOCK_FRAME1_GSIV 0x3A
-
-#define GTX_TIMER_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_MODE
-#define GTX_TIMER_LEVEL_TRIGGERED 0
-#define GTX_TIMER_ACTIVE_LOW EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_FLAG_TIMER_INTERRUPT_POLARITY
-#define GTX_TIMER_ACTIVE_HIGH 0
-
-#define FVP_GTX_TIMER_FLAGS (GTX_TIMER_ACTIVE_HIGH | GTX_TIMER_LEVEL_TRIGGERED)
-
-#define GTX_TIMER_SECURE EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_SECURE_TIMER
-#define GTX_TIMER_NON_SECURE 0
-#define GTX_TIMER_SAVE_CONTEXT EFI_ACPI_6_1_GTDT_GT_BLOCK_COMMON_FLAG_ALWAYS_ON_CAPABILITY
-#define GTX_TIMER_LOSE_CONTEXT 0
-
-#define FVP_GTX_COMMON_FLAGS_S (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_SECURE)
-#define FVP_GTX_COMMON_FLAGS_NS (GTX_TIMER_SAVE_CONTEXT | GTX_TIMER_NON_SECURE)
-
-#define FVP_SBSA_WATCHDOG_REFRESH_BASE 0x000000002a450000
-#define FVP_SBSA_WATCHDOG_CONTROL_BASE 0x000000002a440000
-#define FVP_SBSA_WATCHDOG_GSIV 0x3B
-
-#define SBSA_WATCHDOG_EDGE_TRIGGERED EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_MODE
-#define SBSA_WATCHDOG_LEVEL_TRIGGERED 0
-#define SBSA_WATCHDOG_ACTIVE_LOW EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_TIMER_INTERRUPT_POLARITY
-#define SBSA_WATCHDOG_ACTIVE_HIGH 0
-#define SBSA_WATCHDOG_SECURE EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_FLAG_SECURE_TIMER
-#define SBSA_WATCHDOG_NON_SECURE 0
-
-#define FVP_SBSA_WATCHDOG_FLAGS (SBSA_WATCHDOG_NON_SECURE | SBSA_WATCHDOG_ACTIVE_HIGH | SBSA_WATCHDOG_LEVEL_TRIGGERED)
-
-#pragma pack (1)
-
-typedef struct {
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE Gtdt;
- EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE GtBlock;
- EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE Frames[FVP_TIMER_FRAMES_COUNT];
-#if (FVP_WATCHDOG_COUNT != 0)
- EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE Watchdogs[FVP_WATCHDOG_COUNT];
-#endif
-} FVP_GENERIC_TIMER_DESCRIPTION_TABLES;
-
-#pragma pack ()
-
-FVP_GENERIC_TIMER_DESCRIPTION_TABLES Gtdt = {
- {
- ARM_ACPI_HEADER(
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_SIGNATURE,
- FVP_GENERIC_TIMER_DESCRIPTION_TABLES,
- EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE_REVISION
- ),
- FVP_SYSTEM_TIMER_BASE_ADDRESS, // UINT64 PhysicalAddress
- EFI_ACPI_RESERVED_DWORD, // UINT32 Reserved
- FVP_SECURE_TIMER_EL1_GSIV, // UINT32 SecurePL1TimerGSIV
- FVP_GTDT_GTIMER_FLAGS, // UINT32 SecurePL1TimerFlags
- FVP_NON_SECURE_TIMER_EL1_GSIV, // UINT32 NonSecurePL1TimerGSIV
- FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL1TimerFlags
- FVP_VIRTUAL_TIMER_GSIV, // UINT32 VirtualTimerGSIV
- FVP_GTDT_GTIMER_FLAGS, // UINT32 VirtualTimerFlags
- FVP_NON_SECURE_EL2_GSIV, // UINT32 NonSecurePL2TimerGSIV
- FVP_GTDT_GTIMER_FLAGS, // UINT32 NonSecurePL2TimerFlags
- FVP_CNT_READ_BASE_ADDRESS, // UINT64 CntReadBasePhysicalAddress
- FVP_PLATFORM_TIMER_COUNT, // UINT32 PlatformTimerCount
-#if (FVP_PLATFORM_TIMER_COUNT != 0)
- sizeof (EFI_ACPI_6_1_GENERIC_TIMER_DESCRIPTION_TABLE) // UINT32 PlatfromTimerOffset
-#else
- 0
-#endif
- },
- {
- EFI_ACPI_6_1_GTDT_GT_BLOCK, // UINT8 Type
- sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT16 Length
- + sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_TIMER_STRUCTURE) *
- FVP_TIMER_FRAMES_COUNT,
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved
- FVP_GT_BLOCK_CTL_BASE, // UINT64 CntCtlBase
- FVP_TIMER_FRAMES_COUNT, // UINT32 GTBlockTimerCount
- sizeof(EFI_ACPI_6_1_GTDT_GT_BLOCK_STRUCTURE) // UINT32 GTBlockTimerOffset
- },
- {
- {
- 0, // UINT8 GTFrameNumber
- {EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3]
- FVP_GT_BLOCK_FRAME0_CTL_BASE, // UINT64 CntBaseX
- FVP_GT_BLOCK_FRAME0_CTL_EL0_BASE, // UINT64 CntEL0BaseX
- FVP_GT_BLOCK_FRAME0_GSIV, // UINT32 GTxPhysicalTimerGSIV
- FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags
- 0, // UINT32 GTxVirtualTimerGSIV
- 0, // UINT32 GTxVirtualTimerFlags
- FVP_GTX_COMMON_FLAGS_S // UINT32 GTxCommonFlags
- },
- {
- 1, // UINT8 GTFrameNumber
- {EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE}, // UINT8 Reserved[3]
- FVP_GT_BLOCK_FRAME1_CTL_BASE, // UINT64 CntBaseX
- FVP_GT_BLOCK_FRAME1_CTL_EL0_BASE, // UINT64 CntEL0BaseX
- FVP_GT_BLOCK_FRAME1_GSIV, // UINT32 GTxPhysicalTimerGSIV
- FVP_GTX_TIMER_FLAGS, // UINT32 GTxPhysicalTimerFlags
- 0, // UINT32 GTxVirtualTimerGSIV
- 0, // UINT32 GTxVirtualTimerFlags
- FVP_GTX_COMMON_FLAGS_NS // UINT32 GTxCommonFlags
- }
- },
-#if (FVP_WATCHDOG_COUNT != 0)
- {
- {
- EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG, // UINT8 Type
- sizeof(EFI_ACPI_6_1_GTDT_SBSA_GENERIC_WATCHDOG_STRUCTURE), // UINT16 Length
- EFI_ACPI_RESERVED_BYTE, // UINT8 Reserved
- FVP_SBSA_WATCHDOG_REFRESH_BASE, // UINT64 RefreshFramePhysicalAddress
- FVP_SBSA_WATCHDOG_CONTROL_BASE, // UINT64 WatchdogControlFramePhysicalAddress
- FVP_SBSA_WATCHDOG_GSIV, // UINT32 WatchdogTimerGSIV
- FVP_SBSA_WATCHDOG_FLAGS // UINT32 WatchdogTimerFlags
- }
- }
-#endif
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Gtdt;
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc b/Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc
deleted file mode 100644
index b34422e13f24b6cdf118e80777f2c1763a9fe170..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc
+++ /dev/null
@@ -1,85 +0,0 @@
-/** @file
-* Multiple APIC Description Table (MADT)
-*
-* Copyright (c) 2012 - 2015, ARM Limited. All rights reserved.
-* Copyright (c) 2016 Linaro Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include "FvpPlatform.h"
-#include <Library/AcpiLib.h>
-#include <Library/ArmLib.h>
-#include <Library/PcdLib.h>
-#include <IndustryStandard/Acpi61.h>
-
-//
-// Multiple APIC Description Table
-//
-#pragma pack (1)
-
-typedef struct {
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_HEADER Header;
- EFI_ACPI_6_1_GIC_STRUCTURE GicInterfaces[8];
- EFI_ACPI_6_1_GIC_DISTRIBUTOR_STRUCTURE GicDistributor;
- EFI_ACPI_6_1_GICR_STRUCTURE Gicr;
-} FVP_MULTIPLE_APIC_DESCRIPTION_TABLE;
-
-#pragma pack ()
-
-FVP_MULTIPLE_APIC_DESCRIPTION_TABLE Madt = {
- {
- ARM_ACPI_HEADER (
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_SIGNATURE,
- FVP_MULTIPLE_APIC_DESCRIPTION_TABLE,
- EFI_ACPI_6_1_MULTIPLE_APIC_DESCRIPTION_TABLE_REVISION
- ),
- //
- // MADT specific fields
- //
- 0, // LocalApicAddress
- 0, // Flags
- },
- {
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 0, 0, GET_MPID(0, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 1, 1, GET_MPID(0, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 2, 2, GET_MPID(0, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 3, 3, GET_MPID(0, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 4, 4, GET_MPID(1, 0), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 5, 5, GET_MPID(1, 1), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 6, 6, GET_MPID(1, 2), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- EFI_ACPI_6_0_GICC_STRUCTURE_INIT(
- 7, 7, GET_MPID(1, 3), EFI_ACPI_6_0_GIC_ENABLED, 0, FixedPcdGet64 (PcdGicInterruptInterfaceBase),
- 0x2C02F000, 0x2C010000, 0x19, 0, 0),
- },
- EFI_ACPI_6_0_GIC_DISTRIBUTOR_INIT(0, FixedPcdGet64 (PcdGicDistributorBase), 0, 3),
- /* GIC Redistributor */
- {
- EFI_ACPI_6_1_GICR, // UINT8 Type
- sizeof(EFI_ACPI_6_1_GICR_STRUCTURE), // UINT8 Length
- EFI_ACPI_RESERVED_WORD, // UINT16 Reserved
- FixedPcdGet64 (PcdGicRedistributorsBase), // UINT64 DiscoveryRangeBaseAddress
- 0x00200000, // UINT32 DiscoveryRangeLength
- }
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Madt;
diff --git a/Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc b/Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc
deleted file mode 100644
index 7a6b635ac7dfcab327b14b0bb057904740aa7b68..0000000000000000000000000000000000000000
--- a/Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc
+++ /dev/null
@@ -1,82 +0,0 @@
-/** @file
-* SPCR Table
-*
-* Copyright (c) 2014 - 2016, ARM Limited. All rights reserved.
-* Copyright (c) 2016, Linaro Ltd. All rights reserved.
-*
-* SPDX-License-Identifier: BSD-2-Clause-Patent
-*
-**/
-
-#include "FvpPlatform.h"
-#include <Library/AcpiLib.h>
-#include <IndustryStandard/Acpi61.h>
-#include <IndustryStandard/SerialPortConsoleRedirectionTable.h>
-
-/**
- * References:
- * Serial Port Console Redirection Table Specification Version 1.03 - August 10, 2015
- **/
-
-
-///
-/// SPCR Flow Control
-///
-#define SPCR_FLOW_CONTROL_NONE 0
-
-
-STATIC EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE Spcr = {
- ARM_ACPI_HEADER (EFI_ACPI_6_1_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_SIGNATURE,
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE,
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_REVISION),
- // UINT8 InterfaceType;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERFACE_TYPE_ARM_PL011_UART,
- // UINT8 Reserved1[3];
- {
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE,
- EFI_ACPI_RESERVED_BYTE
- },
- // EFI_ACPI_5_0_GENERIC_ADDRESS_STRUCTURE BaseAddress;
- ARM_GAS32 (0x1C090000),
- // UINT8 InterruptType;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_INTERRUPT_TYPE_GIC,
- // UINT8 Irq;
- 0, // Not used on ARM
- // UINT32 GlobalSystemInterrupt;
- 0x25,
- // UINT8 BaudRate;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_BAUD_RATE_115200,
- // UINT8 Parity;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_PARITY_NO_PARITY,
- // UINT8 StopBits;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_STOP_BITS_1,
- // UINT8 FlowControl;
- SPCR_FLOW_CONTROL_NONE,
- // UINT8 TerminalType;
- EFI_ACPI_SERIAL_PORT_CONSOLE_REDIRECTION_TABLE_TERMINAL_TYPE_ANSI,
- // UINT8 Reserved2;
- EFI_ACPI_RESERVED_BYTE,
- // UINT16 PciDeviceId;
- 0xFFFF,
- // UINT16 PciVendorId;
- 0xFFFF,
- // UINT8 PciBusNumber;
- 0x00,
- // UINT8 PciDeviceNumber;
- 0x00,
- // UINT8 PciFunctionNumber;
- 0x00,
- // UINT32 PciFlags;
- 0x00000000,
- // UINT8 PciSegment;
- 0x00,
- // UINT32 Reserved3;
- EFI_ACPI_RESERVED_DWORD
-};
-
-//
-// Reference the table being generated to prevent the optimizer from removing the
-// data structure from the executable
-//
-VOID* CONST ReferenceAcpiTable = &Spcr;
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
index 12562ceafd8ab020d61d4ba70fdd6c8c128da6a2..ccef0839570cdceb23d7ad68f1ca022f6276e427 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc
@@ -30,12 +30,9 @@ [Defines]
!endif
DT_SUPPORT = FALSE
- DYNAMIC_TABLES_FRAMEWORK = TRUE
!include Platform/ARM/VExpressPkg/ArmVExpress.dsc.inc
-!ifdef DYNAMIC_TABLES_FRAMEWORK
- !include DynamicTablesPkg/DynamicTables.dsc.inc
-!endif
+!include DynamicTablesPkg/DynamicTables.dsc.inc
[LibraryClasses.common]
ArmLib|ArmPkg/Library/ArmLib/ArmBaseLib.inf
@@ -284,16 +281,11 @@ [Components.common]
!endif
}
-!ifndef DYNAMIC_TABLES_FRAMEWORK
- MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf
-!else
Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf {
<PcdsFixedAtBuild>
gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase|0x1c090000
gArmPlatformTokenSpaceGuid.PL011UartInterrupt|0x25
}
-!endif
ArmPkg/Drivers/ArmGic/ArmGicDxe.inf
ArmPlatformPkg/Drivers/NorFlashDxe/NorFlashDxe.inf
diff --git a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
index 418566673981a9655fbc7a834942443a2005c403..7635cb7a8406bca4b5ff60ab7ac1774db40ee6fc 100644
--- a/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
+++ b/Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf
@@ -92,10 +92,7 @@ [FV.FvMain]
# ACPI Support
#
INF MdeModulePkg/Universal/Acpi/AcpiTableDxe/AcpiTableDxe.inf
-!ifndef DYNAMIC_TABLES_FRAMEWORK
- INF MdeModulePkg/Universal/Acpi/AcpiPlatformDxe/AcpiPlatformDxe.inf
- INF RuleOverride=ACPITABLE Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf
-!else
+
# Configuration Manager
INF Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf
@@ -103,7 +100,6 @@ [FV.FvMain]
# Dynamic Table fdf
#
!include DynamicTablesPkg/DynamicTables.fdf.inc
-!endif
#
# Multiple Console IO support
@@ -341,10 +337,3 @@ [Rule.Common.UEFI_APPLICATION.BINARY]
VERSION STRING="$(INF_VERSION)" Optional BUILD_NUM=$(BUILD_NUMBER)
}
-!ifndef DYNAMIC_TABLES_FRAMEWORK
-[Rule.Common.USER_DEFINED.ACPITABLE]
- FILE FREEFORM = $(NAMED_GUID) {
- RAW ACPI |.acpi
- RAW ASL |.aml
- }
-!endif
--
'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
^ permalink raw reply related [flat|nested] 14+ messages in thread* Re: [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model
2021-02-12 10:23 [PATCH edk2-platforms v1 00/12] Platform/ARM: Add support for FVP RevC Model Sami Mujawar
` (11 preceding siblings ...)
2021-02-12 10:23 ` [PATCH edk2-platforms v1 12/12] Platform/ARM/VExpressPkg: Remove redundant traditional ACPI support Sami Mujawar
@ 2021-02-13 10:26 ` Ard Biesheuvel
12 siblings, 0 replies; 14+ messages in thread
From: Ard Biesheuvel @ 2021-02-13 10:26 UTC (permalink / raw)
To: Sami Mujawar
Cc: devel, Ard Biesheuvel, thomas.abraham, Leif Lindholm,
Matteo.Carlini, Ben.Adderson, nd
On Fri, 12 Feb 2021 at 11:24, Sami Mujawar <sami.mujawar@arm.com> wrote:
>
> The Armv8-A Base RevC AEM FVP model includes a SMMUv3 and a PCIe
> subsystem. The FVP RevC model has an AHCI controller that appears
> as a device on the PCIe bus. The model parameters further allow
> a file on the host PC to be exposed as a SATA disk.
>
> AHCI is one of the defined boot mechanisms for a standards-based
> Operating System. Therefore, add support for the FVP RevC model.
>
> More information on the Armv8-A Base RevC AEM FVP model can be
> found at: https://developer.arm.com/tools-and-software/
> simulation-models/fixed-virtual-platforms/arm-ecosystem-models
>
> The ACPI support for RevC model is implemented using Dynamic
> Tables Framework. This enables unification of the firmware
> for FVP_Base_AEMv8A-AEMv8A and FVP_Base_RevC-2xAEMv8A models
> such that the same firmware binary can be used by both models.
>
> The last patch in this series drops support for the traditional
> ACPI tables as these are now redundant.
>
> The changes can be seen at:
> https://github.com/samimujawar/edk2-platforms/tree/1599_fvp_revc_v1
>
> Sami Mujawar (12):
> Platform/ARM/VExpressPkg: FVP RevC SysID.Rev defintion
> Platform/ARM/VExpressPkg: Add PCIe Host Bridge lib for FVP
> Platform/ARM/VExpressPkg: Memory map for FVP RevC model
> Platform/ARM/VExpressPkg: Configure SMMUv3 for FVP RevC
> Platform/ARM/VExpressPkg: Helper macro to map reference token
> Platform/ARM/VExpressPkg: ACPI support for FVP RevC model
> Platform/ARM/VExpressPkg: Add support for FVP RevC model
> Platform/ARM/VExpressPkg: Update ACPI Revision to 6.3
> Platform/ARM/VExpressPkg: Add SMC91x device description
> Platform/ARM/VExpressPkg: Add Virtio Block Device description
> Platform/ARM/VExpressPkg: Make Dynamic Tables Framework default
> Platform/ARM/VExpressPkg: Remove redundant traditional ACPI support
>
For the series,
Reviewed-by: Ard Biesheuvel <ardb@kernel.org>
Pushed as f62887cbb37e..404a76c577fc
Thanks!
> Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf | 38 --
> Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl | 123 -------
> Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc | 80 -----
> Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h | 40 ---
> Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc | 169 ---------
> Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc | 85 -----
> Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc | 82 -----
> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.dsc | 49 ++-
> Platform/ARM/VExpressPkg/ArmVExpress-FVP-AArch64.fdf | 33 +-
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/Dsdt.asl | 27 +-
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl | 204 +++++++++++
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.c | 376 +++++++++++++++++++-
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManager.h | 36 +-
> Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf | 10 +-
> Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c | 110 +++++-
> Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf | 4 +-
> Platform/ARM/VExpressPkg/Include/Platform/RTSM/ArmPlatform.h | 6 +-
> Platform/ARM/VExpressPkg/Include/VExpressMotherBoard.h | 5 +-
> Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/ArmVExpressLib.inf | 12 +-
> Platform/ARM/VExpressPkg/Library/ArmVExpressLibRTSM/RTSMMem.c | 31 +-
> Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c | 208 +++++++++++
> Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf | 48 +++
> Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni | 14 +
> 23 files changed, 1124 insertions(+), 666 deletions(-)
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/AcpiTables.inf
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/Dsdt.asl
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/Fadt.aslc
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/FvpPlatform.h
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/Gtdt.aslc
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/Madt.aslc
> delete mode 100644 Platform/ARM/VExpressPkg/AcpiTables/Spcr.aslc
> create mode 100644 Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslTables/SsdtPci.asl
> create mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.c
> create mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.inf
> create mode 100644 Platform/ARM/VExpressPkg/Library/ArmVExpressPciHostBridgeLib/ArmVExpressPciHostBridgeLib.uni
>
> --
> 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'
>
^ permalink raw reply [flat|nested] 14+ messages in thread