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dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by DB5EUR03FT037.mail.protection.outlook.com (10.152.20.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3846.25 via Frontend Transport; Fri, 12 Feb 2021 10:23:55 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2044.4; Fri, 12 Feb 2021 10:23:45 +0000 Received: from E107187.Arm.com (10.57.49.120) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2044.4 via Frontend Transport; Fri, 12 Feb 2021 10:23:45 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , Subject: [PATCH edk2-platforms v1 04/12] Platform/ARM/VExpressPkg: Configure SMMUv3 for FVP RevC Date: Fri, 12 Feb 2021 10:23:33 +0000 Message-ID: <20210212102341.24056-5-sami.mujawar@arm.com> X-Mailer: git-send-email 2.11.0.windows.3 In-Reply-To: <20210212102341.24056-1-sami.mujawar@arm.com> References: <20210212102341.24056-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: 61ddc02e-6eac-46ed-87e8-08d8cf4051d5 X-MS-TrafficTypeDiagnostic: AM6PR08MB4965:|AS8PR08MB6247: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:8273;OLM:8273; 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X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2021 10:24:03.0650 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 61ddc02e-6eac-46ed-87e8-08d8cf4051d5 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: DB5EUR03FT064.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AS8PR08MB6247 Content-Type: text/plain Base Platform RevC is a configuration of the Base Platform that includes a SMMUv3. TF-A configures the SMMUv3 to 'Abort all incoming transactions in order to implement a default deny policy on reset'. This prevents the firmware from using the AHCI-SATA disk that is available as a PCIe device. According to Server Base System Architecture (SBSA) 6.1, Section A Level 3 - firmware, Sub-section A.1 Memory map, 'All Non-secure on-chip masters in a base server system that are expected to be used by the platform firmware must be capable of addressing all of the Non-secure address space. If the master goes through a SMMU then the master must be capable of addressing all of the Non-secure address space even when the SMMU is off.' Therefore, configure the SMMUv3 to set Non-secure streams to bypass the SMMU. On firmware hand-off the OS is expected to reconfigure the SMMU. Signed-off-by: Sami Mujawar --- Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c | 110 +++++++++++++++++++- Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf | 4 +- 2 files changed, 112 insertions(+), 2 deletions(-) diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c index 189069484b57533ce43bcdccb30c85c882fc7ffb..1f1dfd3de5b9aedc1515d55a15963df75a295326 100644 --- a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.c @@ -1,6 +1,6 @@ /** @file - Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+ Copyright (c) 2013-2021, Arm Ltd. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -11,6 +11,8 @@ #include #include #include +#include +#include #include #include @@ -18,6 +20,13 @@ #define ARM_FVP_BASE_VIRTIO_BLOCK_BASE 0x1c130000 +// SMMUv3 Global Bypass Attribute (GBPA) register offset. +#define SMMU_GBPA 0x0044 + +// SMMU_GBPA register fields. +#define SMMU_GBPA_UPDATE BIT31 +#define SMMU_GBPA_ABORT BIT20 + #pragma pack(1) typedef struct { VENDOR_DEVICE_PATH Vendor; @@ -49,6 +58,92 @@ VIRTIO_BLK_DEVICE_PATH mVirtioBlockDevicePath = }; /** + Poll the SMMU register and test the value based on the mask. + + @param [in] SmmuReg Base address of the SMMU register. + @param [in] Mask Mask of register bits to monitor. + @param [in] Value Expected value. + + @retval EFI_SUCCESS Success. + @retval EFI_TIMEOUT Timeout. +**/ +STATIC +EFI_STATUS +EFIAPI +SmmuV3Poll ( + IN UINT64 SmmuReg, + IN UINT32 Mask, + IN UINT32 Value + ) +{ + UINT32 RegVal; + UINTN Count; + + // Set 1ms timeout value. + Count = 10; + do { + RegVal = MmioRead32 (SmmuReg); + if ((RegVal & Mask) == Value) { + return EFI_SUCCESS; + } + MicroSecondDelay (100); + } while ((--Count) > 0); + + DEBUG ((DEBUG_ERROR, "Timeout polling SMMUv3 register @%p\n", SmmuReg)); + DEBUG (( + DEBUG_ERROR, + "Read value 0x%x, expected 0x%x\n", + RegVal, + ((Value == 0) ? (RegVal & ~Mask) : (RegVal | Mask)) + )); + return EFI_TIMEOUT; +} + +/** + Initialise the SMMUv3 to set Non-secure streams to bypass the SMMU. + + @param [in] SmmuReg Base address of the SMMUv3. + + @retval EFI_SUCCESS Success. + @retval EFI_TIMEOUT Timeout. +**/ +STATIC +EFI_STATUS +EFIAPI +SmmuV3Init ( + IN UINT64 SmmuBase + ) +{ + EFI_STATUS Status; + UINT32 RegVal; + + // Attribute update has completed when SMMU_(S)_GBPA.Update bit is 0. + Status = SmmuV3Poll (SmmuBase + SMMU_GBPA, SMMU_GBPA_UPDATE, 0); + if (EFI_ERROR (Status)) { + return Status; + } + + // SMMU_(S)_CR0 resets to zero with all streams bypassing the SMMU, + // so just abort all incoming transactions. + RegVal = MmioRead32 (SmmuBase + SMMU_GBPA); + + // TF-A configures the SMMUv3 to abort all incoming transactions. + // Clear the SMMU_GBPA.ABORT to allow Non-secure streams to bypass + // the SMMU. + RegVal &= ~SMMU_GBPA_ABORT; + RegVal |= SMMU_GBPA_UPDATE; + + MmioWrite32 (SmmuBase + SMMU_GBPA, RegVal); + + Status = SmmuV3Poll (SmmuBase + SMMU_GBPA, SMMU_GBPA_UPDATE, 0); + if (EFI_ERROR (Status)) { + return Status; + } + + return EFI_SUCCESS; +} + +/** * Generic UEFI Entrypoint for 'ArmFvpDxe' driver * See UEFI specification for the details of the parameters */ @@ -60,6 +155,7 @@ ArmFvpInitialise ( ) { EFI_STATUS Status; + UINT32 SysId; Status = gBS->InstallProtocolInterface (&ImageHandle, &gEfiDevicePathProtocolGuid, EFI_NATIVE_INTERFACE, @@ -80,5 +176,17 @@ ArmFvpInitialise ( DEBUG ((EFI_D_ERROR, "ArmFvpDxe: Failed to install ShellDynCmdRunAxf\n")); } + // If FVP RevC - Configure SMMUv3 to set NS transactions in bypass mode. + SysId = MmioRead32 (ARM_VE_SYS_ID_REG); + if ((SysId & ARM_FVP_SYS_ID_REV_MASK) == ARM_FVP_BASE_REVC_REV) { + Status = SmmuV3Init (FVP_REVC_SMMUV3_BASE); + if (EFI_ERROR (Status)) { + DEBUG (( + DEBUG_ERROR, + "ArmFvpDxe: Failed to initialise SMMUv3 in bypass mode.\n" + )); + } + } + return Status; } diff --git a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf index a4021c2d9e241845736eea428a479a4abddd6413..c5f41795310141ae9d7c175c26d5694590a0a08a 100644 --- a/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf +++ b/Platform/ARM/VExpressPkg/Drivers/ArmVExpressDxe/ArmFvpDxe.inf @@ -1,6 +1,6 @@ #/** @file # -# Copyright (c) 2013-2015, ARM Ltd. All rights reserved.
+# Copyright (c) 2013-2021, Arm Ltd. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent # @@ -28,6 +28,8 @@ [Packages] [LibraryClasses] ArmShellCmdRunAxfLib BaseMemoryLib + IoLib + TimerLib UefiDriverEntryPoint UefiBootServicesTableLib VirtioMmioDeviceLib -- 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'