From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from EUR01-HE1-obe.outbound.protection.outlook.com (EUR01-HE1-obe.outbound.protection.outlook.com [40.107.13.77]) by mx.groups.io with SMTP id smtpd.web12.2014.1613125582238480723 for ; Fri, 12 Feb 2021 02:26:22 -0800 Authentication-Results: mx.groups.io; dkim=fail reason="body hash did not verify" header.i=@armh.onmicrosoft.com header.s=selector2-armh-onmicrosoft-com header.b=OMO3gQ47; spf=pass (domain: arm.com, ip: 40.107.13.77, mailfrom: sami.mujawar@arm.com) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EW8wvJHgPt2mXdrfXAqAtZ3ESmq9xvhpVV2PGIC9lxE=; b=OMO3gQ472IjaSikrjAG1IqZCFK7t3G/o6ubzA0iDwVGFHcTJy3Kb2pVmuhpxieBxESznqukvaF0VEzCogHvsYgNB4bit5gcPYaWnyxugJn0EksUrVoZ2sZcAprXnJErHdgHJfOQLsxJwrYHUhuZyp35kHxevWSlWnq8I2Hw+mRM= Received: from AM6PR08CA0013.eurprd08.prod.outlook.com (2603:10a6:20b:b2::25) by AM5PR0802MB2483.eurprd08.prod.outlook.com (2603:10a6:203:9b::22) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.31; Fri, 12 Feb 2021 10:26:14 +0000 Received: from VE1EUR03FT021.eop-EUR03.prod.protection.outlook.com (2603:10a6:20b:b2:cafe::dc) by AM6PR08CA0013.outlook.office365.com (2603:10a6:20b:b2::25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.26 via Frontend Transport; Fri, 12 Feb 2021 10:26:14 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 63.35.35.123) smtp.mailfrom=arm.com; edk2.groups.io; dkim=pass (signature was verified) header.d=armh.onmicrosoft.com;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 63.35.35.123 as permitted sender) receiver=protection.outlook.com; client-ip=63.35.35.123; helo=64aa7808-outbound-1.mta.getcheckrecipient.com; Received: from 64aa7808-outbound-1.mta.getcheckrecipient.com (63.35.35.123) by VE1EUR03FT021.mail.protection.outlook.com (10.152.18.117) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.25 via Frontend Transport; Fri, 12 Feb 2021 10:26:13 +0000 Received: ("Tessian outbound 587c3d093005:v71"); Fri, 12 Feb 2021 10:26:13 +0000 X-CheckRecipientChecked: true X-CR-MTA-CID: 340d7aaeea1fef7f X-CR-MTA-TID: 64aa7808 Received: from 48956fc437de.1 by 64aa7808-outbound-1.mta.getcheckrecipient.com id 6BC13822-0EF4-4479-B612-D05D69D4265C.1; Fri, 12 Feb 2021 10:26:07 +0000 Received: from EUR04-DB3-obe.outbound.protection.outlook.com by 64aa7808-outbound-1.mta.getcheckrecipient.com with ESMTPS id 48956fc437de.1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384); Fri, 12 Feb 2021 10:26:07 +0000 ARC-Seal: i=1; a=rsa-sha256; s=arcselector9901; d=microsoft.com; cv=none; b=BbdjD7nO74Oym2Esvwl2Cpk2cFbWpj7E3t7gOz08mJocFa7pLr3YkpqiLQ+xRuVyv/ltNDPwizyElxo9OK5EKdnUKXtnvoq3SM+axIF7NOvT277zbXvStH6IfrdEahrON79Mkg4BmesITj9X140G/SsEKuVpZ8rbbfOaj1kCpYGfX6oZPIoDh/wk759uqvbIThryBZK4gQr69S/Rmd8xGXYQjtj1lto3S8RbwNDo50OebGRix4mt3qd8ivBfRzlVK7cpZrjj2byfaPvKU5HgaQrhDQOtqaBi/jvb/LlbZFe2zJdEjCcCvyRdjtZuqQfN0TzKvTn6iNNk+JZpMOM0dQ== ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=microsoft.com; s=arcselector9901; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EW8wvJHgPt2mXdrfXAqAtZ3ESmq9xvhpVV2PGIC9lxE=; b=kNm7uN34eVnxPXfu01mGv+bHds++/YPleXZYhXfbsaZvt8AbCqROk38YcAsNg5TFOfWICeI4pVQwbNRy4t1UC/Z68N44jiLZkkaHPSfy0X6Awy+rykC/5ZFAvi+GIZ1UNJFUlyhbDpZ0UrdE5pHMKUEArUegdRsrNUTNrOf0OmZt0THrA7Vo8cuai5IyboY2ZMwG+Evc/KEM60QzBxtzq7sc17gzPnKTP3RPr3W+fL6vD9IM2hA3IyShRvzeNKMoY3uBF+NcsESaPzzCvnnedMKT8BkxhutDuqaWwQ4AJZHvprsphVoIqSscFG1ICBEp08x0HZTvEAR6itrK2toTFA== ARC-Authentication-Results: i=1; mx.microsoft.com 1; spf=pass (sender ip is 40.67.248.234) smtp.rcpttodomain=edk2.groups.io smtp.mailfrom=arm.com; dmarc=pass (p=none sp=none pct=100) action=none header.from=arm.com; dkim=none (message not signed); arc=none DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=armh.onmicrosoft.com; s=selector2-armh-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=EW8wvJHgPt2mXdrfXAqAtZ3ESmq9xvhpVV2PGIC9lxE=; b=OMO3gQ472IjaSikrjAG1IqZCFK7t3G/o6ubzA0iDwVGFHcTJy3Kb2pVmuhpxieBxESznqukvaF0VEzCogHvsYgNB4bit5gcPYaWnyxugJn0EksUrVoZ2sZcAprXnJErHdgHJfOQLsxJwrYHUhuZyp35kHxevWSlWnq8I2Hw+mRM= Received: from DB6PR0601CA0005.eurprd06.prod.outlook.com (2603:10a6:4:7b::15) by DB8PR08MB3980.eurprd08.prod.outlook.com (2603:10a6:10:b1::23) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.27; Fri, 12 Feb 2021 10:23:56 +0000 Received: from DB5EUR03FT037.eop-EUR03.prod.protection.outlook.com (2603:10a6:4:7b:cafe::e6) by DB6PR0601CA0005.outlook.office365.com (2603:10a6:4:7b::15) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.3846.27 via Frontend Transport; Fri, 12 Feb 2021 10:23:56 +0000 X-MS-Exchange-Authentication-Results: spf=pass (sender IP is 40.67.248.234) smtp.mailfrom=arm.com; edk2.groups.io; dkim=none (message not signed) header.d=none;edk2.groups.io; dmarc=pass action=none header.from=arm.com; Received-SPF: Pass (protection.outlook.com: domain of arm.com designates 40.67.248.234 as permitted sender) receiver=protection.outlook.com; client-ip=40.67.248.234; helo=nebula.arm.com; Received: from nebula.arm.com (40.67.248.234) by DB5EUR03FT037.mail.protection.outlook.com (10.152.20.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.20.3846.25 via Frontend Transport; Fri, 12 Feb 2021 10:23:56 +0000 Received: from AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) by AZ-NEU-EX04.Arm.com (10.251.24.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2044.4; Fri, 12 Feb 2021 10:23:48 +0000 Received: from AZ-NEU-EX04.Arm.com (10.251.24.32) by AZ-NEU-EX01.Emea.Arm.com (10.251.26.4) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1779.2; Fri, 12 Feb 2021 10:23:46 +0000 Received: from E107187.Arm.com (10.57.49.120) by mail.arm.com (10.251.24.32) with Microsoft SMTP Server id 15.1.2044.4 via Frontend Transport; Fri, 12 Feb 2021 10:23:46 +0000 From: "Sami Mujawar" To: CC: Sami Mujawar , , , , , , Subject: [PATCH edk2-platforms v1 06/12] Platform/ARM/VExpressPkg: ACPI support for FVP RevC model Date: Fri, 12 Feb 2021 10:23:35 +0000 Message-ID: <20210212102341.24056-7-sami.mujawar@arm.com> X-Mailer: git-send-email 2.11.0.windows.3 In-Reply-To: <20210212102341.24056-1-sami.mujawar@arm.com> References: <20210212102341.24056-1-sami.mujawar@arm.com> MIME-Version: 1.0 X-EOPAttributedMessage: 1 X-MS-Office365-Filtering-HT: Tenant X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: eacc485f-c295-4320-c6f5-08d8cf409fd3 X-MS-TrafficTypeDiagnostic: DB8PR08MB3980:|AM5PR0802MB2483: X-Microsoft-Antispam-PRVS: x-checkrecipientrouted: true NoDisclaimer: true X-MS-Oob-TLC-OOBClassifiers: OLM:9508;OLM:9508; X-MS-Exchange-SenderADCheck: 1 X-Microsoft-Antispam-Untrusted: BCL:0; X-Microsoft-Antispam-Message-Info-Original: vqUvBeCkodHVK+ni9CXSN8FlSg711EnJJVjEiaKKT/zIzBK++Zr3UlGI7xyG0moTZwRoLltcpAPdb1bD0Qdorg3FUncqmqIMhD0ZpzqnWSzXNiigmS1yirClinagZorwWD+xe+Gt6hL6U5k7hYpXCPnzHpg5zyEFELfnjOtUnvzJrVVt7G40j1Ojbn2E1pXwE3Aw0lCCGwk2sb2kysScUnh65M5BNzUnT5ysOhmAvquY0nMFN/Xg/13qX1ZSVkaYUGZVZTJxDlFzeXLCdVK7E9eLBXqRliKLOTc4NA4uOPnLcS9istTgQ7z6zvlik8spK6LkAWwlqrcDUK5++scdqtNPQZEicgJJcrmzM96Nfa4myfp+S8fSn6wJM6uIVRb27jdkieEkfymfhWd/M5BGN3ZYNHRedXoto/FSBDhyWcLQeb/fA3wUxR6Mvm4uefDxdVfU+tLgYst+ijvRwO4vEzu8FKtHb/OV3Pynsl2lTfwPTpmRU5BrPcf1gi1usHExR1yzt/U71IifxbNc+AO+C1DBeVMpp656wvdoTmqHa54iHGL3+zqDP1sQ5/k5JIXlPgmesAu2Sdn+N1CpA9D2Jq5giS5n4jqy2euHO1Btja9vxYRm+gP6DHleE1fciMJB5l2SZ0mrpP6m21gc4uz822IbbjaDpiXM2nRPgWRs+2i6YIay8svPwUE9qvXvbU9Y X-Forefront-Antispam-Report-Untrusted: CIP:40.67.248.234;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:nebula.arm.com;PTR:InfoDomainNonexistent;CAT:NONE;SFS:(4636009)(36840700001)(46966006)(7696005)(82310400003)(6666004)(83380400001)(336012)(36756003)(356005)(19627235002)(47076005)(70586007)(5660300002)(81166007)(498600001)(86362001)(36860700001)(8936002)(426003)(44832011)(2616005)(26005)(8676002)(30864003)(2906002)(1076003)(186003)(70206006)(54906003)(4326008)(6916009)(36900700001);DIR:OUT;SFP:1101; X-MS-Exchange-Transport-CrossTenantHeadersStamped: DB8PR08MB3980 Return-Path: Sami.Mujawar@arm.com X-MS-Exchange-Transport-CrossTenantHeadersStripped: VE1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Office365-Filtering-Correlation-Id-Prvs: 8a65bb8b-e74a-4575-5942-08d8cf404df1 X-Microsoft-Antispam: BCL:0; X-Microsoft-Antispam-Message-Info: k/Fj88EozINjt0O2UlNr035D9u12bbwQ6JxFXId0+7DHtwKDJXlQJ754BczVV1SDkpql0wEHTwigLkn5xW8ntLEB08wp2lpIA8+KEWptgqjhbOsgmvfa1dI0F48qR+cm+mLQZB5p983IQ9WmDgsTTXLyPvTUlYpyfIUfUYnQvP65eI4/W+fbxtXyIvtA0kLOfpUfeSEi1mlGPuO/MbZXGuvsfEm7lWWyH/sxWtAHuzTlmgmEvYUVGgryWd0xK7hesJuY9PNbzlLUgDz8L5CKBqECgsUigGM8g34YI+nW7SWW0g2xdXPw1oRXPfzxFMiyFoWGAPQsuD9mOm04Effiuicp3an9y+aMJQkCuBhGCttpsMkEEkNLL8GRCW417dGa/Z8jAxXoI7uOc8ZB9ba5ETKkg6K/fZpAgu+e7GgJjEl2TIiwszVhTZM79/X4O0fz6stKnC+nrTdYj4YZkzSxD0suITBNbqc0QiJe0Zr4cSLczNOx5czo6Hwc82m39GFyJi3AW8in8mHzTMgXmPwN7wIv8e3jJhZ64SgCAQrG8+S5Rlx6KBnM7sqBmqsW4qx0/BiQwKkAmwBfNLo0ZJhICBLKbF64ugewyks/ts8ZLfOLNYVG4w3elRhyZs7aaCcIF1mxPKyiqBFQU8hK1u1mgMd3O676r6t0puvZnnQVfCw= X-Forefront-Antispam-Report: CIP:63.35.35.123;CTRY:IE;LANG:en;SCL:1;SRV:;IPV:CAL;SFV:NSPM;H:64aa7808-outbound-1.mta.getcheckrecipient.com;PTR:ec2-63-35-35-123.eu-west-1.compute.amazonaws.com;CAT:NONE;SFS:(4636009)(39860400002)(346002)(136003)(376002)(396003)(46966006)(36840700001)(186003)(36756003)(2616005)(426003)(6666004)(1076003)(6916009)(70586007)(70206006)(30864003)(478600001)(5660300002)(54906003)(336012)(316002)(19627235002)(4326008)(8676002)(8936002)(82310400003)(86362001)(2906002)(83380400001)(7696005)(44832011)(47076005)(36860700001)(82740400003)(81166007)(26005);DIR:OUT;SFP:1101; X-OriginatorOrg: arm.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 12 Feb 2021 10:26:13.7529 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: eacc485f-c295-4320-c6f5-08d8cf409fd3 X-MS-Exchange-CrossTenant-Id: f34e5979-57d9-4aaa-ad4d-b122a662184d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=f34e5979-57d9-4aaa-ad4d-b122a662184d;Ip=[63.35.35.123];Helo=[64aa7808-outbound-1.mta.getcheckrecipient.com] X-MS-Exchange-CrossTenant-AuthSource: VE1EUR03FT021.eop-EUR03.prod.protection.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: AM5PR0802MB2483 Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable Base Platform RevC is a configuration of the Base Platform that includes a PCIe subsystem and a SMMUv3. It also has an AHCI-SATA disk controller as a device on the PCIe bus. To enable an OS to use these features add the following ACPI tables: - IORT - MCFG - SSDT PCIe Also add checks such that these additional tables are only installed if the FVP model is RevC. This allows a unified firmware for use with both the FVP_Base_AEMv8A-AEMv8A model and the FVP_Base_RevC-2xAEMv8A model. Note: The CPU affinities are shifted in the FVP_Base_RevC-2xAEMv8A model and this is adjusted in InitializePlatformRepository(). Signed-off-by: Sami Mujawar --- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/AslT= ables/SsdtPci.asl | 204 ++++++++++++ Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.c | 349 +++++++++++++++++++- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManager.h | 30 +- Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe/Conf= igurationManagerDxe.inf | 10 +- 4 files changed, 588 insertions(+), 5 deletions(-) diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/AslTables/SsdtPci.asl b/Platform/ARM/VExpressPkg/ConfigurationManag= er/ConfigurationManagerDxe/AslTables/SsdtPci.asl new file mode 100644 index 0000000000000000000000000000000000000000..e4b5a02cc9571743c4a0300a065= 7f090ae996326 --- /dev/null +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /AslTables/SsdtPci.asl @@ -0,0 +1,204 @@ +/** @file + SSDT for FVP PCIe + + Copyright (c) 2017 - 2021, Arm Ltd. All rights reserved.
+ + SPDX-License-Identifier: BSD-2-Clause-Patent + +**/ + +#include "ArmPlatform.h" + +/* + See ACPI 6.1 Section 6.2.13 + + There are two ways that _PRT can be used. + + In the first model, a PCI Link device is used to provide additional + configuration information such as whether the interrupt is Level or + Edge triggered, it is active High or Low, Shared or Exclusive, etc. + + In the second model, the PCI interrupts are hardwired to specific + interrupt inputs on the interrupt controller and are not + configurable. In this case, the Source field in _PRT does not + reference a device, but instead contains the value zero, and the + Source Index field contains the global system interrupt to which the + PCI interrupt is hardwired. + + We use the first model with link indirection to set the correct + interrupt type as PCI defaults (Level Triggered, Active Low) are not + compatible with GICv2. +*/ +#define LNK_DEVICE(Unique_Id, Link_Name, irq) \ + Device (Link_Name) { \ + Name (_HID, EISAID("PNP0C0F")) \ + Name (_UID, Unique_Id) \ + Name (_PRS, ResourceTemplate() { \ + Interrupt (ResourceProducer, Level, ActiveHigh, Exclusive) { irq } \ + }) \ + Method (_CRS, 0) { Return (_PRS) } \ + Method (_SRS, 1) { } \ + Method (_DIS) { } \ +} + +#define PRT_ENTRY(Address, Pin, Link) = \ + Package (4) { = \ + Address, /* uses the same format as _ADR */ = \ + Pin, /* The PCI pin number of the device (0-INTA, 1-INTB, 2-INTC,= 3-INTD) */ \ + Link, /* Interrupt allocated via Link device */ = \ + Zero /* global system interrupt number (no used) */ = \ +} + +/* + See Reference [1] 6.1.1 + "High word=EF=BF=BDDevice #, Low word=EF=BF=BDFunction #. (for example, = device 3, + function 2 is 0x00030002). To refer to all the functions on a device #, + use a function number of FFFF)." +*/ +#define ROOT_PRT_ENTRY(Pin, Link) PRT_ENTRY (0x0000FFFF, Pin, Link) // = Device 0 for Bridge. + +DefinitionBlock ("SsdtPci.aml", "SSDT", 2, "ARMLTD", "FVP-REVC", 1) { + Scope(_SB) { + // + // PCI Root Complex + // + LNK_DEVICE (1, LNKA, 168) + LNK_DEVICE (2, LNKB, 169) + LNK_DEVICE (3, LNKC, 170) + LNK_DEVICE (4, LNKD, 171) + + Device(PCI0) + { + Name (_HID, EISAID ("PNP0A08")) // PCI Express Root Bridge + Name (_CID, EISAID ("PNP0A03")) // Compatible PCI Root Bridge + Name (_SEG, Zero) // PCI Segment Group number + Name (_BBN, Zero) // PCI Base Bus Number + Name (_CCA, 1) // Initially mark the PCI coherent + + // Root Complex 0 + Device (RP0) { + Name (_ADR, 0xF0000000) // Dev 0, Func 0 + } + + // PCI Routing Table + Name (_PRT, Package () { + ROOT_PRT_ENTRY (0, LNKA), // INTA + ROOT_PRT_ENTRY (1, LNKB), // INTB + ROOT_PRT_ENTRY (2, LNKC), // INTC + ROOT_PRT_ENTRY (3, LNKD), // INTD + }) + // Root complex resources + Method (_CRS, 0, Serialized) { + Name (RBUF, ResourceTemplate () { + WordBusNumber ( // Bus numbers assigned to this root + ResourceProducer, + MinFixed, MaxFixed, PosDecode, + 0, // AddressGranularity + 0, // AddressMinimum - Minimum Bus Number + 255, // AddressMaximum - Maximum Bus Number + 0, // AddressTranslation - Set to 0 + 256 // RangeLength - Number of Busses + ) + + DWordMemory ( // 32-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x50000000, // Min Base Address + 0x57FFFFFF, // Max Base Address + 0x00000000, // Translate + 0x08000000 // Length + ) + + QWordMemory ( // 64-bit BAR Windows + ResourceProducer, + PosDecode, + MinFixed, + MaxFixed, + Cacheable, + ReadWrite, + 0x00000000, // Granularity + 0x4000000000, // Min Base Address + 0x40FFFFFFFF, // Max Base Address + 0x00000000, // Translate + 0x100000000 // Length + ) + + DWordIo ( // IO window + ResourceProducer, + MinFixed, + MaxFixed, + PosDecode, + EntireRange, + 0x00000000, // Granularity + 0x00000000, // Min Base Address + 0x007fffff, // Max Base Address + 0x5f800000, // Translate + 0x00800000, // Length + , + , + , + TypeTranslation + ) + }) // Name (RBUF) + + Return (RBUF) + } // Method(_CRS) + + // + // OS Control Handoff + // + Name (SUPP, Zero) // PCI _OSC Support Field value + Name (CTRL, Zero) // PCI _OSC Control Field value + + /* + See [1] 6.2.10, [2] 4.5 + */ + Method (_OSC,4) { + // Check for proper UUID + If(LEqual (Arg0,ToUUID ("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) = { + // Create DWord-adressable fields from the Capabilities Buffer + CreateDWordField (Arg3, 0, CDW1) + CreateDWordField (Arg3, 4, CDW2) + CreateDWordField (Arg3, 8, CDW3) + + // Save Capabilities DWord2 & 3 + Store (CDW2, SUPP) + Store (CDW3, CTRL) + + // Only allow native hot plug control if OS supports: + // * ASPM + // * Clock PM + // * MSI/MSI-X + If(LNotEqual (And (SUPP, 0x16), 0x16)) { + And (CTRL, 0x1E, CTRL) // Mask bit 0 (and undefined bits) + } + + // Always allow native PME, AER (no dependencies) + + // Never allow SHPC (no SHPC controller in this system) + And (CTRL, 0x1D, CTRL) + + If(LNotEqual (Arg1, One)) { // Unknown revision + Or (CDW1, 0x08, CDW1) + } + + If(LNotEqual (CDW3, CTRL)) { // Capabilities bits were masked + Or (CDW1, 0x10, CDW1) + } + + // Update DWORD3 in the buffer + Store (CTRL,CDW3) + Return (Arg3) + } Else { + Or (CDW1, 4, CDW1) // Unrecognized UUID + Return (Arg3) + } + } // End _OSC + } // PCI0 + } +} diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.c b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.c index 49aa16184a2da587471239a7c90ed864f963896c..273ae35ffcdae2fbe1214676a10= f6a3ca04e4242 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.c @@ -12,6 +12,8 @@ =20 #include #include +#include +#include #include #include #include @@ -74,7 +76,30 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInf= o =3D { EFI_ACPI_DBG2_DEBUG_DEVICE_INFORMATION_STRUCT_REVISION, CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdDbg2), NULL - } + }, + + // Note: The last 3 tables in this list are for FVP RevC only. + // IORT Table - FVP RevC + { + EFI_ACPI_6_2_IO_REMAPPING_TABLE_SIGNATURE, + EFI_ACPI_IO_REMAPPING_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdIort), + NULL + }, + // PCI MCFG Table - FVP RevC + { + EFI_ACPI_6_2_PCI_EXPRESS_MEMORY_MAPPED_CONFIGURATION_SPACE_BASE_ADDR= ESS_DESCRIPTION_TABLE_SIGNATURE, + EFI_ACPI_MEMORY_MAPPED_CONFIGURATION_SPACE_ACCESS_TABLE_REVISION, + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdMcfg), + NULL + }, + // SSDT table describing the PCI root complex - FVP RevC + { + EFI_ACPI_6_2_SECONDARY_SYSTEM_DESCRIPTION_TABLE_SIGNATURE, + 0, // Unused + CREATE_STD_ACPI_TABLE_GEN_ID (EStdAcpiTableIdSsdt), + (EFI_ACPI_DESCRIPTION_HEADER*)ssdtpci_aml_code + }, }, =20 // Boot architecture information @@ -90,6 +115,8 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepositoryInf= o =3D { =20 /* GIC CPU Interface information GIC_ENTRY (CPUInterfaceNumber, Mpidr, PmuIrq, VGicIrq, EnergyEfficien= cy) + Note: The MPIDR is fixed up in InitializePlatformRepository() if the + platform is FVP RevC. */ { GICC_ENTRY (0, GET_MPID (0, 0), 92, 25, 0), @@ -215,7 +242,121 @@ EDKII_PLATFORM_REPOSITORY_INFO VExpressPlatRepository= Info =3D { 0, // The physical address for the Interrupt Translation Service 0x2f020000 - } + }, + + // SMMUv3 Node + { + // Reference token for this Iort node + REFERENCE_TOKEN (SmmuV3Info), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN (DeviceIdMapping[0]), + + // SMMU Base Address + FVP_REVC_SMMUV3_BASE, + // SMMU flags + EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, + // VATOS address + 0, + // Model + EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, + // GSIV of the Event interrupt if SPI based + 0x6A, + // PRI Interrupt if SPI based + 0x6B, + // GERR interrupt if GSIV based + 0x6F, + // Sync interrupt if GSIV based + 0x6D, + + // Proximity domain flag, ignored in this case + 0, + // Index into the array of ID mapping, ignored as SMMU + // control interrupts are GSIV based + 0 + }, + + // ITS group node + { + // Reference token for this Iort node + REFERENCE_TOKEN (ItsGroupInfo), + // The number of ITS identifiers in the ITS node. + 1, + // Reference token for the ITS identifier array + REFERENCE_TOKEN (ItsIdentifierArray) + }, + // ITS identifier array + { + { + // The ITS Identifier + 0 + } + }, + + // Root Complex node info + { + // Reference token for this Iort node + REFERENCE_TOKEN (RootComplexInfo), + // Number of ID mappings + 1, + // Reference token for the ID mapping array + REFERENCE_TOKEN (DeviceIdMapping[1]), + + // Memory access properties : Cache coherent attributes + EFI_ACPI_IORT_MEM_ACCESS_PROP_CCA, + // Memory access properties : Allocation hints + 0, + // Memory access properties : Memory access flags + 0, + // ATS attributes + EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED, + // PCI segment number + 0 + }, + + // Array of Device ID mappings + { + /* Mapping When SMMUv3 is defined + RootComplex -> SMMUv3 -> ITS Group + */ + + // SMMUv3 device ID mapping + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference + REFERENCE_TOKEN (ItsGroupInfo), + // Flags + 0 + }, + // Device ID mapping for Root complex node + { + // Input base + 0x0, + // Number of input IDs + 0x0000FFFF, + // Output Base + 0x0, + // Output reference token for the IORT node + REFERENCE_TOKEN (SmmuV3Info), + // Flags + 0 + } + }, + + // PCI Configuration Space Info + { + FixedPcdGet64 (PcdPciExpressBaseAddress), + // PciSegmentGroupNumber + 0, + FixedPcdGet32 (PcdPciBusMin), + FixedPcdGet32 (PcdPciBusMax) + }, }; =20 /** A helper function for returning the Configuration Manager Objects. @@ -324,6 +465,24 @@ InitializePlatformRepository ( IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This ) { + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + PlatformRepo =3D This->PlatRepoInfo; + + PlatformRepo->SysId =3D MmioRead32 (ARM_VE_SYS_ID_REG); + if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) =3D=3D + ARM_FVP_BASE_REVC_REV) { + // REVC affinity is shifted, update the MPIDR + PlatformRepo->GicCInfo[0].MPIDR =3D GET_MPID_MT (0, 0, 0); + PlatformRepo->GicCInfo[1].MPIDR =3D GET_MPID_MT (0, 1, 0); + PlatformRepo->GicCInfo[2].MPIDR =3D GET_MPID_MT (0, 2, 0); + PlatformRepo->GicCInfo[3].MPIDR =3D GET_MPID_MT (0, 3, 0); + + PlatformRepo->GicCInfo[4].MPIDR =3D GET_MPID_MT (1, 0, 0); + PlatformRepo->GicCInfo[5].MPIDR =3D GET_MPID_MT (1, 1, 0); + PlatformRepo->GicCInfo[6].MPIDR =3D GET_MPID_MT (1, 2, 0); + PlatformRepo->GicCInfo[7].MPIDR =3D GET_MPID_MT (1, 3, 0); + } return EFI_SUCCESS; } =20 @@ -370,6 +529,91 @@ GetGTBlockTimerFrameInfo ( return EFI_SUCCESS; } =20 +/** Return an ITS identifier array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +*/ +EFI_STATUS +EFIAPI +GetItsIdentifierArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo; + + if (Token !=3D (CM_OBJECT_TOKEN)&PlatformRepo->ItsIdentifierArray) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (PlatformRepo->ItsIdentifierArray); + CmObject->Data =3D (VOID*)&PlatformRepo->ItsIdentifierArray; + CmObject->Count =3D ARRAY_SIZE (PlatformRepo->ItsIdentifierArray); + return EFI_SUCCESS; +} + +/** Return a device Id mapping array. + + @param [in] This Pointer to the Configuration Manager Protocol. + @param [in] CmObjectId The Configuration Manager Object ID. + @param [in] Token A token for identifying the object + @param [out] CmObject Pointer to the Configuration Manager Object + descriptor describing the requested Object. + + @retval EFI_SUCCESS Success. + @retval EFI_INVALID_PARAMETER A parameter is invalid. + @retval EFI_NOT_FOUND The required object information is not fou= nd. +*/ +EFI_STATUS +EFIAPI +GetDeviceIdMappingArray ( + IN CONST EDKII_CONFIGURATION_MANAGER_PROTOCOL * CONST This, + IN CONST CM_OBJECT_ID CmObjectId, + IN CONST CM_OBJECT_TOKEN Token, + IN OUT CM_OBJ_DESCRIPTOR * CONST CmObject + ) +{ + EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + + if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { + ASSERT (This !=3D NULL); + ASSERT (CmObject !=3D NULL); + return EFI_INVALID_PARAMETER; + } + + PlatformRepo =3D This->PlatRepoInfo; + + if ((Token !=3D (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[0]) && + (Token !=3D (CM_OBJECT_TOKEN)&PlatformRepo->DeviceIdMapping[1])) { + return EFI_NOT_FOUND; + } + + CmObject->ObjectId =3D CmObjectId; + CmObject->Size =3D sizeof (CM_ARM_ID_MAPPING); + CmObject->Data =3D (VOID*)Token; + CmObject->Count =3D 1; + return EFI_SUCCESS; +} + /** Return a standard namespace object. =20 @param [in] This Pointer to the Configuration Manager Protoc= ol. @@ -394,7 +638,9 @@ GetStandardNameSpaceObject ( { EFI_STATUS Status; EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN AcpiTableCount; =20 + Status =3D EFI_SUCCESS; if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { ASSERT (This !=3D NULL); ASSERT (CmObject !=3D NULL); @@ -402,8 +648,16 @@ GetStandardNameSpaceObject ( } =20 Status =3D EFI_NOT_FOUND; + AcpiTableCount =3D ARRAY_SIZE (PlatformRepo->CmAcpiTableList); PlatformRepo =3D This->PlatRepoInfo; =20 + if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) !=3D + ARM_FVP_BASE_REVC_REV) { + // The last 3 tables in the ACPI table list are for FVP RevC + // Reduce the count by 3 if the platform is not FVP RevC + AcpiTableCount -=3D 3; + } + switch (GET_CM_OBJECT_ID (CmObjectId)) { case EStdObjCfgMgrInfo: Status =3D HandleCmObject ( @@ -420,7 +674,7 @@ GetStandardNameSpaceObject ( CmObjectId, &PlatformRepo->CmAcpiTableList, sizeof (PlatformRepo->CmAcpiTableList), - ARRAY_SIZE (PlatformRepo->CmAcpiTableList), + AcpiTableCount, CmObject ); break; @@ -464,6 +718,12 @@ GetArmNameSpaceObject ( { EFI_STATUS Status; EDKII_PLATFORM_REPOSITORY_INFO * PlatformRepo; + UINTN Smmuv3Count; + UINTN ItsGroupCount; + UINTN ItsIdentifierArrayCount; + UINTN RootComplexCount; + UINTN DeviceIdMappingArrayCount; + UINTN PciConfigSpaceCount; =20 if ((This =3D=3D NULL) || (CmObject =3D=3D NULL)) { ASSERT (This !=3D NULL); @@ -474,6 +734,23 @@ GetArmNameSpaceObject ( Status =3D EFI_NOT_FOUND; PlatformRepo =3D This->PlatRepoInfo; =20 + if ((PlatformRepo->SysId & ARM_FVP_SYS_ID_REV_MASK) =3D=3D + ARM_FVP_BASE_REVC_REV) { + Smmuv3Count =3D 1; + ItsGroupCount =3D 1; + ItsIdentifierArrayCount =3D ARRAY_SIZE (PlatformRepo->ItsIdentifierArr= ay); + RootComplexCount =3D 1; + DeviceIdMappingArrayCount =3D ARRAY_SIZE (PlatformRepo->DeviceIdMappin= g); + PciConfigSpaceCount =3D 1; + } else { + Smmuv3Count =3D 0; + ItsGroupCount =3D 0; + ItsIdentifierArrayCount =3D 0; + RootComplexCount =3D 0; + DeviceIdMappingArrayCount =3D 0; + PciConfigSpaceCount =3D 0; + } + switch (GET_CM_OBJECT_ID (CmObjectId)) { case EArmObjBootArchInfo: Status =3D HandleCmObject ( @@ -609,6 +886,72 @@ GetArmNameSpaceObject ( ); break; =20 + case EArmObjSmmuV3: + Status =3D HandleCmObject ( + CmObjectId, + &PlatformRepo->SmmuV3Info, + sizeof (PlatformRepo->SmmuV3Info), + Smmuv3Count, + CmObject + ); + break; + + case EArmObjItsGroup: + Status =3D HandleCmObject ( + CmObjectId, + &PlatformRepo->ItsGroupInfo, + sizeof (PlatformRepo->ItsGroupInfo), + ItsGroupCount, + CmObject + ); + break; + + case EArmObjGicItsIdentifierArray: + Status =3D HandleCmObjectRefByToken ( + This, + CmObjectId, + PlatformRepo->ItsIdentifierArray, + sizeof (PlatformRepo->ItsIdentifierArray), + ItsIdentifierArrayCount, + Token, + GetItsIdentifierArray, + CmObject + ); + break; + + case EArmObjRootComplex: + Status =3D HandleCmObject ( + CmObjectId, + &PlatformRepo->RootComplexInfo, + sizeof (PlatformRepo->RootComplexInfo), + 1, + CmObject + ); + break; + + case EArmObjIdMappingArray: + Status =3D HandleCmObjectRefByToken ( + This, + CmObjectId, + PlatformRepo->DeviceIdMapping, + sizeof (PlatformRepo->DeviceIdMapping), + ARRAY_SIZE (PlatformRepo->DeviceIdMapping), + Token, + GetDeviceIdMappingArray, + CmObject + ); + break; + + case EArmObjPciConfigSpaceInfo: + Status =3D HandleCmObject ( + CmObjectId, + &PlatformRepo->PciConfigInfo, + sizeof (PlatformRepo->PciConfigInfo), + PciConfigSpaceCount, + CmObject + ); + break; + default: { Status =3D EFI_NOT_FOUND; DEBUG (( diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManager.h b/Platform/ARM/VExpressPkg/ConfigurationMana= ger/ConfigurationManagerDxe/ConfigurationManager.h index c21f160dd082bddb9e8e1ab666143887d67869cd..aebf0a355291df5df5f588e8b70= 76e21eda9a152 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManager.h @@ -17,6 +17,7 @@ containing the AML bytecode array. */ extern CHAR8 dsdt_aml_code[]; +extern CHAR8 ssdtpci_aml_code[]; =20 /** The configuration manager version. */ @@ -77,13 +78,18 @@ typedef EFI_STATUS (*CM_OBJECT_HANDLER_PROC) ( (CM_OBJECT_TOKEN)((UINT8*)&VExpressPlatRepositoryInfo + \ OFFSET_OF (EDKII_PLATFORM_REPOSITORY_INFO, Field)) =20 +/** Macro to return MPIDR for Multi Threaded Cores +*/ +#define GET_MPID_MT(Cluster, Core, Thread) \ + (((Cluster) << 16) | ((Core) << 8) | (Thread)) + /** The number of CPUs */ #define PLAT_CPU_COUNT 8 =20 /** The number of ACPI tables to install */ -#define PLAT_ACPI_TABLE_COUNT 6 +#define PLAT_ACPI_TABLE_COUNT 9 =20 /** The number of platform generic timer blocks */ @@ -145,6 +151,28 @@ typedef struct PlatformRepositoryInfo { =20 /// GIC ITS information CM_ARM_GIC_ITS_INFO GicItsInfo; + + // FVP RevC components + /// SMMUv3 node + CM_ARM_SMMUV3_NODE SmmuV3Info; + + /// ITS Group node + CM_ARM_ITS_GROUP_NODE ItsGroupInfo; + + /// ITS Identifier array + CM_ARM_ITS_IDENTIFIER ItsIdentifierArray[1]; + + /// PCI Root complex node + CM_ARM_ROOT_COMPLEX_NODE RootComplexInfo; + + /// Array of DeviceID mapping + CM_ARM_ID_MAPPING DeviceIdMapping[2]; + + /// PCI configuration space information + CM_ARM_PCI_CONFIG_SPACE_INFO PciConfigInfo; + + /// System ID + UINT32 SysId; } EDKII_PLATFORM_REPOSITORY_INFO; =20 #endif // CONFIGURATION_MANAGER_H__ diff --git a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationMan= agerDxe/ConfigurationManagerDxe.inf b/Platform/ARM/VExpressPkg/Configuratio= nManager/ConfigurationManagerDxe/ConfigurationManagerDxe.inf index c17595b7ec37cdd1c99b258cd32d1bde6c76a5ed..b53daf51d4b1afd45e41d0debb0= b9f084f135f6a 100644 --- a/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManagerDxe.inf +++ b/Platform/ARM/VExpressPkg/ConfigurationManager/ConfigurationManagerDxe= /ConfigurationManagerDxe.inf @@ -1,7 +1,7 @@ ## @file # Configuration Manager Dxe # -# Copyright (c) 2017 - 2020, Arm Limited. All rights reserved.
+# Copyright (c) 2017 - 2021, Arm Limited. All rights reserved.
# # SPDX-License-Identifier: BSD-2-Clause-Patent ## @@ -23,6 +23,7 @@ [Defines] [Sources] ConfigurationManager.c AslTables/Dsdt.asl + AslTables/SsdtPci.asl =20 [Packages] ArmPkg/ArmPkg.dec @@ -68,6 +69,13 @@ [FixedPcd] gEfiMdeModulePkgTokenSpaceGuid.PcdSerialRegisterBase gEfiMdePkgTokenSpaceGuid.PcdUartDefaultBaudRate =20 + # PCI Root complex specific PCDs + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseAddress + gEfiMdePkgTokenSpaceGuid.PcdPciExpressBaseSize + + gArmTokenSpaceGuid.PcdPciBusMin + gArmTokenSpaceGuid.PcdPciBusMax + [Pcd] =20 [Depex] --=20 'Guid(CE165669-3EF3-493F-B85D-6190EE5B9759)'