[PATCH edk2-platforms v1 1/1] TigerlakeOpenBoardPkg/TigerlakeURvp: Fix build errors with GCC5

["Takuto Naito" <naitaku@gmail.com>]

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This change fixes build errors of TigerlakeURvp with GCC5.
- Fix the path of TigerLakeFspBinPkg
- Fix misuse of RETURN_ERROR
- Fix the Teton Glacier Endpoint entry in mPciDeviceTable
- Remove unused function CheckNationalSio.

Signed-off-by: Takuto Naito <naitaku@gmail.com>
---
I tried to build TigerlakeURvp, but I faced some build errors. 
This patch fixes the build errors.

Build error 1:
Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf(55): error 000E: File/directory not found in workspace
TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec is not found in packages path:
It seems that the correct path is TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec.

Build error 2:
Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c:91:5: note: in expansion of macro ‘RETURN_ERROR’
   91 |     RETURN_ERROR (Status);
      |     ^~~~~~~~~~~~
It seems that ASSERT_EFI_ERROR should be here instead of RETURN_ERROR.

Build error 3:
Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c:18:77: error: missing braces around initializer [-Werror=missing-braces]
   18 | GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
      |                                                                             ^
......
  101 |   { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0, 0, 0 },
      |                                                                                              { }

The number of the fields seems to be wrong.

Build error 4:
Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c:105:1: error: ‘CheckNationalSio’ defined but not used [-Werror=unused-function]

CheckNationalSio function needed to be removed.


 .../PeiFspPolicyInitLib.inf                   |   2 +-
 .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------
 .../DxeSiliconPolicyUpdateLate.c              |   2 +-
 .../DxePchPcieRpPolicyLib.c                   |   2 +-
 4 files changed, 3 insertions(+), 191 deletions(-)

diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
index 9d85d855f5..708fbac08f 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf
@@ -52,7 +52,7 @@
   MdeModulePkg/MdeModulePkg.dec
   IntelFsp2Pkg/IntelFsp2Pkg.dec
   TigerlakeSiliconPkg/SiPkg.dec
-  TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec
+  TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec
   TigerlakeOpenBoardPkg/OpenBoardPkg.dec
   UefiCpuPkg/UefiCpuPkg.dec
   IntelSiliconPkg/IntelSiliconPkg.dec
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
index 6209e50450..cc5337698b 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c
@@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] = {
   {0x30, 0x01}                    // Enable it with Activation bit
 };
 
-/**
-  Detect if a National 393 SIO is docked. If yes, enable the docked SIO
-  and its serial port, and disable the onboard serial port.
-
-  @retval EFI_SUCCESS     Operations performed successfully.
-**/
-STATIC
-VOID
-CheckNationalSio (
-  VOID
-  )
-{
-  UINT8           Data8;
-
-  //
-  // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).
-  // We use (0x2e, 0x2f) which is determined by BADD default strapping
-  //
-
-  //
-  // Read the Pc87393 signature
-  //
-  IoWrite8 (0x2e, 0x20);
-  Data8 = IoRead8 (0x2f);
-
-  if (Data8 == 0xea) {
-    //
-    // Signature matches - National PC87393 SIO is docked
-    //
-
-    //
-    // Enlarge the LPC decode scope to accommodate the Docking LPC Switch
-    // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at
-    // SIO_BASE_ADDRESS + 0x10)
-    //
-    PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20);
-
-    //
-    // Enable port switch
-    //
-    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);
-
-    //
-    // Turn on docking power
-    //
-    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);
-
-    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);
-
-    IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);
-
-    //
-    // Enable port switch
-    //
-    IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);
-
-    //
-    // GPIO setting
-    //
-    IoWrite8 (0x2e, 0x24);
-    IoWrite8 (0x2f, 0x29);
-
-    //
-    // Enable chip clock
-    //
-    IoWrite8 (0x2e, 0x29);
-    IoWrite8 (0x2f, 0x1e);
-
-
-    //
-    // Enable serial port
-    //
-
-    //
-    // Select com1
-    //
-    IoWrite8 (0x2e, 0x7);
-    IoWrite8 (0x2f, 0x3);
-
-    //
-    // Base address: 0x3f8
-    //
-    IoWrite8 (0x2e, 0x60);
-    IoWrite8 (0x2f, 0x03);
-    IoWrite8 (0x2e, 0x61);
-    IoWrite8 (0x2f, 0xf8);
-
-    //
-    // Interrupt: 4
-    //
-    IoWrite8 (0x2e, 0x70);
-    IoWrite8 (0x2f, 0x04);
-
-    //
-    // Enable bank selection
-    //
-    IoWrite8 (0x2e, 0xf0);
-    IoWrite8 (0x2f, 0x82);
-
-    //
-    // Activate
-    //
-    IoWrite8 (0x2e, 0x30);
-    IoWrite8 (0x2f, 0x01);
-
-    //
-    // Disable onboard serial port
-    //
-    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);
-
-    //
-    // Power Down UARTs
-    //
-    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);
-    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);
-
-    //
-    // Dissable COM1 decode
-    //
-    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);
-    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
-
-    //
-    // Disable COM2 decode
-    //
-    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);
-    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);
-
-    //
-    // Disable interrupt
-    //
-    IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);
-    IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);
-
-    IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);
-
-    //
-    // Enable floppy
-    //
-
-    //
-    // Select floppy
-    //
-    IoWrite8 (0x2e, 0x7);
-    IoWrite8 (0x2f, 0x0);
-
-    //
-    // Base address: 0x3f0
-    //
-    IoWrite8 (0x2e, 0x60);
-    IoWrite8 (0x2f, 0x03);
-    IoWrite8 (0x2e, 0x61);
-    IoWrite8 (0x2f, 0xf0);
-
-    //
-    // Interrupt: 6
-    //
-    IoWrite8 (0x2e, 0x70);
-    IoWrite8 (0x2f, 0x06);
-
-    //
-    // DMA 2
-    //
-    IoWrite8 (0x2e, 0x74);
-    IoWrite8 (0x2f, 0x02);
-
-    //
-    // Activate
-    //
-    IoWrite8 (0x2e, 0x30);
-    IoWrite8 (0x2f, 0x01);
-
-  } else {
-
-    //
-    // No National pc87393 SIO is docked, turn off dock power and
-    // disable port switch
-    //
-    // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);
-    // IoWrite8 (0x690, 0);
-
-    //
-    // If no National pc87393, just return
-    //
-    return ;
-  }
-}
-
 /**
 Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports
 
diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
index 2eee9958be..410a8d1073 100644
--- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
+++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c
@@ -88,8 +88,8 @@ SiliconPolicyUpdateLate (
     // GOP Dxe Policy Initialization
     //
     Status = GopPolicyInitDxe (gImageHandle);
-    RETURN_ERROR (Status);
     DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));
+    ASSERT_EFI_ERROR (Status);
   }
 
   return Policy;
diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
index 577e436e32..1553d2e2aa 100644
--- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
+++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c
@@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceTable[] = {
   //
   // Teton Glacier Endpoint
   //
-  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0, 0, 0 },
+  { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x3C, 0, 5, 0, 0 },
 
   //
   // End of Table
-- 
2.30.1