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Sun, 14 Feb 2021 07:54:50 -0800 (PST) From: "Takuto Naito" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Heng Luo , Takuto Naito Subject: [PATCH edk2-platforms v1 1/1] TigerlakeOpenBoardPkg/TigerlakeURvp: Fix build errors with GCC5 Date: Mon, 15 Feb 2021 00:53:33 +0900 Message-Id: <20210214155333.21424-1-naitaku@gmail.com> X-Mailer: git-send-email 2.30.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable This change fixes build errors of TigerlakeURvp with GCC5.=0D - Fix the path of TigerLakeFspBinPkg=0D - Fix misuse of RETURN_ERROR=0D - Fix the Teton Glacier Endpoint entry in mPciDeviceTable=0D - Remove unused function CheckNationalSio.=0D =0D Signed-off-by: Takuto Naito =0D ---=0D I tried to build TigerlakeURvp, but I faced some build errors. =0D This patch fixes the build errors.=0D =0D Build error 1:=0D Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib= /PeiFspPolicyInitLib.inf(55): error 000E: File/directory not found in works= pace=0D TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec is not found in packages path:=0D It seems that the correct path is TigerLakeFspBinPkg/Client/TigerLakeFspBin= Pkg.dec.=0D =0D Build error 2:=0D Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateL= ib/DxeSiliconPolicyUpdateLate.c:91:5: note: in expansion of macro =E2=80=98= RETURN_ERROR=E2=80=99=0D 91 | RETURN_ERROR (Status);=0D | ^~~~~~~~~~~~=0D It seems that ASSERT_EFI_ERROR should be here instead of RETURN_ERROR.=0D =0D Build error 3:=0D Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieR= pPolicyLib/DxePchPcieRpPolicyLib.c:18:77: error: missing braces around init= ializer [-Werror=3Dmissing-braces]=0D 18 | GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mPcieDeviceT= able[] =3D {=0D | = ^=0D ......=0D 101 | { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0= xff, 0x3C, 0, 5, 0, 0, 0, 0 },=0D | = { }=0D =0D The number of the fields seems to be wrong.=0D =0D Build error 4:=0D Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatfo= rmHookLib.c:105:1: error: =E2=80=98CheckNationalSio=E2=80=99 defined but no= t used [-Werror=3Dunused-function]=0D =0D CheckNationalSio function needed to be removed.=0D =0D =0D .../PeiFspPolicyInitLib.inf | 2 +-=0D .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------=0D .../DxeSiliconPolicyUpdateLate.c | 2 +-=0D .../DxePchPcieRpPolicyLib.c | 2 +-=0D 4 files changed, 3 insertions(+), 191 deletions(-)=0D =0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFsp= PolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPk= g/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf=0D index 9d85d855f5..708fbac08f 100644=0D --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf=0D +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyI= nitLib/PeiFspPolicyInitLib.inf=0D @@ -52,7 +52,7 @@=0D MdeModulePkg/MdeModulePkg.dec=0D IntelFsp2Pkg/IntelFsp2Pkg.dec=0D TigerlakeSiliconPkg/SiPkg.dec=0D - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec=0D + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec=0D TigerlakeOpenBoardPkg/OpenBoardPkg.dec=0D UefiCpuPkg/UefiCpuPkg.dec=0D IntelSiliconPkg/IntelSiliconPkg.dec=0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookL= ib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/Bas= ePlatformHookLib/BasePlatformHookLib.c=0D index 6209e50450..cc5337698b 100644=0D --- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.c=0D +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/Base= PlatformHookLib.c=0D @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWi= nbond_x374[] =3D {=0D {0x30, 0x01} // Enable it with Activation bit=0D };=0D =0D -/**=0D - Detect if a National 393 SIO is docked. If yes, enable the docked SIO=0D - and its serial port, and disable the onboard serial port.=0D -=0D - @retval EFI_SUCCESS Operations performed successfully.=0D -**/=0D -STATIC=0D -VOID=0D -CheckNationalSio (=0D - VOID=0D - )=0D -{=0D - UINT8 Data8;=0D -=0D - //=0D - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f).=0D - // We use (0x2e, 0x2f) which is determined by BADD default strapping=0D - //=0D -=0D - //=0D - // Read the Pc87393 signature=0D - //=0D - IoWrite8 (0x2e, 0x20);=0D - Data8 =3D IoRead8 (0x2f);=0D -=0D - if (Data8 =3D=3D 0xea) {=0D - //=0D - // Signature matches - National PC87393 SIO is docked=0D - //=0D -=0D - //=0D - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch= =0D - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at=0D - // SIO_BASE_ADDRESS + 0x10)=0D - //=0D - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7= F), 0x20);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06);=0D -=0D - //=0D - // Turn on docking power=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc);=0D -=0D - //=0D - // Enable port switch=0D - //=0D - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7);=0D -=0D - //=0D - // GPIO setting=0D - //=0D - IoWrite8 (0x2e, 0x24);=0D - IoWrite8 (0x2f, 0x29);=0D -=0D - //=0D - // Enable chip clock=0D - //=0D - IoWrite8 (0x2e, 0x29);=0D - IoWrite8 (0x2f, 0x1e);=0D -=0D -=0D - //=0D - // Enable serial port=0D - //=0D -=0D - //=0D - // Select com1=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x3);=0D -=0D - //=0D - // Base address: 0x3f8=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf8);=0D -=0D - //=0D - // Interrupt: 4=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x04);=0D -=0D - //=0D - // Enable bank selection=0D - //=0D - IoWrite8 (0x2e, 0xf0);=0D - IoWrite8 (0x2f, 0x82);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - //=0D - // Disable onboard serial port=0D - //=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55);=0D -=0D - //=0D - // Power Down UARTs=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00);=0D -=0D - //=0D - // Dissable COM1 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable COM2 decode=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0);=0D -=0D - //=0D - // Disable interrupt=0D - //=0D - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28);=0D - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0);=0D -=0D - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA);=0D -=0D - //=0D - // Enable floppy=0D - //=0D -=0D - //=0D - // Select floppy=0D - //=0D - IoWrite8 (0x2e, 0x7);=0D - IoWrite8 (0x2f, 0x0);=0D -=0D - //=0D - // Base address: 0x3f0=0D - //=0D - IoWrite8 (0x2e, 0x60);=0D - IoWrite8 (0x2f, 0x03);=0D - IoWrite8 (0x2e, 0x61);=0D - IoWrite8 (0x2f, 0xf0);=0D -=0D - //=0D - // Interrupt: 6=0D - //=0D - IoWrite8 (0x2e, 0x70);=0D - IoWrite8 (0x2f, 0x06);=0D -=0D - //=0D - // DMA 2=0D - //=0D - IoWrite8 (0x2e, 0x74);=0D - IoWrite8 (0x2f, 0x02);=0D -=0D - //=0D - // Activate=0D - //=0D - IoWrite8 (0x2e, 0x30);=0D - IoWrite8 (0x2f, 0x01);=0D -=0D - } else {=0D -=0D - //=0D - // No National pc87393 SIO is docked, turn off dock power and=0D - // disable port switch=0D - //=0D - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf);=0D - // IoWrite8 (0x690, 0);=0D -=0D - //=0D - // If no National pc87393, just return=0D - //=0D - return ;=0D - }=0D -}=0D -=0D /**=0D Check whether the IT8628 SIO present on LPC. If yes, enable its serial por= ts=0D =0D diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSilicon= PolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpen= BoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLat= e.c=0D index 2eee9958be..410a8d1073 100644=0D --- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c=0D +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyU= pdateLib/DxeSiliconPolicyUpdateLate.c=0D @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate (=0D // GOP Dxe Policy Initialization=0D //=0D Status =3D GopPolicyInitDxe (gImageHandle);=0D - RETURN_ERROR (Status);=0D DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n"));=0D + ASSERT_EFI_ERROR (Status);=0D }=0D =0D return Policy;=0D diff --git a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivat= e/DxePchPcieRpPolicyLib/DxePchPcieRpPolicyLib.c b/Silicon/Intel/TigerlakeSi= liconPkg/IpBlock/PcieRp/LibraryPrivate/DxePchPcieRpPolicyLib/DxePchPcieRpPo= licyLib.c=0D index 577e436e32..1553d2e2aa 100644=0D --- a/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePc= hPcieRpPolicyLib/DxePchPcieRpPolicyLib.c=0D +++ b/Silicon/Intel/TigerlakeSiliconPkg/IpBlock/PcieRp/LibraryPrivate/DxePc= hPcieRpPolicyLib/DxePchPcieRpPolicyLib.c=0D @@ -98,7 +98,7 @@ GLOBAL_REMOVE_IF_UNREFERENCED PCH_PCIE_DEVICE_OVERRIDE mP= cieDeviceTable[] =3D {=0D //=0D // Teton Glacier Endpoint=0D //=0D - { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x= 3C, 0, 5, 0, 0, 0, 0 },=0D + { 0x8086, 0x0975, 0xff, 0, 0, 0, PchPcieL1SubstatesOverride, 0, 0xff, 0x= 3C, 0, 5, 0, 0 },=0D =0D //=0D // End of Table=0D -- =0D 2.30.1=0D =0D