From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by mx.groups.io with SMTP id smtpd.web08.29688.1613385156748952720 for ; Mon, 15 Feb 2021 02:32:37 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: arm.com, ip: 217.140.110.172, mailfrom: vivek.gautam@arm.com) Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EF710101E; Mon, 15 Feb 2021 02:32:35 -0800 (PST) Received: from usa.arm.com (a074945.blr.arm.com [10.162.16.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 7B9113F40C; Mon, 15 Feb 2021 02:32:34 -0800 (PST) From: "Vivek Kumar Gautam" To: devel@edk2.groups.io Cc: Ard Biesheuvel , Leif Lindholm , Sami Mujawar Subject: [edk2-platforms][PATCH V1 0/2] Enable SMMUv3 for Arm SGI/RD platforms Date: Mon, 15 Feb 2021 16:02:27 +0530 Message-Id: <20210215103229.12310-1-vivek.gautam@arm.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Arm's SMMUv3 present in various SGI/RD platforms provides address translation support for devices such as the ones present over PCIe. SMMUv3 also supports Address Translation Service (ATS) and Page Request Interface (PRI) to work with PCIe devices. ATS allows PCIe devices to cache translation in their private caches called as Address Translation Cache (ATC). The ITS block present in the system accepts the downstream traffic from SMMUv3 and provides the right interrupt translation for LPIs. Thus, the overall topology looks like below - --------------- ------------ ------------ | PCIe device |---->| SMMUv3 |---->| ITS | | (RequesterID) | | (StreamID) | | (DeviceID) | --------------- ------------ ------------ Vivek Gautam (2): Platform/Sgi: Add smmu node in the iort acpi table Platform/Sgi: Enable ATS mode over PCI root complex Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 60 ++++++++++++++++++-- 1 file changed, 55 insertions(+), 5 deletions(-) --=20 2.17.1