[edk2-platforms][PATCH V1 0/2] Enable SMMUv3 for Arm SGI/RD platforms

[edk2-platforms][PATCH V1 0/2] Enable SMMUv3 for Arm SGI/RD platforms

[Vivek Kumar Gautam]

Arm's SMMUv3 present in various SGI/RD platforms provides address
translation support for devices such as the ones present over PCIe.
SMMUv3 also supports Address Translation Service (ATS) and Page
Request Interface (PRI) to work with PCIe devices.
ATS allows PCIe devices to cache translation in their private
caches called as Address Translation Cache (ATC).

The ITS block present in the system accepts the downstream traffic
from SMMUv3 and provides the right interrupt translation for LPIs.
Thus, the overall topology looks like below -

	 ---------------       ------------       ------------
	|  PCIe device  |---->|  SMMUv3    |---->|   ITS      |
	| (RequesterID) |     | (StreamID) |     | (DeviceID) |
	 ---------------       ------------       ------------

Vivek Gautam (2):
  Platform/Sgi: Add smmu node in the iort acpi table
  Platform/Sgi: Enable ATS mode over PCI root complex

 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 60 ++++++++++++++++++--
 1 file changed, 55 insertions(+), 5 deletions(-)

-- 
2.17.1

[edk2-platforms][PATCH V1 1/2] Platform/Sgi: Add smmu node in the iort acpi table

[Vivek Kumar Gautam]

Add the generic SMMUv3 type node in the iort table and
setup the rid->stream-id->device-id mapping accordingly.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 58 ++++++++++++++++++--
 1 file changed, 54 insertions(+), 4 deletions(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
index 58ec31ddc837..df9bd501158c 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
@@ -20,6 +20,12 @@ typedef struct
   UINT32                                   ItsIdentifiers;
 } ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE;
 
+typedef struct
+{
+  EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE     SmmuNode;
+  EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE       SmmuIdMap[2];
+} ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE;
+
 typedef struct
 {
   EFI_ACPI_6_0_IO_REMAPPING_RC_NODE        RcNode;
@@ -30,6 +36,7 @@ typedef struct
 {
   EFI_ACPI_6_0_IO_REMAPPING_TABLE          Header;
   ARM_EFI_ACPI_6_0_IO_REMAPPING_ITS_NODE   ItsNode;
+  ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE SmmuNode;
   ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE    RcNode;
 } ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE;
 
@@ -45,7 +52,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
        ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE,
        EFI_ACPI_IO_REMAPPING_TABLE_REVISION
      ),
-     2,  // NumNodes
+     3,  // NumNodes
      sizeof (EFI_ACPI_6_0_IO_REMAPPING_TABLE),  // NodeOffset
      0,  // Reserved
   },
@@ -62,9 +69,52 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
         0,  // NumIdMappings
         0,  // IdReference
       },
-      1,    // GIC ITS Identifiers
+      1,    // ITS count
+    },
+    0,      // GIC ITS Identifiers
+  },
+  // SMMU
+  {
+    // EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE
+    {
+      // EFI_ACPI_6_0_IO_REMAPPING_NODE
+      {
+        EFI_ACPI_IORT_TYPE_SMMUv3, // Type
+        sizeof (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE), // Length
+        2, // Revision
+        0, // Reserved
+        2, // NumIdMapping
+        __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_SMMU3_NODE, SmmuIdMap), // IdReference
+      },
+      0x4F000000, // Base address
+      EFI_ACPI_IORT_SMMUv3_FLAG_COHAC_OVERRIDE, // Flags
+      0,   // Reserved
+      0,   // VATOS address
+      EFI_ACPI_IORT_SMMUv3_MODEL_GENERIC, // SMMUv3 Model
+      260, // Event
+      0,   // Pri
+      262, // Gerror
+      261, // Sync
+      0,   // Proximity domain
+      1,   // DevIDMappingIndex
+    },
+    // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
+    {
+      {
+        0x0000, // InputBase
+        0xffff, // NumIds
+        0x0000, // OutputBase
+        __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference
+        0, // Flags
+      },
+      {
+        0x0,     // InputBase
+        0x1,     // NumIds
+        0x10000, // OutputBase
+        __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode), // OutputReference
+        EFI_ACPI_IORT_ID_MAPPING_FLAGS_SINGLE, // Flags
+      },
     },
-    0,
   },
   // ARM_EFI_ACPI_6_0_IO_REMAPPING_RC_NODE
   {
@@ -91,7 +141,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
       0x0000,  // InputBase
       0xffff,  // NumIds
       0x0000,  // OutputBase
-      OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode),  // OutputReference
+      OFFSET_OF (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, SmmuNode),  // OutputReference
       0,       // Flags
     }
   }
-- 
2.17.1

Re: [edk2-devel] [edk2-platforms][PATCH V1 1/2] Platform/Sgi: Add smmu node in the iort acpi table

[Sami Mujawar]

[-- Attachment #1: Type: text/plain, Size: 362 bytes --]

Hi Vivek,

Can you include the description you included in the cover letter in the commit message for this patch, please?

On Mon, Feb 15, 2021 at 01:00 PM, Vivek Kumar Gautam wrote:

> 
> + __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode=

Use OFFSET_OF() macro as __builtin_offsetof is compiler specific.

Regards,

Sami Mujawar

[-- Attachment #2: Type: text/html, Size: 415 bytes --]

Re: [edk2-devel] [edk2-platforms][PATCH V1 1/2] Platform/Sgi: Add smmu node in the iort acpi table

[Vivek Kumar Gautam]

Hi Sami,


On 3/1/21 8:08 PM, Sami Mujawar via Groups.Io wrote:
> Hi Vivek,
>
> Can you include the description you included in the cover letter in the commit message for this patch, please?

Sure, I will update the commit message.

>
> On Mon, Feb 15, 2021 at 01:00 PM, Vivek Kumar Gautam wrote:
>
>>
>> + __builtin_offsetof (ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE, ItsNode=
>
> Use OFFSET_OF() macro as __builtin_offsetof is compiler specific.

Sure. Thanks for the input and the review.

Best regards
Vivek

>
> Regards,
>
> Sami Mujawar
>
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[edk2-platforms][PATCH V1 2/2] Platform/Sgi: Enable ATS mode over PCI root complex

[Vivek Kumar Gautam]

Enable Address Translation Service (ATS) support for the PCI root
complex listed in the iort table. Enabling ATS mode also enables
PRI support.

Signed-off-by: Vivek Gautam <vivek.gautam@arm.com>
---
 Platform/ARM/SgiPkg/AcpiTables/Iort.aslc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
index df9bd501158c..98f86eb7fb45 100644
--- a/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
+++ b/Platform/ARM/SgiPkg/AcpiTables/Iort.aslc
@@ -133,7 +133,7 @@ ARM_EFI_ACPI_6_0_IO_REMAPPING_TABLE Iort =
       0,  // AllocationHints
       0,  // Reserved
       0,  // MemoryAccessFlags
-      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_UNSUPPORTED,  // AtsAttribute
+      EFI_ACPI_IORT_ROOT_COMPLEX_ATS_SUPPORTED,    // AtsAttribute
       0x0,                                         // PciSegmentNumber
     },
     // EFI_ACPI_6_0_IO_REMAPPING_ID_TABLE
-- 
2.17.1