From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by mx.groups.io with SMTP id smtpd.web08.2537.1613790933607717865 for ; Fri, 19 Feb 2021 19:15:34 -0800 Authentication-Results: mx.groups.io; dkim=missing; spf=pass (domain: intel.com, ip: 134.134.136.65, mailfrom: w.sheng@intel.com) IronPort-SDR: j1lBreC/tNW25nd4QTEBU4NZYkORQ6VrIBekMu9FLHq5pST+psSWUs7vE0u2s8DWJrBvS3yTln QmZZv5SLa+xg== X-IronPort-AV: E=McAfee;i="6000,8403,9900"; a="184082922" X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="184082922" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 19 Feb 2021 19:15:32 -0800 IronPort-SDR: 3eansEYTzR78aPlR7rnno8V/pyMKRd9n+2NYY/hsKf4LdIGzBwv36m5yEnEFWys58eyRxt0ucW jRZR2gHfmh/A== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.81,192,1610438400"; d="scan'208";a="440520710" Received: from unknown (HELO shwdeSSSDDPDWEI.ccr.corp.intel.com) ([10.239.157.35]) by orsmga001.jf.intel.com with ESMTP; 19 Feb 2021 19:15:29 -0800 From: "Sheng Wei" To: devel@edk2.groups.io Cc: Eric Dong , Ray Ni , Laszlo Ersek , Rahul Kumar , Jiewen Yao , Michael D Kinney , Liming Gao , Zhiguang Liu , Roger Feng Subject: [PATCH v5 0/2] Fix CET shadow stack token busy bit clear issue Date: Sat, 20 Feb 2021 11:14:59 +0800 Message-Id: <20210220031501.24284-1-w.sheng@intel.com> X-Mailer: git-send-email 2.16.2.windows.1 If CET shadows stack feature enabled in SMM and stack switch is enabled. When code execute from SMM handler to SMM exception, CPU will check SMM exception shadow stack token busy bit if it is cleared or not. If it is set, it will trigger #DF exception. If it is not set, CPU will set the busy bit when enter SMM exception. So, the busy bit should be cleared when return back form SMM exception to SMM handler. Otherwise, keeping busy bit 1 will cause to trigger #DF exception when enter SMM exception next time. So, we use instruction SAVEPREVSSP, CLRSSBSY and RSTORSSP to clear the shadow stack token busy bit before RETF instruction in SMM exception. Since open CI is using NASM 2.14.02, it has not supported CET instructions yet. DB-encoded CET instructions will to be removed after open CI update to NASM 2.15.01. Change from patch v1 to patch v2: 1 Add behavior description in source code comment. 2 Structure interrupt shadow stack memory in InitShadowStack(). 3 Update commit comment. Change from patch v2 to patch v3: 1 Add comment /UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c Change from patch v3 to patch v4: Update comment and commit message. Change from patch v4 to patch v5: Update commit message. REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3192 Signed-off-by: Sheng Wei Cc: Eric Dong Cc: Ray Ni Cc: Laszlo Ersek Cc: Rahul Kumar Cc: Jiewen Yao Cc: Michael D Kinney Cc: Liming Gao Cc: Zhiguang Liu Cc: Roger Feng Sheng Wei (2): MdePkg/Include: Add CET instructions to Nasm.inc UefiCpuPkg/CpuExceptionHandlerLib: Clear CET shadow stack token busy bit MdePkg/Include/Ia32/Nasm.inc | 12 ++++++ MdePkg/Include/X64/Nasm.inc | 12 ++++++ .../DxeCpuExceptionHandlerLib.inf | 3 ++ .../PeiCpuExceptionHandlerLib.inf | 3 ++ .../SecPeiCpuExceptionHandlerLib.inf | 4 ++ .../SmmCpuExceptionHandlerLib.inf | 3 ++ .../X64/Xcode5ExceptionHandlerAsm.nasm | 46 +++++++++++++++++++++- .../Xcode5SecPeiCpuExceptionHandlerLib.inf | 4 ++ UefiCpuPkg/PiSmmCpuDxeSmm/X64/SmmFuncsArch.c | 15 ++++++- 9 files changed, 99 insertions(+), 3 deletions(-) -- 2.16.2.windows.1