From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mail-pj1-f41.google.com (mail-pj1-f41.google.com [209.85.216.41]) by mx.groups.io with SMTP id smtpd.web12.21024.1613920228010698849 for ; Sun, 21 Feb 2021 07:10:28 -0800 Authentication-Results: mx.groups.io; dkim=pass header.i=@gmail.com header.s=20161025 header.b=UrjzBkoM; spf=pass (domain: gmail.com, ip: 209.85.216.41, mailfrom: naitaku@gmail.com) Received: by mail-pj1-f41.google.com with SMTP id l18so7096136pji.3 for ; Sun, 21 Feb 2021 07:10:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jJPNgYFNrAzoaal94s323TxWxvi0WlKpVS7DCz4lV9E=; b=UrjzBkoMW0lOFA5xzLdXx/hmXWkoiNWYjI57PGUOPdYmM75moUx1ipXF0NzAsBxuRu WNOUDCfHHn4ONtqibbzeXnQXbC73SWfGovWmFkEoaGcx1qgHe5CxK5fkpTCsD3IjLiJ3 6m4BlfCnwJlBzd7DrLf5em74jz/b67zGTohJ/eMyePbf8jBcK3UehlI/hcwZP4UwLb6Q nWsEBLBPYhYzqEHdeveWaF1clkAQHg6kZsnIzibs4iQ0E3mKqIsawhpSY32pYZrwIa4U Lwqhrt4xETP00z/ms+x7zlSePEsWKoFutFjwADqrWe0tB9a6RUAr7JD9egmNMcuEkstB 6GUQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jJPNgYFNrAzoaal94s323TxWxvi0WlKpVS7DCz4lV9E=; b=jsU/Tf8p2qLvSCj5N1NvHIkXwUv07a9X9FanKN8H9TKwzNTq9FIqgqYi2JytzACguZ /GI/V4aCzakmlCd6dPilNSJxh/ko89lDG5ihtJTNput8GTdqCv/xeTI+bjkFZplUKOIS mEaZCafPFh4UKuCSW4pvtZM8VZ4qlWsJpsJkYjYM6Eb98pCg/xaqZLr7HPen8Ro/rT1s RFxVSYlE9IGyomekwcvXK28yyhqrv4mFfJIoMeMa5g9tBConfleyXuVUZTQ76Kx2avHr 0Abzqh5IWzgmHOh3alEv5CORYV4RQnUD1vCeYdqgQoOCx5hcFB7XG/0BniDUftkDCI54 wzFw== X-Gm-Message-State: AOAM532LJ9YqcAhxy4NXN0oGZFvmKf4+Vh9xQf72aAE1Drea8DapBmcK InpVQJ31OLnu6jvu9oQgSEo/DXKkLSqFkWCn X-Google-Smtp-Source: ABdhPJwn5WELYf7b5ldIFjLD9l0BJKcYUQ61BO4iA+xkER7KXl7mlfQMIsgRJgayyyc1mhTC8Z5qSQ== X-Received: by 2002:a17:902:e886:b029:de:57b2:da69 with SMTP id w6-20020a170902e886b02900de57b2da69mr10786334plg.65.1613920227141; Sun, 21 Feb 2021 07:10:27 -0800 (PST) Return-Path: Received: from localhost.localdomain ([240d:1e:84:2c00:4c90:1fc7:fcf3:2538]) by smtp.googlemail.com with ESMTPSA id o62sm5073511pga.43.2021.02.21.07.10.25 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Sun, 21 Feb 2021 07:10:26 -0800 (PST) From: "Takuto Naito" To: devel@edk2.groups.io Cc: Sai Chaganty , Nate DeSimone , Heng Luo Subject: [PATCH v2 1/2] TigerlakeOpenBoardPkg: Fix build errors with GCC5 Date: Mon, 22 Feb 2021 00:10:19 +0900 Message-Id: <20210221151020.40242-2-naitaku@gmail.com> X-Mailer: git-send-email 2.30.1 In-Reply-To: <20210221151020.40242-1-naitaku@gmail.com> References: <20210221151020.40242-1-naitaku@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3224 - Fix the path of TigerLakeFspBinPkg - Fix misuse of RETURN_ERROR - Remove unused function CheckNationalSio. Cc: Sai Chaganty Cc: Nate DeSimone Cc: Heng Luo Signed-off-by: Takuto Naito --- Notes: v2: - Split the v1 patch into 2 patches, One is for Platform/Intel/TigerlakeOpenBoardPkg, another one is for edk2-platforms\Silicon\Intel\TigerlakeSiliconPkg. .../PeiFspPolicyInitLib.inf | 2 +- .../BasePlatformHookLib/BasePlatformHookLib.c | 188 ------------------ .../DxeSiliconPolicyUpdateLate.c | 2 +- 3 files changed, 2 insertions(+), 190 deletions(-) diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf index 9d85d855f5..708fbac08f 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf +++ b/Platform/Intel/TigerlakeOpenBoardPkg/FspWrapper/Library/PeiFspPolicyInitLib/PeiFspPolicyInitLib.inf @@ -52,7 +52,7 @@ MdeModulePkg/MdeModulePkg.dec IntelFsp2Pkg/IntelFsp2Pkg.dec TigerlakeSiliconPkg/SiPkg.dec - TigerLakeFspBinPkg/TigerLakeFspBinPkg.dec + TigerLakeFspBinPkg/Client/TigerLakeFspBinPkg.dec TigerlakeOpenBoardPkg/OpenBoardPkg.dec UefiCpuPkg/UefiCpuPkg.dec IntelSiliconPkg/IntelSiliconPkg.dec diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c index 6209e50450..cc5337698b 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Library/BasePlatformHookLib/BasePlatformHookLib.c @@ -94,194 +94,6 @@ GLOBAL_REMOVE_IF_UNREFERENCED EFI_SIO_TABLE mSioTableWinbond_x374[] = { {0x30, 0x01} // Enable it with Activation bit }; -/** - Detect if a National 393 SIO is docked. If yes, enable the docked SIO - and its serial port, and disable the onboard serial port. - - @retval EFI_SUCCESS Operations performed successfully. -**/ -STATIC -VOID -CheckNationalSio ( - VOID - ) -{ - UINT8 Data8; - - // - // Pc87393 access is through either (0x2e, 0x2f) or (0x4e, 0x4f). - // We use (0x2e, 0x2f) which is determined by BADD default strapping - // - - // - // Read the Pc87393 signature - // - IoWrite8 (0x2e, 0x20); - Data8 = IoRead8 (0x2f); - - if (Data8 == 0xea) { - // - // Signature matches - National PC87393 SIO is docked - // - - // - // Enlarge the LPC decode scope to accommodate the Docking LPC Switch - // Register (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS is allocated at - // SIO_BASE_ADDRESS + 0x10) - // - PchLpcGenIoRangeSet ((FixedPcdGet16 (PcdSioBaseAddress) & (UINT16)~0x7F), 0x20); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x06); - - // - // Turn on docking power - // - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x8c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0x9c); - - IoWrite8 (FixedPcdGet16 (PcdSioBaseAddress) + 0x0E, 0xBc); - - // - // Enable port switch - // - IoWrite8 (SIO_DOCKING_LPC_SWITCH_REGISTER_ADDRESS, 0x7); - - // - // GPIO setting - // - IoWrite8 (0x2e, 0x24); - IoWrite8 (0x2f, 0x29); - - // - // Enable chip clock - // - IoWrite8 (0x2e, 0x29); - IoWrite8 (0x2f, 0x1e); - - - // - // Enable serial port - // - - // - // Select com1 - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x3); - - // - // Base address: 0x3f8 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf8); - - // - // Interrupt: 4 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x04); - - // - // Enable bank selection - // - IoWrite8 (0x2e, 0xf0); - IoWrite8 (0x2f, 0x82); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - // - // Disable onboard serial port - // - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0x55); - - // - // Power Down UARTs - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x2); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x00); - - // - // Dissable COM1 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x24); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable COM2 decode - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x25); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0); - - // - // Disable interrupt - // - IoWrite8 (PcdGet16 (PcdLpcSioIndexPort), 0x28); - IoWrite8 (PcdGet16 (PcdLpcSioDataPort), 0x0); - - IoWrite8 (FixedPcdGet16 (PcdLpcSioConfigDefaultPort), 0xAA); - - // - // Enable floppy - // - - // - // Select floppy - // - IoWrite8 (0x2e, 0x7); - IoWrite8 (0x2f, 0x0); - - // - // Base address: 0x3f0 - // - IoWrite8 (0x2e, 0x60); - IoWrite8 (0x2f, 0x03); - IoWrite8 (0x2e, 0x61); - IoWrite8 (0x2f, 0xf0); - - // - // Interrupt: 6 - // - IoWrite8 (0x2e, 0x70); - IoWrite8 (0x2f, 0x06); - - // - // DMA 2 - // - IoWrite8 (0x2e, 0x74); - IoWrite8 (0x2f, 0x02); - - // - // Activate - // - IoWrite8 (0x2e, 0x30); - IoWrite8 (0x2f, 0x01); - - } else { - - // - // No National pc87393 SIO is docked, turn off dock power and - // disable port switch - // - // IoWrite8 (SIO_BASE_ADDRESS + 0x0E, 0xbf); - // IoWrite8 (0x690, 0); - - // - // If no National pc87393, just return - // - return ; - } -} - /** Check whether the IT8628 SIO present on LPC. If yes, enable its serial ports diff --git a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c index 2eee9958be..410a8d1073 100644 --- a/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c +++ b/Platform/Intel/TigerlakeOpenBoardPkg/Policy/Library/DxeSiliconPolicyUpdateLib/DxeSiliconPolicyUpdateLate.c @@ -88,8 +88,8 @@ SiliconPolicyUpdateLate ( // GOP Dxe Policy Initialization // Status = GopPolicyInitDxe (gImageHandle); - RETURN_ERROR (Status); DEBUG ((DEBUG_INFO, "GOP Dxe Policy Initialization done\n")); + ASSERT_EFI_ERROR (Status); } return Policy; -- 2.30.1